Display panel, driving method thereof and display device

Abstract

The invention discloses a display panel, a driving method thereof and a display device, and relates to the technical field of display. The display panel comprises a light-emitting element and a plurality of pixel circuits. The pixel circuit comprises a driving module, a first reset module and a second reset module. The first reset module is connected with the control end of the driving module and a first reset line; the second reset module is connected with the first pole of the light-emitting element and a second reset line; in the first refresh rate range, one picture refresh cycle of the pixel circuit comprises a first data writing stage and at least one holding stage; the first data write-in stage comprises a first reset sub-stage, in the first reset sub-stage, a first reset module is switched on, and the voltage of a first reset signal is VREF1; the holding stage comprises a second reset sub-stage, in the second reset sub-stage, the first reset module is switched on, the second reset module is switched off, the voltage of the first reset signal is VREF2, and VREF1 is not equal to VREF2. According to the embodiment of the invention, the use performance of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a driving method thereof, and a display device, which are beneficial to improving the performance of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including a light-emitting element and a plurality of pixel circuits;

[0006] Wherein, the pixel circuit includes a driving module, a first reset module and a second reset module;

[0007] The first reset module is connected to the control end of the driving module and the first reset line, and is used to provide a first reset signal on the first reset line to the control end of the driving module;

[0008] The second reset module is connected to the first electrode of the light emitting element and the second reset line, and is used to provide a second reset signal on the second reset line to the first electrode of the light emitting element;

[0009] Within the first refresh rate range, a picture refresh cycle of the pixel circuit includes a first data writing phase and at least one holding phase;

[0010] The first data writing phase includes a first reset sub-phase. In the first reset sub-phase, the first reset module is turned on, and the voltage of the first reset signal is VREF1;

[0011] The holding phase includes a second reset sub-phase. In the second reset sub-phase, the first reset module is turned on, the second reset module is turned off, and the voltage of the first reset signal is VREF2, VREF1≠VREF2.

[0012] In some implementations of the first aspect, the driving module includes a P-type transistor, and VREF1<VREF2.

[0013] In some embodiments of the first aspect, -4V<VREF2<0V.

[0014] In some implementations of the first aspect, the driving transistor comprises an N-type transistor, and VREF1>VREF2.

[0015] In some embodiments of the first aspect, the display panel has a first brightness level and a second brightness level, the first brightness level being higher than the second brightness level;

[0016] At the first brightness level and the second reset sub-stage, the voltage of the first reset signal is VREF21;

[0017] At the second brightness level and the second reset sub-phase, the voltage of the first reset signal is VREF22, VREF21≠VREF22.

[0018] In some implementations of the first aspect, VREF21>VREF22.

[0019] In some implementations of the first aspect, the first refresh rate range includes a first refresh rate and a second refresh rate, and the first refresh rate is greater than the second refresh rate;

[0020] At the first refresh rate and the second reset sub-phase, the voltage of the first reset signal is VREF23;

[0021] At the second refresh rate and the second reset sub-phase, the voltage of the second reset signal is VREF24, VREF23≠VREF24.

[0022] In some embodiments of the first aspect, VREF23<VREF24.

[0023] In some implementations of the first aspect, the display panel supports a third refresh rate, and the third refresh rate is greater than any refresh rate within the range of the first refresh rate;

[0024] At the third refresh rate, a picture refresh cycle of the pixel circuit includes a second data writing phase;

[0025] The second data writing phase includes a third reset sub-phase. In the third reset sub-phase, the first reset module is turned on, and the voltage of the first reset signal is VREF3, VREF3=VREF1.

[0026] In some implementations of the first aspect, the first reset line and the second reset line are connected to different signal terminals.

[0027] In some implementations of the first aspect, a voltage of the second reset signal is different from at least one of a voltage of the first reset signal in the first reset sub-stage and a voltage of the first reset signal in the second reset sub-stage.

[0028] In some implementations of the first aspect, the pixel circuit further includes a data writing module, a threshold compensation module, a light emitting control module, and a storage module;

[0029] The data writing module is connected to the first end of the driving module and the data line;

[0030] The threshold compensation module is connected to the second end of the driving module and the control end of the driving module;

[0031] The light emitting control module is connected to the first power line, the first end of the driving module, the second end of the driving module, the light emitting element and the light emitting control line;

[0032] The storage module is connected to the first power line and the control end of the driving module.

[0033] In some embodiments of the first aspect, the light control module includes a first light control module and a second light control module;

[0034] The first light emitting control module is connected to the first power line, the first end of the driving module and the light emitting control line;

[0035] The second light emitting control module is connected to the second end of the driving module, the first pole of the light emitting element and the light emitting control line.

[0036] In some embodiments of the first aspect, the driving module includes a first transistor, the first reset module includes a second transistor, the second reset module includes a third transistor, the data writing module includes a fourth transistor, the threshold compensation module includes a fifth transistor, the light emitting control module includes a sixth transistor and a seventh transistor, and the storage module includes a storage capacitor.

[0037] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a method for driving a display panel, which is applied to the display panel of any one of the first aspects;

[0038] A picture refresh cycle of the pixel circuit includes a first data writing phase and at least one holding phase;

[0039] Methods include:

[0040] The first data writing stage includes a first reset sub-stage. In the first reset sub-stage, the first reset module is controlled to be turned on, and the voltage of the first reset signal is controlled to be VREF1;

[0041] The holding stage includes a second reset sub-stage. In the second reset sub-stage, the first reset module is controlled to be turned on, the second reset module is controlled to be turned off, and the voltage of the first reset signal is controlled to be VREF2, VREF1≠VREF2.

[0042] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, comprising the display panel of any one of the first aspects.

[0043] According to the display panel and its driving method and display device provided by the embodiments of the present application, in the first reset sub-stage and the second reset sub-stage within the first refresh rate range, different voltages are used to reset the control end of the driving module, respectively. In this way, the voltage of the control end of the driving module in the first reset sub-stage is different from the voltage of the control end of the driving module in the second reset sub-stage, which provides the possibility of reducing the display brightness of the display panel in the holding stage, and further provides the possibility of improving or solving the flicker problem of the display panel when switching from high frequency to low frequency or at low frequency, which is beneficial to improving the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0045] Figure 1 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0046] Figure 2 A timing diagram of a display panel provided by an embodiment of the present application is shown;

[0047] Figure 3 Another timing diagram of a display panel provided by an embodiment of the present application is shown;

[0048] Figure 4 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0049] Figure 5 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0050] Figure 6 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0051] Figure 7 Another schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown;

[0052] Figure 8 A schematic diagram showing a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0053] Fig. 9 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0054] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0055] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0056] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0057] The term "connect" may mean "electrically connected" or "not electrically connected through an intermediate transistor". The term "insulation" may mean "electrically insulating" or "electrically isolated". The term "drive" may mean "control" or "operate". The term "part" may mean "local". The term "pattern" may mean "component". The term "end" may mean "end segment" or "end edge". The display panel may be a display device or a module / part of a display device.

[0058] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not actual circuit units.

[0059] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0060] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0061] OLED display devices have many advantages such as self-luminescence and high contrast, and are a display device with broad application prospects.

[0062] In the related technology, the gamma voltage value of the display panel at low frequency shares the gamma voltage value based on high-frequency debugging, but since the data writing frequency of the display panel at high frequency and at low frequency is different, the hysteresis effect of the pixel circuit in the display panel is different, which in turn causes the display panel to flicker when switching from high frequency to low frequency (for example, switching the refresh rate of the display panel from 90Hz to 10Hz), or at low frequency (for example, the refresh rate of the display panel is 10Hz). The performance of OLED display products needs to be improved.

[0063] To solve the above problems, the embodiments of the present application provide a display panel and a driving method thereof, and a display device. The following will describe various embodiments of the display panel and a driving method thereof, and a display device in conjunction with the accompanying drawings.

[0064] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown. Figure 2 A timing diagram of a display panel provided in an embodiment of the present application is shown.

[0065] like Figure 1 As shown, the display panel 100 provided in the embodiment of the present application includes a light emitting element D and a plurality of pixel circuits 10. The light emitting element D can be connected to both the pixel circuit 10 and the second power line ELVSS.

[0066] Exemplarily, the light emitting element D includes but is not limited to an OLED. The second power line ELVSS may be a signal line providing a negative voltage signal.

[0067] The pixel circuit 10 may include a driving module 11 , a first reset module 12 and a second reset module 13 .

[0068] The first reset module 12 is connected to the control end of the driving module 11 and the first reset line VREF, and is used to provide a first reset signal on the first reset line VREF to the control end of the driving module 11 .

[0069] Exemplarily, the first end of the first reset module 12 may be connected to the first reset line VREF, the second end of the first reset module 12 may be connected to the control end of the driving module 11, and the control end of the first reset module 12 may be connected to the first scan line S1. The first reset module 12 may be turned on or off under the control of the scan signal on the first scan line S1. When the scan signal on the first scan line S1 controls the first reset module 12 to be turned on, the first reset module 12 may provide the first reset signal on the first reset line VREF to the control end of the driving module 11 to achieve the reset of the control end of the driving module 11.

[0070] The second reset module 13 is connected to the first electrode of the light emitting element D and the second reset line INIT, and is used to provide the first electrode of the light emitting element D with a second reset signal on the second reset line INIT.

[0071] Exemplarily, the first end of the second reset module 13 may be connected to the second reset line INIT, the second end of the second reset module 13 may be connected to the anode of the light emitting element D, and the control end of the second reset module 13 may be connected to the second scan line S2. The second reset module 13 may be turned on or off under the control of the scan signal on the second scan line S2. When the scan signal on the second scan line S2 controls the second reset module 13 to be turned on, the second reset module 13 may provide the second reset signal on the second reset line INIT to the anode of the light emitting element D, so as to reset the anode of the light emitting element D.

[0072] In the first refresh rate range, a picture refresh cycle of the pixel circuit 10 includes a first data writing phase and at least one holding phase.

[0073] like Figure 2 As shown, the i-th picture refresh cycle of the pixel circuit includes a first data writing phase and three holding phases, i is a positive integer. The number of holding phases can be set according to actual conditions and is not limited here.

[0074] Exemplarily, the first refresh rate range may include a refresh rate range in which other refresh rates except the maximum refresh rate supported by the display panel are located.

[0075] The picture refresh cycle may be determined according to the minimum cycle of writing the data signal into the control terminal of the driving module 11. For example, in one picture refresh cycle, the data signal may be written into the control terminal of the driving module 11 once.

[0076] In the first data writing phase, the data signal can be written into the control end of the driving module 11 ; in the holding phase, the data signal is not written into the control end of the driving module 11 .

[0077] The first data writing phase includes a first reset sub-phase r1 . In the first reset sub-phase r1 , the first reset module 12 is turned on, and the voltage of the first reset signal is VREF1 .

[0078] In the first reset sub-phase r1 , the first reset module 12 is turned on, and the voltage VREF1 of the first reset signal is transmitted to the control end of the driving module 11 through the first reset module 12 to reset the control end of the driving module 11 .

[0079] It should be noted that in the first reset sub-stage r1, the second reset module 13 can be turned on or off. That is to say, the control end of the driving module 11 and the anode of the light-emitting element D can both be reset in the first reset sub-stage r1, or the control end of the driving module 11 can be reset in the first reset sub-stage r1, and the anode of the light-emitting element D can be reset in other periods except the first reset sub-stage r1 in the first data writing stage.

[0080] The number of the first resetting sub-phases r1 included in the first data writing phase can be set according to actual conditions and is not limited here.

[0081] The holding phase includes a second reset sub-phase r2. In the second reset sub-phase r2, the first reset module 12 is turned on, the second reset module 13 is turned off, and the voltage of the first reset signal is VREF2, VREF1≠VREF2.

[0082] In the second reset sub-stage r2, the first reset module 12 is turned on, the second reset module 13 is turned off, and the voltage VREF1 of the first reset signal is transmitted to the control end of the driving module 11 through the first reset module 12 to reset the control end of the driving module 11, and the second reset signal cannot be transmitted to the anode of the light-emitting element D through the second reset module 13.

[0083] The number of the second resetting sub-phases r2 included in the holding phase can be set according to actual conditions and is not limited here.

[0084] In this way, in the first reset sub-stage r1 and the second reset sub-stage r2 within the first refresh rate range, different voltages are used to reset the control end of the driving module 11, so that the voltage of the control end of the driving module 11 in the first reset sub-stage r1 is different from the voltage of the control end of the driving module 11 in the second reset sub-stage r2, which provides the possibility of reducing the display brightness of the display panel in the holding stage, and further provides the possibility of improving or solving the flicker problem of the display panel when switching from high frequency to low frequency or at low frequency, which is beneficial to improving the performance of the display panel.

[0085] In some embodiments, Figure 1 and Figure 2 As shown, the driving module 11 includes a P-type transistor, VREF1<VREF2.

[0086] It is understandable that, when the driving module 11 includes a P-type transistor, VREF1 and VREF2 may both be negative values.

[0087] In some examples, the P-type transistor may include a PMOS (Metal Oxide Semiconductor) transistor.

[0088] For example, taking the driving module 11 as a PMOS transistor, due to the hysteresis effect of the PMOS transistor and the leakage of the first reset module 12 and other modules connected to the gate of the PMOS transistor, the display brightness of the display panel in the first data writing stage is less than the display brightness in the holding stage, resulting in a flickering problem when the display panel switches from high frequency to low frequency or at low frequency. In the embodiment of the present application, by setting the voltage VREF1 of the first reset signal in the first reset sub-stage r1 to be less than the voltage VREF2 of the first reset signal in the second reset sub-stage r2, it is beneficial to reduce the display brightness of the display panel in the second reset sub-stage r2, reduce the display brightness difference of the display panel in the second reset sub-stage r2 and the first reset sub-stage r1, and then help reduce the display brightness of the display panel in the holding stage, reduce the display brightness difference of the display panel in the holding stage and the first data writing stage, so as to improve or solve the flickering problem of the display panel when switching from high frequency to low frequency or at low frequency, and improve the performance of the display panel.

[0089] In some examples, |VREF1-VREF2|=2V. In this way, it is helpful to further reduce the display brightness of the display panel in the second reset sub-stage r2, further reduce the display brightness difference between the display panel in the second reset sub-stage r2 and the first reset sub-stage r1, and further reduce the display brightness of the display panel in the holding stage, and further reduce the display brightness difference between the display panel in the holding stage and the first data writing stage, so as to further improve or solve the flicker problem of the display panel when switching from high frequency to low frequency or at low frequency, and improve the performance of the display panel.

[0090] In some examples, -4V<VREF2<0V, that is, VREF2 can be adjusted between 0V and -4V according to actual conditions.

[0091] Exemplarily, VREF1 = -4V, VREF2 = -2V.

[0092] Table 1 exemplarily illustrates the relationship between display brightness, VREF2 and the probability of flickering on the display panel.

[0093] Table 1

[0094]

[0095] Among them, 3.15% in Table 1 indicates the probability of flickering of the display panel when the display brightness is 30nit and VREF2 is -4V; 5.39% in Table 1 indicates the probability of flickering of the display panel when the display brightness is 50nit and VREF2 is -4V, and so on. It can be seen from Table 1 that under the same display brightness, the larger the VREF2, the smaller the probability of flickering of the display panel.

[0096] It is to be understood that the numerical values ​​in Table 1 are only used for illustration and are not intended to limit the present application.

[0097] In some embodiments, Figure 1 and Figure 3 As shown, the driving module 11 includes an N-type transistor, VREF1>VREF2.

[0098] It is understandable that, when the driving module 11 includes an N-type transistor, VREF1 and VREF2 may both be positive values.

[0099] In some examples, the N-type transistor may include an NMOS (Metal Oxide Semiconductor) transistor.

[0100] For example, taking the driving module 11 as an NMOS transistor, due to the hysteresis effect of the NMOS transistor and the leakage of the first reset module 12 and other modules connected to the gate of the NMOS transistor, the display brightness of the display panel in the first data writing stage is less than the display brightness in the holding stage, resulting in a flickering problem when the display panel switches from high frequency to low frequency or at low frequency. In the embodiment of the present application, by setting the voltage VREF1 of the first reset signal in the first reset sub-stage r1 to be greater than the voltage VREF2 of the first reset signal in the second reset sub-stage r2, it is beneficial to reduce the display brightness of the display panel in the second reset sub-stage r2, reduce the display brightness difference of the display panel in the second reset sub-stage r2 and the first reset sub-stage r1, and then help reduce the display brightness of the display panel in the holding stage, reduce the display brightness difference of the display panel in the holding stage and the first data writing stage, so as to improve or solve the flickering problem of the display panel when switching from high frequency to low frequency or at low frequency, and improve the performance of the display panel.

[0101] In some embodiments, the display panel has a first brightness level and a second brightness level, and the first brightness level is higher than the second brightness level. That is, the display brightness of the display panel at the first brightness level is greater than the display brightness at the second brightness level.

[0102] like Figure 4 As shown, at the first brightness level and the second reset sub-stage r2, the voltage of the first reset signal is VREF21;

[0103] At the second brightness level and the second reset sub-phase r2 , the voltage of the first reset signal is VREF22 , VREF21 ≠ VREF22 .

[0104] In this embodiment, for different brightness levels, different voltages of the first reset signal can be set in the second reset sub-stage r2 to achieve differentiated compensation for the second reset sub-stage r2 at different brightness levels, which is beneficial to improve or solve the flicker problem of the display panel when switching from high frequency to low frequency or at low frequency, thereby improving the performance of the display panel.

[0105] In some examples, VREF21 > VREF22 .

[0106] In this embodiment, VREF21 and VREF22 can both be negative values. At this time, the higher the brightness level of the display panel, the smaller the absolute value of the voltage of the first reset signal in the second reset sub-stage r2. This is conducive to achieving differentiated compensation for the second reset sub-stage r2 at different brightness levels, and thus is conducive to improving or solving the flicker problem of the display panel at different brightness levels, thereby improving the performance of the display panel.

[0107] In some embodiments, the first refresh rate range includes a first refresh rate and a second refresh rate, and the first refresh rate is greater than the second refresh rate;

[0108] like Figure 5 As shown, at the first refresh rate and the second reset sub-phase r2, the voltage of the first reset signal is VREF23;

[0109] At the second refresh rate and the second reset sub-phase r2 , the voltage of the second reset signal is VREF24 , and VREF23 ≠ VREF24 .

[0110] In this embodiment, for different refresh rates within the first refresh rate range, different voltages of the first reset signal can be set in the second reset sub-stage r2 to achieve differentiated compensation for the second reset sub-stage r2 at different refresh rates, which is beneficial to improve or solve the flicker problem of the display panel when switching from high frequency to low frequency or at low frequency, thereby improving the performance of the display panel.

[0111] In some examples, VREF23 < VREF24 .

[0112] In the first refresh rate range, as the refresh rate of the display panel decreases, the display brightness of the display panel increases, that is, the display brightness difference of the display panel in the first data writing stage and the holding stage increases. Taking the first refresh rate range including the first refresh rate and the second refresh rate, and the first refresh rate is greater than the second refresh rate as an example, the display brightness difference of the display panel in the first data writing stage and the holding stage at the first refresh rate is less than the display brightness difference of the display panel in the first data writing stage and the holding stage at the second refresh rate. By setting VREF23<VREF24, the display brightness of the display panel in the holding stage at the second refresh rate is reduced, and then the display brightness difference of the display panel in the first data writing stage and the holding stage at the second refresh rate is reduced, which is conducive to improving or solving the flickering problem of the display panel when switching from high frequency to low frequency or at low frequency, and improving the performance of the display panel.

[0113] In some embodiments, the display panel supports a third refresh rate, and the third refresh rate is greater than any refresh rate within the first refresh rate range;

[0114] At the third refresh rate, a picture refresh cycle of the pixel circuit includes a second data writing phase;

[0115] like Figure 6 As shown, the jth second data writing phase of the pixel circuit includes a third reset sub-phase r3, in which the first reset module 12 is turned on, the voltage of the first reset signal is VREF3, VREF3 = VREF1. j is a positive integer, and i≠j.

[0116] In this embodiment, by setting the voltage VREF3 of the first reset signal in the third reset sub-stage r3 at the third refresh rate equal to the voltage VREF1 of the first reset signal in the first reset sub-stage r1 within the first refresh rate range, the driving timing is simplified.

[0117] Exemplarily, the third refresh rate may be a maximum refresh rate that the display panel can support. At the third refresh rate, a picture refresh cycle of the pixel circuit may not include a holding phase.

[0118] In the second data writing phase, the data signal can be written into the control terminal of the driving module.

[0119] In the third reset sub-phase r3, the first reset module is turned on, and the voltage VREF3 of the first reset signal can be transmitted to the control end of the driving module through the first reset module to achieve the reset of the control end of the driving module.

[0120] It should be noted that in the third reset sub-stage r3, the second reset module can be turned on or off. That is to say, the control end of the driving module and the anode of the light-emitting element can both be reset in the first reset sub-stage r1, or the control end of the driving module can be reset in the third reset sub-stage r3, and the anode of the light-emitting element can be reset in other periods of the second data writing stage except the third reset sub-stage r3.

[0121] Understandably, Figures 2 to 5 Taking the example that the i-th screen refresh cycle includes three holding stages, and each holding stage includes the second reset sub-stage r2, in actual implementation, some holding stages in at least one holding stage may include the second reset sub-stage r2; for example, the second holding stage among the three holding stages includes the second reset sub-stage r2; for another example, the first holding stage and the second holding stage among the three holding stages both include the second reset sub-stage r2.

[0122] In some embodiments, the first reset line VREF and the second reset line INIT may be connected to different signal terminals. That is, the first reset signal on the first reset line VREF and the second reset signal on the second reset line INIT may be controlled independently of each other.

[0123] In some examples, a voltage of the second reset signal is different from at least one of a voltage of the first reset signal in the first reset sub-phase and a voltage of the first reset signal in the second reset sub-phase.

[0124] In some embodiments, Figure 1 and Figure 7 As shown, the pixel circuit 10 may further include a data writing module 14 , a threshold compensation module 15 , a light emitting control module 16 and a storage module 17 .

[0125] The data writing module 14 is connected to the first end of the driving module 11 and the data line Vdata.

[0126] Exemplarily, the control end of the data writing module 14 is connected to the third scan line S3, the first end of the data writing module 14 is connected to the data line Vdata, and the second end of the data writing module 14 is connected to the first end of the driving module 11. The data writing module 14 can be turned on or off under the control of the scan signal on the third scan line S3. When the scan signal on the third scan line S3 controls the data writing module 14 to be turned on, the data signal on the data line Vdata can be transmitted to the first end of the driving module 11 through the data writing module 14.

[0127] The threshold compensation module 15 is connected to the second end of the driving module 11 and the control end of the driving module 11 .

[0128] Exemplarily, the control end of the threshold compensation module 15 can be connected to the fourth scan line S4, the first end of the threshold compensation module 15 is connected to the control end of the driving module 11, and the second end of the threshold compensation module 15 is connected to the second end of the driving module 11. The threshold compensation module 15 can be turned on or off under the control of the scan signal on the fourth scan line S4. In the case where the scan signal on the fourth scan line S4 controls the threshold compensation module 15 to be turned on, the data signal at the second end of the driving module 11 can be transmitted to the control end of the driving module 11 through the threshold compensation module to achieve threshold compensation for the driving module 11.

[0129] In some examples, the third scan line S3 may be multiplexed as the fourth scan line S4.

[0130] The light emitting control module 16 is connected to the first power line ELVDD, the first end of the driving module 11 , the second end of the driving module 11 , the light emitting element D and the light emitting control line EM.

[0131] The first power line ELVDD may be a signal line providing a positive voltage signal.

[0132] The light control module 16 can be turned on or off under the control of the light control signal on the light control line EM. When the light control module 16 is turned on, the driving module 11 can provide a corresponding driving current to the light emitting element D according to the received data signal, so that the light emitting element D emits light.

[0133] In some examples, the light control module 16 includes a first light control module 161 and a second light control module 162 ;

[0134] The first light emitting control module 161 is connected to the first power line ELVDD, the first end of the driving module 11 and the light emitting control line EM;

[0135] The second light emitting control module 162 is connected to the second end of the driving module 11 , the first electrode of the light emitting element D and the light emitting control line EM.

[0136] Exemplarily, the control end of the first light emitting control module 161 and the control end of the second light emitting control module 162 may both be connected to the light emitting control line EM, the first end of the first light emitting control module 161 is connected to the first power line ELVDD, the second end of the first light emitting control module 161 is connected to the first end of the driving module 11, the first end of the second light emitting control module 162 is connected to the second end of the driving module 11, and the second end of the second light emitting control module 162 is connected to the first electrode of the light emitting element D. The first light emitting control module 161 and the second light emitting control module 162 may both be turned on or off under the control of the light emitting control signal on the light emitting control line EM. When the first light emitting control module 161 and the second light emitting control module 162 are both turned on, the driving current generated by the driving module 11 may be transmitted to the light emitting element D to drive the light emitting element D to emit light.

[0137] The storage module 17 is connected to the first power line ELVDD and the control terminal of the driving module 11 .

[0138] Exemplarily, a first end of the storage module 17 is connected to the first power line ELVDD, and a second end of the storage module 17 is connected to the control end of the driving module 11. The storage module 17 can be used to maintain the potential of the control end of the driving module 11.

[0139] In some examples, such as Figure 7 As shown, the driving module 11 includes a first transistor T1, the first reset module 12 includes a second transistor T2, the second reset module 13 includes a third transistor T3, the data writing module 14 includes a fourth transistor T4, the threshold compensation module 15 includes a fifth transistor T5, the light emitting control module 16 includes a sixth transistor T6 and a seventh transistor T7, and the storage module 17 includes a storage capacitor Cst.

[0140] A gate of the second transistor T2 may be connected to the first scan line S1 , a first electrode of the second transistor T2 may be connected to the first reset line VREF, and a second electrode of the second transistor T2 may be connected to the gate of the first transistor T1 .

[0141] A gate electrode of the third transistor T3 may be connected to the second scan line S2 , a first electrode of the third transistor T3 may be connected to the second reset line INIT, and a second electrode of the third transistor T3 may be connected to the anode electrode of the light emitting element D.

[0142] A gate of the fourth transistor T4 may be connected to the third scan line S3 , a first electrode of the fourth transistor T4 may be connected to the data line Vdata, and a second electrode of the fourth transistor T4 may be connected to the first electrode of the first transistor T1 .

[0143] A gate of the fifth transistor T5 may be connected to the fourth scan line S4 , a first electrode of the fifth transistor T5 may be connected to the gate of the first transistor T1 , and a second electrode of the fifth transistor T5 may be connected to the second electrode of the first transistor T1 .

[0144] A gate of the sixth transistor T6 may be connected to the light emitting control line EM, a first electrode of the sixth transistor T6 may be connected to the first power line ELVDD, and a second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1.

[0145] A gate of the seventh transistor T7 can be connected to the light emitting control line EM, a first electrode of the seventh transistor T7 can be connected to the second electrode of the first transistor T1 , and a second electrode of the seventh transistor T7 can be connected to the anode of the light emitting element D.

[0146] A first electrode of the storage capacitor Cst may be connected to the first power line ELVDD, and a second electrode of the storage capacitor Cst may be connected to the gate of the first transistor T1.

[0147] Both the first data writing phase and the second data writing phase may include a data writing sub-phase w. In the data writing sub-phase w, the data writing module 14 and the threshold compensation module 15 are both turned on, and the data signal on the data line Vdata can be written to the control end of the driving module 11 through the data writing module 14 and the threshold compensation module 15. The holding phase does not include the data writing sub-phase w.

[0148] The first data writing stage, the second data writing stage and the holding stage may all include a light-emitting sub-stage g. In the light-emitting sub-stage g, the light-emitting control signal on the light-emitting control line EM is at the on-level, the light-emitting control module 16 is turned on, and the driving current generated by the driving module 11 is transmitted to the light-emitting element D to make the light-emitting element D emit light.

[0149] Based on the same inventive concept as the above-mentioned display panel, an embodiment of the present application further provides a method for driving a display panel. The method for driving a display panel provided by the embodiment of the present application is introduced below in conjunction with the accompanying drawings.

[0150] The driving method of the display panel provided in the embodiment of the present application can be applied to the display panel in the above embodiment.

[0151] A picture refresh cycle of the pixel circuit includes a first data writing phase and at least one holding phase;

[0152] like Figure 8 As shown, the display panel driving method provided in the embodiment of the present application includes S810 to S820.

[0153] S810, the first data writing phase includes a first reset sub-phase, in which the first reset module is controlled to be turned on, and the voltage of the first reset signal is controlled to be VREF1;

[0154] S820, the holding phase includes a second reset sub-phase. In the second reset sub-phase, the first reset module is controlled to be turned on, the second reset module is controlled to be turned off, and the voltage of the first reset signal is controlled to be VREF2, VREF1≠VREF2.

[0155] According to the driving method provided in the embodiment of the present application, in the first reset sub-stage and the second reset sub-stage within the first refresh rate range, different voltages are used to reset the control end of the driving module, respectively. In this way, the voltage of the control end of the driving module in the first reset sub-stage is different from the voltage of the control end of the driving module in the second reset sub-stage, which provides the possibility of reducing the display brightness of the display panel in the holding stage, and further provides the possibility of improving or solving the flicker problem of the display panel when switching from high frequency to low frequency or at low frequency, which is beneficial to improving the performance of the display panel.

[0156] In some embodiments, the display panel has a first brightness level and a second brightness level, the first brightness level being higher than the second brightness level;

[0157] The driving method also includes:

[0158] At the first brightness level and the second reset sub-stage, the voltage of the first reset signal is controlled to be VREF21;

[0159] At the second brightness level and the second reset sub-phase, the voltage of the first reset signal is controlled to be VREF22, VREF21≠VREF22.

[0160] In some embodiments, the first refresh rate range includes a first refresh rate and a second refresh rate, and the first refresh rate is greater than the second refresh rate;

[0161] The driving method also includes:

[0162] In the first refresh rate and the second reset sub-phase, the voltage of the first reset signal is controlled to be VREF23;

[0163] In the second refresh rate and the second reset sub-phase, the voltage of the second reset signal is controlled to be VREF24, VREF23≠VREF24.

[0164] In some embodiments, the display panel supports a third refresh rate, and the third refresh rate is greater than any refresh rate within the first refresh rate range;

[0165] At the third refresh rate, a picture refresh cycle of the pixel circuit includes a second data writing phase;

[0166] The driving method also includes:

[0167] The second data writing phase includes a third reset sub-phase. In the third reset sub-phase, the first reset module is controlled to be turned on, and the voltage of the first reset signal is controlled to be VREF3, VREF3=VREF1.

[0168] The driving method of the display panel provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0169] The present application also provides a display device, including the display panel 100 provided in the present application. Fig. 9 , Fig. 9 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig. 9 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig. 9The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0170] It should be noted that the transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the on-level is a high level and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first pole and the second pole are connected, and when the gate potential of the N-type transistor is a low level, the first pole and the second pole are disconnected. For a P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first pole and the second pole are connected, and when the gate potential of the P-type transistor is a high level, the first pole and the second pole are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / shut down the transistor.

[0171] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: comprising a light emitting element and a plurality of pixel circuits; Wherein, the pixel circuit includes a driving module, a first reset module and a second reset module; The first reset module is connected to the control end of the driving module and the first reset line, and is used to provide a first reset signal on the first reset line to the control end of the driving module; The second reset module is connected to the first electrode of the light emitting element and the second reset line, and is used to provide a second reset signal on the second reset line to the first electrode of the light emitting element; Within the first refresh rate range, a picture refresh cycle of the pixel circuit includes a first data writing phase and at least one holding phase; The first data writing phase includes a first reset sub-phase. In the first reset sub-phase, the first reset module is turned on, and the voltage of the first reset signal is VREF1; The holding phase includes a second reset sub-phase. In the second reset sub-phase, the first reset module is turned on, the second reset module is turned off, and the voltage of the first reset signal is VREF2, VREF1≠VREF2.

2. The display panel according to claim 1, characterized in that: The driving module includes a P-type transistor, VREF1<VREF2; Preferably, -4V<VREF2<0V.

3. The display panel according to claim 1, characterized in that: The driving transistor includes an N-type transistor, VREF1>VREF2.

4. The display panel according to claim 1, characterized in that: The display panel has a first brightness level and a second brightness level, the first brightness level being higher than the second brightness level; At the first brightness level and the second reset sub-phase, the voltage of the first reset signal is VREF21; At the second brightness level and the second reset sub-phase, the voltage of the first reset signal is VREF22, VREF21≠VREF22; Preferably, VREF21>VREF22.

5. The display panel according to claim 1, characterized in that: The first refresh rate range includes a first refresh rate and a second refresh rate, and the first refresh rate is greater than the second refresh rate; At the first refresh rate and the second reset sub-phase, the voltage of the first reset signal is VREF23; At the second refresh rate and the second reset sub-phase, the voltage of the second reset signal is VREF24, VREF23≠VREF24; Preferably, VREF23<VREF24.

6. The display panel according to claim 1, characterized in that: The display panel supports a third refresh rate, and the third refresh rate is greater than any refresh rate within the first refresh rate range; At the third refresh rate, a picture refresh cycle of the pixel circuit includes a second data writing phase; The second data writing phase includes a third reset sub-phase. In the third reset sub-phase, the first reset module is turned on, and the voltage of the first reset signal is VREF3, VREF3=VREF1.

7. The display panel according to claim 1, characterized in that: The first reset line and the second reset line are connected to different signal terminals; Preferably, a voltage of the second reset signal is different from at least one of a voltage of the first reset signal in the first reset sub-stage and a voltage of the first reset signal in the second reset sub-stage.

8. The display panel according to claim 1, characterized in that: The pixel circuit also includes a data writing module, a threshold compensation module, a light emitting control module and a storage module; The data writing module is connected to the first end of the driving module and the data line; The threshold compensation module is connected to the second end of the driving module and the control end of the driving module; The light emitting control module is connected to the first power line, the first end of the driving module, the second end of the driving module, the light emitting element and the light emitting control line; The storage module is connected to the first power line and the control end of the driving module; Preferably, the light emitting control module comprises a first light emitting control module and a second light emitting control module; The first light emitting control module is connected to the first power line, the first end of the driving module and the light emitting control line; The second light emitting control module is connected to the second end of the driving module, the first pole of the light emitting element and the light emitting control line; Preferably, the driving module includes a first transistor, the first reset module includes a second transistor, the second reset module includes a third transistor, the data writing module includes a fourth transistor, the threshold compensation module includes a fifth transistor, the light emitting control module includes a sixth transistor and a seventh transistor, and the storage module includes a storage capacitor.

9. A method for driving a display panel, characterized in that: Applicable to a display panel as claimed in any one of claims 1 to 8; A picture refresh cycle of the pixel circuit includes a first data writing phase and at least one holding phase; The method comprises: The first data writing phase includes a first reset sub-phase, in which the first reset module is controlled to be turned on, and the voltage of the first reset signal is controlled to be VREF1; The holding stage includes a second reset sub-stage. In the second reset sub-stage, the first reset module is controlled to be turned on, the second reset module is controlled to be turned off, and the voltage of the first reset signal is controlled to be VREF2, VREF1≠VREF2.

10. A display device, characterized in that: Comprising the display panel according to any one of claims 1 to 8.

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