Display substrate and display device

Abstract

A base substrate (111) of a display substrate (110) comprises a display area (1111), a plurality of pixel units (112) are located in the display area (1111), the pixel unit (112) comprises a pixel circuit (1121), and the pixel circuit (1121) comprises a first pixel circuit (1121a) and a second pixel circuit (1121b) adjacent to each other along a first direction; an initialization signal line (113) extends along the first direction and provides initialization to the first pixel circuit (1121a) and the second pixel circuit (1121b). The invention relates to a method for manufacturing a light emitting device for displaying a first pixel circuit (1121a) and a second pixel circuit (1121b). The method comprises the following steps: providing a first control signal line (114A) extending in a first direction and providing a gate signal to the first pixel circuit (1121a) and the second pixel circuit (1121b). The first control signal line (114A) extends in a first direction and provides a gate signal to the first pixel circuit (1121a) and the second pixel circuit (1121b). The light emitting control signal line (115) extends in a first direction and provides a light emitting control signal to the first pixel circuit (1121a) and the second pixel circuit (1121b). The initialization signal line (113) is located on a side of the light emitting control signal line (115) away from the first control signal line (114A), extends in the first direction, and is arranged in intervals and segments.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display substrate and a display device. Background Art

[0002] In the related art, users' demands for mobile devices are becoming increasingly stringent, with lighter, thinner, brighter, and more energy-efficient devices still the most popular requirements. However, organic light-emitting diode (OLED) display panels, with their self-luminous properties, can achieve display functions without a backlight, making them the preferred display panel for lighter and thinner displays. Furthermore, the current market demand for display panels is no longer limited to flat surfaces. Shaped, curved, and transparent displays are all expected to make OLED display panels the most widely used display technology in the future. In particular, active-matrix organic light-emitting diode (AMOLED) display panels require relatively complex pixel compensation circuits to prevent display unevenness caused by process-related variations in the Vth of the drive transistors. Achieving overall circuit performance within a limited space has become a technical challenge. Summary of the Invention

[0003] Embodiments of the present application provide a display substrate and a display device.

[0004] An embodiment of the present application provides a display substrate, comprising a base substrate, a plurality of pixel units, an initialization signal line, a first control signal line and a light-emitting control signal line; the base substrate comprises a display area, a plurality of pixel units are located in the display area, the pixel units comprise pixel circuits, the pixel circuits comprise a first pixel circuit and a second pixel circuit adjacent to each other along a first direction; the initialization signal line extends along the first direction and is configured to provide an initialization signal to the first pixel circuit and the second pixel circuit; the first control signal line extends along the first direction and is configured to provide a gate signal to the first pixel circuit and the second pixel circuit; the light-emitting control signal line extends along the first direction and is configured to provide a light-emitting control signal to the first pixel circuit and the second pixel circuit; wherein the initialization signal line is located on a side of the light-emitting control signal line away from the first control signal line, extends along the first direction and is arranged in intervals and segments.

[0005] In some embodiments, the display substrate further includes an initialization bus located on a side of the initialization signal line away from the base substrate, and the initialization bus is electrically connected to the initialization signal line.

[0006] In some embodiments, the initialization bus includes multiple main parts, multiple connecting parts and multiple branches; the multiple main parts extend along the first direction and are spaced apart along the second direction, and are configured to provide the initialization signal to the corresponding multiple initialization signal lines extending along the first direction and spaced apart in segments; the multiple connecting parts extend along the second direction to connect two adjacent main parts; the multiple branches are connected to at least one of the two adjacent main parts, the multiple connecting parts and the multiple branches are alternately spaced apart along the first direction, and the multiple branches are configured to provide the initialization signal to the corresponding multiple initialization signal lines extending along the first direction and spaced apart in segments between the two adjacent main parts.

[0007] In some embodiments, the display substrate further includes a second control signal line located on a side of the initialization signal line away from the light-emitting control signal line, the second control signal line extending along the first direction and configured to provide a reset control signal to the first pixel circuit and the second pixel circuit.

[0008] In some embodiments, the display substrate includes a plurality of first power lines extending along the second direction and spaced apart along the first direction, and the plurality of first power lines are configured to provide a first power signal to the pixel circuit.

[0009] In some embodiments, the pixel circuit structure includes a light-emitting control transistor; the gate of the light-emitting control transistor is connected to the light-emitting control signal line, and the light-emitting control transistor includes a first electrode and a second electrode, and the second electrode and the first electrode of the light-emitting control transistor are respectively located on the first side and the second side opposite to the light-emitting control signal line.

[0010] In some embodiments, the pixel circuit structure includes a driving transistor located on the second side of the light-emitting control signal line; the driving transistor includes a first electrode and a second electrode, and the first electrode of the driving transistor is connected to the first power line; the second electrode of the driving transistor is connected to the first electrode of the light-emitting control transistor.

[0011] In some embodiments, the pixel circuit includes a first reset transistor located between the second control signal line and the light emitting control signal line; the second control signal line is connected to the gate of the first reset transistor, the first reset transistor includes a first electrode and a second electrode, the first electrode of the first reset transistor is connected to the gate of the driving transistor, and the second electrode of the first reset transistor is connected to the initialization signal line.

[0012] In some embodiments, the display substrate includes a plurality of data lines extending along the second direction and spaced apart along the first direction, and the data lines are configured to provide data signals to the pixel circuits.

[0013] In some embodiments, the pixel circuit includes a storage capacitor, a data write transistor and a first compensation transistor; the first control signal line is respectively connected to the gate of the data write transistor and the gate of the first compensation transistor; the data write transistor includes a first pole and a second pole, and the first pole of the data write transistor is connected to the data line; the storage capacitor includes a first pole and a second pole, the first pole of the storage capacitor is connected to the second pole of the data write transistor, and the second pole of the storage capacitor is connected to the gate of the driving transistor; the first compensation transistor includes a first pole and a second pole, the first pole of the first compensation transistor is connected to the gate of the driving transistor, and the second pole of the first compensation transistor is connected to the second pole of the driving transistor.

[0014] In some embodiments, the initialization signal line and the first electrode of the storage capacitor are arranged in the same layer and spaced apart.

[0015] In some embodiments, the data writing transistor and the first compensation transistor are located on a side of the first control signal line close to the light emission control signal line.

[0016] In some embodiments, the pixel circuit includes a second compensation transistor, the light-emitting control signal line is connected to the gate of the second compensation transistor, the second compensation transistor includes a first electrode located on the first side of the light-emitting control signal line, and the first electrode of the second compensation transistor is connected to the first electrode of the first reset transistor.

[0017] In some embodiments, the display substrate includes a first connecting electrode extending along the second direction, the first connecting electrode connecting the gate of the driving transistor, the first electrode of the first compensation transistor, and the first electrode of the second compensation transistor.

[0018] In some embodiments, the pixel circuit includes a second reset transistor and a third reset transistor located between the second control signal line and the light-emitting control signal line; the second control signal line is connected to the gate of the second reset transistor, and the light-emitting control signal line is connected to the gate of the third reset transistor; the second reset transistor includes a first electrode and a second electrode, the first electrode of the second reset transistor is connected to the second electrode of the data write transistor, and the second electrode of the second reset transistor is connected to the initialization signal line; the third reset transistor includes a first electrode and a second electrode, the first electrode of the third reset transistor is connected to the second electrode of the data write transistor, and the second electrode of the third reset transistor is connected to the initialization signal line.

[0019] In some embodiments, the display substrate includes a second connecting electrode extending along the second direction, and the second connecting electrode connects the first electrode of the third reset transistor and the second electrode of the data writing transistor.

[0020] In some embodiments, the first connecting electrode, the second connecting electrode, the data line, and the first power line are disposed on the same layer.

[0021] In some embodiments, the display substrate further includes a light-emitting element, the second electrode of the light-emitting control transistor is connected to the first electrode of the light-emitting element, and the light-emitting control bus is spaced apart from the first electrode of the light-emitting element in the same layer.

[0022] In some embodiments, the pixel circuit includes a fourth reset transistor located between the second control signal line and the light-emitting control signal line; the second control signal line is connected to the gate of the fourth reset transistor, the fourth reset transistor includes a first electrode and a second electrode, the first electrode of the fourth reset transistor is connected to the first electrode of the light-emitting element, and the second electrode of the fourth reset transistor is connected to the initialization signal line.

[0023] An embodiment of the present application further provides a display device, comprising the display substrate described in any of the above embodiments.

[0024] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0026] Figure 1 It is a schematic structural diagram of an electronic device according to an embodiment of the present application.

[0027] Figure 2 It is a schematic diagram of the planar structure of the display substrate according to the embodiment of the present application.

[0028] Figure 3 2 is a circuit schematic diagram of a pixel circuit according to an embodiment of the present application.

[0029] Figure 4 It is a schematic cross-sectional view of a display substrate according to an embodiment of the present application.

[0030] Figure 5 It is a partial top view schematic diagram of a display substrate according to an embodiment of the present application.

[0031] Figure 6 Schematic diagram of a semiconductor pattern layer of a display substrate according to an embodiment of the present application.

[0032] Figure 7 Schematic diagram of the first conductive pattern layer of the display substrate according to an embodiment of the present application.

[0033] Figure 8 It is a schematic structural diagram of a display substrate according to an embodiment of the present application after the semiconductor pattern layer is subjected to a conductorization process using a self-alignment process.

[0034] Figure 9 Schematic diagram of the second conductive pattern layer of the display substrate according to an embodiment of the present application.

[0035] Figure 10 Schematic diagram of the third conductive pattern layer of the display substrate according to an embodiment of the present application.

[0036] Figure 11 Schematic diagram of the anode circuit pattern layer of the display substrate according to an embodiment of the present application.

[0037] Figure 12 Schematic diagram of a cathode circuit pattern layer of a display substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application.

[0039] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0040] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0041] With the improvement of screen pixel density (Pixels Per Inch, PPI), the resolution of organic light emitting diode (OLED) display devices is getting higher and higher, which makes the pixel size of the backplane circuit of the display device gradually reduce. The design space of a single pixel unit is getting smaller and smaller. For example, in an organic light emitting diode display panel, the pixel circuit structure of a single pixel unit may include multiple transistors, such as 7 or more transistors. For example, the pixel circuit structure includes a 9T1C pixel circuit structure, but is not limited to this. As the width of the circuit traces in the substrate circuit and the line spacing of the circuit traces are reduced, the difficulty of circuit layout also increases accordingly. The embodiments of the present disclosure are described using the 9T1C pixel circuit structure as an example.

[0042] Please also refer to Figures 1 to 5In one embodiment of the present application, a display substrate 110 is provided, including a base substrate 111, a plurality of pixel units 112, an initialization signal line 113, a first control signal line 114A, and a light-emission control signal line 115. The base substrate 111 includes a display area 1111, wherein the plurality of pixel units 112 are located in the display area 1111 and arranged in a matrix. Each pixel unit 112 includes a pixel circuit 1121, wherein the pixel circuit 1121 includes a first pixel circuit 1121a and a second pixel circuit 1121b adjacent to each other along a first direction. The initialization signal line 113 extends along the first direction and is configured to provide an initialization signal Vinit to the first pixel circuit 1121a and the second pixel circuit 1121b. The first control signal line 114A extends along the first direction and is configured to provide a gate signal Sn to the first pixel circuit 1121a and the second pixel circuit 1121b. The light-emission control signal line 115 extends along the first direction and is configured to provide a light-emission control signal EM to the first pixel circuit 1121a and the second pixel circuit 1121b. The initialization signal line 113 is located on a side of the light emitting control signal line 115 away from the first control signal line 114A, extends along the first direction, and is arranged in intervals and segments.

[0043] The display substrate 110 provided in the embodiment of the present application can be applied to the display device 100 in the embodiment of the present application. That is, the display device 100 in the embodiment of the present application can display images through the display substrate 110 in the embodiment of the present application.

[0044] In the display substrate 110 and the display device 100 of the present application, the initialization signal line 113 is designed to be arranged in segments and intervals along the first direction, which reduces the space occupied by the initialization signal line 113 in the substrate, is conducive to optimizing the wiring layout of the display substrate 110 within a limited space, and meets more performance requirements.

[0045] In some embodiments, the display device 100 may be a smart phone, a tablet computer, a smart bracelet, a virtual reality device, a personal data terminal, a laptop computer, or any other display device 100 capable of displaying an image, but is not limited thereto. Figure 1 In the illustrated embodiment, the display device 100 is a smart phone.

[0046] In some embodiments, the display substrate 110 includes a plurality of first power lines 116A, which extend along the second direction and are spaced apart along the first direction. The plurality of first power lines 116A are configured to provide a first power signal ELVDD to the pixel circuit 1121. Specifically, the first power signal ELVDD is a constant high-level voltage signal.

[0047] In some embodiments, the display substrate 110 includes a plurality of data lines 117 , which extend along the second direction and are spaced apart along the first direction. The data lines 117 are configured to provide data signals to the pixel circuits 1121 .

[0048] When the display substrate 110 is displaying, a pixel may include multiple pixel units 112. Furthermore, a pixel may include multiple pixel units 112 that emit light of different colors. For example, a pixel includes a pixel unit 112 that emits red light, a pixel unit 112 that emits green light, and a pixel unit 112 that emits blue light, but the present invention is not limited thereto. The number of pixel units 112 included in a pixel and the light emission conditions of each pixel unit 112 can be determined as needed. The display device 100 can generate a corresponding data signal based on each pixel value in the image and provide the data signal to the corresponding pixel circuit 1121 via the data line 117.

[0049] In some embodiments, the display substrate 110 also includes a second control signal line 114B located on a side of the initialization signal line 113 away from the light-emitting control signal line 115, the second control signal line extends along the first direction and is configured to provide a reset control signal RESET to the first pixel circuit 1121a and the second pixel circuit 1121b.

[0050] Furthermore, the display substrate 110 includes a third pixel circuit 1121c and a fourth pixel circuit 1121d. The third pixel circuit 1121c and the fourth pixel circuit 1121d are adjacent to each other along a first direction. The first pixel circuit 1121a and the third pixel circuit 1121c are adjacent to each other along a second direction. The second pixel circuit 1121b and the fourth pixel circuit 1121d are adjacent to each other along the second direction. The second control signal line 114B may also be configured to provide a gate signal Sn to the third pixel circuit 1121c and the fourth pixel circuit 1121d. Specifically, the second control signal line 114B may provide a gate signal Sn to the third pixel circuit 1121c and the fourth pixel circuit 1121d while providing a reset control signal RESET to the first pixel circuit 1121a and the second pixel circuit 1121b.

[0051] In some embodiments, the display substrate 110 includes a light emitting element 118, and the pixel circuit 1121 is connected to the light emitting element 118 to drive the light emitting element 118 to emit light. The display substrate 110 may include a second power line 119, which is configured to provide a second power signal ELVSS to the light emitting element 118.

[0052] Specifically, the second power signal ELVSS is a constant low-level voltage signal. The first power signal ELVDD is greater than the second power signal ELVSS. It should be noted that the initialization signal Vinit is a constant voltage signal whose magnitude can, for example, be between the first power signal ELVDD and the second power signal ELVSS, but is not limited thereto. For example, the initialization signal Vinit can be less than or equal to the second power signal ELVSS.

[0053] In some embodiments, the display substrate 110 may include a plurality of third power lines 116B extending along the first direction, and the plurality of third power lines 116B are spaced apart along the second direction. The third power lines 116B may be connected to the first power lines 116A and configured to provide the first power signal ELVDD to the pixel circuit 1121.

[0054] In this way, the staggered arrangement of the first power lines 116A and the third power lines 116B extending in different directions is beneficial for maintaining the stability of the first power signal ELVDD provided by the display substrate 110 as a whole to the pixel circuit 1121 .

[0055] In some embodiments, the pixel circuit 1121 includes a data writing transistor T1, a first compensation transistor T2, a driving transistor T3, a first reset transistor T4, a second reset transistor T5, a third reset transistor T6, a light emitting control transistor T7, a fourth reset transistor T8, a second compensation transistor T9 and a storage capacitor C1.

[0056] It can be understood that during the reset phase, the pixel circuit 1121 can initialize the driving transistor T3, the storage capacitor C1, and the light-emitting element 118 through the initialization signal Vinit under the action of the reset control signal RESET, thereby ensuring that the state of the pixel circuit 1121 remains consistent when each frame of the display image is refreshed, ensuring that the display device 100 can display normally. During the data writing phase, the pixel circuit 1121 can write the data signal provided by the data signal line into the storage capacitor C1 for storage under the action of the gate signal Sn, and compensate for the threshold voltage of the third transistor T3. During the light control phase, the pixel circuit 1121 can convert the data signal into a current signal under the action of the light control signal EM to drive the light-emitting element 118 to emit light, thereby realizing image display.

[0057] The display device 100 provided in the embodiment of the present application further includes: a data driving circuit 120 and a scan driving circuit 130. The data driving circuit 120 is configured to provide a data signal to the pixel unit 112 according to the instruction of the control circuit; the scan driving circuit 130 is configured to provide a light emitting control signal EM, a gate signal Sn, a reset control signal RESET, an initialization signal Vinit, and other signals to the pixel unit 112 according to the instruction of the control circuit.

[0058] exist Figure 2 In the illustrated embodiment, the display substrate 110 includes a non-display area 1112. The data driver circuit 120 and the scan driver circuit 130 may be disposed in the non-display area of ​​the display substrate 110, but the present invention is not limited thereto. For example, the data driver circuit 120 and the scan driver circuit 130 may be disposed in a circuit board, such as a printed circuit board and / or a flexible circuit board, that connects the electronic device 100 to the display substrate 110.

[0059] In some embodiments, the control circuit of the display substrate 110 includes an external integrated circuit (IC), but is not limited thereto. In some embodiments, the scan driver circuit 130 is a GOA (Gate On Array) structure mounted on the display panel, or a driver chip (IC) structure bonded to the display panel. For example, different driver circuits can also be used to provide the light-emitting control signal EM and the gate signal Sn respectively. In some embodiments, the display device 100 further includes a power supply (not shown in the figure) to provide the above-mentioned power supply signal, which can be a voltage source or a current source as needed. The power supply is configured to provide the first power supply signal ELVDD, the second power supply signal ELVSS, and the initialization signal Vinit, etc. to the pixel unit 112 through the first power supply line 116A, the second power supply line 119, and the initialization signal line 113, respectively.

[0060] In some embodiments, the light emitting control signal line 115 is connected to the gate T70 of the light emitting control transistor T7 , wherein a portion of the light emitting control signal line 115 serves as the gate T70 of the light emitting control transistor T7 .

[0061] Furthermore, the light emission control transistor T7 includes a first electrode T71 and a second electrode T72 . The second electrode T72 and the first electrode T71 of the light emission control transistor T7 are located on a first side and a second side opposite to the light emission control signal line 115 , respectively.

[0062] In some embodiments, the driving transistor T3 is located on the second side of the light-emitting control signal line 115, and the driving transistor T3 includes a first electrode T31 and a second electrode T32. The first electrode T31 of the driving transistor T3 is connected to the first power line 116A, and the second electrode T32 of the driving transistor T3 is connected to the first electrode T71 of the light-emitting control transistor T7.

[0063] In some embodiments, the first reset transistor T4 is located between the second control signal line 114B and the light-emitting control signal line 115. The second control signal line 114B is connected to the gate T40 of the first reset transistor T4. The first reset transistor T4 includes a first electrode T41 and a second electrode T42. The first electrode T41 of the first reset transistor T4 is connected to the gate T30 of the driving transistor T3, and the second electrode T42 of the first reset transistor T4 is connected to the initialization signal line 113.

[0064] Specifically, a portion of the second control signal line 114B serves as the gate T40 of the first reset transistor T4. The first control signal line 114A can provide a reset control signal RESET to the first reset transistor T4. Under the action of the reset control signal RESET, the first reset transistor T4 provides an initialization signal Vinit to the gate T30 of the driving transistor T3 for initialization.

[0065] In some embodiments, the first control signal line 114A is connected to the gate T10 of the data writing transistor T1 and the gate T20 of the first compensation transistor T2 , respectively.

[0066] Specifically, a portion of the first control signal line 114A may serve as the gate T10 of the data writing transistor T1 ; another portion of the first control signal line 114A may serve as the gate T20 of the first compensation transistor T2 .

[0067] Furthermore, in some examples, the data write transistor T1 includes a first electrode T11 and a second electrode T12, the first electrode T11 of the data write transistor T1 is connected to the data line 117, the storage capacitor C1 includes a first electrode C11 and a second electrode C12, the first electrode C11 of the storage capacitor C1 is connected to the second electrode T12 of the data write transistor T1, and the second electrode C12 of the storage capacitor C1 is connected to the gate T30 of the driving transistor T3.

[0068] Specifically, the second electrode C12 of the storage capacitor C1 can serve as the gate T30 of the driving transistor T3. The first control signal line 114A can provide a gate signal Sn to the data writing transistor T1. Under the action of the gate signal Sn, the data writing transistor T1 writes the data signal provided by the data line 117 into the storage capacitor C1.

[0069] In one example, the storage capacitor C1 is located between the first control signal line 114A and the light emitting control signal line 115 .

[0070] Furthermore, the first compensation transistor T2 includes a first electrode T21 and a second electrode T22 . The first electrode T21 of the first compensation transistor T2 is connected to the gate T30 of the driving transistor T3 , and the second electrode T22 of the first compensation transistor T2 is connected to the second electrode T32 of the driving transistor T3 .

[0071] In this way, the first control signal line 114A provides a gate signal Sn to the first compensation transistor T2. Under the action of the gate signal Sn, the first compensation transistor T2 can connect the gate T30 and the second electrode T32 of the driving transistor T3, thereby compensating the threshold voltage of the driving transistor T3 when the data signal is written.

[0072] In some embodiments, the data writing transistor T1 and the first compensation transistor T2 are located on a side of the first control signal line 114A close to the light emission control signal line 115 .

[0073] That is, the first control signal line 114A is configured to provide a gate signal Sn to the first pixel circuit 1121a and the second pixel circuit 1121b on one side of the first control signal line 114A. It should be noted that the first control signal line 114A can also be configured to provide a reset control signal RESET to other pixel circuits 1121 on the other side of the first control signal line 114A opposite the first pixel circuit 1121a and the second pixel circuit 1121b, which is not specifically limited here.

[0074] In some embodiments, the light emitting control signal line 115 is connected to the gate T90 of the second compensation transistor T9. The second compensation transistor T9 includes a first electrode T91 located on a first side of the light emitting control signal line 115. The first electrode T91 of the second compensation transistor T9 is connected to the first electrode T41 of the first reset transistor T4.

[0075] Specifically, a portion of the light emission control signal line 115 can serve as the gate T90 of the second compensation transistor T9 .

[0076] During the data writing process, the pixel circuit 1121 short-circuits the first compensation transistor T2 into a diode connection to compensate for the threshold voltage of the driving transistor T3. An equivalent capacitance exists between the gate and drain of the short-circuited first compensation transistor T2. When the storage capacitor C1 is fully charged, the potential of the terminal connected to the gate of the driving transistor T3 is the threshold voltage of the driving transistor T1. During the process of turning off the short-circuited first compensation transistor T2, the charge stored in the equivalent capacitance of the first compensation transistor T2 is injected into the storage capacitor C1 due to changes in bias and capacitance, which can easily cause errors in the threshold voltage signal maintained on the storage capacitor C1. Thus, by providing the second compensation transistor T9, after the data writing phase ends, since the second compensation transistor T9 has an equivalent capacitance, when the first compensation transistor T2 is turned off, the charge released by the equivalent capacitance between the gate and drain of the first compensation transistor T2 can be fully or partially absorbed by the equivalent capacitance of the second compensation transistor T9, thereby achieving the purpose of maintaining an accurate and stable threshold voltage.

[0077] It should be noted that the second electrode (not shown) of the second compensation transistor T9 located on the second side of the light emitting control signal line 115 can be suspended.

[0078] In some embodiments, the display substrate 110 includes a first connection electrode 11211 extending along the second direction, and the first connection electrode 11211 connects the gate T30 of the driving transistor T3 (the second electrode C12 of the storage capacitor C1), the first electrode T21 of the first compensation transistor T2, and the first electrode T91 of the second compensation transistor T9.

[0079] Specifically, the display substrate 110 includes a multi-layer structure. The various traces in the pixel circuit 1121 can be arranged on different layers, and the electrodes of different components can also be located at different positions on the same layer or different layers. Thus, a first connection electrode 11211 can be provided on a layer of the substrate to electrically connect the gate electrode T30 of the driving transistor T3, the first electrode T21 of the first compensation transistor T2, and the first electrode T91 of the second compensation transistor T9, which are located at different layers or at different positions. The first connection electrode 11211 can be connected to the corresponding components through vias provided in each layer of the substrate.

[0080] In one example, a plate via is formed on the first electrode C11 of the storage capacitor C1 , and the first connection electrode 11211 can be connected to the second electrode C12 of the storage capacitor C1 , ie, the gate T30 of the driving transistor T3 , through the plate via.

[0081] In some embodiments, the second reset transistor T5 and the third reset transistor T6 are located between the second control signal line 114B and the light emitting control signal line 115; the second control signal line 114B is connected to the gate T50 of the second reset transistor T5, and the light emitting control signal line 115 is connected to the gate T60 of the third reset transistor T6.

[0082] Specifically, a portion of the second control signal line 114B may serve as the gate T50 of the second reset transistor T5 , and the light emission control signal line 115 may serve as the gate T60 of the third reset transistor T6 .

[0083] Furthermore, in some embodiments, the second reset transistor T5 includes a first electrode T51 and a second electrode T52 . The first electrode T51 of the second reset transistor T5 is connected to the second electrode T12 of the data writing transistor T1 , and the second electrode T52 of the second reset transistor T5 is connected to the initialization signal line 113 .

[0084] In this way, the second control signal line 114B can provide a reset control signal RESET to the second reset transistor T5. Under the action of the reset control signal RESET, the second reset transistor T5 can provide an initialization signal Vinit to the second electrode T12 of the data writing transistor T1 and the first electrode C11 of the storage capacitor C1 for initialization.

[0085] In some embodiments, the third reset transistor T6 includes a first electrode T61 and a second electrode T62 . The first electrode T61 of the third reset transistor T6 is connected to the second electrode T12 of the data writing transistor T1 . The second electrode T62 of the third reset transistor T6 is connected to the initialization signal line 113 .

[0086] Thus, the light emitting control signal EM provides the light emitting control signal EM to the third reset transistor T6. Under the action of the light emitting control signal EM, the third reset transistor T6 can provide the initialization signal Vinit to the second electrode T12 of the data writing transistor T1 and the first electrode C11 of the storage capacitor C1 for initialization.

[0087] In some embodiments, the display substrate 110 includes a second connection electrode 11212 extending along the second direction, and the second connection electrode 11212 connects the first electrode T51 of the second reset transistor T5, the first electrode T61 of the third reset transistor T6, the first electrode C11 of the storage capacitor C1, and the second electrode T12 of the data writing transistor T1.

[0088] Similarly, a second connection electrode 11212 is provided to electrically connect the first electrode T51 of the second reset transistor T5, the first electrode T61 of the third reset transistor T6, the first electrode C11 of the storage capacitor C1, and the second electrode T12 of the data write transistor T1, which are located at different layers or positions. The second connection electrode 11212 can be connected to corresponding components through vias provided in various layers of the substrate.

[0089] In some embodiments, the first connection electrode 11211 , the second connection electrode 11212 , the data line 117 , and the first power line 116A are disposed in the same layer.

[0090] In some embodiments, the second electrode T72 of the light emitting control transistor T7 is connected to the first electrode 1181 of the light emitting element 118 .

[0091] Specifically, the light emitting control transistor T7 can be turned on under the action of the light emitting control signal EM, and the driving transistor T3 generates a driving current under the action of the first power supply signal ELVDD. The light emitting control transistor T7 transmits the driving current to the first electrode 1181 of the light emitting element 118 to drive the light emitting element 118 to emit light.

[0092] In some embodiments, the fourth reset transistor T8 is located between the second control signal line 114B and the light emitting control signal line 115 ; the second control signal line 114B is connected to the gate T80 of the fourth reset transistor T8 .

[0093] Specifically, a portion of the second control signal line 114B may serve as the gate T80 of the fourth reset transistor T8 .

[0094] Furthermore, in some embodiments, the fourth reset transistor T8 includes a first electrode T81 and a second electrode T82 . The first electrode T81 of the fourth reset transistor T8 is connected to the first electrode 1181 of the light emitting element 118 , and the second electrode T82 of the fourth reset transistor T8 is connected to the initialization signal line 113 .

[0095] Thus, the second control signal line 114B can provide the reset control signal RESET to the fourth reset transistor T8 . Under the action of the reset control signal RESET, the fourth reset transistor T8 can provide the initialization signal Vinit to the first electrode 1181 of the light emitting element 118 for initialization.

[0096] In some embodiments, the display substrate 110 includes a buffer layer 120 on a base substrate 111, and the pixel circuit 1121 includes an active layer 121 located on the buffer layer 120, a first insulating layer 122 located on the side of the active layer 121 away from the base substrate 111, a gate layer 123 located on the first insulating layer 122, a second insulating layer 124 located on the side of the gate layer 123 away from the base substrate 111, a third insulating layer 125 located on the second insulating layer 124, and a source and drain layer 126 located on the third insulating layer 125.

[0097] In some embodiments, the material of the buffer layer 120 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The material of one or more of the third insulating layer 125, the second insulating layer 124, and the first insulating layer 122 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The materials of the third insulating layer 125, the second insulating layer 124, and the first insulating layer 122 may be the same or different.

[0098] In some embodiments, in some examples of the above embodiments of the present application, such as Figure 4 As shown, the active layer 121 may include a source region 1211 and a drain region 1212, as well as a channel region 1213 located between the source region 1211 and the drain region 1212. The third insulating layer 125, the second insulating layer 124, and the first insulating layer 122 have vias to expose the source region 1211 and the drain region 1212. The first electrode 1261 and the second electrode 1262 of the transistor are electrically connected to the source region 1211 and the drain region 1212, respectively, through the vias. The gate layer 123 overlaps with the channel region 1213 located between the source region 1211 and the drain region 1212 in the active layer 121 in a direction perpendicular to the substrate 111.

[0099] In some embodiments, the display substrate 110 further includes a planarization layer 127 on the side of the source / drain layer 126 away from the base substrate 111. The planarization layer 127 is located above the first pole 1261 and the second pole 1262 of the transistor and is used to planarize the surface of the pixel circuit 1121 away from the base substrate 111. Vias are formed in the planarization layer 127 to expose the first pole 1261 and the second pole 1262 of the transistor (as shown in the figure). A passivation layer 128 may also be formed between the pixel circuit 1121 and the planarization layer 127, and the passivation layer 128 includes a passivation layer via. The passivation layer 128 may protect the first pole 1261 and the second pole 1262 of the transistor of the pixel circuit 1121 from being corroded by water vapor.

[0100] Figure 4The transistor shown in the figure can be the fourth reset transistor T8 or the light emitting control transistor T7. It can be understood that other transistors of the circuit can be formed at other positions of the substrate. Accordingly, the connection method of other transistors can also be designed as needed and is not normally specifically limited.

[0101] For example, the material of the active layer 121 may include polycrystalline silicon or an oxide semiconductor (for example, indium gallium zinc oxide). The material of the gate may include a metal material or an alloy material, for example, a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). The material of the source and drain may include a metal material or an alloy material, for example, a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). The embodiments of the present disclosure do not specifically limit the materials of the functional layers.

[0102] In some embodiments, the material of the passivation layer 128 may include an organic insulating material or an inorganic insulating material, such as silicon nitride material, which has a high dielectric constant and good hydrophobicity and can well protect the pixel driving circuit from being corroded by water vapor.

[0103] In some embodiments, a light-emitting element 118 may be formed on the planarization layer 127, i.e., the light-emitting element 118 is disposed on a side of the planarization layer 127 away from the substrate 111. The light-emitting element 118 includes a first electrode 1181, a light-emitting layer 1182, and a second electrode 1183. The first electrode 1181 of the light-emitting element 118 is electrically connected to the first electrode 1261 and / or the second electrode 1262 of the corresponding transistor through a via in the planarization layer 127. A pixel-defining layer 130 is formed on the first electrode 1181 of the light-emitting element 118. The pixel-defining layer 130 includes a plurality of openings to define a plurality of pixel units 112. Each of the multiple openings exposes the first pole 1181 of the corresponding light-emitting element 118; then, the light-emitting layer 1182 is arranged in the multiple openings of the pixel defining layer 130, and the second pole 1183 of the light-emitting element 118 is arranged on the pixel defining layer 130 and the light-emitting layer 1182. For example, the second pole 1183 can be arranged in part or the entire display area 1111, so that the entire surface can be formed in the preparation process.

[0104] In some embodiments, the pixel circuit 1121 may include a transfer electrode 11213, and the display substrate 110 connects the first electrode 1181 of the light-emitting element 118 to the first electrode 1261 and / or the second electrode 1262 of the corresponding transistor via the transfer electrode 11213. Thus, the transfer electrode 11213 can make the relative positions of the pixel circuit 1121 and the light-emitting element 118 on the display panel 110 more flexible.

[0105] For example, the first pole 1181 of the light-emitting element 118 may include a reflective layer (not shown), and the second pole 1182 of the light-emitting element 118 may include a transparent layer or a semi-transparent layer. Thus, the first pole 1181 of the light-emitting element 118 may reflect light emitted from the light-emitting layer 1182, and this portion of light is emitted into the external environment through the second pole 1183 of the light-emitting element 118, thereby improving light extraction efficiency. When the second pole 1183 of the light-emitting element 118 includes a semi-transmissive layer, some of the light reflected by the first pole 1181 of the light-emitting element 118 is reflected again by the second pole 1183 of the light-emitting element 118, so that the first pole 1181 of the light-emitting element 118 and the second pole 1183 of the light-emitting element 118 form a resonant structure, thereby improving light extraction efficiency.

[0106] For example, the material of the first electrode 1181 of the light-emitting element 118 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 1181 of the light-emitting element 118 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0107] For example, for OLED, the light-emitting layer 1182 may include small molecule organic materials or polymer molecule organic materials, may be fluorescent materials or phosphorescent materials, may emit red light, green light, blue light, or may emit white light; and, as needed, the light-emitting layer 1182 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0108] For example, the second electrode 1182 of the light emitting element 118 may include various conductive materials. For example, the second electrode 1183 of the light emitting element 118 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).

[0109] For example, the material of the pixel defining layer 130 may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited in the embodiments of the present disclosure.

[0110] In addition, the first electrode C11 of the storage capacitor C1 is arranged between the second insulating layer 124 and the third insulating layer 125; the second electrode C12 is arranged between the first insulating layer 122 and the second insulating layer 124. The first electrode C11 and the second electrode C12 of the storage capacitor C1 are stacked and at least partially overlap in the direction perpendicular to the base substrate 111. The first electrode C11 and the second electrode C12 of the storage capacitor C1 use the second insulating layer 124 as a dielectric material to form the storage capacitor C1. The second electrode C12 of the storage capacitor C1 is arranged in the same layer as the gate layer 123 in the pixel circuit 1121. Similarly, as described above, in a variation of the above example, the first electrode C11 and the second electrode C12 of the storage capacitor C1 can also be located in other layers, thereby obtaining sub-pixels with different structures.

[0111] In certain embodiments, as Figure 4 As shown, the display substrate 110 may further include an encapsulation layer 131 disposed on the light-emitting element 118. The encapsulation layer 131 seals the light-emitting element 118, thereby reducing or preventing degradation of the light-emitting element 118 caused by moisture and / or oxygen in the environment. The encapsulation layer 131 may have a single-layer structure or a composite layer structure including a stacked structure of inorganic and organic layers. For example, the encapsulation layer 131 may include a first inorganic encapsulation layer 1311, a first organic encapsulation layer 1312, and a second inorganic encapsulation layer 1313 disposed in sequence.

[0112] For example, the material of the encapsulation layer 131 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like. The material of the organic encapsulation layer 131 may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, to planarize the surface of the display substrate 110 and relieve stress in the first and second inorganic encapsulation layers 1311 and 1313. It may also include a desiccant or other absorbent material to absorb intruding water, oxygen, and the like.

[0113] See also Figures 6 to 8 , Figure 6 FIG. 1 is a schematic diagram of a semiconductor pattern layer L1 of a display substrate 110 , wherein a first insulating layer 122 may be formed on the semiconductor pattern layer L1 . Figure 7 Schematic diagram showing a first conductive pattern layer L2 formed on a first insulating layer 122 of a display substrate 110, Figure 8The structure diagram of the display substrate 110 after the semiconductor pattern layer is subjected to a conductorization process using a self-alignment process is shown. In some embodiments, during the manufacturing process of the display substrate 110, a self-alignment process is used to conduct the semiconductor pattern layer L1 using the first conductive pattern layer L2 as a mask. For example, ion implantation is used to heavily dope the semiconductor pattern layer L1, so that the portion of the semiconductor pattern layer L1 not covered by the first conductive pattern layer L2 is conducted, forming the source region (first electrode T11) and drain region (second electrode T12) of the data writing transistor T1, the source region (first electrode T21) and drain region (second electrode T22) of the first compensation transistor T2, and the source region (first electrode T31) and drain region ( the second electrode T32), the source region (first electrode T41) and the drain region (second electrode T42) of the first reset transistor T4, the source region (first electrode T51) and the drain region (second electrode T52) of the second reset transistor T5, the source region (first electrode T61) and the drain region (second electrode T62) of the third reset transistor T6, the source region (first electrode T71) and the drain region (second electrode T72) of the light emitting control transistor T7, the source region (first electrode T81) and the drain region (second electrode T82) of the fourth reset transistor T8, and the source region (first electrode T91) and the drain region (second electrode T92) of the second compensation transistor T9. The portion of the semiconductor pattern layer L1 covered by the first conductive pattern layer L2 retains semiconductor properties, forming a channel region T14 of the data write transistor T1, a channel region T24 of the first compensation transistor T2, a channel region T34 of the drive transistor T3, a channel region T44 of the first reset transistor T4, a channel region T54 of the second reset transistor T5, a channel region T64 of the third reset transistor T6, a channel region T74 of the light emitting control transistor T7, a channel region T84 of the fourth reset transistor T8, and a channel region T94 of the second compensation transistor T9.

[0114] like Figure 8 As shown, the second electrode T82 of the fourth reset transistor T8 and the second electrode T42 of the first reset transistor T4 are integrally formed. The first electrode T91 of the second compensation transistor T9 and the first electrode T41 of the first reset transistor T4 are integrally formed. The first electrode T81 of the fourth reset transistor T8 and the second electrode T72 of the emission control transistor T7 are integrally formed. The first electrode T71 of the emission control transistor T7, the second electrode T32 of the drive transistor T3, and the second electrode T22 of the first compensation transistor T2 are integrally formed. The first electrode T51 of the second reset transistor T5 and the first electrode T61 of the third reset transistor T6 are integrally formed. The second electrode T52 of the second reset transistor T5 and the second electrode T62 of the third reset transistor T6 are integrally formed. In particular, the second electrode C12 of the storage capacitor C1 can serve as the gate T30 of the drive transistor T3.

[0115] For example, the channel region 1213 (active layer 121) of the transistor used in the embodiment of the present disclosure can be single crystal silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon) or metal oxide semiconductor materials (e.g., IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low-temperature polycrystalline silicon (LTPS) thin film transistors. In another embodiment, the first compensation transistor T2 and the first reset transistor T4 directly connected to the gate T30 of the driving transistor T3 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (e.g., IGZO, AZO, etc.). Metal oxide semiconductor thin film transistors have low leakage current, which can help reduce the gate leakage current of the driving transistor T3.

[0116] For example, the transistors used in the embodiments of the present disclosure may include various structures, such as top-gate, bottom-gate, or dual-gate structures. In one embodiment, the first compensation transistor T2 and the first reset transistor T4 directly connected to the gate of the driving transistor T3 are dual-gate thin-film transistors, which can help reduce the leakage current of the gate T30 of the driving transistor T3.

[0117] It should be noted that the semiconductor pattern layer L1 may be the active layer 121 discussed above, and the first conductive pattern layer L2 may be the gate layer 123 discussed above.

[0118] In some embodiments, the corresponding relationship between the semiconductor pattern layer L1 and the via holes VH1, VH2, VH3, VH4, VH5, VH6, VH7 and VH8 formed on the display substrate 110 is as follows: Figure 6 As shown, the semiconductor pattern layer L1 can be connected to other layers of the display substrate 110 through via holes.

[0119] See also Figure 9 In some embodiments, a second insulating layer 124 is formed on the structure after the conductorization process, and a second conductive pattern layer L3 is formed on the second insulating layer 124. The second conductive pattern layer L3 includes the first electrode C11 of the storage capacitor C1 and the initialization signal line 113. The first electrode C11 of the storage capacitor C1 and the initialization signal line 113 are arranged on the same layer. The first electrode C11 of the storage capacitor C1 has an electrode via C111, which facilitates the first connection electrode 11211 to pass through the electrode via C111 and electrically connect to the second electrode C12 of the storage capacitor C1 (the gate T30 of the driving transistor T3). The first connection electrode 11211 is insulated from the first electrode C11 of the storage capacitor C1.

[0120] In some embodiments, the via VH3 can penetrate the first insulating layer 122 and the second insulating layer 124, so that the initialization signal line 113 can be connected to the second electrode T42 of the first reset transistor T4, the second electrode T52 of the second reset transistor T5, the second electrode T62 of the third reset transistor T6, and the second electrode T82 of the fourth reset transistor T8 through the via VH3.

[0121] It should be noted that the second conductive pattern layer L3 may be located between the second insulating layer 124 and the third insulating layer 125 .

[0122] In some embodiments, the second conductive pattern layer L3 further includes a third power line 116B, that is, the third power line 116B is provided on the same layer as the first electrode C11 of the storage capacitor C1 and the initialization signal line 113. Specifically, the third power line 116B is located between the first electrode C11 of the storage capacitor C1 and the initialization signal line 113.

[0123] like Figure 10 As shown, the display substrate 110 may further form a third insulating layer 125 on a side of the second conductive pattern layer L3 away from the first conductive pattern layer L2, and then form a third conductive pattern layer L4 on a side of the third insulating layer 125 away from the second conductive pattern layer L3. The third conductive pattern layer L4 is formed with a first connection electrode 11211, a second connection electrode 11212, a first switching electrode 11213, a data line 117, and a first power line 116A. The first connection electrode 11211, the second connection electrode 11212, the switching electrode 11213, the data line 117, and the first power line 116A are located on the same layer.

[0124] For example, the first conductive pattern layer L2, the second conductive pattern layer L3, and the third conductive pattern layer L4 are all made of metal materials. For example, the first conductive pattern layer L2 is formed from the same metal material using the same patterning process, the second conductive pattern layer L3 is formed from the same metal material using the same patterning process, and the third conductive pattern layer L4 is formed from the same metal material using the same patterning process. For example, the metal materials include, but are not limited to, molybdenum (Mo), aluminum, and titanium. For example, the first conductive pattern layer L2, the second conductive pattern layer L3, and the third conductive pattern layer L4 can be formed of, but are not limited to, molybdenum.

[0125] It is understood that the third conductive pattern layer L4 can be the source / drain electrode layer 123 discussed above. The display substrate 110 further includes vias VH9, VH10, and VH11. Vias VH1, VH2, VH4, VH5, VH6, VH7, and VH8 can penetrate the first insulating layer 122, the second insulating layer 124, and the third insulating layer 125. Vias VH9 can penetrate the second insulating layer 124 and the third insulating layer 125. Vias VH10 and VH11 can penetrate the third insulating layer 125.

[0126] In this way, the transfer electrode 11213 can be connected to the first electrode T81 of the fourth reset transistor T8 and the second electrode T72 of the light-emitting control transistor T7 through the via VH1. The first connection electrode 11211 can be connected to the first electrode T91 of the second compensation transistor T9 and the first electrode T41 of the first reset transistor T4 through the via VH2, and to the second electrode C12 of the storage capacitor C1 through the via VH9, and to the first electrode T21 of the first compensation transistor T2 through the via VH7, where the via VH9 corresponds to the electrode via C111. The second connection electrode 11212 can be connected to the first electrode T51 of the second reset transistor T5 and the second electrode T62 of the third reset transistor T6 through the via VH4, and to the first electrode C11 of the storage capacitor C1 through the via VH11, and to the second electrode T12 of the data write transistor T1 through the via VH6. The data line 117 can be connected to the first electrode T11 of the data write transistor T1 through the via VH8. The first power line 116A may be connected to the third power line 116B through a via VH10 .

[0127] In some embodiments, the second conductive layer L3 further includes a capacitor plate C21 . The capacitor plate C21 is disposed corresponding to the data line 117 . The capacitor plate C21 can shield interference between the data line 117 and other signal lines.

[0128] See also Figure 11In some embodiments, the display substrate 110 includes an initialization bus 132 located on a side of the initialization signal line 113 facing away from the base substrate 111. The initialization bus 132 is electrically connected to the initialization signal line 113. Specifically, a passivation layer 128 may be formed on the side of the third conductive pattern layer L4 facing away from the second conductive pattern layer L3, and a planarization layer 127 may be formed on the side of the passivation layer 128 facing away from the third conductive pattern layer L4. An anode circuit pattern L5 is then formed on the side of the planarization layer 127 facing away from the third conductive pattern layer L4. The anode circuit pattern L5 includes a first electrode 1181 of the light-emitting element 118 and the initialization bus 132. The initialization bus 132 and the first electrode 1181 of the light-emitting element 118 are disposed on the same layer. In one example, the light-emitting element 118 is an OLED, and the first electrode 1181 of the light-emitting element 118 serves as the anode of the OLED. The initialization bus 132 may be connected to the initialization signal line 113 of the second conductive pattern layer L3 through vias in the passivation layer 128 and the planarization layer 127.

[0129] In this way, the initialization bus 132 can fully utilize the wiring space of the anode conductive layer, and then the initialization signal Vinit is further provided to the adjacent first pixel circuit 1121a and the second pixel circuit 1121b through the segmented initialization signal line 113.

[0130] In some embodiments, the display substrate 110 may further include a via hole VH12 and a via hole VH13 . The via hole VH12 penetrates the passivation layer 128 and the planarization layer 127 , and the via hole VH13 penetrates the passivation layer 128 and the planarization layer 127 .

[0131] In this way, the transfer electrode 11213 can be connected to the first electrode 1181 of the light-emitting element 118 through the via hole VH12, and the initialization signal line 113 can be connected to the initialization bus 132 through the via hole VH13.

[0132] In some embodiments, the initialization bus 132 includes multiple main bodies 1321, multiple connecting parts 1322 and multiple branches 1323; the multiple main bodies 1321 extend along the first direction and are spaced apart along the second direction, and are configured to provide the initialization signal Vinit to the corresponding multiple initialization signal lines 113 extending along the first direction and spaced apart in segments; the multiple connecting parts 1322 extend along the second direction to connect two adjacent main bodies 1321; the multiple branches 1323 are connected to at least one of the two adjacent main bodies 1321, the multiple connecting parts 1322 and the multiple branches 1323 are alternately spaced apart along the first direction, and the multiple branches 1323 are configured to provide the initialization signal Vinit to the corresponding multiple initialization signal lines 113 extending along the first direction and spaced apart in segments between the two adjacent main bodies 1321.

[0133] See also Figure 12 In some embodiments, the display substrate 110 may have a pixel opening layer L6 formed on a side of the anode circuit pattern L5 away from the substrate, and the pixel opening layer L6 has a pixel opening 1301 corresponding to the anode circuit pattern L5.

[0134] It should be noted that the pixel opening layer L6 may be the pixel defining layer 130 discussed above.

[0135] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0136] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display substrate, comprising: A base substrate, including a display area; A plurality of pixel units are located in the display area, the pixel units include pixel circuits, and the pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other along a first direction; an initialization signal line extending along the first direction and configured to provide an initialization signal to the first pixel circuit and the second pixel circuit; a first control signal line extending along the first direction and configured to provide a gate signal to the first pixel circuit and the second pixel circuit; a light emitting control signal line extending along the first direction and configured to provide a light emitting control signal to the first pixel circuit and the second pixel circuit; The initialization signal line is located on a side of the light emitting control signal line away from the first control signal line, extends along the first direction and is arranged in intervals and segments; The display substrate further comprises an initialization bus located on a side of the initialization signal line away from the base substrate, wherein the initialization bus is electrically connected to the initialization signal line; The initialization bus includes a plurality of main parts, a plurality of connecting parts and a plurality of branches; The plurality of main bodies extend along the first direction and are spaced apart along the second direction, and are configured to provide the initialization signal to the corresponding plurality of initialization signal lines extending along the first direction and spaced apart in segments; A plurality of connecting portions extend along the second direction to connect two adjacent main body portions; The multiple branches are connected to at least one of the two adjacent main bodies, and the multiple branches are configured to provide the initialization signal to the corresponding multiple initialization signal lines extending along the first direction and spaced apart between the two adjacent main bodies.

2. The display substrate according to claim 1, wherein: The display substrate further includes a second control signal line located on a side of the initialization signal line away from the light emitting control signal line. The second control signal line extends along the first direction and is configured to provide a reset control signal to the first pixel circuit and the second pixel circuit.

3. The display substrate according to claim 2, wherein: The display substrate includes a plurality of first power lines extending along the second direction and arranged at intervals along the first direction. The plurality of first power lines are configured to provide a first power signal to the pixel circuit.

4. The display substrate according to claim 3, wherein: The display substrate includes a plurality of third power lines, which are spaced apart along the second direction and connected to the first power lines. The third power lines are configured to provide the first power signal to the pixel circuit.

5. The display substrate according to claim 3, wherein: The pixel circuit includes a light emitting control transistor; The gate of the light emitting control transistor is connected to the light emitting control signal line, the light emitting control transistor includes a first electrode and a second electrode, and the pixel circuit includes a driving transistor; The driving transistor includes a first electrode and a second electrode, and the first electrode of the driving transistor is connected to the first power line; The second electrode of the driving transistor is connected to the first electrode of the light emission control transistor.

6. The display substrate according to claim 5, wherein: The pixel circuit includes a first reset transistor and a storage capacitor, and the second control signal line is connected to the gate of the first reset transistor; The storage capacitor includes a first electrode and a second electrode, and the second electrode of the storage capacitor is connected to the gate of the driving transistor; The first reset transistor includes a first electrode and a second electrode, the second electrode of the first reset transistor is connected to the gate of the driving transistor, and the first reset transistor is configured to initialize the driving transistor and the storage capacitor through the initialization signal during a reset phase.

7. The display substrate according to claim 6, wherein: The initialization signal line and the first electrode of the storage capacitor are arranged in the same layer and spaced apart.

8. The display substrate according to claim 6, wherein: The display substrate includes a plurality of data lines extending along the second direction and spaced apart along the first direction. The data lines are configured to provide data signals to the pixel circuits.

9. The display substrate according to claim 8, wherein: The pixel circuit includes a data writing transistor and a first compensation transistor; The data writing transistor includes a first electrode and a second electrode, and the first electrode of the data writing transistor is connected to the data line; The first electrode of the storage capacitor is connected to the second electrode of the data writing transistor; The first compensation transistor includes a first electrode and a second electrode. The first electrode of the first compensation transistor is connected to the gate of the driving transistor, and the second electrode of the first compensation transistor is connected to the second electrode of the driving transistor.

10. The display substrate according to claim 9, wherein: The data writing transistor and the first compensation transistor are located on a side of the first control signal line close to the light emission control signal line.

11. The display substrate according to claim 10, wherein: The pixel circuit includes a second reset transistor and a third reset transistor located between the second control signal line and the light emission control signal line; The second control signal line is connected to the gate of the second reset transistor, and the light emitting control signal line is connected to the gate of the third reset transistor; The second reset transistor includes a first electrode and a second electrode, the first electrode of the second reset transistor is connected to the second electrode of the data writing transistor, and the second electrode of the second reset transistor is connected to the initialization signal line; The third reset transistor includes a first electrode and a second electrode. The first electrode of the third reset transistor is connected to the second electrode of the data writing transistor, and the second electrode of the third reset transistor is connected to the initialization signal line.

12. The display substrate according to claim 5, wherein The display substrate further includes a light emitting element, the second electrode of the light emitting control transistor is connected to the first electrode of the light emitting element, and the pixel circuit includes a fourth reset transistor located between the second control signal line and the light emitting control signal line; The fourth reset transistor includes a first electrode and a second electrode. The first electrode of the fourth reset transistor is connected to the first electrode of the light emitting element, and the second electrode of the fourth reset transistor is connected to the initialization signal line.

13. The display substrate according to claim 12, wherein: The display substrate includes a second power line configured to provide a second power signal to the light emitting element.

14. The display substrate according to claim 13, wherein: The initialization signal is a constant voltage signal, and the magnitude of the initialization signal is between the first power signal and the second power signal.

15. The display substrate according to claim 1, wherein One pixel of the display substrate includes a pixel unit emitting red light, a pixel unit emitting green light, and a pixel unit emitting blue light.

16. The display substrate according to claim 1, wherein The first control signal line is further configured to provide a reset control signal to a pixel circuit on the other side of the first control signal line opposite to the first pixel circuit and the second pixel circuit.

17. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 16.

18. The display device according to claim 17, wherein: The display device also includes: a data driving circuit and a scan driving circuit, the data driving circuit is configured to provide a data signal to the pixel unit according to the instruction of the control circuit; the scan driving circuit is configured to provide a reset control signal, the light emitting control signal, the gate signal and the initialization signal to the pixel unit according to the instruction of the control circuit.

19. The display device according to claim 18, wherein The display substrate includes a non-display area, and the data driving circuit and the scan driving circuit are disposed in the non-display area.

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