Driving circuit, display device and in-cell touch panel device

Abstract

The invention provides a drive circuit, a display device, and an in-cell touch panel device capable of preventing changes in characteristics of a transistor in a latch circuit. The gate drive circuit includes a latch circuit (22). The latch circuit (22) includes nodes (N21-N23), a transistor (T22), a node (N21), a transistor (T21) to which an RSM signal is supplied at the end of the stop period, and a transistor (T28) to which a TRS signal is supplied, the TRS signal being supplied after the point in time at which the stop period starts and before the point in time at which the RSM signal is supplied. The node (N23) and the node (N22) are turned on by supplying a TRS signal to the transistor (T28).

Description

Technical Field

[0001] The present disclosure relates to a driving circuit, a display device and an embedded touch panel device. Background Art

[0002] Patent document 1 discloses a driving circuit capable of stopping operation in the middle of a scan. The driving circuit (shift register) includes a plurality of unit circuits that respectively constitute a plurality of stages. The plurality of unit circuits include: a first unit circuit that outputs a shift pulse to a gate bus and a subsequent stage; and a second unit circuit that outputs a shift pulse to a subsequent stage. The second unit circuit includes: a transistor having a first electrode connected to a subsequent stage; and an internal node connected to a control electrode of the transistor. The potential of the internal node continuously maintains a high level during the period when the operation of the driving circuit is stopped. Then, at a time point before the time point when the operation of the driving circuit is to be restarted, the level of the signal supplied to the second electrode of the transistor becomes a high level. Thus, the transistor that becomes conductive by maintaining a high-level internal node outputs a shift pulse to the subsequent stage, and the operation of the driving circuit is restarted. Prior art literature Patent Literature

[0003] Patent Document 1: International Publication No. 2017 / 006815 Summary of the invention Technical Problems to be Solved by the Invention

[0004] In the shift register described in Patent Document 1, during the period of operation stop, the internal node continuously connected to the control electrode (gate electrode) of the transistor of the second unit circuit (latch circuit) becomes a high level. Therefore, by continuously applying a high level (on-level) voltage to the gate electrode of the transistor, the characteristics of the transistor may change.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a drive circuit, a display device, and an in-cell touch panel device that can prevent a change in characteristics of a transistor in a latch circuit. Solutions for solving problems

[0006] In order to solve the above-mentioned problem, the first mode of the present disclosure involves a driving circuit which is composed of a plurality of stages and supplies driving signals to a scanning signal line group according to input of a plurality of clock signals. The driving circuit has a plurality of unit circuits constituting each of the plurality of stages, and the plurality of unit circuits include: a shift register unit circuit, which is a shift register unit circuit connected to a scanning signal line in the scanning signal line group and supplies an output signal to the scanning signal line and a subsequent stage of the shift register unit circuit; a latch circuit, which is a latch circuit that holds the output signal input from a previous stage during a stop period in which the supply of the plurality of clock signals is stopped and the operation of the driving circuit is stopped, and supplies an output signal to a subsequent stage of the latch circuit at the end of the stop period, and the latch circuit includes: a signal holding node; a conduction circuit that changes the level of the signal holding node from an off level to an on level based on the output signal input from the preceding stage; a first output node connected to the The subsequent stage; a first transistor having a first electrode supplied with a first control signal at the end of the stop period, a second electrode connected to the first output node, and a first control electrode; a second output node connected to the first control electrode; a second transistor having a third electrode connected to the signal holding node; a fourth electrode connected to the second output node; and a second control electrode supplied with a second control signal, the second control signal being supplied after a time point at which the stop period has started and before a time point at which the first control signal is supplied to the first electrode, the second transistor turning on the signal holding node and the second output node by supplying the second control signal to the second control electrode, the first transistor turning on through the signal holding node and the second output node, the level of the second output node changing from a cut-off level to a conduction level, thereby supplying the first control signal as an output signal to the first output node.

[0007] A display device according to a second aspect includes: the driving circuit according to the first aspect; and a display including the scanning signal line group.

[0008] An in-cell touch panel device according to a third aspect includes: the driving circuit according to the first aspect; and an in-cell touch panel provided with the scanning signal line group, and detecting a touch of a pointer during the stop period. Effects of the Invention

[0009] According to the above configuration, during the stop period when the operation of the driving circuit is stopped, the first control electrode of the first transistor of the latch circuit is disconnected from the signal holding node that maintains the on-level. Thus, it is possible to prevent the on-level voltage from being continuously applied to the first control electrode of the first transistor during the stop period. As a result, it is possible to prevent the characteristics of the first transistor of the latch circuit from changing. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a block diagram showing the configuration of a display device 100 according to the first embodiment. Figure 2 2 is a schematic circuit diagram showing the configuration of the display unit 10 . Figure 3 2 is a diagram showing the structure of the touch panel 1 . Figure 4 2 is a diagram showing a partial configuration of the gate drive circuit 20 . Figure 5 2 is a circuit diagram showing the configuration of the shift register unit circuit 21 . Figure 6 2 is a circuit diagram showing the configuration of the latch circuit 22 . Figure 7 is a timing chart of control signals input to the gate drive circuit 20 . Figure 8 2 is a diagram showing a configuration of a gate driving circuit 220 of a display device 200 according to a second embodiment. Fig. 9 is a circuit diagram of the latch circuit 222 according to the second embodiment. Fig.10 2 is a circuit diagram of a latch circuit 322 of a gate driving circuit 320 according to the second embodiment. Fig.11 2 is a diagram showing a configuration of a gate driving circuit 420 according to a fourth embodiment. Fig.12 : is a circuit diagram of a latch circuit 522 according to a first modification example of the first to fourth embodiments. Fig.13 : is a circuit diagram of a latch circuit 622 according to a second modification example of the first to fourth embodiments. DETAILED DESCRIPTION

[0011] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are used for the same or corresponding parts in the drawings, and their descriptions will not be repeated. In addition, in order to make the description easy to understand, the configuration is simplified or schematically shown in the drawings referred to below, or a part of the components is omitted. In addition, the size ratios between the components shown in the drawings do not necessarily represent the actual size ratios.

[0012] [First embodiment] (Overall Structure of Display Device) The configuration of the display device 100 according to the first embodiment will be described. Figure 1 It is a block diagram showing the configuration of a display device 100 according to the first embodiment. Figure 2 2 is a schematic circuit diagram showing the configuration of the display unit 10 . Figure 3 2 is a diagram showing the structure of the touch panel 1 .

[0013] like Figure 1 As shown, the display device 100 includes a touch panel 1 and a control circuit 2. In the first embodiment, the touch panel 1 is configured as an embedded touch panel that realizes a touch detection function and an image display function. That is, the touch panel 1 also serves as a display. In addition, in the first embodiment, the display device 100 is an embedded touch panel device.

[0014] The control circuit 2 includes a processor that performs control processing of the display device 100. Then, the control circuit 2 sends a control signal to the touch panel 1 based on the input image signal. The touch panel 1 displays an image based on the control signal. In addition, the control circuit 2 sends an instruction to detect a touch to the touch panel 1, and receives information indicating the touch coordinates of the indicator from the touch panel 1 (hereinafter referred to as "touch detection processing"). In addition, the control circuit 2 performs display processing and touch detection processing for causing the gate drive circuit 20 to perform an action in a time-division manner during one frame period. That is, one frame period includes a touch detection period TP (refer to Figure 7 ) and a display period TD (refer to Figure 7 ). The control circuit 2 performs the touch detection process multiple times in one frame period, for example. In addition, during the touch detection process, the operation of the gate drive circuit 20 is stopped. In addition, during the period when the operation of the gate drive circuit 20 is stopped, that is, during the stop period TR (refer to Figure 7 ) includes a touch detection period TP.

[0015] like Figure 1 As shown, the touch panel 1 includes a display unit 10, a gate drive circuit 20, a source drive circuit 30 and a touch detection control circuit 40. Figure 1 , it is illustrated that the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 are provided in the touch panel 1, but at least one of the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 may be provided on another substrate arranged outside the touch panel 1. In this case, at least one of the touch panel 1, the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 is connected through wiring or a flexible printed substrate.

[0016] like Figure 2 As shown, the display unit 10 includes a plurality of gate lines 11, a plurality of source lines 12, a plurality of transistors 13, a plurality of pixel electrodes 14, and a plurality of common electrodes 15. The plurality of gate lines 11 intersect with the plurality of source lines 12 in a plan view. Moreover, transistors 13 and pixel electrodes 14 are arranged in each region divided by the plurality of gate lines 11 and the plurality of source lines 12. Furthermore, the transistor 13 includes a gate electrode 13a, a source electrode 13b, and a drain electrode 13c. The gate electrode 13a is connected to the gate line 11. In addition, the source electrode 13b is connected to the source line 12. The drain electrode 13c is connected to the pixel electrode 14. The plurality of gate lines 11 is an example of a scanning signal line group. In addition, in Figure 2 , an example is shown in which the gate driving circuit 20 is arranged on one side of the display unit 10 , but the gate driving circuits 20 may be arranged on both sides of the display unit 10 .

[0017] The gate drive circuit 20 is formed on the substrate of the touch panel 1 (formed as a single chip). The gate drive circuit 20 outputs gate signals to the plurality of gate lines 11 in sequence. The source drive circuit 30 is mounted on the substrate of the touch panel 1. The source drive circuit 30 receives the image signal and the source control signal output from the control circuit 2, and generates a source signal (data signal) based on the image signal and the source control signal. Then, the source drive circuit 30 supplies the source signal to the plurality of source lines 12, respectively. Then, when the gate signal is supplied to the transistor 13 (when the gate is turned on), the source signal is written to the pixel electrode 14 via the transistor 13. As a result, an electric field is generated between the pixel electrode 14 and the common electrode 15, the liquid crystal layer not shown is driven, and an image is displayed on the touch panel 1.

[0018] like Figure 3 As shown, the plurality of common electrodes 15 are arranged, for example, in a matrix shape. The touch detection control circuit 40 is connected to each of the plurality of common electrodes 15 via the wiring 16. The common electrode 15 changes its electrostatic capacitance through capacitive coupling with the indicator. The touch detection control circuit 40 supplies a touch drive signal (pulse signal) to the plurality of common electrodes 15 during the touch detection process (touch detection period TP). The waveform of the pulse signal changes according to the size of the electrostatic capacitance of the common electrode 15. The touch detection control circuit 40 detects the touch of the indicator (the touched position) based on the waveform of the pulse signal from the common electrode 15. That is, the common electrode 15 also serves as a touch detection electrode. The touch panel 1 is a self-capacitance touch panel. In addition, without being limited to this example, the touch panel 1 may also be configured as a mutual capacitance touch panel.

[0019] (Configuration of Gate Drive Circuit 20) Next, refer to Figures 4 to 6The configuration of the gate drive circuit 20 will be described. Figure 4 2 is a diagram showing a partial configuration of the gate drive circuit 20 . Figure 5 2 is a circuit diagram showing the configuration of the shift register unit circuit 21 . Figure 6 2 is a circuit diagram showing the configuration of the latch circuit 22 .

[0020] like Figure 4 As shown in FIG. 1 , the gate driving circuit 20 is composed of a plurality of stages and is a shift register that supplies gate signals to a plurality of gate lines 11 according to a plurality of clock signals input thereto. Figure 4 , an nth (n is a natural number) stage, four stages before the nth stage, and three stages after the nth stage are shown among the multiple stages.

[0021] The gate driving circuit 20 includes a shift register unit circuit 21 constituting a part of a plurality of stages and a latch circuit 22 constituting a part of a plurality of stages. Figure 4 In FIG. 1 , an example is shown in which the latch circuit 22 constitutes the nth stage, and the plurality of shift register unit circuits 21 constitute the n-4th to n-1th stages and the n+1th to n+3th stages. Figure 4 Although one latch circuit 22 is shown in the figure, a plurality of latch circuits 22 may be provided in the gate driving circuit 20 .

[0022] like Figure 4 As shown, the control circuit 2 (refer to Figure 1 ) as control signals, and supplies a plurality of clock signals (hereinafter referred to as "CLK1A signal, CLK2A signal, CLK1B signal and CLK2B signal", and referred to as "CLK signal" when the CLK1A signal, CLK2A signal, CLK1B signal and CLK2B signal are not distinguished), VSS signal, RSM signal, VDD signal, VTP signal, TRS signal, and TPC signal to the gate drive circuit 20. The VSS signal is a signal having a reference potential (low level, off-level). The RSM signal is a signal instructing the gate drive circuit 20 to restart the operation. The VDD signal is a signal having a reference potential (high level, on-level). The VTP signal is a signal supplied during a stop period (a period during which touch detection processing is performed). The TRS signal is a signal instructing charging of a node N22 to be described later. In addition, node N22 is an example of a "second output node". In addition, although in Figure 4 Although not shown in the figure, the control circuit 2 supplies a gate start pulse (GSP) signal as a SET signal to the shift register unit circuits 21 of the first stage and the second stage.

[0023] The CLK signal, VDD signal, VTP signal, and VSS signal are input to the shift register unit circuit 21. The shift register unit circuit 21 supplies the output signal Q to the gate line 11 and the subsequent stages of the shift register unit circuit 21. In addition, in the following description, the output signal Q of the nth stage is recorded as "output signal Qn". For example, m is a natural number, and the mth shift register unit circuit 21 inputs the output signal Qm as a SET signal to the m+2th stage. In addition, the mth shift register unit circuit 21 inputs the output signal Qm as a RESET signal to the m-3th stage. In addition, the TPC signal is input as a RESET signal to the shift register unit circuits 21 of the n-3th to n-1th stages.

[0024] The RSM signal, the VDD signal, the VTP signal, and the VSS signal are input to the latch circuit 22. The latch circuit 22 holds the output signal Q (SET signal) input from the previous stage during the stop period in which the supply of the plurality of clock signals (CLK1A signal, CLK2A signal, CLK1B signal, and CLK2B signal) is stopped and the operation of the gate drive circuit 20 is stopped. For example, when the output signal Qn-1 is input to the latch circuit 22 constituting the nth stage as the LSET signal (set signal for the latch circuit 22), the latch circuit 22 stops the operation of the gate drive circuit 20.

[0025] Then, when the stop period ends, the latch circuit 22 supplies an output signal (SET signal) to the subsequent stage of the latch circuit 22. For example, when the TRS signal is input to the latch circuit 22 and the RSM signal is input to the latch circuit 22, the output signal Lout (output signal Qn) is output to the (n+1)th stage and the (n+2)th stage shift register unit circuit 21. Thus, the operation of the gate drive circuit 20 is restarted.

[0026] <Circuit Configuration of Shift Register Unit Circuit 21> like Figure 5 As shown in FIG. 1 , the shift register unit circuit 21 includes transistors T11 to T18, a capacitor C1, and nodes N11 to N13. Figure 5 , a shift register unit circuit 21 constituting the m-th stage is shown.

[0027] The transistor T11 has a drain electrode for supplying a CLK signal, a source electrode connected to the node N11, and a gate electrode connected to the node N12. The transistor T12 forms a conduction circuit that changes the level of the node N12 from a cut-off level (low level) to a conduction level (high level) based on the output signal Qm-2 input from the previous stage (for example, the m-2 stage). The output signal Qm-2 is input to the gate electrode of the transistor T12 as a SET signal. The VDD signal is input to the drain electrode of the transistor T12. The source electrode of the transistor T12 is connected to the node N12.

[0028] The transistor T13 forms a cutoff circuit that changes the level of the node N12 from the on-level to the off-level based on the output signal Qm+3 input from the subsequent stage (for example, the m+3 stage). The output signal Qm+3 is input to the gate electrode of the transistor T13 as a RESET signal (reset signal). The drain electrode of the transistor T13 is connected to the node N12. The VSS signal is input to the source electrode of the transistor T13.

[0029] Transistors T14 to T16 constitute a stabilization circuit 21a, which is a circuit for maintaining node N12 at an off-level during a period other than a period when node N12 is at an on-level. Transistor T14 connects a VDD signal to node N13 via a diode. Node N12 is connected to a gate electrode of transistor T15, and when node N12 becomes an on-level, node N13 is switched from an on-level to an off-level. Transistor T16 supplies a VSS signal to node N12 when node N13 is at an on-level, so that node N12 is maintained at an off-level.

[0030] The transistor T17 constitutes a stabilization circuit 21b, which is a circuit for maintaining the node N11 at an off level during periods other than the period when the node N12 is at an on level. When the node N13 is at an on level, the transistor T17 supplies a VSS signal to the node N11 to maintain the node N11 at an off level.

[0031] The VTP signal supplied in the touch detection period TP is input to the gate electrode of the transistor T18. When the VTP signal is input to the transistor T18, the transistor T18 is turned on and the node N11 is turned off.

[0032] The capacitance element C1 is disposed between the node N11 and the node N12. The capacitance element C1 is a bootstrap capacitor.

[0033] The node N11 is connected to the gate line 11 and the (m+2)th stage.

[0034] <Circuit Configuration of Latch Circuit 22> like Figure 6As shown, the latch circuit 22 includes transistors T21 to T28 , capacitors C2 and C3 , and nodes N21 to N24 .

[0035] The transistor T21 has a drain electrode T21d to which the RSM signal is supplied when the stop period TR ends, a source electrode T21s connected to the node N21, and a gate electrode T21g. The transistor T21 is a buffer transistor. In addition, the RSM signal is an example of the "first control signal" of the present disclosure. The drain electrode T21d is an example of the "first electrode" of the present disclosure. The source electrode T21s is an example of the "second electrode" of the present disclosure. The gate electrode T21g is an example of the "first control electrode" of the present disclosure.

[0036] The transistor T22 forms a conduction circuit that changes the level of the node N23 from the cut-off level (high level) to the conduction level (low level) based on the output signal Qn-1 input from the previous stage (for example, the n-1 stage). The output signal Qn-1 is input to the gate electrode of the transistor T22 as the LSET signal. The VDD signal is input to the drain electrode of the transistor T22. The source electrode of the transistor T22 is connected to the node N23.

[0037] The transistor T23a forms a cut-off circuit that changes the level of the node N23 from the on-level to the off-level based on the output signal Qn+3 input from the subsequent level (for example, the n+3th level). The output signal Qn+3 is input to the gate electrode of the transistor T23a as an LRESET signal (latch reset signal). The drain electrode of the transistor T23a is connected to the node N23. The VSS signal is input to the source electrode of the transistor T23a.

[0038] The transistor T23b ​​forms a cut-off circuit that changes the level of the node N22 from the on-level to the off-level based on the output signal Qn+3 input from the subsequent level (e.g., the n+3th level). The output signal Qn+3 is input to the gate electrode of the transistor T23b ​​as an LRESET signal (latch reset signal). The drain electrode of the transistor T23b ​​is connected to the node N22. The VSS signal is input to the source electrode of the transistor T23b.

[0039] Transistors T24 to T26 constitute a stabilization circuit 22a, which is a circuit for maintaining node N22 at an off level during periods other than the stop period TR. Transistor T24 connects the VDD signal to node N24 with a diode. Node N23 is connected to the gate electrode of transistor T25, and when node N23 becomes an on level, node N24 is switched from an on level to an off level. When node N24 is at an on level, transistor T26 supplies a VSS signal to node N22 to maintain node N22 at an off level.

[0040] The transistor T27 constitutes the stabilization circuit 22b and is a circuit for maintaining the node N21 at an OFF level during periods other than the rest period TR. When the node N24 is at an ON level, the transistor T27 supplies a VSS signal to the node N21 to maintain the node N21 at an OFF level.

[0041] The transistor T28 has a drain electrode T28d connected to the node N23, a source electrode T28s connected to the node N22, and a gate electrode T28g to which a TRS signal is supplied, which is supplied after the time point when the stop period TR has started and before the time point when the RSM signal is supplied to the drain electrode T21d of the transistor T21. In addition, the TRS signal is an example of the "second control signal" of the present disclosure. The drain electrode T28d is an example of the "third electrode" of the present disclosure. The source electrode T28s is an example of the "fourth electrode" of the present disclosure. The gate electrode T28g is an example of the "second control electrode" of the present disclosure.

[0042] The capacitor element C2 is disposed between the node N22 and the node N21. The capacitor element C2 is a bootstrap capacitor. The capacitor element C2 is an example of a "second capacitor element" in the present disclosure.

[0043] Capacitor element C3 is configured between node N23 and VSS signal line. Capacitor element C3 has a capacitance greater than capacitor element C2. For example, capacitor element C3 has a capacitance greater than 3 times of capacitor element C2. Thus, since the amount of charge accumulated in capacitor element C3 increases, after transistor T28 is turned on, capacitor element C2 connected to node N22 can be fully charged.

[0044] Node N21 is connected to the n+1th stage and the n+2th stage. Node N22 is connected to the gate electrode T21g. Node N23 is a node for maintaining the conduction level (signal) when the operation of the gate drive circuit 20 stops. In addition, node N21 is an example of the "first output node" of the present disclosure. Node N22 is an example of the "second output node" of the present disclosure. Node N23 is an example of the "signal holding node" of the present disclosure.

[0045] Here, in the first embodiment, the node N21 is not connected to the gate line 11. Therefore, since the latch circuit 22 is not connected to the gate line 11 even when the characteristics of the transistor T21 of the latch circuit 22 change, the change in the characteristics of the transistor T21 does not affect the display of the touch panel 1.

[0046] (Operation of Gate Drive Circuit 20) Next, refer to Figures 4 to 7 , the operation of the gate driving circuit 20 is described. Figure 7is a timing chart of control signals input to the gate drive circuit 20 .

[0047] <Operation of Shift Register Unit Circuit 21> like Figure 7 As shown, in the display period TD, the CLK1A signal, the CLK2A signal, the CLK1B signal and the CLK2B signal are sequentially input to the gate drive circuit 20. Figure 5 As shown, in the shift register unit circuit 21 constituting the mth stage, at a time point before the CLK signal is input, according to the output signal Qm-2 (SET signal) from the m-2th stage, the transistor T12 becomes a conducting state. Thus, the node N12 and the capacitor C1 are charged to the conducting level. In addition, by the node N12 becoming the conducting level, the transistor T14 becomes the conducting state, and the node N13 becomes the off level. Thus, the transistor T16 and the transistor T17 become the off state.

[0048] Then, when the CLK signal is input, the node N11 becomes the on level via the transistor T11. Thus, the output signal Qm (gate signal) is output to the gate line 11 and the subsequent level. Then, when the output signal Qm+3 (RESET signal) from the m+3th level is input to the shift register unit circuit 21, the transistor T13 is turned on and the node N12 is cut off to the cut-off level. In addition, by turning the node N12 into the cut-off level, the transistor T15 becomes the cut-off state, and the node N13 becomes the on level. Thus, the transistor T16 and the transistor T17 become the on state, respectively, and the node N12 and the node N11 are maintained at the cut-off level. By performing the above-mentioned actions at each stage, the output signal Q is outputted sequentially from the shift register unit circuits 21 of multiple stages (the gate drive circuit 20 is operated).

[0049] Then, if Figure 7 As shown, at time point t1, when the touch detection period TP and the stop period TR begin, as shown in FIG. Figure 4 As shown in FIG. 1 , the VTP signal is supplied to all the shift register unit circuits 21. Figure 5 As shown, when the VTP signal is supplied to the shift register unit circuit 21, the transistor T18 becomes conductive, and the output of the output signal Q is stopped. In addition, during the period from time point t1 to time point t2, the TPC signal is input as a RESET signal to the shift register unit circuits 21 of the n-3th to n-1th stages. As a result, the transistor T13 becomes off, and the node N12 becomes off level.

[0050] <Operation of Latch Circuit 22> like Figure 7As shown in FIG. 1 , in the display period TD, the CLK signal is input to the shift register unit circuit 21, and the output signal Q is sequentially output (the operation of the gate drive circuit 20 is executed). Figure 6 As shown, the output signal Qn-1 (LSET signal) from the shift register unit circuit 21 constituting the n-1th stage is input to the latch circuit 22 constituting the nth stage. As a result, the transistor T22 becomes conductive, and the node N23 becomes conductive. As a result, the capacitor C3 is charged.

[0051] In the display period TD, the TRS signal is at the off level, so that the transistor T28 is not turned on and the node N23 and the node N22 are disconnected. As a result, the node N23 can maintain the on-level voltage without applying the on-level voltage to the gate electrode T21g of the transistor T21.

[0052] In addition, in the display period TD, the RSM signal is at the off level, so that the output signal Q (SET signal) is not output to the subsequent stage of the latch circuit 22, and the operation of the gate drive circuit 20 stops.

[0053] After that, at time point t1, after the touch detection period TP and the stop period TR start, in the latch circuit 22, the state where the voltage of the on-level is maintained at the node N23 (the state where the capacitor C3 is charged), and the state where the voltage of the on-level is not applied to the gate electrode T21g of the transistor T21 is maintained. Thus, the characteristic change of the transistor T21 of the latch circuit 22 can be prevented.

[0054] like Figure 7 As shown, at time point t3, the touch detection period TP ends, and at time point t4, the TRS signal is input to the latch circuit 22 (the level of the TRS signal is the on level). Figure 6 As shown, the transistor T28 is turned on, and the node N23 and the node N22 are turned on. As a result, the node N22 is turned on, and the capacitor C2 is charged. Therefore, the transistor T21 is turned on.

[0055] like Figure 7 As shown in FIG. 1 , at time point t5, the level of the TRS signal becomes the off level, and the level of the RSM signal becomes the on level. Figure 6 As shown, the node N21 becomes the on level via the transistor T21. Therefore, the output signal Qn is output to the subsequent stages (for example, the shift register unit circuits 21 of the n+1th and n+2th stages). Afterwards, at time point t6, when the supply of the CLK signal is restarted, the stop period TR ends and the operation of the gate drive circuit 20 is restarted.

[0056] Then, when the output signal Qn+3 (LRESET signal) from the (n+3)th level is input to the latch circuit 22, the transistors T23a and T23b ​​are turned on, and the nodes N23 and N22 are turned off to the off level. In addition, by turning the node N23 into the off level, the transistor T25 is turned off, and the node N24 is turned on. Thus, the transistors T26 and T27 are turned on, respectively, and the nodes N22 and N21 are maintained at the off level. As described above, during the period until the TRS signal is input in the stop period TR, since the voltage of the on level (high level) is not applied to the gate electrode T21g of the transistor T21, the characteristic change of the transistor T21 of the latch circuit 22 can be prevented.

[0057] [Second embodiment] Next, refer to Figure 8 and Fig. 9 , the configuration of the display device 200 according to the second embodiment will be described. In the second embodiment, the VTP signal is input to the latch circuit 222. In addition, the same reference numerals are attached to the same configurations as those in the first embodiment, and the description thereof will be omitted. Figure 8 2 is a diagram showing a configuration of a gate driving circuit 220 of a display device 200 according to a second embodiment. Fig. 9 is a circuit diagram of the latch circuit 222 according to the second embodiment.

[0058] like Figure 8 As shown, the gate driving circuit 220 of the display device 200 includes a latch circuit 222. The VTP signal is input to the latch circuit 222. Fig. 9 As shown, the source electrode of the transistor T223a of the latch circuit 222 is connected to the node N221. The VTP signal is input to the node N221. In addition, the transistor T223a is an example of the "third transistor" of the present disclosure. In addition, the VTP signal is an example of the "third control signal" of the present disclosure. The node N221 is an example of the "input node" of the present disclosure. The drain electrode of the transistor T223a is an example of the "fifth electrode" of the present disclosure. The source electrode of the transistor T223a is an example of the "sixth electrode" of the present disclosure.

[0059] According to the configuration of the second embodiment, during the touch detection period TP, the potential difference between the drain electrode and the source electrode of the transistor T223a can be reduced. As a result, the off-leakage through the transistor T223a can be suppressed, so that the potential of the node N23 can be prevented from changing from the on-level during the period. In addition, the other configurations and effects of the second embodiment are the same as those of the first embodiment.

[0060] [Third Embodiment] Next, refer to Fig.10, the configuration of the gate drive circuit 320 according to the third embodiment is described. In the third embodiment, the transistors in the stabilization circuit 322a of the latch circuit 322 are cascade-connected. In addition, the same reference numerals are attached to the same configuration as the first embodiment and the description thereof is omitted. Fig.10 2 is a circuit diagram of a latch circuit 322 of a gate driving circuit 320 according to the second embodiment.

[0061] like Fig.10 As shown, the gate drive circuit 320 includes a latch circuit 322. A stabilization circuit 322a is provided in the latch circuit 322. The stabilization circuit 322a includes transistors T324a, T324b, T325a, T325b and T326. Transistor T326 is an example of the "fourth transistor" of the present disclosure. The drain electrode, source electrode and gate electrode of transistor T326 are examples of the "seventh electrode", "eighth electrode" and "fourth control electrode" of the present disclosure. Transistor T325a is an example of the "fifth transistor" of the present disclosure. The drain electrode, source electrode and gate electrode of transistor T325a are examples of the "ninth electrode", "tenth electrode" and "fifth control electrode" of the present disclosure. Transistor T325b is an example of the "sixth transistor" of the present disclosure. The drain electrode, source electrode and gate electrode of transistor T325b are examples of the "eleventh electrode", "twelfth electrode" and "sixth control electrode" of the present disclosure. The transistor T324a is an example of the "seventh transistor" of the present disclosure. The drain electrode, source electrode, and gate electrode of the transistor T324a are examples of the "thirteenth electrode", "fourteenth electrode", and "seventh control electrode" of the present disclosure. The transistor T324b is an example of the "eighth transistor" of the present disclosure. The drain electrode, source electrode, and gate electrode of the transistor T324b are examples of the "fifteenth electrode", "sixteenth electrode", and "eighth control electrode" of the present disclosure.

[0062] In addition, a node N324a and a node N324b are provided in the stabilization circuit 322a. The node N324a is an example of a "first intermediate node" of the present disclosure. The node N324b is an example of a "second intermediate node" of the present disclosure.

[0063] The drain electrode of the transistor T326 is connected to the node N22. The VSS signal is supplied to the source electrode of the transistor T326. The gate electrode of the transistor T326 is connected to the node N324a. In addition, the potential of the VSS signal is an example of the "first reference potential" of the present disclosure.

[0064] The drain electrode of the transistor T325a is connected to the node N324a. The VSS signal is supplied to the source electrode of the transistor T325a. The gate electrode of the transistor T325a is connected to the node N23.

[0065] The drain electrode of the transistor T325b is connected to the node N324b. The VSS signal is supplied to the source electrode of the transistor T325b. The gate electrode of the transistor T325b is connected to the node N23.

[0066] The VDD signal is supplied to the drain electrode of the transistor T324a. The source electrode of the transistor T324a is connected to the node N324a. The gate electrode of the transistor T324a is connected to the node N324b. In addition, the potential of the VDD signal is an example of the "second reference potential" of the present disclosure.

[0067] The VDD signal is supplied to the drain electrode and the gate electrode of the transistor T324b. The source electrode of the transistor T324b is connected to the node N324b.

[0068] According to the configuration of the third embodiment, a cascade connection including a node N324b is formed between the node N23 and the node N324a. Thus, during the period when the level of the node N324a is the cut-off level, it is possible to prevent the generation of a through current (intrusion of the VDD signal) at the node N324a, and to prevent noise from intruding into the transistor T326 connected to the node N324a. As a result, it is possible to prevent the characteristic of the transistor T326 from changing. In addition, the other configurations and effects of the third embodiment are the same as those of the first embodiment.

[0069] [Fourth Embodiment] Next, refer to Fig.11 , the configuration of the gate driving circuit 420 according to the fourth embodiment will be described. In the fourth embodiment, the latch circuit 422 is connected to the gate line 11. In addition, the same reference numerals are attached to the same configurations as those in the first embodiment, and the description thereof will be omitted. Fig.11 2 is a diagram showing a configuration of a gate driving circuit 420 according to a fourth embodiment.

[0070] like Fig.11 As shown, the gate drive circuit 420 includes a latch circuit 422. The latch circuit 422 is connected to the gate line 11. The latch circuit 422 constituting the nth stage outputs the output signal Qn to the gate line 11, the n+1th stage, and the n+2th stage shift register unit circuit 21. According to the configuration of the fourth embodiment, since the latch circuit 422 also serves as a circuit for driving the gate line 11, the gate drive circuit 420 can be miniaturized. In addition, the other configurations and effects of the fourth embodiment are the same as those of the first embodiment.

[0071] [Deformation, etc.] The above-mentioned embodiments are merely examples for implementing the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and the above-mentioned embodiments can be appropriately modified and implemented within the scope not departing from the gist thereof.

[0072] (1) In the first to fourth embodiments described above, an example in which a capacitive element (bootstrap condenser) is provided in a unit circuit is shown, but the present disclosure is not limited thereto. Fig.12 In the latch circuit 522 of the first modification shown, no capacitor is connected to the transistor T521. In this case, the function of the capacitor C2 in the first to fourth embodiments can be replaced by the capacitor component of the transistor T521.

[0073] (2) In the first to fourth embodiments described above, an example is shown in which VDD is supplied to the drain electrode of the transistor constituting the conduction circuit of the unit circuit, but the present disclosure is not limited to this. Fig.13 The transistor T622 of the latch circuit 622 of the second modification example shown may be diode-connected to the node N23 by inputting the LSET signal (output signal Qn-1) to the gate electrode and the drain electrode of the transistor T622.

[0074] (3) In the first to fourth embodiments described above, an example in which a touch detection function is provided on the display device is shown, but the present disclosure is not limited thereto. That is, the touch detection function may not be provided on the display device.

[0075] (4) In the first to fourth embodiments described above, an example in which four CLK signals are supplied to the gate drive circuit is shown, but the present disclosure is not limited thereto. That is, the number of CLK signals (number of phases) may be 3 or less, or 5 or more. In addition, the destinations of the SET signal and the RESET signal input as the output signal Q may be designed to be any level according to the number of CLK signals.

[0076] (5) In the first to fourth embodiments described above, an example is shown in which the display device is composed of a liquid crystal display panel including a liquid crystal layer, but the present disclosure is not limited thereto. For example, the display device may be composed of an organic EL (Electro Luminescence) display panel.

[0077] (6) In the first to fourth embodiments, the capacitance of the capacitor C3 is larger than that of the capacitor C2, but the present disclosure is not limited thereto. The capacitance of the capacitor C3 may be smaller than that of the capacitor C2.

[0078] The control method of the driving circuit, display device, and embedded touch panel device can also be described as follows.

[0079] The first structure involves a driving circuit composed of a plurality of stages, and the driving circuit supplies driving signals to a scanning signal line group according to a plurality of clock signals inputted thereto, and has a plurality of unit circuits constituting each of the plurality of stages, wherein the plurality of unit circuits include: a shift register unit circuit, which is a shift register unit circuit connected to a scanning signal line in the scanning signal line group, and supplies an output signal to the scanning signal line and a subsequent stage of the shift register unit circuit; a latch circuit, which is a latch circuit that holds the output signal inputted from a previous stage during a stop period in which the supply of the plurality of clock signals is stopped and the operation of the driving circuit is stopped, and supplies an output signal to a subsequent stage of the latch circuit at the end of the stop period, wherein the latch circuit includes: a signal holding node; a conduction circuit that changes the level of the signal holding node from an off level to an on level based on the output signal inputted from the preceding stage; a first output node, which is connected to the subsequent stage; a first crystal A body tube, which has a first electrode supplied with a first control signal at the end of the stop period, a second electrode connected to the first output node, and a first control electrode; a second output node connected to the first control electrode; a second transistor, which has a third electrode connected to the signal holding node; a fourth electrode connected to the second output node; and a second control electrode supplied with a second control signal, the second control signal being supplied after a time point when the stop period has started and before a time point when the first control signal is supplied to the first electrode, the second transistor turns on the signal holding node and the second output node by supplying the second control signal to the second control electrode, the first transistor is turned on through the signal holding node and the second output node, the level of the second output node changes from a cut-off level to a conduction level, thereby supplying the first control signal as an output signal to the first output node (a first configuration).

[0080] According to the first configuration, during the stop period when the operation of the driving circuit is stopped, the first control electrode of the first transistor of the latch circuit is disconnected from the signal holding node that maintains the on-level. Thus, it is possible to prevent the on-level voltage from being continuously applied to the first control electrode of the first transistor during the stop period. As a result, it is possible to prevent the characteristics of the first transistor of the latch circuit from changing.

[0081] In the above-mentioned first configuration, the latch circuit may include a first capacitive element connected to the signal holding node (second configuration).

[0082] According to the second configuration, when the signal holding node and the second output node are connected, the electric charge accumulated in the first capacitor element can be used to change the potential of the second output node.

[0083] In the second configuration, the latch circuit may include a second capacitor connected to the second output node. The capacitance of the first capacitor may be greater than the capacitance of the second capacitor (third configuration).

[0084] According to the third configuration, since the amount of charge accumulated in the first capacitor element increases, the second capacitor element connected to the second output node can be sufficiently charged.

[0085] In any one of the first to third configurations described above, the latch circuit further includes: an input node supplied with a third control signal which becomes an on-level during at least a portion of the stop period; and a third transistor having a fifth electrode connected to the signal holding node, a sixth electrode connected to the input node, and a third control electrode to which an output signal from a stage later than the latch circuit is input (fourth configuration).

[0086] According to the fourth configuration, the potential difference between the fifth electrode and the sixth electrode of the third transistor can be reduced during at least a portion of the stop period. As a result, the off-leakage through the third transistor can be suppressed, thereby preventing the potential of the signal holding node from changing from the on-level during this period.

[0087] In any one of the first to fourth configurations described above, the latch circuit may also include: a first intermediate node and a second intermediate node; a fourth transistor having a seventh electrode connected to the second output node, an eighth electrode connected to the first reference potential, and a fourth control electrode connected to the first intermediate node; a fifth transistor having a ninth electrode connected to the first intermediate node, a tenth electrode connected to the first reference potential, and a fifth control electrode connected to the signal holding node; a sixth transistor having an eleventh electrode connected to the second intermediate node, a twelfth electrode connected to the first reference potential, and a sixth control electrode connected to the signal holding node; a seventh transistor having a thirteenth electrode connected to the second reference potential, a fourteenth electrode connected to the second intermediate node, and a seventh control electrode connected to the second reference potential; an eighth transistor having a fifteenth electrode connected to the second reference potential, a sixteenth electrode connected to the first intermediate node, and an eighth control electrode connected to the second intermediate node (fifth configuration).

[0088] According to the fifth configuration, a cascade connection including the second intermediate node is formed between the signal holding node and the first intermediate node. Thus, it is possible to prevent a through current from the second reference potential to the first intermediate node, and to prevent noise from intruding into the fourth transistor connected to the first intermediate node. As a result, it is possible to prevent the characteristics of the fourth transistor from changing.

[0089] In any one of the first to fifth configurations, the first output node may be connected to any one scanning signal line in the scanning signal line group and the subsequent stage (sixth configuration).

[0090] According to the sixth configuration, since the latch circuit also serves as a circuit for driving the scanning signal line, the driving circuit can be miniaturized.

[0091] In any one of the first to fifth configurations, the first output node may be connected to the subsequent stage instead of the scanning signal line group (seventh configuration).

[0092] According to the seventh configuration, even when the characteristics of the first transistor of the latch circuit change, the latch circuit is not connected to the scanning signal line group, and therefore the change in the characteristics of the first transistor does not affect display.

[0093] A display device according to an eighth configuration includes: the drive circuit according to any one of the first to seventh configurations; and a display provided with the scanning signal line group (eighth configuration).

[0094] According to the eighth configuration, it is possible to provide a display device capable of preventing a change in characteristics of a transistor in a latch circuit.

[0095] The in-cell touch panel device according to the ninth configuration includes: the driving circuit according to any one of the first to seventh configurations; and an in-cell touch panel provided with the scanning signal line group, and detecting a touch of a pointer during the stop period (ninth configuration).

[0096] According to the ninth configuration, it is possible to provide an in-cell touch panel device capable of preventing a characteristic change of a transistor in a latch circuit. Description of Reference Numerals

[0097] 1: touch panel, 2: control circuit, 10: display unit, 11: gate line, 12: source line, 13: transistor, 13a: gate electrode, 13b: source electrode, 13c: drain electrode, 14: pixel electrode, 15: common electrode, 16: wiring, 20: gate drive circuit, 21: shift register unit circuit, 21a: stabilization circuit, 21b: stabilization circuit, 22: latch circuit, 22a: stabilization circuit, 22b: stabilization circuit, 30: source drive circuit, 40: touch detection control circuit, 10 0: display device, 200: display device, 220: gate drive circuit, 222: latch circuit, 320: gate drive circuit, 322: latch circuit, 322a: stabilization circuit, 420: gate drive circuit, 422: latch circuit, 522: latch circuit, 622: latch circuit, C1: capacitor element, C2: capacitor element, C3: capacitor element, Lout: output signal, N11: node, N12: node, N13: node, N21: node, N22: node, N221: node point, N23: node, N24: node, N324a: node, N324b: node, Q: output signal, Qm: output signal, Qn: output signal, Qn-1: output signal, T11: transistor, T12: transistor, T13: transistor, T14: transistor, T15: transistor, T16: transistor, T17: transistor, T18: transistor, T21: transistor, T21d: drain electrode, T21g: gate electrode, T21s: source electrode, T22: transistor, T223a : transistor, T23: transistor, T23a: transistor, T23b: transistor, T24: transistor, T25: transistor, T26: transistor, T27: transistor, T28: transistor, T28d: drain electrode, T28g: gate electrode, T28s: source electrode, T324a: transistor, T324b: transistor, T325a: transistor, T326: transistor, T521: transistor, T622: transistor, TD: display period, TP: touch detection period, TR: stop period

Claims

1. A driving circuit, which is composed of a plurality of stages and supplies a driving signal to a scanning signal line group according to a plurality of clock signals input, wherein the driving circuit is characterized in that: A plurality of unit circuits constituting each of the plurality of stages are provided, the plurality of unit circuits including: a shift register unit circuit connected to one scanning signal line in the scanning signal line group, and supplying an output signal to the scanning signal line and a subsequent stage of the shift register unit circuit; as well as a latch circuit that holds the output signal input from a previous stage during a stop period in which the supply of the plurality of clock signals is stopped and the operation of the drive circuit is stopped, and supplies the output signal to a subsequent stage of the latch circuit at the end of the stop period, The latch circuit comprises: a signal holding node; a conduction circuit for changing the level of the signal holding node from an off-level to an on-level based on the output signal input from the preceding stage; a first output node connected to the subsequent stage; a first transistor having a first electrode supplied with a first control signal when the stop period ends, a second electrode connected to the first output node, and a first control electrode; a second output node connected to the first control electrode; as well as a second transistor having: a third electrode connected to the signal holding node; and a fourth electrode connected to the second output node; and a second control electrode supplied with a second control signal, the second control signal being supplied after a time point at which the stop period has started and before a time point at which the first control signal is supplied to the first electrode, The second transistor conducts the signal holding node and the second output node by supplying the second control signal to the second control electrode. The first transistor is turned on through the signal holding node and the second output node, and the level of the second output node is changed from an off level to an on level, thereby supplying the first control signal to the first output node as an output signal.

2. The driving circuit according to claim 1, characterized in that: The latch circuit includes a first capacitive element connected to the signal holding node.

3. The driving circuit according to claim 2, characterized in that: The latch circuit includes a second capacitive element connected to the second output node, The capacitance of the first capacitance element is greater than the capacitance of the second capacitance element.

4. The driving circuit according to any one of claims 1 to 3, characterized in that: The latch circuit further comprises: an input node to which a third control signal which is turned into an on level during at least a part of the stop period is supplied; and The third transistor has a fifth electrode connected to the signal holding node, a sixth electrode connected to the input node, and a third control electrode to which an output signal from a stage subsequent to the latch circuit is input.

5. The driving circuit according to any one of claims 1 to 3, characterized in that: The latch circuit comprises: a first intermediate node and a second intermediate node; a fourth transistor having a seventh electrode connected to the second output node, an eighth electrode connected to the first reference potential, and a fourth control electrode connected to the first intermediate node; a fifth transistor having a ninth electrode connected to the first intermediate node, a tenth electrode connected to the first reference potential, and a fifth control electrode connected to the signal holding node; a sixth transistor having an eleventh electrode connected to the second intermediate node, a twelfth electrode connected to the first reference potential, and a sixth control electrode connected to the signal holding node; a seventh transistor having a thirteenth electrode connected to the second reference potential, a fourteenth electrode connected to the second intermediate node, and a seventh control electrode connected to the second reference potential; and The eighth transistor has a fifteenth electrode connected to the second reference potential, a sixteenth electrode connected to the first intermediate node, and an eighth control electrode connected to the second intermediate node.

6. The driving circuit according to any one of claims 1 to 3, characterized in that: The first output node is connected to any one scanning signal line in the scanning signal line group and the subsequent stage.

7. The driving circuit according to any one of claims 1 to 3, characterized in that: The first output node is not connected to the scanning signal line group but is connected to the subsequent stage.

8. A display device, characterized in that: include: The driving circuit according to claim 1; as well as A display is provided with the scanning signal line group.

9. An embedded touch panel device, characterized in that: include: The driving circuit according to claim 1; as well as The in-cell touch panel is an in-cell touch panel provided with the scanning signal line group, and detects a touch of a pointer during the stop period.

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