Clock data recovery circuit, display chip and display equipment

Abstract

The invention provides a clock data recovery circuit, a display chip and a display device, a differential-to-single circuit converts a differential data signal into a single-ended data signal, a frequency division module performs frequency division on the single-ended data signal and a sampling clock signal at a preset phase to generate a first frequency division signal and a second frequency division signal, and the first frequency division signal and the second frequency division signal are transmitted to the display chip. The digital controller compares a first phase signal obtained by the first frequency division signal with a second phase signal obtained by the second frequency division signal, and outputs a frequency control signal or a switching control signal after generating a phase error; the clock signal generation module generates a plurality of sampling clock signals based on a first current signal output by the current source circuit based on the frequency control signal, or generates a target clock signal after generating a second current signal based on the switching control signal. The control signal or the switching control signal is output based on the phase error ratio and the frequency error, when the data signal transmission rate is high, a high-precision digital controller is not needed, and the design difficulty is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a clock data recovery circuit, a display chip and a display device. Background Art

[0002] With the development of display technology, the requirements for the resolution, color gamut and refresh rate of display devices are getting higher and higher, which leads to a significant increase in the amount of data that display devices need to process and the data transmission rate. In high-speed serial data transmission, the integrity and accuracy of data are crucial to display quality. In order to ensure that the data signal can be read and recovered correctly, the receiving end needs to use a clock and data recovery (CDR) circuit to synchronize the data transmission frequency and recover the clock signal.

[0003] The CDR circuit provided by the related technology, the digital controller in the CDR circuit detects the frequency of the data signal and the frequency of the sampling clock signal at a preset phase, that is, detects the difference between the frequency of the data signal and the frequency of the sampling clock signal at a preset phase. As the transmission frequency of the data signal increases, the above difference will also change accordingly. The higher the transmission frequency of the data signal, the higher the comparison accuracy requirement for the digital controller. Summary of the invention

[0004] The present application provides a clock data recovery circuit, a display chip and a display device, which are used to solve the problem in the prior art that as the transmission frequency of data signals increases, the comparative accuracy requirements of a digital controller in the clock data recovery circuit are high.

[0005] In a first aspect, the present application provides a clock data recovery circuit, comprising: A differential-to-single-ended circuit, used for converting an input differential data signal into a single-ended data signal; A frequency division module, configured to divide the single-ended data signal based on a first frequency division value to generate a first frequency division signal, and to divide the sampling clock signal at a preset phase among a plurality of sampling clock signals based on a second frequency division value to generate a second frequency division signal, wherein the first frequency division value is greater than the second frequency division value; A digital controller, configured to compare a first phase signal and a second phase signal to generate a phase error, wherein the first phase signal is obtained based on the first frequency-divided signal, and the second phase signal is obtained based on the second frequency-divided signal; and output a frequency control signal or a switching control signal based on the phase error; a current source circuit, configured to generate a first current signal based on the frequency control signal; The clock signal generating module is used to generate the plurality of sampling clock signals based on the first current signal, or to generate a second current signal under the control of the switching control signal, and to generate a target clock signal based on the second current signal.

[0006] In a possible implementation, the digital controller is further used for: Performing phase conversion on the first frequency-divided signal based on the first frequency-divided value to obtain the first phase signal, and performing phase conversion on the second frequency-divided signal based on the second frequency-divided value to obtain the second phase signal, wherein the first phase signal includes a first-bit digital signal, and the second phase signal includes a second-bit digital signal; The digital controller is specifically used for: The phase error is generated based on the first bit and the second bit.

[0007] In a possible implementation manner, in each cycle of the first frequency-divided signal, the digital controller is specifically configured to: When it is determined that the absolute value of the phase error is less than a second preset value, outputting the switching control signal; When it is determined that the absolute value of the phase error is greater than or equal to the second preset value, the frequency control signal is output.

[0008] In a possible implementation, the current source circuit includes a first current source branch and a second current source branch, the frequency control signal includes a first frequency control signal and a second frequency control signal, and the digital controller is specifically used for: When it is determined that the absolute value of the phase error is greater than or equal to a first preset value, adjusting the current first frequency control signal, and outputting the adjusted first frequency control signal; The current source circuit is specifically used for: Based on the adjusted first frequency control signal, adjusting the number of first current sources operating in the first current source branch; When it is determined that the absolute value of the phase error is greater than or equal to the second preset value and less than the first preset value, adjusting the current second frequency control signal and outputting the adjusted second frequency control signal; The current source circuit is specifically used for: adjusting the number of second current sources operating in the second current source branch based on the adjusted second frequency control signal; The current value of the output current of the first current source in the first current source branch is greater than the current value of the output current of the second current source in the second current source branch.

[0009] In a possible implementation manner, after the digital controller outputs the adjusted first frequency control signal, the digital controller is further configured to: When it is determined that the next phase error is less than the first preset value, keeping the first frequency control signal unchanged; Determining whether the absolute value of the next phase error is greater than or equal to the second preset value; When the absolute value of the next phase error is greater than or equal to the second preset value, adjusting the current second frequency control signal, and outputting the adjusted second frequency control signal; When the absolute value of the next phase error is smaller than the second preset value, the switching control signal is output.

[0010] In a possible implementation manner, after keeping the first frequency control signal unchanged, and before determining in the next cycle of the first frequency-divided signal that the absolute value of the next phase error is greater than or equal to the second preset value, the digital controller is further used to: After determining that the current cycle of the first frequency-divided signal ends, in each cycle of a preset number of consecutive cycles, when determining that the phase error is less than the first preset value, keeping the first frequency control signal unchanged, wherein the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first frequency-divided signal.

[0011] In a possible implementation manner, the current source circuit is specifically used for: If the absolute value of the phase error is greater than or equal to a first preset value, and the phase error is a positive number, increasing the number of first current sources operating in the first current source branch based on the first frequency control signal; If the absolute value of the phase error is greater than or equal to a first preset value and the phase error is a negative number, the number of first current sources operating in the first current source branch is reduced according to the first frequency control signal.

[0012] In a possible implementation, after outputting the second frequency control signal, the digital controller is further used to: When it is determined that the absolute value of the next phase error is less than the second preset value, the second frequency control signal is kept unchanged, and the switching control signal is output; When the absolute value of the next phase error is greater than or equal to the second preset value, the current second frequency control signal is adjusted, and the adjusted second frequency control signal is output.

[0013] In a possible implementation manner, after keeping the second frequency control signal unchanged, and before determining in the next cycle of the first frequency-divided signal that the absolute value of the next phase error is greater than or equal to the second preset value, the digital controller is further used to: After determining that the current cycle of the first frequency-divided signal ends, in each cycle of a preset number of consecutive cycles, when determining that the absolute value of the phase error in each cycle is less than the second preset value, keeping the second frequency control signal unchanged, wherein the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first frequency-divided signal.

[0014] In a possible implementation manner, after the phase error is generated, the digital controller is further used to: Based on the error accuracy selection signal, the phase error is calculated to obtain a phase selection error; The digital controller is specifically used for: Based on the phase selection error, the frequency control signal or the switching control signal is output.

[0015] In a second aspect, the present application provides a display chip, comprising a clock data recovery circuit as described in any one of the first aspects.

[0016] In a third aspect, the present application provides a display device, comprising the display chip as described in the second aspect.

[0017] The beneficial effects of this application are as follows: The present application provides a clock data recovery circuit, a display chip and a display device, in which a differential-to-single circuit converts a differential data signal into a single-ended data signal, a frequency division module divides the single-ended data signal and a sampling clock signal at a preset phase based on first and second frequency division values, respectively, to generate first and second frequency division signals, a digital controller compares a first phase signal obtained based on the first frequency division signal and a second phase signal obtained based on the second frequency division signal, generates a phase error, and outputs a frequency control signal or a switching control signal accordingly; a current source circuit outputs a first current signal based on the frequency control signal; a clock signal generation module generates multiple sampling clock signals based on the first current signal, or generates a second current signal based on the switching control signal, and then generates a target clock signal. In the above manner, when the data signal transmission rate is high, the performance and accuracy of the digital controller are enhanced, and the design difficulty is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A schematic diagram of the structure of a clock data recovery circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a clock signal generation module provided in an embodiment of the present application; Figure 3 A circuit diagram of a phase detector provided in an embodiment of the present application; Figure 4 A circuit diagram of a charge pump and a low-pass filter provided in an embodiment of the present application; Figure 5 A circuit diagram of a voltage-to-current converter provided in an embodiment of the present application; Figure 6 A circuit diagram of a voltage-controlled oscillator provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a digital controller provided in an embodiment of the present application; Figure 8 A circuit diagram of a current source circuit provided in an embodiment of the present application; Fig. 9 A schematic diagram of the working process of a digital controller provided in an embodiment of the present application; Fig.10 A schematic diagram of another working process of a digital controller provided in an embodiment of the present application; Fig.11 A workflow diagram of a digital controller provided in an embodiment of the present application; Fig.12 A schematic diagram of the structure of another digital controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0022] The clock and data recovery (CDR) circuit based on a single-loop system provided in the related art has no reference clock signal and is locked based on the frequency of an input data signal.

[0023] For example, the clock data recovery circuit disclosed in the publication number CN115714596B includes a digital controller, which inputs a data signal Din and a sampling clock signal Clki at a preset phase among a plurality of sampling clock signals output by a voltage-controlled oscillator, and compares the frequency of the data signal Din with the frequency of the sampling clock signal Clki at the preset phase. When the transmission rate is high, the frequency of the data signal Din and the frequency of the pre-sampling clock signal are also high, the frequency becomes larger, and the period becomes smaller. In order to achieve high-frequency comparison of the data signal, higher requirements are placed on the performance of the digital controller, which increases the design difficulty.

[0024] In order to solve the above problems, an embodiment of the present application provides a clock data recovery circuit, a display chip and a display device. For ease of understanding, the clock data recovery circuit, the display chip and the display device provided in the embodiment of the present application are described in detail below in conjunction with the accompanying drawings.

[0025] like Figure 1 , which is a schematic diagram of the structure of a clock data recovery circuit provided in an embodiment of the present application, wherein the clock data recovery circuit includes a differential-to-single circuit 11, a frequency division module 12, a digital controller 13, a current source circuit 14 and a clock signal generation module 15; The differential-to-single-ended circuit 11 is used to convert the input differential data signal (positive phase differential signal Din_P and negative phase differential signal Din_N) into a single-ended data signal Din; The frequency division module 12 is used to divide the single-ended data signal Din based on a first frequency division value to generate a first frequency division signal F_Din, and to divide the sampling clock signal Clki at a preset phase among a plurality of sampling clock signals based on a second frequency division value to generate a second frequency division signal F_Clki, wherein the first frequency division value is greater than the second frequency division value; The digital controller 13 is used to compare the first phase signal Ph_CKR and the second phase signal Ph_CKV to generate a phase error ph_err, wherein the first phase signal Ph_CKR is obtained based on the first frequency-divided signal F_Din, and the second phase signal Ph_CKV is obtained based on the second frequency-divided signal F_Clki; based on the phase error ph_err, output a frequency control signal or a switching control signal Mode_Switch; The current source circuit 14 is used to output a first current signal based on the frequency control signal; The clock signal generating module 15 is used to generate a plurality of sampling clock signals (Clk1, ... Clki, ... Clkn) based on the first current signal, or to generate a second current signal under the control of the switching control signal Mode_Switch, and to generate a target clock signal based on the second current signal.

[0026] It should be noted that the differential data signals (Din_P and Din_N) in the embodiment of the present application are sent externally.

[0027] The present application provides a clock data recovery circuit, which includes a differential-to-single-ended circuit, a frequency division module, a digital controller, a current source circuit and a clock signal generation module. The differential-to-single-ended circuit converts an input differential data signal into a single-ended data signal. The frequency division module divides the single-ended data signal based on a first frequency division value to generate a first frequency division signal, and divides a sampling clock signal at a preset phase in a plurality of sampling clock signals based on a second frequency division value to generate a second frequency division signal. The digital controller compares the first phase signal and the second phase signal to generate a phase error, and outputs a frequency control signal or a switching control signal based on the phase error, wherein the first phase signal is obtained based on the first frequency division signal, and the second phase signal is obtained based on the second frequency division signal. The current source circuit outputs a first current signal based on the frequency control signal. The clock signal generation module generates a plurality of sampling clock signals based on the first current signal, or generates a second current signal under the control of the switching control signal, and generates a target clock signal based on the second current signal.

[0028] In the embodiment of the present application, the single-ended data signal is first divided to generate a first divided signal, the sampling clock signal at the preset phase is divided to generate a second divided signal, and then the first phase signal is obtained based on the first divided signal, and the second phase signal is obtained based on the second divided signal. The first phase signal and the second phase signal are compared to generate a phase error. The single-ended data signal Din and the sampling clock signal Clki are divided by the frequency division module 12, and the frequencies of the single-ended data signal Din and the sampling clock signal Clki are reduced, so that the frequency required for comparison by the digital controller is reduced; because in the digital controller, the higher the comparison frequency, the higher the performance requirements for the digital controller, so the performance requirements for the digital controller are reduced in the present application. In addition, the phase conversion is performed on the reduced frequency, and then the phase error is detected, so that the detection of the phase error is easier to achieve and the detection accuracy is higher. When the frequency is high and the frequencies of the two are close, it is difficult to detect the frequency error between the two. At this time, a high-precision frequency detector is required to accurately detect the frequency error. Therefore, compared with outputting a frequency control signal or a switching control signal based on a frequency error, outputting a frequency control signal or a switching control signal based on a phase error does not require a higher-precision digital controller when the data signal transmission rate is high, thereby reducing the design difficulty of the digital controller.

[0029] The clock signal generating module 15 provided in the embodiment of the present application includes a phase detector 151, a charge pump 152, a low-pass filter 153, a voltage-to-current converter 154 and a voltage-controlled oscillator 155. Figure 2 As shown, the phase detector 151, the charge pump 152, the low-pass filter 153, the voltage-to-current converter 154 and the voltage-controlled oscillator 155 are electrically connected in sequence; the input end of the voltage-to-current converter 154 is also electrically connected to the digital controller 13; the input end of the voltage-controlled oscillator 155 is also electrically connected to the output end of the current source circuit 14, and the output end of the voltage-controlled oscillator 155 is electrically connected to the input end of the phase detector 151 and the input end of the frequency division module 12.

[0030] In a specific implementation, the phase detector 151 is used to receive the differential data signal (Din_P and Din_N) and a plurality of sampling clock signals (Clk1, ...Clki, ...Clkn) output by the voltage-controlled oscillator 155, and respectively compare the phase of the differential data signal (Din_P and Din_N) with the phase of each sampling clock signal (Clk1, ...Clki, ...Clkn), and output a pull-up pulse signal or a pull-down pulse signal; A charge pump 152, used to generate a low-frequency control signal according to the pull-up pulse signal or the pull-down pulse signal; A low-pass filter 153, used to filter the low-frequency control signal to generate a phase control signal; The voltage-to-current converter 154 is used to output a second current signal according to the phase control signal under the control of the switching control signal output by the digital controller 13; The voltage controlled oscillator 155 is used to output a plurality of sampling clock signals (Clk1 , . . . Clki, . . . Clkn) according to the first current signal output by the current source circuit 14 , or to output a target clock signal according to the second current signal output by the voltage-to-current converter 154 .

[0031] In the embodiment of the present application, the phase detector 151 includes multiple input terminals, and the multiple input terminals are used to receive the positive phase differential signal Din_P, the negative phase differential signal Din_N and multiple sampling clock signals (Clk1, ...Clki, ...Clkn) output by the voltage controlled oscillator 155.

[0032] like Figure 3, which is a circuit diagram of a phase detector 151, wherein the phase detector 151 includes a first latch L1, a second latch L2, a third latch L3, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a first XOR gate XOR1 and a second XOR gate XOR2, wherein a positive phase input terminal of the first latch L1 is electrically connected to a positive phase input terminal of the second latch L2 and a positive phase input terminal of the third latch L3, respectively, for inputting a positive phase differential signal Din_P, an inverting input terminal of the first latch L1 is electrically connected to an inverting input terminal of the second latch L2 and an inverting input terminal of the third latch L3, respectively, for inputting an inverted phase differential signal Din_N, and the first latch L The positive phase output terminal of the first latch L1 is electrically connected to the positive phase input terminal of the first D flip-flop D1, the inverting output terminal of the first latch L1 is electrically connected to the inverting input terminal of the first D flip-flop D1, the clock terminal of the first latch L1 is electrically connected to the first output terminal EClk of the voltage controlled oscillator 155, the positive phase output terminal of the first D flip-flop D1 is electrically connected to the first input terminal of the second XOR gate XOR2, the inverting output terminal of the first D flip-flop D1 is electrically connected to the second input terminal of the second XOR gate XOR2, the clock terminal of the first D flip-flop D1 is electrically connected to the first output terminal EClk of the voltage controlled oscillator 155, the positive phase output terminal of the second latch L2 is electrically connected to the positive phase input terminal of the second D flip-flop D2, and the second latch L2 is electrically connected to the positive phase input terminal of the second D flip-flop D2. The inverting output terminal of the third latch L2 is electrically connected to the inverting input terminal of the second D flip-flop D2, the clock terminal of the second latch L2 is electrically connected to the second output terminal DClk of the voltage-controlled oscillator 155, the positive phase output terminal of the second D flip-flop D2 is electrically connected to the first input terminal of the first XOR gate XOR1 and the second input terminal of the second XOR gate XOR2, the inverting output terminal of the second D flip-flop D2 is electrically connected to the second input terminal of the first XOR gate XOR1 and the first input terminal of the second XOR gate XOR2, the clock terminal of the second D flip-flop D2 is electrically connected to the second output terminal DClk of the voltage-controlled oscillator 155, and the positive phase output terminal of the third latch L3 is electrically connected to the positive phase input terminal of the third D flip-flop D3. The inverting output terminal of the third latch L3 is electrically connected to the inverting input terminal of the third D flip-flop D3, the clock terminal of the third latch L3 is electrically connected to the third output terminal LClk of the voltage-controlled oscillator 155, the positive output terminal of the third D flip-flop D3 is electrically connected to the second input terminal of the first XOR gate XOR1, the inverting output terminal of the third D flip-flop D3 is electrically connected to the first input terminal of the first XOR gate XOR1, the clock terminal of the third D flip-flop D3 is electrically connected to the third output terminal LClk of the voltage-controlled oscillator 155, the output terminal of the first XOR gate XOR1 is electrically connected to the first input terminal of the charge pump 152, and the output terminal of the second XOR gate XOR2 is electrically connected to the second input terminal of the charge pump 152.

[0033] In the phase detector 151, the first latch L1 and the first D flip-flop D1 together constitute a first sampler, the second latch L2 and the second D flip-flop D2 together constitute a second sampler, and the third latch L3 and the third D flip-flop D3 together constitute a third sampler. The first sampler samples the positive phase differential signal Din_P and the negative phase differential signal Din_N according to the first sampling clock signal EClk, outputs the first positive phase sampling signal EOUT<0,1> to the first input end of the second XOR gate XOR2, and outputs the first negative phase sampling signal EOUTB<0,1> to the second input end of the second XOR gate XOR2; the second sampler samples the positive phase differential signal Din_P and the negative phase differential signal Din_N according to the second sampling clock signal DClk. The differential signal Din_N is sampled, and a second positive phase sampling signal DOUT<0,1> is output to the first input terminal of the first XOR gate XOR1 and the second input terminal of the second XOR gate XOR2, and a second negative phase sampling signal DOUTB<0,1> is output to the second input terminal of the first XOR gate XOR1 and the first input terminal of the second XOR gate XOR2; the third sampler samples the positive phase differential signal Din_P and the negative phase differential signal Din_N according to the third sampling clock signal LClk, and outputs a third positive phase sampling signal LOUT<0,1> to the second input terminal of the first XOR gate XOR1, and outputs a third negative phase sampling signal LOUTB<0,1> to the first input terminal of the first XOR gate XOR1. The first XOR gate XOR1 performs XOR processing on the input sampling signal and outputs a pull-up pulse signal UP<0,1> to the first input terminal of the charge pump 152; the second XOR gate XOR2 performs XOR processing on the input sampling signal and outputs a pull-down pulse signal DN<0,1> to the second input terminal of the charge pump 152.

[0034] It should be noted that Figure 3 The multiple sampling clock signals output by the medium voltage controlled oscillator 155 include a first sampling clock signal EClk, a second sampling clock signal DClk and a third sampling clock signal LClk, which is an example description, and the number and type of the sampling clock signals are not specifically limited in this application.

[0035] Specifically, Figure 4As shown, it is a circuit schematic diagram of a charge pump 152 and a low-pass filter 153 provided in an embodiment of the present application, wherein the charge pump 152 includes a pull-up current source S1, a pull-down current source S2, a first switch K1 and a second switch K2, wherein a first end of the pull-up current source S1 is electrically connected to a power supply voltage end VDD, a second end of the pull-up current source S1 is electrically connected to one end of the first switch K1, a control end of the first switch K1 is electrically connected to a first output end of a phase detector 151 as a first input end of the charge pump 152, the other end of the first switch K1 is electrically connected to one end of a second switch K2 as an output end of the charge pump 152, a control end of the second switch K2 is electrically connected to a second output end of the phase detector 151 as a second input end of the charge pump 152, the other end of the second switch K2 is electrically connected to a first end of the pull-down current source S2, and a second end of the pull-down current source S2 is grounded.

[0036] In the charge pump 152, the pull-up current source S1 serves as the pull-up current source of the charge pump 152, and the pull-down current source S2 serves as the pull-down current source of the charge pump 152. When the first output end of the phase detector 151 outputs the pull-up pulse signal UP<0,1>, the first switch K1 is closed to enable the pull-up current source S1 to work, convert the high-frequency pull-up pulse signal UP<0,1> into a low-frequency control signal, and output it to the low-pass filter 153; when the second output end of the phase detector 151 outputs the pull-down pulse signal DN<0,1>, the second switch K2 is closed to enable the pull-down current source S2 to work, convert the high-frequency pull-down pulse signal DN<0,1> into a low-frequency control signal, and output it to the low-pass filter 153.

[0037] like Figure 4 As shown, the low-pass filter 153 includes a first resistor R1 and a first capacitor C1, wherein one end of the first resistor R1 is electrically connected to the output end of the charge pump 152, the other end of the first resistor R1 is electrically connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded. The low-pass filter 153 is used to filter high-frequency noise signals in the circuit, that is, to filter the low-frequency control signal and output a phase control signal.

[0038] like Figure 5, which is a circuit diagram of a voltage-to-current converter 154 provided in an embodiment of the present application. The voltage-to-current converter 154 includes a transmission gate G1, a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6 and a seventh switch tube M7. The forward control end of the transmission gate G1 is electrically connected to the output end of the first inverter INV1, the input end of the first inverter INV1 is electrically connected to the first output end of the digital controller 13, and the reverse control end of the transmission gate G1 is electrically connected to the first output end of the digital controller 13. As the control end of the voltage-to-current converter 154, the input end of the transmission gate G1 is electrically connected to the output end of the low-pass filter 153 and the control end of the first switch tube M1, respectively. As the input end of the voltage-to-current converter 154, the output end of the transmission gate G1 is electrically connected to the control end of the second switch tube M2. The first end of the switch tube M1 is electrically connected to the first end of the second switch tube M2 and the second end of the seventh switch tube M7, respectively; the second end of the first switch tube M1 is electrically connected to the second end of the third switch tube M3 and the control end of the third switch tube M3, respectively; the second end of the second switch tube M2 is electrically connected to the second end of the fourth switch tube M4, the control end of the fourth switch tube M4 and the control end of the fifth switch tube M5, respectively; the first end of the third switch tube M3 is electrically connected to the first end of the fourth switch tube M4, the first end of the fifth switch tube M5 and the power supply voltage terminal VDD, respectively; the second end of the fifth switch tube M5 is electrically connected to the control end of the sixth switch tube M6 as the output end of the voltage-current converter 154; the first end of the sixth switch tube M6 is electrically connected to the second end of the sixth switch tube M6, the first end of the seventh switch tube M7 and the ground, respectively; and the control end of the seventh switch tube M7 is electrically connected to the bias voltage terminal VBIAS.

[0039] It should be noted that the first inverter INV1 may be in the digital controller 13 or in the voltage-to-current converter 154 , and the present application does not impose any specific limitation on the location of the first inverter INV1 .

[0040] The forward control end of the transmission gate G1 and the reverse control end of the transmission gate G1 are anti-phase signals. For example, if the forward control end of the transmission gate G1 is 0, the reverse control end of the transmission gate G1 is 1, and the transmission gate G1 is turned on; if the forward control end of the transmission gate G1 is 1, the reverse control end of the transmission gate G1 is 0, and the transmission gate G1 is turned off.

[0041] In the voltage-current converter 154, the fourth switch tube M4 and the fifth switch tube M5 form a current mirror. Before the digital controller 13 outputs the switching control signal Mode_Switch, the forward control terminal of the transmission gate G1 is at a high level, the reverse control terminal of the transmission gate G1 is at a low level, and the transmission gate G1 is disconnected. At this time, the positive phase differential voltage signal VCON input to the second switch tube M2 and the negative phase differential voltage signal VCOP input to the first switch tube M1 remain equal, then the current output from the control terminal of the fourth switch tube M4 remains unchanged, the fifth switch tube M5 copies the current output from the control terminal of the fourth switch tube M4, and uses the current as the second current signal I2, and outputs the second current signal I2 to the input terminal of the voltage-controlled oscillator 155 through the second terminal of the fifth switch tube M5. During this period, since the second current signal I2 remains unchanged, the phase of the sampling clock signal output by the voltage-controlled oscillator 155 does not change. After the digital controller 13 outputs the switching control signal Mode_Switch, the forward control terminal of the transmission gate G1 is at a low level, the reverse control terminal of the transmission gate G1 is at a high level, and the transmission gate G1 is turned on. At this time, the positive phase differential voltage signal VCON input to the second switch tube M2 and the negative phase differential voltage signal VCOP input to the first switch tube M1 are not equal, so the current output from the control terminal of the fourth switch tube M4 changes, and the fifth switch tube M5 copies the current output from the control terminal of the fourth switch tube M4, and uses the current as the second current signal I2, and outputs the second current signal I2 to the input terminal of the voltage controlled oscillator 155 through the second terminal of the fifth switch tube M5, so that the voltage controlled oscillator 155 adjusts the phase of the output sampling clock signal according to the change of the second current signal I2. For example, if the positive phase differential voltage signal VCON is greater than or equal to the negative phase differential voltage signal VCOP, the second current signal I2 output from the second terminal of the fifth switch tube M5 also increases accordingly.

[0042] like Figure 6As shown, it is a circuit diagram of a voltage-controlled oscillator 155 provided in an embodiment of the present application, wherein the voltage-controlled oscillator 155 includes a second inverter INV2, a third inverter INV3 and a fourth inverter INV4, wherein the positive phase input terminal of the second inverter INV2 is electrically connected to the inverting output terminal of the fourth inverter INV4, the inverting input terminal of the second inverter INV2 is electrically connected to the positive phase output terminal of the fourth inverter INV4, the control terminal of the second inverter INV2 is electrically connected to the control terminal of the third inverter INV3 and the control terminal of the fourth inverter INV4, respectively, as the input terminal of the voltage-controlled oscillator 155, for inputting the first current signal I1 output by the current source circuit 14, or the second current signal I2 output by the voltage-current converter 154, the inverting output terminal of the second inverter INV2 is electrically connected to the third inverter INV3 and the control terminal of the fourth inverter INV4, The positive phase input terminal of NV3 is electrically connected, the positive phase output terminal of the second inverter INV2 is electrically connected to the inverting input terminal of the third inverter INV3, serving as the first output terminal of the voltage-controlled oscillator 155, for outputting the first sampling clock signal EClk, the inverting output terminal of the third inverter INV3 is electrically connected to the positive phase input terminal of the fourth inverter INV4, the positive phase output terminal of the third inverter INV3 is electrically connected to the inverting input terminal of the fourth inverter INV4, serving as the second output terminal of the voltage-controlled oscillator 155, for outputting the second sampling clock signal DClk, and after the clock data recovery circuit completes frequency locking and phase locking, outputs the target clock signal DClk_A, the positive phase output terminal of the fourth inverter INV4 serves as the third output terminal of the voltage-controlled oscillator 155, for outputting the third sampling clock signal LClk.

[0043] In the voltage controlled oscillator 155, the control end of the second inverter INV2, the control end of the third inverter INV3, and the control end of the fourth inverter INV4 receive the first current signal or the second current signal. Under the control of the first current signal, the frequency of each sampling clock signal output is adjusted, and under the control of the second current signal, the phase of each sampling clock signal output is adjusted, and finally a target clock signal is obtained, which is the clock signal input by the transmitting end. The positive output end of the second inverter INV2 outputs the first sampling clock signal EClk, the positive output end of the third inverter INV3 outputs the second sampling clock signal DClk, and the positive output end of the fourth inverter INV4 outputs the third sampling clock signal LClk, and there is a 60-degree phase difference between the first sampling clock signal EClk, the second sampling clock signal DClk, and the third sampling clock signal LClk.

[0044] In one embodiment, reference Figure 2 , the frequency division module 12 provided in the embodiment of the present application includes a first frequency divider 121 and a second frequency divider 122; The first frequency divider 121 is used to divide the frequency of the first frequency based on the first frequency division value 2p Frequency-divide the single-ended data signal Din to generate a first frequency-divided signal F_Din; The second frequency divider 122 is used to divide the frequency of the second frequency based on the second frequency division value 2 q Divide the sampling clock signal Clki at a preset phase to generate a second frequency-divided signal F_Clki; Specifically, the first frequency divider 121 inputs the single-ended data signal Din and divides the single-ended data signal Din based on the first frequency division value 2 p The single-ended data signal Din is frequency-divided to generate a first frequency-divided signal F_Din, wherein the first frequency-divided value 2 p is the quotient of the frequency f(Din) of the single-ended data signal Din and the frequency f(F_Din) of the first frequency-divided signal F_Din, that is, , the first frequency-divided signal F_Din is composed of a p bit digital signal; The second frequency divider 122 is used to input the sampling clock signal Clki at a preset phase and divide the sampling clock signal Clki based on the second frequency division value 2 q The sampling clock signal Clki at the preset phase is frequency-divided to generate a second frequency-divided signal F_Clki, wherein the second frequency-divided value 2 q is the quotient of the frequency f(Clki) of the sampling clock signal Clki at the preset phase and the frequency f(F_Clki) of the second frequency-divided signal F_Clki, that is, The second frequency division signal F_Clki is composed of q bit digital signals. p Greater than the second frequency division value 2 q , therefore p>q.

[0045] For example, the first frequency divider 121 inputs the single-ended data signal Din and performs 32 frequency division, that is, the first frequency division value 2 p is 32 , based on the first frequency division value 2 p The single-ended data signal Din is frequency-divided to generate a first frequency-divided signal F_Din; the second frequency divider 122 inputs the sampling clock signal Clki at a preset phase and performs frequency division by 4, that is, the second frequency division value 2 q For 4 , based on the second frequency division value 2 q The sampling clock signal Clki at the preset phase is frequency-divided to generate a second frequency-divided signal F_Clki.

[0046] In one embodiment, if Figure 7, which is a schematic diagram of the structure of a digital controller provided in an embodiment of the present application, the digital controller 13 includes a frequency-phase conversion module 131, a phase error detection module 132, a mode detection module 133, a frequency locking module 134, a coefficient adjustment module 135 and a mode switching module 136; The input end of the frequency-phase conversion module 131 is used to input the first frequency division signal F_Din and the second frequency division signal F_Clki, the first output end of the frequency-phase conversion module 131 is electrically connected to the first input end of the phase error detection module 132, and the second output end of the frequency-phase conversion module 131 is electrically connected to the second input end of the phase error detection module 132.

[0047] The third input terminal of the phase error detection module 132 is electrically connected to the reset terminal of the mode switching module 136 , and the output terminal of the phase error detection module 132 is electrically connected to the first input terminal of the frequency locking module 134 and the first input terminal of the coefficient adjustment module 135 .

[0048] The second input end of the frequency locking module 134 is electrically connected to the output end of the mode detection module 133, the first output end of the frequency locking module 134 is electrically connected to the input end of the mode detection module 133, the second output end of the frequency locking module 134 is electrically connected to the second input end of the coefficient adjustment module 135, and the third output end of the frequency locking module 134 is electrically connected to the input end of the mode switching module 136.

[0049] A first output terminal of the mode switching module 136 is electrically connected to the voltage-to-current converter 154 in the clock signal generating module 15 for outputting a switching control signal Mode_Switch.

[0050] The output end of the coefficient adjustment module 135 is electrically connected to the input end of the current source circuit 14 for outputting a frequency control signal (CCTW / FCTW).

[0051] The frequency-phase conversion module 131, the phase error detection module 132, the mode detection module 133, the frequency locking module 134 and the coefficient adjustment module 135 cooperate to achieve frequency locking. The mode switching module 136 is used to output a clearing signal CLEAR to the clearing terminal of the phase error detection module 132 after the frequency is locked, control the phase error detection module 132 to clear, and output a switching control signal Mode_Switch to turn on the voltage-current converter 154, thereby causing the voltage-current converter 154 to output the second current signal I2 to the voltage-controlled oscillator 155.

[0052] In one embodiment, the frequency-phase conversion module 131 is based on the first frequency division value 2 pThe first frequency division signal F_Din is phase-converted to obtain a first phase signal Ph_CKR, and based on the second frequency division value 2 q Performing phase conversion on the second frequency-divided signal F_Clki to obtain a second phase signal Ph_CKV, wherein the first phase signal Ph_CKR includes a first-bit digital signal, and the second phase signal Ph_CKV includes a second-bit digital signal; The phase error detection module 132 generates a phase error ph_err based on the first bit and the second bit.

[0053] Specifically, the frequency-phase conversion module 131 is based on the preset first frequency division value 2 p The first frequency division signal F_Din is phase-converted to obtain a first phase signal Ph_CKR, and a second frequency division value 2 based on a preset q The second frequency-divided signal F_Clki is phase-converted to obtain a second phase signal Ph_CKV, wherein the first phase signal Ph_CKR includes a digital signal of a first bit n, and the second phase signal Ph_CKV includes a digital signal of a second bit m (that is, the first phase signal Ph_CKR consists of an n-bit digital signal, and the second phase signal Ph_CKV consists of an m-bit digital signal, where m>n).

[0054] because ,so ; In a specific implementation, when n is a preset value, m is calculated based on the above equation, and when m is a preset value, n is calculated based on the above equation; In one embodiment, the first phase signal Ph_CKR is recorded as Ph_CKR[n+p+a-1:p+a]; the second phase signal Ph_CKV is recorded as Ph_CKV[m+q+a-1:q+a], where a is a preset value and a is a positive integer ≥0.

[0055] For example, based on the above example, the single-ended data signal Din is divided by 32, and the preset first division value is 2 p is 32 , generating a first frequency-divided signal F_Din; The sampling clock signal Clki at the preset phase is divided by 4, and the preset second division value 2 q For 4 , generating a second frequency-divided signal F_Clki.

[0056] When n=8, because p+n=q+m, p=5, q=2, a=0, we get m=11. The first phase signal Ph_CKR is an 8-bit digital signal, denoted as Ph_CKR[12:5]; The second phase signal Ph_CKV is an 11-bit digital signal, denoted as Ph_CKV[12:2].

[0057] The phase error detection module 132 generates a phase error ph_err based on the first bit n and the second bit m.

[0058] Specifically, since the number of bits of the first phase signal Ph_CKR and the second phase signal Ph_CKV is different (i.e., the first bit n and the second bit m are different), the first phase signal Ph_CKR can be left-shifted until the number of bits of the first phase signal Ph_CKR and the second phase signal Ph_CKV is the same, generating the phase error ph_err. The specific expression formula of the phase error ph_err is as follows: Among them, (m - n)'b0 represents that the first phase signal Ph_CKR is left-shifted by (m - n) bits.

[0059] Among them, when the preset value a is larger, the error range of the phase error ph_err is larger; when the preset value a is smaller, the error range of the phase error ph_err is smaller.

[0060] For example, on the basis of the above example, first perform a left-shift process on the first phase signal Ph_CKR[12:5] until the number of bits is equal to that of the second phase signal Ph_CKV[12:2], and then generate the phase error .

[0061] In one embodiment, in each cycle of the first divided frequency signal F_Din, when the digital controller 13 determines that the absolute value of the phase error |ph_err| is less than the second preset value B (i.e., |ph_err| < B), it outputs a switching control signal Mode_Switch; when it determines that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B (i.e., |ph_err| ≥ B), it outputs a frequency control signal (CCTW / FCTW).

[0062] Specifically, when |ph_err| < B, the mode switching module 136 outputs the switching control signal Mode_Switch to the voltage-current converter 154 in the clock signal generation module 15; when |ph_err| ≥ B, the coefficient adjustment module 135 outputs the frequency control signal (CCTW / FCTW) to the current source circuit 14.

[0063] In one embodiment, as Figure 8As shown, the current source circuit 14 includes a first current source branch 141 and a second current source branch 142, and the frequency control signal includes a first frequency control signal CCTW and a second frequency control signal FCTW. After determining that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B, the digital controller 13 compares the absolute value of the phase error |ph_err| and the first preset value A. When it is determined that the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A, the current first frequency control signal is adjusted, and the adjusted first frequency control signal CCTW is output to adjust the number of first current sources working in the first current source branch 141; when it is determined that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B and less than the first preset value A, the current second frequency control signal is adjusted, and the adjusted second frequency control signal FCTW is output to adjust the number of second current sources working in the second current source branch 142; the first preset value A is greater than the second preset value B, and the first preset value A and the second preset value B are positive integers.

[0064] The current value of the output current of the first current source in the first current source branch 141 is greater than the current value of the output current of the second current source in the second current source branch 142 .

[0065] Specifically, refer to Figure 7 The frequency locking module 134 receives the phase error ph_err output by the phase error detection module 132, determines the absolute value of the phase error |ph_err|, and compares the absolute value of the phase error |ph_err| with the second preset value B. When it is determined that the absolute value of the phase error |ph_err| is less than the second preset value B, the third output terminal of the frequency locking module 134 outputs a frequency locking signal F_LOCK. After the input terminal of the mode switching module 136 receives the frequency locking signal F_LOCK, it outputs a switching control signal Mode_Switch to the voltage-current converter 154; When the frequency locking module 134 determines that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B (i.e., |ph_err|≥B), the frequency locking module 134 compares the absolute value of the phase error |ph_err| with the first preset value A. When it is determined that the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A (i.e., |ph_err|≥A), the frequency locking module 134 outputs a first control signal to the coefficient adjustment module 135. After receiving the first control signal, the coefficient adjustment module 135 adjusts the current first frequency control signal CCTW and outputs the adjusted first frequency control signal CCTW to the first current source branch 141 in the current source circuit 14, so as to control the coefficient adjustment module 135 to enter coarse adjustment and achieve rapid frequency approximation.

[0066] In another embodiment, when the frequency locking module 134 determines that the absolute value of the phase error |ph_err| is greater than or equal to a second preset value B and less than a first preset value A (i.e., B ≤ |ph_err| < A), it outputs a second control signal to the coefficient adjustment module 135. After receiving the second control signal, the coefficient adjustment module 135 adjusts the current second frequency control signal FCTW, outputs the adjusted second frequency control signal FCTW to the second current source branch 142 in the current source circuit 14, and controls the coefficient adjustment module 135 to enter fine adjustment to achieve accurate frequency locking.

[0067] For example, the first preset value A is 10 and the second preset value B is 5. When the absolute value of the phase error |ph_err| received by the frequency locking module 134 is 11, it is determined that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B (i.e., 11 > 5). Then, the absolute value of the phase error |ph_err| is compared with the first preset value A, and it is determined that the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A (i.e., 11 > 10). The frequency locking module 134 outputs a first control signal to the coefficient adjustment module 135. After receiving the first control signal, the coefficient adjustment module 135 adjusts the current first frequency control signal CCTW, outputs the adjusted first frequency control signal CCTW to the first current source branch 141 in the current source circuit 14 to control the coefficient adjustment module 135 to enter coarse adjustment.

[0068] In one embodiment, if the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A and ph_err is a positive number, it indicates that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. Then, the current source circuit 14 increases the number of first current sources operating in the first current source branch 141 based on the adjusted first frequency control signal CCTW to increase the first current signal. If the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A and ph_err is a negative number, it indicates that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase. Then, the current source circuit 14 reduces the number of first current sources operating in the first current source branch 141 based on the adjusted first frequency control signal CCTW to reduce the first current signal.

[0069] It should be noted that in the embodiments of the present application, when the phase error ph_err is a positive number, it is determined that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. When the phase error ph_err is a negative number, it is determined that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase.

[0070] Reference Figure 8 The current source circuit 14 includes a first current source branch 141 and a second current source branch 142, and the first current source branch 141 and the second current source branch 142 are connected in series. The first current source branch 141 includes m first current sources (S11, S12, ..., S1m) and third switches (K11, K12, ..., K1m) connected one-to-one with each first current source (S11, S12, ..., S1m), the first end of the first current source (S11, S12, ..., S1m) is electrically connected to the power supply voltage terminal VDD, the second end of the first current source (S11, S12, ..., S1m) is electrically connected to one end of the third switch (K11, K12, ..., K1m), and the other end of the third switch (K11, K12, ..., K1m) is electrically connected to the second output end of the digital controller 13 as the input end of the current source circuit 14; the second current source branch 142 includes n second current sources (S21, S22, ..., S2n) and fourth switches (K21, K22, ..., K2n) connected one-to-one with each second current source (S21, S22, ..., S2n), a first end of the second current source (S21, S22, ..., S2n) is electrically connected to the power supply voltage terminal VDD, a second end of the second current source (S21, S22, ..., S2n) is electrically connected to one end of the fourth switch (K21, K22, ..., K2n), and the other end of the fourth switch (K21, K22, ..., K2n) is electrically connected to the input end of the voltage-controlled oscillator 155 and the other end of the third switch (K11, K12, ..., K1m) respectively, as the output end of the current source circuit 14.

[0071] In the current source circuit 14, when the frequency control signal output by the coefficient adjustment module 135 in the digital controller 13 is the first frequency control signal CCTW, the first current source branch 141 works. Under the control of the first frequency control signal CCTW, the first current source branch 141 selectively closes one or more of the third switches (K11, K12, ..., K1m) to enable the first current source (S11, S12, ..., S1m) corresponding to the closed third switch (K11, K12, ..., K1m) to output a current signal, and output the current signal as the first current signal I1 to the voltage-controlled oscillator 155. The voltage-controlled oscillator 155 adjusts the frequency of the output sampling clock signal according to the change of the first current signal I1.

[0072] In the process of coarse frequency adjustment, if the frequency of the single-ended data signal Din is greater than the frequency of the second sampling clock signal DClk, the current source circuit 14 increases the number of the first current sources (S11, S12, ..., S1m) working in the first current source branch 141 in the current source circuit 14 according to the first frequency control signal CCTW, so that the first current signal I1 output by the first current source branch 141 increases. According to the increased first current signal I1, the voltage-controlled oscillator 155 increases the frequencies of the multiple sampling clock signals (Clk1, ...Clki, ...Clkn), so that the frequencies of the multiple sampling clock signals (Clk1, ...Clki, ...Clkn) increase rapidly, thereby achieving rapid frequency approximation. In the process of coarse frequency adjustment, there are at least two methods of frequency increase adjustment, which are as follows: Method 1: The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the first frequency control signal CCTW based on the absolute value of the phase error |ph_err|, and outputs it to the current source circuit 14. For example, the first frequency control signal CCTW is adjusted from the original CCTW<4:0>=00011 to CCTW<4:0>=01111. The current source circuit 14 controls to increase the conduction of an appropriate number of first current sources (S11, S12, ..., S1m) according to the received first frequency control signal CCTW<4:0>=01111. For example, there are 5 in the first current source branch 141. The first current sources (S11, S12, S13, S14, S15) are currently turned on in the first current source branch 141. The first current sources S14 and S15 are turned on. According to the first frequency control signal CCTW<4:0>=01111, the first current source branch 141 additionally turns on the first current source S12 and the first current source S13. The total current output by the first current source S12, the first current source S13, the first current source S14 and the first current source S15 is used as the first current signal I1. The first current signal I1 is output to the voltage-controlled oscillator 155 to control the frequency of the sampling clock signal.

[0073] Method 2: The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the first frequency control signal CCTW based on the absolute value of the phase error |ph_err|, and outputs it to the current source circuit 14. For example, there are five first current sources (S11, S12, S13, S14, S15) in the first current source branch 141. First, the first frequency control signal CCTW is adjusted from the original CCTW<4:0>=00011 to CCTW<4:0>=00111, that is, the current source The circuit 14 controls to add a first current source (S11, S12, S13, S14, S15) according to the received first frequency control signal CCTW<4:0>=00111, for example, to add and turn on the first current source S13, and take the total current output by the first current source S13, the first current source S14 and the first current source S15 as the first current signal I1, and output the first current signal I1 to the voltage controlled oscillator 155 to control the voltage controlled oscillator 155 to adjust the frequency of the sampling clock signal; then, the phase error detection The detection module 132 detects the phase of the single-ended data signal Din and the phase of the adjusted sampling clock signal to obtain the absolute value of the next phase error |ph_err2|. The frequency locking module 134 adjusts the first frequency control signal CCTW to CCTW<4:0>=01111 based on the absolute value of the next phase error |ph_err2|. The control coefficient adjustment module 135 adjusts the first frequency control signal CCTW to CCTW<4:0>=01111. The current source circuit 14 controls the increase of the conduction according to the received first frequency control signal CCTW<4:0>=01111. The first current source (S11, S12, S13, S14, S15), for example, the first current source S12 is newly turned on, and the total current output by the first current source S12, the first current source S13, the first current source S14 and the first current source S15 is used as the first current signal I1, and the first current signal I1 is output to the voltage-controlled oscillator 155 to control the voltage-controlled oscillator 155 to adjust the frequency of the sampling clock signal until the absolute value of the phase error |ph_err| is less than the first preset value A, indicating that the frequency coarse adjustment process is completed.

[0074] If the frequency of the single-ended data signal Din is less than the frequency of the second sampling clock signal DClk, the current source circuit 14 reduces the number of the first current sources (S11, S12, ..., S1m) working in the first current source branch 141 in the current source circuit 14 according to the first frequency control signal CCTW, so that the first current signal I1 output by the first current source branch 141 is reduced. According to the reduced first current signal I1, the voltage-controlled oscillator 155 reduces the frequencies of the multiple sampling clock signals (Clk1, ...Clki, ...Clkn), so that the frequencies of the multiple sampling clock signals (Clk1, ...Clki, ...Clkn) are quickly reduced, so that the frequency of the single-ended data signal Din quickly catches up with the frequency of the second sampling clock signal DClk, thereby achieving rapid frequency approximation. Similarly, in the process of coarse frequency adjustment, there are at least two methods of frequency reduction adjustment, which can refer to the principle of the above-mentioned frequency increase adjustment method, and will not be repeated here.

[0075] In one embodiment, if the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B and less than the first preset value A, and the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase, the current source circuit 14 increases the number of the second current sources operating in the second current source branch 142 based on the second frequency control signal FCTW to increase the first current signal; If the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B and less than the first preset value A, and the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase, then according to the second frequency control signal FCTW, the number of the second current sources working in the second current source branch 142 is reduced to reduce the first current signal.

[0076] When the frequency control signal output by the digital controller 13 is the second frequency control signal FCTW, the second current source branch 142 works. Under the control of the second frequency control signal FCTW, the second current source branch 142 selectively closes one or more of the fourth switches (K21, K22, ..., K2n) to enable the second current sources (S21, S22, ..., S2n) corresponding to the closed fourth switches (K21, K22, ..., K2n) to output a current signal, and output the current signal as the first current signal I1 to the voltage-controlled oscillator 155. The voltage-controlled oscillator 155 adjusts the frequency of the output sampling clock signal according to the change of the first current signal I1.

[0077] In the process of fine frequency adjustment, if the frequency of the single-ended data signal Din is greater than the frequency of the second sampling clock signal DClk, the current source circuit 14 increases the number of the second current sources (S21, S22, ..., S2n) working in the second current source branch 142 in the current source circuit 14 according to the second frequency control signal FCTW, so that the first current signal I1 output by the second current source branch 142 increases. According to the increased first current signal I1, the voltage-controlled oscillator 155 increases the frequency of the multiple sampling clock signals (Clk1, ...Clki, ...Clkn), so that the multiple sampling clock signals (Clk1, ...Clki, ...Clkn) increase slowly, so as to accurately adjust the frequency of the sampling clock signal Clki at the preset phase, so that the frequency of the single-ended data signal Din and the frequency of the sampling clock signal Clki at the preset phase are closer, thereby achieving accurate frequency locking. In the process of fine frequency adjustment, there are at least two methods of frequency increase adjustment, which are as follows: Method 1: The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW based on the absolute value of the phase error |ph_err|, and outputs it to the current source circuit 14. For example, the second frequency control signal FCTW is adjusted from the original FCTW<4:0>=00101 to FCTW<4:0>=11101. The current source circuit 14 controls to increase the conduction of an appropriate number of second current sources (S21, S22, ..., S2n) according to the received second frequency control signal FCTW<4:0>=11101. For example, there are 5 in the second current source branch 142. second current sources (S21, S22, S23, S24, S25), the second current sources currently turned on in the second current source branch 142 are the second current source S23 and the second current source S25, according to the second frequency control signal FCTW<4:0>=11101, the second current source branch 142 additionally turns on the second current source S21 and the second current source S22, and uses the total current output by the second current source S21, the second current source S22, the second current source S23 and the second current source S25 as the first current signal I1, and outputs the first current signal I1 to the voltage-controlled oscillator 155 to control the frequency of the sampling clock signal.

[0078] Method 2: The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW based on the absolute value of the phase error |ph_err|, and outputs it to the current source circuit 14. For example, first, the second frequency control signal FCTW is adjusted from the original FCTW<4:0>=00101 to FCTW<4:0>=00111, and the current source circuit 14 controls to add a second current source (S21, S22, ..., S2n) according to the received second frequency control signal FCTW<4:0>=00111. For example, the second current source S24 is added and turned on, and the total current output by the second current source S23, the second current source S24 and the second current source S25 is used as the first current signal I1, and the first current signal I1 is output to the voltage-controlled oscillator 155 to control the voltage-controlled oscillator 155 to adjust the frequency of the sampling clock signal; then, the phase error detection module 132 adjusts the phase and the frequency of the sampling clock signal Din. The phase of the subsequent sampling clock signal is detected to obtain the absolute value of the next phase error |ph_err2|. The frequency locking module 134 controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW to FCTW<4:0>=10111 based on the absolute value of the next phase error |ph_err2|. The current source circuit 14 controls to add a second current source (S21, S22, ..., S2n) according to the received second frequency control signal FCTW<4:0>=10111. For example, the second current source S21 is added and turned on, and the total current output by the second current sources S21, S23, S24 and S25 is used as the first current signal I1. The first current signal I1 is output to the voltage controlled oscillator 155 to control the voltage controlled oscillator 155 to adjust the frequency of the sampling clock signal until the absolute value of the phase error |ph_err| is less than the second preset value B, indicating that the frequency fine adjustment process is completed. At this time, the frequency is locked and the phase locking link begins.

[0079] If the frequency of the single-ended data signal Din is less than the frequency of the second sampling clock signal DClk, the current source circuit 14 reduces the number of the second current sources (S21, S22, ..., S2n) working in the second current source branch 142 in the current source circuit 14 according to the second frequency control signal FCTW, so that the first current signal I1 output by the second current source branch 142 is reduced. According to the reduced first current signal I1, the voltage-controlled oscillator 155 reduces the frequency of the multiple sampling clock signals (Clk1, ...Clki, ...Clkn) so that the multiple sampling clock signals (Clk1, ...Clki, ...Clkn) are slowly reduced, thereby achieving accurate frequency locking. In the process of fine frequency adjustment, there are at least two methods of frequency reduction adjustment, which can refer to the principle of the above-mentioned frequency increase adjustment method, and will not be repeated here.

[0080] It should be noted that, in the embodiment of the present invention, the current value of the output current of the first current source (S11, S12, ..., S1m) is greater than the current value of the output current of the second current source (S21, S22, ..., S2n), and the number m of the first current sources (S11, S12, ..., S1m) and the number n of the second current sources (S21, S22, ..., S2n) may be equal or different, and the embodiment of the present invention does not impose any restrictions on this.

[0081] In the embodiment of the present application, after receiving the first control signal sent by the frequency locking module 134, the coefficient adjustment module 135 determines whether the received phase error ph_err is a positive number or a negative number. If the phase error ph_err is a positive number, it means that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current first frequency control signal CCTW and outputs the adjusted first frequency control signal CCTW. The adjusted first frequency control signal CCTW is used to reduce the number of first current sources working in the first current source branch 141. If the phase error ph_err is a negative number, it means that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current first frequency control signal CCTW and outputs the adjusted first frequency control signal CCTW. The adjusted first frequency control signal CCTW is used to increase the number of first current sources working in the first current source branch 141.

[0082] After receiving the second control signal sent by the frequency locking module 134, the coefficient adjustment module 135 determines whether the received phase error ph_err is a positive number or a negative number. If the phase error ph_err is a positive number, it means that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current second frequency control signal FCTW and outputs the adjusted second frequency control signal FCTW. The adjusted second frequency control signal FCTW is used to reduce the number of second current sources working in the second current source branch 142. If the phase error ph_err is a negative number, it means that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current second frequency control signal FCTW and outputs the adjusted second frequency control signal FCTW. The adjusted second frequency control signal FCTW is used to increase the number of second current sources working in the second current source branch 142.

[0083] In one embodiment, after the coefficient adjustment module 135 outputs the first frequency control signal CCTW, that is, when performing coarse adjustment, the frequency locking module 134 maintains the first frequency control signal CCTW unchanged when determining that the absolute value of the next phase error |ph_err2| is less than the first preset value A, and in the next cycle of the first frequency-divided signal F_Din, determines whether the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B. When the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B, adjusts the current second frequency control signal and outputs the adjusted second frequency control signal FCTW; when the absolute value of the next phase error |ph_err2| is less than the second preset value B, outputs the switching control signal Mode_Switch.

[0084] In the embodiment of the present application, when the frequency locking module 134 determines that the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A, the frequency locking module 134 outputs a first control signal to the coefficient adjustment module 135. After receiving the first control signal, the coefficient adjustment module 135 determines whether the phase error ph_err is a positive number or a negative number, and outputs an adjusted first frequency control signal CCTW to the first current source branch 141 in the current source circuit 14 based on the judgment result. The first current output by the current source circuit 14 changes, thereby changing the phase error ph_err output by the phase error detection module 132, that is, the phase error detection module 13 2 outputs the next phase error ph_err2, the frequency locking module 134 compares the absolute value of the next phase error |ph_err2| with the first preset value A, if the absolute value of the next phase error |ph_err2| is greater than or equal to the first preset value A, the step of outputting the first control signal to the coefficient adjustment module 135 is executed, if the absolute value of the next phase error |ph_err2| is less than the first preset value A, the coarse adjustment is ended, at this time, the frequency locking module 134 does not output the first control signal to the coefficient adjustment module 135, therefore, the coefficient adjustment module 135 keeps the output first frequency control signal CCTW unchanged.

[0085] In one embodiment, after the coarse adjustment is completed, the fine adjustment is entered. After determining that the absolute value of the next phase error |ph_err2| is less than the first preset value A, the frequency locking module 134 compares the absolute value of the next phase error |ph_err2| with the second preset value B to determine whether the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B. If it is greater than or equal to the second preset value B, the frequency locking module 134 outputs a second control signal to the coefficient adjustment module 135. After receiving the second control signal, the coefficient adjustment module 135 determines whether the phase error ph_err is a positive number or a negative number, adjusts the current second frequency control signal FCTW based on the judgment result, and outputs the adjusted second frequency control signal FCTW to the second current source branch 142. After the second current source branch 142 outputs the adjusted second frequency control signal FCTW, the phase error output by the phase error detection module 132 changes, that is, the phase error detection module 132 outputs the next phase error ph_err3. After receiving the next phase error ph_err3, the frequency locking module 134 determines whether the absolute value of the next phase error |ph_err3| is still greater than or equal to the second preset value B and less than the first preset value A. If so, the current second frequency control signal FCTW is continuously adjusted until the absolute value of the phase error output by the phase error detection module 132 is less than the second preset value B. The fine adjustment is completed, and the frequency locking module 134 outputs a frequency locking signal F_LOCK to the mode switching module 136. After receiving the frequency locking signal F_LOCK, the mode switching module 136 outputs a switching control signal Mode_Switch. If the absolute value of the next phase error |ph_err2| is less than the second preset value B, the frequency locking module 134 outputs a frequency locking signal F_LOCK to the mode switching module 136. After receiving the frequency locking signal F_LOCK, the mode switching module 136 outputs a switching control signal Mode_Switch and outputs a clearing signal CLEAR to the clearing terminal of the phase error detection module 132 to control the phase error detection module 132 to be cleared.

[0086] like Fig. 9 , which is a schematic diagram of the working process of a digital controller provided in an embodiment of the present application; S901: The coefficient adjustment module 135 outputs a first frequency control signal CCTW; S902: The frequency locking module 134 determines that the absolute value of the next phase error |ph_err2| is less than the first preset value A, and the control coefficient adjustment module 135 outputs the first frequency control signal CCTW unchanged; In step 901 , the next phase error ph_err2 is output by the phase error detection module 132 after the coefficient adjustment module 135 outputs the first frequency control signal CCTW.

[0087] In one embodiment, after the frequency locking module 134 outputs the first control signal to the coefficient adjustment module 135, it can also output a low-level coarse adjustment signal LOCK to the mode detection module 133. A , low level coarse adjustment signal LOCK A The coefficient adjustment module is performing rough adjustment; when the frequency locking module 134 controls the coefficient adjustment module 135 to output the first frequency control signal CCTW unchanged, it can also output a high-level rough adjustment signal LOCK to the mode detection module 133 A , high level coarse adjustment signal LOCK A Characterizes that coarse adjustment is complete.

[0088] In the embodiment of the present application, the frequency locking module 134 controls the coefficient adjustment module 135 to output the first frequency control signal CCTW unchanged, that is, the frequency locking module 134 does not output the first control signal to the coefficient adjustment module 135. After the frequency locking module 134 controls the coefficient adjustment module 135 to output the first frequency control signal CCTW unchanged, it can also be determined that after the current cycle of the first frequency-divided signal ends, in each cycle of a preset number of consecutive cycles of the first frequency-divided signal F_Din, when it is determined that the absolute value of the phase error is less than the first preset value, the first frequency control signal CCTW is kept unchanged, wherein the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first frequency-divided signal.

[0089] In a specific implementation, the mode detection module 133 determines whether the received coarse adjustment signal is continuously at a high level within a preset number of cycles of the first frequency-divided signal F_Din. If so, a third control signal is sent to the frequency locking module. After receiving the third control signal, the frequency locking module 134 sends a coarse adjustment locking signal to the coefficient adjustment module 135. After receiving the coarse adjustment locking signal, the coefficient adjustment module 135 locks the current first frequency control signal CCTW.

[0090] For example, in the first cycle of the first frequency-divided signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133. A In the second cycle of the first frequency-divided signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133 A In the third cycle of the first frequency-divided signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133 AIn the fourth cycle of the first frequency-divided signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133 A In the fifth cycle of the first frequency-divided signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133 A The mode detection module 133 receives five high-level coarse adjustment signals LOCK in succession. A Then, a third control signal is output to the frequency locking module 134.

[0091] S903: In the next cycle of the first frequency-divided signal F_Din, the frequency locking module 134 determines whether the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B. If the determination result is yes, execute S904; if the determination result is no, execute S905; S904: The frequency locking module 134 controls the coefficient adjustment module 135 to perform fine adjustment, adjust the current second frequency control signal, and output the adjusted second frequency control signal FCTW; The frequency locking module 134 controls the coefficient adjustment module 135 to perform fine adjustment. In the next cycle of the first frequency-divided signal F_Din, after the frequency locking module 134 determines that the absolute value of the next phase error ph_err2 is greater than or equal to the second preset value B, it outputs a second control signal to the coefficient adjustment module 135 to control the coefficient adjustment module 135 to perform fine adjustment. After receiving the second control signal, the coefficient adjustment module 135 adjusts the current second frequency control signal FCTW. The frequency locking module 134 can also output a second control signal to the coefficient adjustment module 135 after receiving the third control signal sent by the mode detection module 133.

[0092] S905 : The frequency locking module 134 controls the mode switching module 136 to output the switching control signal Mode_Switch, and outputs the clearing signal CLEAR to the clearing terminal of the phase error detection module 132 , so as to control the phase error detection module 132 to be cleared.

[0093] In the embodiment of the present application, in the coarse adjustment mode, it is determined whether the absolute value of the phase error is less than the first preset value in each cycle of the first frequency division signal F_Din. When the absolute value of the phase error is less than the first preset value, the control coefficient adjustment module keeps the first frequency control signal CCTW unchanged in the next cycle of the first frequency division signal F_Din, and controls the coarse adjustment signal LOCK output by the frequency locking module. AWhen the absolute value of the phase error is greater than or equal to the first preset value, the control coefficient adjustment module adjusts the current first frequency control signal CCTW within the next cycle of the first frequency division signal F_Din, and controls the coarse adjustment signal LOCK output by the frequency locking module. A is low level.

[0094] The mode detection module detects the received coarse adjustment signal LOCK A Whether it is continuously at a high level within a preset number of cycles of the first frequency-divided signal F_Din; if it is continuously at a high level, the frequency locking module is controlled to output a coarse adjustment locking signal to enter the fine adjustment mode; if it is discontinuously at a high level, the coefficient adjustment module is controlled to adjust the current first frequency control signal CCTW within the next cycle of the first frequency-divided signal F_Din, and continue the frequency adjustment in the coarse adjustment stage.

[0095] In one embodiment, after the digital controller 13 outputs the second frequency control signal FCTW, when it is determined that the absolute value of the next phase error |ph_err2| is less than the second preset value B, the second frequency control signal FCTW is kept unchanged and a switching control signal is output; when the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B, the current second frequency control signal is adjusted and the adjusted second frequency control signal FCTW is output.

[0096] In the embodiment of the present application, when the frequency locking module 134 determines that the absolute value of the phase error |ph_err| is less than the first preset value and greater than or equal to the second preset value, the frequency locking module 134 outputs a second control signal to the coefficient adjustment module 135. After receiving the second control signal, the coefficient adjustment module 135 outputs the adjusted second frequency control signal FCTW to the second current source branch 142 in the current source circuit 14. The current output by the current source circuit 14 changes, thereby changing the phase error output by the phase error detection module 132, that is, the phase error detection module 132 outputs the next phase error ph_err. rr2, the frequency locking module 134 compares the absolute value of the next phase error |ph_err2| with the second preset value B. If the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B, the second frequency control signal FCTW is continued to be adjusted. If the absolute value of the next phase error |ph_err2| is less than the second preset value B, the current second frequency control signal FCTW is maintained. The frequency locking module 134 outputs a frequency locking signal F_LOCK. After receiving the frequency locking signal F_LOCK, the mode switching module 136 outputs a switching control signal.

[0097] like Fig.10 FIG. 1 is a schematic diagram of another operation flow of a digital controller provided in an embodiment of the present application; S1001: The coefficient adjustment module 135 outputs a second frequency control signal FCTW; S1002: The frequency locking module 134 determines whether the absolute value of the next phase error |ph_err2| is less than the second preset value B; if the determination result is yes, execute S1003; if the determination result is no, execute S1004; The next phase error ph_err2 is output by the phase error detection module 132 after the coefficient adjustment module 135 outputs the adjusted second frequency control signal FCTW.

[0098] S1003: The frequency locking module 134 controls the second frequency control signal FCTW output by the coefficient adjustment module 135 to remain unchanged, and controls the mode switching module 136 to output the switching control signal Mode_Switch, and outputs the clearing signal CLEAR to the clearing terminal of the phase error detection module 132, so as to control the phase error detection module 132 to be cleared; S1004: adjust the current second frequency control signal, output the adjusted second frequency control signal FCTW, and return to S1001.

[0099] When the frequency locking module 134 determines that the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B, it can also output a low-level fine adjustment signal LOCK to the mode detection module. B When the frequency locking module 134 controls the coefficient adjustment module 135 outputs the second frequency control signal FCTW unchanged, it can also output a high-level fine adjustment signal LOCK to the mode detection module 133 B .

[0100] The digital controller 13 can also, after determining that the current cycle of the first frequency-divided signal ends, keep the second frequency control signal FCTW unchanged in each cycle of a preset number of consecutive cycles of the first frequency-divided signal F_Din, when the absolute value of the phase error |ph_err| is less than a second preset value B, wherein the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first frequency-divided signal.

[0101] In a specific implementation, the mode detection module 133 determines whether the received fine adjustment signal is continuously at a high level within a preset number of cycles of the first frequency-divided signal F_Din. If so, a fourth control signal is sent to the frequency locking module. After receiving the fourth control signal, the frequency locking module sends a fine adjustment locking signal to the coefficient adjustment module 135. After receiving the fine adjustment locking signal, the coefficient adjustment module 135 locks the current second frequency control signal FCTW.

[0102] In the embodiment of the present application, in the fine adjustment mode, it is determined whether the absolute value of the phase error is less than the second preset value in each cycle of the first frequency division signal F_Din, wherein the second preset value is less than the first preset value. When the absolute value of the phase error is less than the second preset value, the control coefficient adjustment module 135 keeps the second frequency control signal FCTW unchanged in the next cycle of the first frequency division signal F_Din, and controls the fine adjustment signal LOCK output by the frequency locking module 134. B When the absolute value of the phase error is greater than or equal to the second preset value, the control coefficient adjustment module 135 adjusts the second frequency control signal FCTW in the next cycle of the first frequency division signal F_Din, and controls the fine adjustment signal LOCK output by the frequency locking module 134. B is low level.

[0103] The mode detection module 133 detects the received fine adjustment signal LOCK B Whether it is continuously at a high level within a preset number of cycles of the first frequency-divided signal F_Din; if it is continuously at a high level, the frequency locking module is controlled to output a fine-tuning locking signal, and the mode switching module outputs a mode switching control signal to enter the phase locking mode; if it is discontinuously at a high level, the control coefficient adjustment module adjusts the current second frequency control signal within the next cycle of the first frequency-divided signal F_Din, and continues the frequency adjustment in the fine-tuning stage.

[0104] In one embodiment, the digital controller 13 may further output a switching control signal after receiving an enable signal, wherein the enable signal is used to indicate that phase locking is performed.

[0105] Specifically, Fig.11As shown, it is a working flow chart of the frequency locking stage. The digital controller 13 receives an enable signal no_link from the outside. If the enable signal no_link=1, the digital controller 13 will skip the frequency locking stage and directly output the switching control signal Mode_Switch to the voltage-current converter 154 to enable the phase locking loop to start working and lock the phase; if the enable signal no_link=0, the digital controller 13 enters the frequency locking stage. At this time, the frequency coarse adjustment is first performed. If the coarse adjustment end signal cctw_finish=0 output by the mode detection module 133 to the frequency locking module 134 indicates that the frequency coarse adjustment has not yet ended, and the frequency locking module 134 outputs a locking signal lock=0 to the mode switching module 136; if the coarse adjustment end signal cctw_finish=1, it indicates that the frequency coarse adjustment is ended, and the output locking signal lock=1. Then, fine frequency adjustment is performed. If the fine adjustment end signal fctw_finish=0 output by the mode detection module 133 to the frequency locking module 134 indicates that the fine frequency adjustment has not yet ended, the frequency locking module 134 outputs a locking signal lock=0 to the mode switching module 136. If the fine adjustment end signal fctw_finish=1, it indicates that the fine frequency adjustment is ended, and the locking signal lock=1 is output to enter the phase locking stage.

[0106] In the above solution, after receiving the enable signal, the digital controller 13 can skip the frequency locking stage and directly enter the phase locking stage, thereby improving the flexibility and adaptability of the clock data recovery circuit.

[0107] In one embodiment, after generating the phase error, the digital controller may further calculate the phase error based on the error accuracy selection signal to obtain a phase selection error; and output a frequency control signal or a switching control signal based on the phase selection error.

[0108] Specifically, Fig.12 As shown, it is a structural schematic diagram of another digital controller provided by an embodiment of the present application. The digital controller 13 further includes an error accuracy selection module 137. The input end of the error accuracy selection module 137 is electrically connected to the output end of the phase error detection module 132. The output end of the error accuracy selection module 137 is electrically connected to the first input end of the frequency locking module 134 and the first input end of the coefficient adjustment module 135. Different phase selection errors are selected by the error accuracy selection module 137. The smaller the phase selection error, the more accurate the frequency adjustment of the first frequency control signal CCTW and the second frequency control signal FCTW, so that the output frequency is closer to the input frequency.

[0109] The error accuracy selection module 137 determines the target error accuracy based on the error accuracy selection signal, calculates the phase error ph_err[n+p+a-1:q+a], and obtains the phase selection error ph_err_SW[n+p+a-1:0]; the digital controller 13 outputs a frequency control signal or a switching control signal based on the phase selection error ph_err_SW[n+p+a-1:0].

[0110] The error precision selection signal is selected by the user based on the register setting. The error precision selection signal is a (q+a) bit digital signal, so the number of error precision types is 2. q+a , specifically, phase selection error = 2 x × Phase error, as shown in Table 1, when q=2, a=0: Table 1

[0111] Based on the same inventive concept, an embodiment of the present application also provides a display chip. The principle of the display chip in solving the technical problem is similar to the principle of the above-mentioned clock data recovery circuit in solving the technical problem. The implementation of the display chip can refer to the implementation of the clock data recovery circuit, and the repeated parts will not be repeated.

[0112] An embodiment of the present application provides a display chip, comprising any of the clock data recovery circuits described above.

[0113] Based on the same inventive concept, an embodiment of the present application also provides a display device. The principle of the display device in solving the technical problem is similar to the principle of the above-mentioned display chip. The implementation of the display device can be the implementation of the display chip, and the repeated parts will not be repeated.

[0114] An embodiment of the present application provides a display device, comprising the above-mentioned display chip.

[0115] The present application provides a clock data recovery circuit, a display chip and a display device. In the circuit, a differential-to-single circuit converts a differential data signal into a single-ended data signal. A frequency division module divides the single-ended data signal and a sampling clock signal at a preset phase based on first and second frequency division values ​​to generate first and second frequency division signals. A digital controller compares a first phase signal obtained based on the first frequency division signal and a second phase signal obtained based on the second frequency division signal to generate a phase error, and outputs a frequency control signal or a switching control signal accordingly. A current source circuit outputs a first current signal based on the frequency control signal. A clock signal generation module generates multiple sampling clock signals based on the first current signal, or generates a second current signal based on the switching control signal, and then generates a target clock signal. In the above manner, a control signal or a switching control signal is output based on a phase error ratio or based on a frequency error. When the data signal transmission rate is high, a high-precision digital controller is not required, which reduces the design difficulty.

[0116] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0117] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0118] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0120] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A clock data recovery circuit, characterized in that: include: A differential-to-single-ended circuit, used for converting an input differential data signal into a single-ended data signal; A frequency division module, configured to divide the single-ended data signal based on a first frequency division value to generate a first frequency division signal, and to divide the sampling clock signal at a preset phase among a plurality of sampling clock signals based on a second frequency division value to generate a second frequency division signal, wherein the first frequency division value is greater than the second frequency division value; A digital controller, configured to compare a first phase signal and a second phase signal to generate a phase error, wherein the first phase signal is obtained based on the first frequency-divided signal, and the second phase signal is obtained based on the second frequency-divided signal; and output a frequency control signal or a switching control signal based on the phase error; a current source circuit, configured to generate a first current signal based on the frequency control signal; The clock signal generating module is used to generate the plurality of sampling clock signals based on the first current signal, or to generate a second current signal under the control of the switching control signal, and to generate a target clock signal based on the second current signal.

2. The circuit according to claim 1, characterized in that The digital controller is also used for: Performing phase conversion on the first frequency-divided signal based on the first frequency-divided value to obtain the first phase signal, and performing phase conversion on the second frequency-divided signal based on the second frequency-divided value to obtain the second phase signal, wherein the first phase signal includes a first-bit digital signal, and the second phase signal includes a second-bit digital signal; The digital controller is specifically used for: The phase error is generated based on the first bit and the second bit.

3. The circuit according to claim 2, characterized in that In each cycle of the first frequency-divided signal, the digital controller is specifically used for: When it is determined that the absolute value of the phase error is less than a second preset value, outputting the switching control signal; When it is determined that the absolute value of the phase error is greater than or equal to the second preset value, the frequency control signal is output.

4. The circuit according to claim 3, characterized in that The current source circuit includes a first current source branch and a second current source branch, the frequency control signal includes a first frequency control signal and a second frequency control signal, and the digital controller is specifically used for: When it is determined that the absolute value of the phase error is greater than or equal to a first preset value, adjusting the current first frequency control signal, and outputting the adjusted first frequency control signal; The current source circuit is specifically used for: Based on the adjusted first frequency control signal, adjusting the number of first current sources operating in the first current source branch; When it is determined that the absolute value of the phase error is greater than or equal to the second preset value and less than the first preset value, adjusting the current second frequency control signal and outputting the adjusted second frequency control signal; The current source circuit is specifically used for: adjusting the number of second current sources operating in the second current source branch based on the adjusted second frequency control signal; The current value of the output current of the first current source in the first current source branch is greater than the current value of the output current of the second current source in the second current source branch.

5. The circuit according to claim 4, characterized in that After the digital controller outputs the adjusted first frequency control signal, the digital controller is further used for: When it is determined that the next phase error is less than the first preset value, keeping the first frequency control signal unchanged; Determining whether the absolute value of the next phase error is greater than or equal to the second preset value; When the absolute value of the next phase error is greater than or equal to the second preset value, adjusting the current second frequency control signal, and outputting the adjusted second frequency control signal; When the absolute value of the next phase error is smaller than the second preset value, the switching control signal is output.

6. The circuit according to claim 5, characterized in that After the first frequency control signal is kept unchanged, and before the absolute value of the next phase error is determined to be greater than or equal to the second preset value in the next cycle of the first frequency-divided signal, the digital controller is further used to: After determining that the current cycle of the first frequency-divided signal ends, in each cycle of a preset number of consecutive cycles, when determining that the phase error is less than the first preset value, keeping the first frequency control signal unchanged, wherein the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first frequency-divided signal.

7. The circuit according to claim 4, characterized in that The current source circuit is specifically used for: If the absolute value of the phase error is greater than or equal to a first preset value, and the phase error is a positive number, increasing the number of first current sources operating in the first current source branch based on the first frequency control signal; If the absolute value of the phase error is greater than or equal to a first preset value and the phase error is a negative number, the number of first current sources operating in the first current source branch is reduced according to the first frequency control signal.

8. The circuit according to claim 4, characterized in that After outputting the second frequency control signal, the digital controller is further used to: When it is determined that the absolute value of the next phase error is less than the second preset value, the second frequency control signal is kept unchanged, and the switching control signal is output; When the absolute value of the next phase error is greater than or equal to the second preset value, the current second frequency control signal is adjusted, and the adjusted second frequency control signal is output.

9. The circuit according to claim 8, characterized in that After the second frequency control signal is kept unchanged, and before the absolute value of the next phase error is determined to be greater than or equal to the second preset value in the next cycle of the first frequency-divided signal, the digital controller is further used to: After determining that the current cycle of the first frequency-divided signal ends, in each cycle of a preset number of consecutive cycles, when determining that the absolute value of the phase error in each cycle is less than the second preset value, keeping the second frequency control signal unchanged, wherein the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first frequency-divided signal.

10. The circuit according to claim 1, characterized in that After the phase error is generated, the digital controller is further configured to: Based on the error accuracy selection signal, the phase error is calculated to obtain a phase selection error; The digital controller is specifically used for: Based on the phase selection error, the frequency control signal or the switching control signal is output.

11. A display chip, characterized in that: It comprises a clock data recovery circuit as described in any one of claims 1 to 10.

12. A display device, characterized in that: Comprising the display chip as claimed in claim 11.

Images