A clock data recovery circuit, a display chip, and a display device

Abstract

The present application provides a clock data recovery circuit, a display chip, and a display device. The differential-to-single-ended circuit converts a differential data signal into a single-ended data signal. The frequency division module divides the single-ended data signal and the sampling clock signal at a preset phase to generate a first frequency division signal and a second frequency division signal. The digital controller compares a first phase signal obtained from the first frequency division signal and a second phase signal obtained from the second frequency division signal. After generating a phase error, it outputs a frequency control signal or a switching control signal. The clock signal generation module generates a plurality of sampling clock signals based on a first current signal output by the current source circuit based on the frequency control signal, or generates a second current signal based on the switching control signal and then generates a target clock signal. By outputting a control signal or a switching control signal based on the phase error rather than the frequency error, when the data signal transmission rate is high, a digital controller with high precision is not required, reducing the design difficulty.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly relates to a clock data recovery circuit, a display chip, and a display device. Background Art

[0002] With the development of display technologies, the requirements for the resolution, color gamut, and refresh rate of display devices are getting higher and higher, which leads to a significant increase in the amount of data and the data transmission rate that display devices need to process. In high-speed serial data transmission, the integrity and accuracy of data are crucial for display quality. To ensure that data signals can be correctly read and recovered, a receiving end needs to use a clock data recovery (CDR) circuit to synchronize the data transmission frequency and recover the clock signal.

[0003] In the CDR circuit provided by related technologies, a digital controller in the CDR circuit detects the frequency of a data signal and the frequency of a sampling clock signal at a preset phase, that is, detects the difference between the frequency of the data signal and the frequency of the sampling clock signal at the preset phase. As the transmission frequency of the data signal increases, the above difference will also change. The higher the transmission frequency of the data signal, the higher the comparison accuracy requirement for the digital controller. Summary of the Invention

[0004] The present application provides a clock data recovery circuit, a display chip, and a display device to solve the problem in the prior art that as the transmission frequency of a data signal increases, the comparison accuracy requirement for the digital controller in the clock data recovery circuit is high.

[0005] In a first aspect, the present application provides a clock data recovery circuit, including:

[0006] A differential-to-single-ended circuit, configured to convert an input differential data signal into a single-ended data signal;

[0007] A frequency division module, configured to divide the single-ended data signal based on a first division value to generate a first division signal, and divide a sampling clock signal at a preset phase among a plurality of sampling clock signals based on a second division value to generate a second division signal, where the first division value is greater than the second division value;

[0008] A digital controller, configured to compare a first phase signal and a second phase signal to generate a phase error, where the first phase signal is obtained based on the first division signal, and the second phase signal is obtained based on the second division signal; and output a frequency control signal or a switching control signal based on the phase error;

[0009] A current source circuit, configured to generate a first current signal based on the frequency control signal;

[0010] A clock signal generation module, configured to generate the plurality of sampling clock signals based on the first current signal, or generate a second current signal under the control of the switching control signal, and generate a target clock signal based on the second current signal.

[0011] In a possible implementation manner, the digital controller is further configured to:

[0012] Perform phase conversion on the first frequency division signal based on the first frequency division value to obtain the first phase signal, and perform phase conversion on the second frequency division signal based on the second frequency division value to obtain the second phase signal, where the first phase signal includes a digital signal of a first bit, and the second phase signal includes a digital signal of a second bit;

[0013] Specifically, the digital controller is configured to:

[0014] Generate the phase error based on the first bit and the second bit.

[0015] In a possible implementation manner, in each period of the first frequency division signal, the digital controller is specifically configured to:

[0016] Output the switching control signal when it is determined that the absolute value of the phase error is less than a second preset value;

[0017] Output the frequency control signal when it is determined that the absolute value of the phase error is greater than or equal to the second preset value.

[0018] In a possible implementation manner, the current source circuit includes a first current source branch and a second current source branch, the frequency control signal includes a first frequency control signal and a second frequency control signal, and the digital controller is specifically configured to:

[0019] Adjust the current first frequency control signal and output the adjusted first frequency control signal when it is determined that the absolute value of the phase error is greater than or equal to a first preset value;

[0020] Specifically, the current source circuit is configured to:

[0021] Adjust the number of first current sources operating in the first current source branch based on the adjusted first frequency control signal;

[0022] Adjust the current second frequency control signal and output the adjusted second frequency control signal when it is determined that the absolute value of the phase error is greater than or equal to the second preset value and less than the first preset value;

[0023] Specifically, the current source circuit is configured to:

[0024] Adjust the number of second current sources operating in the second current source branch based on the adjusted second frequency control signal;

[0025] Wherein, the current value of the current output by the first current source in the first current source branch is greater than the current value of the current output by the second current source in the second current source branch.

[0026] In a possible implementation, after the digital controller outputs the adjusted first frequency control signal, the digital controller is further configured to:

[0027] Keep the first frequency control signal unchanged when it is determined that the next phase error is less than the first preset value;

[0028] Determine whether the absolute value of the next phase error is greater than or equal to the second preset value;

[0029] When the absolute value of the next phase error is greater than or equal to the second preset value, adjust the current second frequency control signal and output the adjusted second frequency control signal;

[0030] When the absolute value of the next phase error is less than the second preset value, output the switching control signal.

[0031] In a possible implementation, after keeping the first frequency control signal unchanged, before determining whether the absolute value of the next phase error is greater than or equal to the second preset value in the next cycle of the first divided-frequency signal, the digital controller is further configured to:

[0032] After determining the end of the current cycle of the first divided-frequency signal, in each of a preset number of consecutive cycles, when it is determined that the phase error is less than the first preset value, keep the first frequency control signal unchanged, where the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first divided-frequency signal.

[0033] In a possible implementation, the current source circuit is specifically configured to:

[0034] If the absolute value of the phase error is greater than or equal to the first preset value and the phase error is positive, increase the number of first current sources operating in the first current source branch based on the first frequency control signal;

[0035] If the absolute value of the phase error is greater than or equal to the first preset value and the phase error is negative, reduce the number of first current sources operating in the first current source branch according to the first frequency control signal.

[0036] In a possible implementation, after the digital controller outputs the second frequency control signal, it is further configured to:

[0037] When it is determined that the absolute value of the next phase error is less than the second preset value, keep the second frequency control signal unchanged and output the switching control signal;

[0038] When the absolute value of the next phase error is greater than or equal to the second preset value, adjust the current second frequency control signal and output the adjusted second frequency control signal.

[0039] In a possible implementation, after keeping the second frequency control signal unchanged, before determining that the absolute value of the next phase error is greater than or equal to the second preset value in the next cycle of the first divided-frequency signal, the digital controller is further configured to:

[0040] After determining the end of the current cycle of the first divided-frequency signal, in each of a preset number of consecutive cycles, when it is determined that the absolute value of the phase error in each cycle is less than the second preset value, keep the second frequency control signal unchanged, where the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first divided-frequency signal.

[0041] In a possible implementation, after generating the phase error, the digital controller is further configured to:

[0042] Calculate the phase error based on the error precision selection signal to obtain a phase selection error;

[0043] Specifically, the digital controller is configured to:

[0044] Output the frequency control signal or the switching control signal based on the phase selection error.

[0045] In a second aspect, the present application provides a display chip, including the clock data recovery circuit according to any one of the first aspect.

[0046] In a third aspect, the present application provides a display device, including the display chip according to the second aspect.

[0047] The beneficial effects of the present application are as follows:

[0048] The present application provides a clock data recovery circuit, a display chip, and a display device. In the circuit, a differential-to-single circuit converts a differential data signal into a single-ended data signal. A frequency division module divides the single-ended data signal and a sampling clock signal at a preset phase based on first and second frequency division values respectively to generate first and second frequency division signals. A digital controller compares a first phase signal obtained based on the first frequency division signal and a second phase signal obtained based on the second frequency division signal to generate a phase error, and accordingly outputs a frequency control signal or a switching control signal. A current source circuit outputs a first current signal based on the frequency control signal. A clock signal generation module generates a plurality of sampling clock signals based on the first current signal, or generates a second current signal based on the switching control signal and then generates a target clock signal. By the above method, when the data signal transmission rate is relatively high, the performance and accuracy of the digital controller are enhanced, and the design difficulty is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings without creative efforts based on these drawings.

[0050] Figure 1 It is a schematic structural diagram of a clock data recovery circuit provided by an embodiment of the present application;

[0051] Figure 2 It is a schematic structural diagram of a clock signal generation module provided by an embodiment of the present application;

[0052] Figure 3 It is a schematic circuit diagram of a phase detector provided by an embodiment of the present application;

[0053] Figure 4 It is a schematic circuit diagram of a charge pump and a low-pass filter provided by an embodiment of the present application;

[0054] Figure 5 It is a schematic circuit diagram of a voltage-current converter provided by an embodiment of the present application;

[0055] Figure 6 It is a schematic circuit diagram of a voltage-controlled oscillator provided by an embodiment of the present application;

[0056] Figure 7 It is a schematic structural diagram of a digital controller provided by an embodiment of the present application;

[0057] Figure 8 It is a schematic circuit diagram of a current source circuit provided by an embodiment of the present application;

[0058] Figure 9 A schematic flowchart of the operation of a digital controller provided by an embodiment of the present application;

[0059] Figure 10 Another schematic flowchart of the operation of a digital controller provided by an embodiment of the present application;

[0060] Figure 11 A working flowchart of a digital controller provided by an embodiment of the present application;

[0061] Figure 12 Another schematic structural diagram of a digital controller provided by an embodiment of the present application. Detailed implementation manners

[0062] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0063] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0064] The clock data recovery (CDR) circuit based on a single-loop system provided by the related art does not have a reference clock signal and locks based on the frequency of the input data signal.

[0065] For example, in the clock data recovery circuit disclosed in Publication No. CN115714596B, the clock data recovery circuit includes a digital controller. The digital controller inputs the data signal Din and the sampling clock signal Clki at a preset phase among multiple sampling clock signals output by a voltage-controlled oscillator, and compares the frequency of the data signal Din with the frequency of the sampling clock signal Clki at the preset phase. When the transmission rate is relatively high, the frequencies of the data signal Din and the pre-sampling clock signal are also relatively high. As the frequency increases, the period decreases. In order to achieve high-frequency comparison of the data signal, higher requirements are imposed on the performance of the digital controller, increasing the design difficulty.

[0066] To solve the above problems, embodiments of the present application provide a clock data recovery circuit, a display chip, and a display device. For ease of understanding, the clock data recovery circuit, the display chip, and the display device provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0067] As Figure 1 shown, it is a schematic structural diagram of a clock data recovery circuit provided by an embodiment of the present application. The clock data recovery circuit includes a differential-to-single circuit 11, a frequency division module 12, a digital controller 13, a current source circuit 14, and a clock signal generation module 15;

[0068] The differential-to-single circuit 11 is configured to convert the input differential data signals (positive-phase differential signal Din_P and negative-phase differential signal Din_N) into a single-ended data signal Din;

[0069] The frequency division module 12 is configured to divide the single-ended data signal Din based on a first frequency division value to generate a first divided signal F_Din, and divide the sampling clock signal Clki at a preset phase among a plurality of sampling clock signals based on a second frequency division value to generate a second divided signal F_Clki, where the first frequency division value is greater than the second frequency division value;

[0070] The digital controller 13 is configured to compare a first phase signal Ph_CKR and a second phase signal Ph_CKV to generate a phase error ph_err, where the first phase signal Ph_CKR is obtained based on the first divided signal F_Din, and the second phase signal Ph_CKV is obtained based on the second divided signal F_Clki; based on the phase error ph_err, output a frequency control signal or a switching control signal Mode_Switch;

[0071] The current source circuit 14 is configured to output a first current signal based on the frequency control signal;

[0072] The clock signal generation module 15 is configured to generate a plurality of sampling clock signals (Clk1,... Clki,... Clkn) based on the first current signal, or generate a second current signal under the control of the switching control signal Mode_Switch, and generate a target clock signal based on the second current signal.

[0073] It should be noted that the differential data signals (Din_P and Din_N) in the embodiments of the present application are externally transmitted.

[0074] A clock data recovery circuit provided by the present application, the clock data recovery circuit includes a differential-to-single circuit, a frequency division module, a digital controller, a current source circuit, and a clock signal generation module. The differential-to-single circuit converts an input differential data signal into a single-ended data signal. The frequency division module divides the single-ended data signal based on a first frequency division value to generate a first divided frequency signal, and divides the sampling clock signal at a preset phase among a plurality of sampling clock signals based on a second frequency division value to generate a second divided frequency signal. The digital controller compares the first phase signal and the second phase signal to generate a phase error, and based on the phase error, outputs a frequency control signal or a switching control signal, wherein the first phase signal is obtained based on the first divided frequency signal, and the second phase signal is obtained based on the second divided frequency signal; the current source circuit outputs a first current signal based on the frequency control signal; the clock signal generation module generates a plurality of sampling clock signals based on the first current signal, or generates a second current signal under the control of the switching control signal, and generates a target clock signal based on the second current signal.

[0075] In the embodiment of the present application, the single-ended data signal is first divided in frequency to generate a first divided frequency signal, the sampling clock signal at a preset phase is divided in frequency to generate a second divided frequency signal, then the first phase signal is obtained based on the first divided frequency signal, the second phase signal is obtained based on the second divided frequency signal, and the first phase signal and the second phase signal are compared to generate a phase error. The single-ended data signal Din and the sampling clock signal Clki are divided in frequency by the frequency division module 12 to reduce the frequencies of the single-ended data signal Din and the sampling clock signal Clki, so that the frequency required for comparison by the digital controller is reduced; because in the digital controller, the higher the comparison frequency, the higher the performance requirement for the digital controller, so the performance requirement for the digital controller is reduced in the present application. In addition, the reduced frequency is subjected to phase conversion, and then the phase error is detected, so that the detection of the phase error is easier to implement and the detection accuracy is higher. When the frequencies are high and the two frequencies are close to each other, it is difficult to detect the frequency error between the two. At this time, a high-precision frequency detector is required to accurately detect the frequency error. Therefore, a frequency control signal or a switching control signal is output based on the phase error. Compared with outputting a frequency control signal or a switching control signal based on the frequency error, when the data signal transmission rate is high, a digital controller with high precision is not required, thereby reducing the design difficulty of the digital controller.

[0076] The clock signal generation module 15 provided in the embodiment of the present application includes a phase detector 151, a charge pump 152, a low-pass filter 153, a voltage-current converter 154, and a voltage-controlled oscillator 155, as Figure 2As shown, a phase detector 151, a charge pump 152, a low-pass filter 153, a voltage-current converter 154, and a voltage-controlled oscillator 155 are electrically connected in sequence; the input end of the voltage-current converter 154 is also electrically connected to the digital controller 13; the input end of the voltage-controlled oscillator 155 is also electrically connected to the output end of the current source circuit 14, and the output end of the voltage-controlled oscillator 155 is electrically connected to the input end of the phase detector 151 and the input end of the frequency division module 12.

[0077] In a specific implementation, the phase detector 151 is configured to receive a differential data signal (Din_P and Din_N) and a plurality of sampling clock signals (Clk1,... Clki,... Clkn) output by the voltage-controlled oscillator 155, and respectively compare the phases of the differential data signal (Din_P and Din_N) and the phases of each sampling clock signal (Clk1,... Clki,... Clkn), and output a pull-up pulse signal or a pull-down pulse signal.

[0078] The charge pump 152 is configured to generate a low-frequency control signal according to the pull-up pulse signal or the pull-down pulse signal.

[0079] The low-pass filter 153 is configured to filter the low-frequency control signal to generate a phase control signal.

[0080] The voltage-current converter 154 is configured to output a second current signal according to the phase control signal under the control of a switching control signal output by the digital controller 13.

[0081] The voltage-controlled oscillator 155 is configured to output a plurality of sampling clock signals (Clk1,... Clki,... Clkn) according to the first current signal output by the current source circuit 14, or output a target clock signal according to the second current signal output by the voltage-current converter 154.

[0082] In the embodiment of the present application, the phase detector 151 includes a plurality of input ends, and the plurality of input ends are configured to receive a positive-phase differential signal Din_P, a negative-phase differential signal Din_N, and a plurality of sampling clock signals (Clk1,... Clki,... Clkn) output by the voltage-controlled oscillator 155.

[0083] Such as Figure 3As shown, it is a circuit schematic diagram of the phase detector 151. The phase detector 151 includes a first latch L1, a second latch L2, a third latch L3, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a first exclusive-OR gate XOR1, and a second exclusive-OR gate XOR2. Among them, the positive input terminals of the first latch L1 are electrically connected to the positive input terminals of the second latch L2 and the third latch L3 respectively, and are used to input the positive differential signal Din_P. The negative input terminals of the first latch L1 are electrically connected to the negative input terminals of the second latch L2 and the third latch L3 respectively, and are used to input the negative differential signal Din_N. The positive output terminal of the first latch L1 is electrically connected to the positive input terminal of the first D flip-flop D1, and the negative output terminal of the first latch L1 is electrically connected to the negative input terminal of the first D flip-flop D1. The clock terminal of the first latch L1 is electrically connected to the first output terminal EClk of the voltage-controlled oscillator 155. The positive output terminal of the first D flip-flop D1 is electrically connected to the first input terminal of the second exclusive-OR gate XOR2, and the negative output terminal of the first D flip-flop D1 is electrically connected to the second input terminal of the second exclusive-OR gate XOR2. The clock terminal of the first D flip-flop D1 is electrically connected to the first output terminal EClk of the voltage-controlled oscillator 155. The positive output terminal of the second latch L2 is electrically connected to the positive input terminal of the second D flip-flop D2, and the negative output terminal of the second latch L2 is electrically connected to the negative input terminal of the second D flip-flop D2. The clock terminal of the second latch L2 is electrically connected to the second output terminal DClk of the voltage-controlled oscillator 155. The positive output terminal of the second D flip-flop D2 is electrically connected to the first input terminal of the first exclusive-OR gate XOR1 and the second input terminal of the second exclusive-OR gate XOR2 respectively, and the negative output terminal of the second D flip-flop D2 is electrically connected to the second input terminal of the first exclusive-OR gate XOR1 and the first input terminal of the second exclusive-OR gate XOR2 respectively. The clock terminal of the second D flip-flop D2 is electrically connected to the second output terminal DClk of the voltage-controlled oscillator 155. The positive output terminal of the third latch L3 is electrically connected to the positive input terminal of the third D flip-flop D3, and the negative output terminal of the third latch L3 is electrically connected to the negative input terminal of the third D flip-flop D3. The clock terminal of the third latch L3 is electrically connected to the third output terminal LClk of the voltage-controlled oscillator 155. The positive output terminal of the third D flip-flop D3 is electrically connected to the second input terminal of the first exclusive-OR gate XOR1, and the negative output terminal of the third D flip-flop D3 is electrically connected to the first input terminal of the first exclusive-OR gate XOR1. The clock terminal of the third D flip-flop D3 is electrically connected to the third output terminal LClk of the voltage-controlled oscillator 155. The output terminal of the first exclusive-OR gate XOR1 is electrically connected to the first input terminal of the charge pump 152, and the output terminal of the second exclusive-OR gate XOR2 is electrically connected to the second input terminal of the charge pump 152.

[0084] In the phase detector 151, the first latch L1 and the first D flip-flop D1 together form the first sampler, the second latch L2 and the second D flip-flop D2 together form the second sampler, and the third latch L3 and the third D flip-flop D3 together form the third sampler. The first sampler samples the positive differential signal Din_P and the negative differential signal Din_N according to the first sampling clock signal EClk, and outputs the first positive-phase sampling signal EOUT<0,1> to the first input terminal of the second exclusive-OR gate XOR2, and outputs the first negative-phase sampling signal EOUTB<0,1> to the second input terminal of the second exclusive-OR gate XOR2. The second sampler samples the positive differential signal Din_P and the negative differential signal Din_N according to the second sampling clock signal DClk, and outputs the second positive-phase sampling signal DOUT<0,1> to the first input terminal of the first exclusive-OR gate XOR1 and the second input terminal of the second exclusive-OR gate XOR2, and outputs the second negative-phase sampling signal DOUTB<0,1> to the second input terminal of the first exclusive-OR gate XOR1 and the first input terminal of the second exclusive-OR gate XOR2. The third sampler samples the positive differential signal Din_P and the negative differential signal Din_N according to the third sampling clock signal LClk, and outputs the third positive-phase sampling signal LOUT<0,1> to the second input terminal of the first exclusive-OR gate XOR1, and outputs the third negative-phase sampling signal LOUTB<0,1> to the first input terminal of the first exclusive-OR gate XOR1. The first exclusive-OR gate XOR1 performs an exclusive-OR operation on the input sampling signals and outputs the pull-up pulse signal UP<0,1> to the first input terminal of the charge pump 152. The second exclusive-OR gate XOR2 performs an exclusive-OR operation on the input sampling signals and outputs the pull-down pulse signal DN<0,1> to the second input terminal of the charge pump 152.

[0085] It should be noted that Figure 3 The example description is that the multiple sampling clock signals output by the medium voltage-controlled oscillator 155 include the first sampling clock signal EClk, the second sampling clock signal DClk, and the third sampling clock signal LClk. The number and types of sampling clock signals are not specifically limited in this application.

[0086] Specifically, such as Figure 4As shown in the figure, it is a schematic circuit diagram of a charge pump 152 and a low-pass filter 153 provided by an embodiment of the present application. The charge pump 152 includes a pull-up current source S1, a pull-down current source S2, a first switch K1, and a second switch K2. Among them, the first end of the pull-up current source S1 is electrically connected to the power supply voltage terminal VDD, the second end of the pull-up current source S1 is electrically connected to one end of the first switch K1, the control end of the first switch K1 is electrically connected to the first output end of the phase detector 151, serving as the first input end of the charge pump 152, the other end of the first switch K1 is electrically connected to one end of the second switch K2, serving as the output end of the charge pump 152, the control end of the second switch K2 is electrically connected to the second output end of the phase detector 151, serving as the second input end of the charge pump 152, and the other end of the second switch K2 is electrically connected to the first end of the pull-down current source S2, and the second end of the pull-down current source S2 is grounded.

[0087] In the charge pump 152, the pull-up current source S1 serves as the pull-up current source of the charge pump 152, and the pull-down current source S2 serves as the pull-down current source of the charge pump 152. When the first output end of the phase detector 151 outputs a pull-up pulse signal UP<0,1>, the first switch K1 closes, enabling the pull-up current source S1 to work, converting the high-frequency pull-up pulse signal UP<0,1> into a low-frequency control signal, and outputting it to the low-pass filter 153; when the second output end of the phase detector 151 outputs a pull-down pulse signal DN<0,1>, the second switch K2 closes, enabling the pull-down current source S2 to work, converting the high-frequency pull-down pulse signal DN<0,1> into a low-frequency control signal, and outputting it to the low-pass filter 153.

[0088] As Figure 4 shown in the figure, the low-pass filter 153 includes a first resistor R1 and a first capacitor C1. Among them, one end of the first resistor R1 is electrically connected to the output end of the charge pump 152, the other end of the first resistor R1 is electrically connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded. The low-pass filter 153 is used to filter out high-frequency noise signals in the circuit, that is, filter the low-frequency control signal and output a phase control signal.

[0089] As Figure 5As shown in the figure, it is a schematic circuit diagram of a voltage-current converter 154 provided by an embodiment of the present application. The voltage-current converter 154 includes a transmission gate G1, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, and a seventh switching transistor M7. The forward control terminal of the transmission gate G1 is electrically connected to the output terminal of the first inverter INV1. The input terminal of the first inverter INV1 is electrically connected to the first output terminal of the digital controller 13. The reverse control terminal of the transmission gate G1 is electrically connected to the first output terminal of the digital controller 13, serving as the control terminal of the voltage-current converter 154. The input terminal of the transmission gate G1 is respectively electrically connected to the output terminal of the low-pass filter 153 and the control terminal of the first switching transistor M1, serving as the input terminal of the voltage-current converter 154. The output terminal of the transmission gate G1 is electrically connected to the control terminal of the second switching transistor M2. The first terminal of the first switching transistor M1 is respectively electrically connected to the first terminal of the second switching transistor M2 and the second terminal of the seventh switching transistor M7. The second terminal of the first switching transistor M1 is respectively electrically connected to the second terminal of the third switching transistor M3 and the control terminal of the third switching transistor M3. The second terminal of the second switching transistor M2 is respectively electrically connected to the second terminal of the fourth switching transistor M4, the control terminal of the fourth switching transistor M4, and the control terminal of the fifth switching transistor M5. The first terminal of the third switching transistor M3 is respectively electrically connected to the first terminal of the fourth switching transistor M4, the first terminal of the fifth switching transistor M5, and the power supply voltage terminal VDD. The second terminal of the fifth switching transistor M5 is electrically connected to the control terminal of the sixth switching transistor M6, serving as the output terminal of the voltage-current converter 154. The first terminal of the sixth switching transistor M6 is respectively electrically connected to the second terminal of the sixth switching transistor M6, the first terminal of the seventh switching transistor M7, and the ground. The control terminal of the seventh switching transistor M7 is electrically connected to the bias voltage terminal VBIAS.

[0090] It should be noted that the first inverter INV1 can be in the digital controller 13 or in the voltage-current converter 154. The present application does not make specific restrictions on the position of the first inverter INV1.

[0091] The forward control terminal of the transmission gate G1 and the reverse control terminal of the transmission gate G1 are anti-phase signals. For example, if the forward control terminal of the transmission gate G1 is 0, then the reverse control terminal of the transmission gate G1 is 1, and the transmission gate G1 is turned on; if the forward control terminal of the transmission gate G1 is 1, then the reverse control terminal of the transmission gate G1 is 0, and the transmission gate G1 is turned off.

[0092] In the voltage-current converter 154, the fourth switching transistor M4 and the fifth switching transistor M5 form a current mirror. Before the digital controller 13 outputs the switching control signal Mode_Switch, the positive control terminal of the transmission gate G1 is at a high level, the negative control terminal of the transmission gate G1 is at a low level, and the transmission gate G1 is turned off. At this time, the positive differential voltage signal VCON input to the second switching transistor M2 and the negative differential voltage signal VCOP input to the first switching transistor M1 are kept equal. Then, the current output from the control terminal of the fourth switching transistor M4 remains unchanged. The fifth switching transistor M5 replicates the current output from the control terminal of the fourth switching transistor M4 and uses this current as the second current signal I2, and outputs the second current signal I2 to the input terminal of the voltage-controlled oscillator 155 through the second terminal of the fifth switching transistor M5. During this period, since the second current signal I2 remains unchanged, the phase of the sampling clock signal output by the voltage-controlled oscillator 155 will not change. After the digital controller 13 outputs the switching control signal Mode_Switch, the positive control terminal of the transmission gate G1 is at a low level, the negative control terminal of the transmission gate G1 is at a high level, and the transmission gate G1 is turned on. At this time, the positive differential voltage signal VCON input to the second switching transistor M2 and the negative differential voltage signal VCOP input to the first switching transistor M1 are not equal. Then, the current output from the control terminal of the fourth switching transistor M4 changes. The fifth switching transistor M5 replicates the current output from the control terminal of the fourth switching transistor M4 and uses this current as the second current signal I2, and outputs the second current signal I2 to the input terminal of the voltage-controlled oscillator 155 through the second terminal of the fifth switching transistor M5, so that the voltage-controlled oscillator 155 adjusts the phase of the output sampling clock signal according to the change of the second current signal I2. For example, if the positive differential voltage signal VCON is greater than or equal to the negative differential voltage signal VCOP, the second current signal I2 output from the second terminal of the fifth switching transistor M5 also increases accordingly.

[0093] As Figure 6As shown in the figure, it is a circuit schematic diagram of a voltage-controlled oscillator 155 provided by an embodiment of the present application. The voltage-controlled oscillator 155 includes a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. Among them, the positive input terminal of the second inverter INV2 is electrically connected to the inverted output terminal of the fourth inverter INV4, the inverted input terminal of the second inverter INV2 is electrically connected to the positive output terminal of the fourth inverter INV4, and the control terminal of the second inverter INV2 is electrically connected to the control terminals of the third inverter INV3 and the fourth inverter INV4 respectively, serving as the input terminal of the voltage-controlled oscillator 155 for inputting the first current signal I1 output by the current source circuit 14 or the second current signal I2 output by the voltage-current converter 154. The inverted output terminal of the second inverter INV2 is electrically connected to the positive input terminal of the third inverter INV3, and the positive output terminal of the second inverter INV2 is electrically connected to the inverted input terminal of the third inverter INV3, serving as the first output terminal of the voltage-controlled oscillator 155 for outputting the first sampling clock signal EClk. The inverted output terminal of the third inverter INV3 is electrically connected to the positive input terminal of the fourth inverter INV4, and the positive output terminal of the third inverter INV3 is electrically connected to the inverted input terminal of the fourth inverter INV4, serving as the second output terminal of the voltage-controlled oscillator 155 for outputting the second sampling clock signal DClk, and after the clock data recovery circuit completes frequency locking and phase locking, it outputs the target clock signal DClk_A. The positive output terminal of the fourth inverter INV4 serves as the third output terminal of the voltage-controlled oscillator 155 for outputting the third sampling clock signal LClk.

[0094] In the voltage-controlled oscillator 155, the control terminals of the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 receive the first current signal or the second current signal. Under the control of the first current signal, the frequency of each output sampling clock signal is adjusted. Under the control of the second current signal, the phase of each output sampling clock signal is adjusted, and finally the target clock signal is obtained. This target clock signal is the clock signal input by the sending end. The positive output terminal of the second inverter INV2 outputs the first sampling clock signal EClk, the positive output terminal of the third inverter INV3 outputs the second sampling clock signal DClk, and the positive output terminal of the fourth inverter INV4 outputs the third sampling clock signal LClk, and there is a 60-degree phase difference between the first sampling clock signal EClk, the second sampling clock signal DClk, and the third sampling clock signal LClk.

[0095] In one embodiment, referring to Figure 2 , the frequency division module 12 provided by the embodiment of the present application includes a first frequency divider 121 and a second frequency divider 122;

[0096] The first frequency divider 121 is configured to divide the single-ended data signal Din based on the first division value 2 p to generate a first divided signal F_Din;

[0097] The second frequency divider 122 is configured to divide the sampling clock signal Clki at a preset phase based on the second division value 2 q to generate a second divided signal F_Clki;

[0098] Specifically, the first frequency divider 121 receives the single-ended data signal Din and divides the single-ended data signal Din based on the first division value 2 p to generate a first divided signal F_Din, where the first division value 2 p is the quotient of the frequency f(Din) of the single-ended data signal Din and the frequency f(F_Din) of the first divided signal F_Din, that is , and the first divided signal F_Din is composed of a digital signal of p bits (bits);

[0099] The second frequency divider 122 is configured to receive the sampling clock signal Clki at a preset phase and divide the sampling clock signal Clki at the preset phase based on the second division value 2 q to generate a second divided signal F_Clki, where the second division value 2 q is the quotient of the frequency f(Clki) of the sampling clock signal Clki at the preset phase and the frequency f(F_Clki) of the second divided signal F_Clki, that is , and the second divided signal F_Clki is composed of a digital signal of q bits (bits). Since the first division value 2 p is greater than the second division value 2 q , so p > q.

[0100] For example, the first frequency divider 121 receives the single-ended data signal Din and performs a 32-fold division, that is, the first division value 2 p is 32 , and divides the single-ended data signal Din based on the first division value 2 p to generate a first divided signal F_Din; the second frequency divider 122 receives the sampling clock signal Clki at a preset phase and performs a 4-fold division, that is, the second division value 2 q is 4 , and divides the sampling clock signal Clki at the preset phase based on the second division value 2 q to generate a second divided signal F_Clki.

[0101] In one embodiment, as Figure 7As shown in the figure, it is a schematic structural diagram of a digital controller provided by an embodiment of the present application. The digital controller 13 includes a frequency-phase conversion module 131, a phase error detection module 132, a mode detection module 133, a frequency locking module 134, a coefficient adjustment module 135, and a mode switching module 136;

[0102] The input end of the frequency-phase conversion module 131 is used to input a first divided-frequency signal F_Din and a second divided-frequency signal F_Clki. The first output end of the frequency-phase conversion module 131 is electrically connected to the first input end of the phase error detection module 132, and the second output end of the frequency-phase conversion module 131 is electrically connected to the second input end of the phase error detection module 132.

[0103] The third input end of the phase error detection module 132 is electrically connected to the clear end of the mode switching module 136. The output end of the phase error detection module 132 is electrically connected to the first input end of the frequency locking module 134 and the first input end of the coefficient adjustment module 135.

[0104] The second input end of the frequency locking module 134 is electrically connected to the output end of the mode detection module 133. The first output end of the frequency locking module 134 is electrically connected to the input end of the mode detection module 133. The second output end of the frequency locking module 134 is electrically connected to the second input end of the coefficient adjustment module 135. The third output end of the frequency locking module 134 is electrically connected to the input end of the mode switching module 136.

[0105] The first output end of the mode switching module 136 is electrically connected to the voltage-current converter 154 in the clock signal generation module 15, and is used to output a switching control signal Mode_Switch.

[0106] The output end of the coefficient adjustment module 135 is electrically connected to the input end of the current source circuit 14, and is used to output a frequency control signal (CCTW / FCTW).

[0107] Among them, the frequency-phase conversion module 131, the phase error detection module 132, the mode detection module 133, the frequency locking module 134, and the coefficient adjustment module 135 cooperate to jointly achieve frequency locking. The mode switching module 136 is used to output a clear signal CLEAR to the clear end of the phase error detection module 132 after frequency locking, control the phase error detection module 132 to be cleared, and output a switching control signal Mode_Switch to turn on the voltage-current converter 154, so that the voltage-current converter 154 outputs a second current signal I2 to the voltage-controlled oscillator 155.

[0108] In one embodiment, the frequency-phase conversion module 131 is based on a first division value of 2 pPerform phase conversion on the first divided-frequency signal F_Din to obtain the first phase signal Ph_CKR, and based on the second division value 2 q Perform phase conversion on the second divided-frequency signal F_Clki to obtain the second phase signal Ph_CKV. Among them, the first phase signal Ph_CKR includes digital signals of the first bit, and the second phase signal Ph_CKV includes digital signals of the second bit;

[0109] The phase error detection module 132 generates a phase error ph_err based on the first bit and the second bit.

[0110] Specifically, the frequency and phase conversion module 131 performs phase conversion on the first divided-frequency signal F_Din based on the preset first division value 2 p Perform phase conversion on the first divided-frequency signal F_Din to obtain the first phase signal Ph_CKR, and based on the preset second division value 2 q Perform phase conversion on the second divided-frequency signal F_Clki to obtain the second phase signal Ph_CKV. Among them, the first phase signal Ph_CKR includes digital signals of the first bit n, and the second phase signal Ph_CKV includes digital signals of the second bit m (that is to say, the first phase signal Ph_CKR is composed of n bit digital signals, and the second phase signal Ph_CKV is composed of m bit digital signals, where m > n).

[0111] Since , so ;

[0112] In a specific implementation, when n is a preset value, m is calculated based on the above equation. When m is a preset value, n is calculated based on the above equation;

[0113] In one embodiment, the first phase signal Ph_CKR is denoted as Ph_CKR[n + p + a - 1:p + a]; the second phase signal Ph_CKV is denoted as Ph_CKV[m + q + a - 1:q + a], where a is a preset value and a is a positive integer ≥ 0.

[0114] For example, based on the above example description, perform 32 - division on the single - ended data signal Din, and the preset first division value 2 p is 32 , to generate the first divided - frequency signal F_Din;

[0115] Perform 4 - division on the sampling clock signal Clki at the preset phase, and the preset second division value 2 q is 4 , to generate the second divided - frequency signal F_Clki.

[0116] When n is set to 8, since p + n = q + m, p = 5, q = 2, and a = 0, m is calculated to be 11;

[0117] The first phase signal Ph_CKR is an 8-bit digital signal, denoted as Ph_CKR[12:5];

[0118] The second phase signal Ph_CKV is an 11-bit digital signal, denoted as Ph_CKV[12:2].

[0119] The phase error detection module 132 generates a phase error ph_err based on the first bit n and the second bit m.

[0120] Specifically, since the number of bits of the first phase signal Ph_CKR and the second phase signal Ph_CKV is different (i.e., the first bit n and the second bit m are different), the first phase signal Ph_CKR can be left-shifted until the number of bits of the first phase signal Ph_CKR and the second phase signal Ph_CKV is the same to generate the phase error ph_err. The specific expression formula of the phase error ph_err is as follows: Among them, (m - n)'b0 represents that the first phase signal Ph_CKR is left-shifted by (m - n) bits.

[0121] Among them, the larger the preset value a, the larger the error range of the phase error ph_err, and the smaller the preset value a, the smaller the error range of the phase error ph_err.

[0122] For example, on the basis of the above example, first perform a left-shift process on the first phase signal Ph_CKR[12:5] until the number of bits is equal to that of the second phase signal Ph_CKV[12:2], and then generate a phase error .

[0123] In one embodiment, in each cycle of the first divided-frequency signal F_Din, when the digital controller 13 determines that the absolute value of the phase error |ph_err| is less than the second preset value B (i.e., |ph_err| < B), it outputs a switching control signal Mode_Switch; when it determines that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B (i.e., |ph_err| ≥ B), it outputs a frequency control signal (CCTW / FCTW).

[0124] Specifically, when |ph_err| < B, the mode switching module 136 outputs the switching control signal Mode_Switch to the voltage-current converter 154 in the clock signal generation module 15; when |ph_err| ≥ B, the coefficient adjustment module 135 outputs the frequency control signal (CCTW / FCTW) to the current source circuit 14.

[0125] In one embodiment, as Figure 8 shown, the current source circuit 14 includes a first current source branch 141 and a second current source branch 142. The frequency control signal includes a first frequency control signal CCTW and a second frequency control signal FCTW. After the digital controller 13 determines that the absolute value |ph_err| of the phase error is greater than or equal to a second preset value B, it compares the absolute value |ph_err| of the phase error with a first preset value A. When it determines that the absolute value |ph_err| of the phase error is greater than or equal to the first preset value A, it adjusts the current first frequency control signal and outputs an adjusted first frequency control signal CCTW to adjust the number of first current sources operating in the first current source branch 141; when it determines that the absolute value |ph_err| of the phase error is greater than or equal to the second preset value B and less than the first preset value A, it adjusts the current second frequency control signal and outputs an adjusted second frequency control signal FCTW to adjust the number of second current sources operating in the second current source branch 142; the first preset value A is greater than the second preset value B, and the first preset value A and the second preset value B are positive integers.

[0126] Among them, the current value of the current output by the first current source in the first current source branch 141 is greater than the current value of the current output by the second current source in the second current source branch 142.

[0127] Specifically, referring to Figure 7 , the frequency locking module 134 receives the phase error ph_err output by the phase error detection module 132, determines the absolute value |ph_err| of the phase error, compares the absolute value |ph_err| of the phase error with the second preset value B. When it determines that the absolute value |ph_err| of the phase error is less than the second preset value B, the third output terminal of the frequency locking module 134 outputs a frequency locking signal F_LOCK. After the input terminal of the mode switching module 136 receives the frequency locking signal F_LOCK, it outputs a switching control signal Mode_Switch to the voltage-current converter 154;

[0128] When the frequency locking module 134 determines that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B (i.e., |ph_err|≥B), it compares the absolute value of the phase error |ph_err| with the first preset value A. When it determines that the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A (i.e., |ph_err|≥A), the frequency locking module 134 outputs a first control signal to the coefficient adjustment module 135. After receiving the first control signal, the coefficient adjustment module 135 adjusts the current first frequency control signal CCTW, and outputs the adjusted first frequency control signal CCTW to the first current source branch 141 in the current source circuit 14, so as to control the coefficient adjustment module 135 to enter the coarse adjustment and achieve the rapid approximation of the frequency.

[0129] In another embodiment, when the frequency locking module 134 determines that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B and less than the first preset value A (i.e., B≤|ph_err|<A), it outputs a second control signal to the coefficient adjustment module 135. After receiving the second control signal, the coefficient adjustment module 135 adjusts the current second frequency control signal FCTW, and outputs the adjusted second frequency control signal FCTW to the second current source branch 142 in the current source circuit 14, to control the coefficient adjustment module 135 to enter the fine adjustment and achieve the accurate locking of the frequency.

[0130] For example, the first preset value A is 10 and the second preset value B is 5. When the absolute value of the phase error |ph_err| received by the frequency locking module 134 is 11, it determines that the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B (i.e., 11>5), and then compares the absolute value of the phase error |ph_err| with the first preset value A, and determines that the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A (i.e., 11>10). The frequency locking module 134 outputs a first control signal to the coefficient adjustment module 135. After receiving the first control signal, the coefficient adjustment module 135 adjusts the current first frequency control signal CCTW, and outputs the adjusted first frequency control signal CCTW to the first current source branch 141 in the current source circuit 14, so as to control the coefficient adjustment module 135 to enter the coarse adjustment.

[0131] In one embodiment, if the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A and ph_err is a positive number, it indicates that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. Then, based on the adjusted first frequency control signal CCTW, the current source circuit 14 increases the number of the first current sources working in the first current source branch 141 to increase the first current signal;

[0132] If the absolute value of the phase error |ph_err| is greater than or equal to the first preset value A and ph_err is negative, it indicates that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase. Then, the current source circuit 14 reduces the number of first current sources operating in the first current source branch 141 based on the adjusted first frequency control signal CCTW to reduce the first current signal.

[0133] It should be noted that in the embodiments of the present application, when the phase error ph_err is positive, it is determined that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. When the phase error ph_err is negative, it is determined that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase.

[0134] Reference Figure 8 , the current source circuit 14 includes a first current source branch 141 and a second current source branch 142. The first current source branch 141 and the second current source branch 142 are connected in series. The first current source branch 141 includes m first current sources (S11, S12,..., S1m) and third switches (K11, K12,..., K1m) connected to each first current source (S11, S12,..., S1m) in one-to-one correspondence. The first ends of the first current sources (S11, S12,..., S1m) are electrically connected to the power supply voltage terminal VDD. The second ends of the first current sources (S11, S12,..., S1m) are electrically connected to one ends of the third switches (K11, K12,..., K1m). The other ends of the third switches (K11, K12,..., K1m) are electrically connected to the second output terminal of the digital controller 13, serving as the input end of the current source circuit 14. The second current source branch 142 includes n second current sources (S21, S22,..., S2n) and fourth switches (K21, K22,..., K2n) connected to each second current source (S21, S22,..., S2n) in one-to-one correspondence. The first ends of the second current sources (S21, S22,..., S2n) are electrically connected to the power supply voltage terminal VDD. The second ends of the second current sources (S21, S22,..., S2n) are electrically connected to one ends of the fourth switches (K21, K22,..., K2n). The other ends of the fourth switches (K21, K22,..., K2n) are respectively electrically connected to the input end of the voltage-controlled oscillator 155 and the other ends of the third switches (K11, K12,..., K1m), serving as the output end of the current source circuit 14.

[0135] In the current source circuit 14, when the frequency control signal output by the coefficient adjustment module 135 in the digital controller 13 is the first frequency control signal CCTW, the first current source branch 141 operates. Under the control of the first frequency control signal CCTW, the first current source branch 141 selectively closes one or more of the third switches (K11, K12, …, K1m), so that the first current sources (S11, S12, …, S1m) corresponding to the closed third switches (K11, K12, …, K1m) output current signals, and the current signals are output as the first current signal I1 to the voltage-controlled oscillator 155. The voltage-controlled oscillator 155 adjusts the frequency of the output sampling clock signal according to the change of the first current signal I1.

[0136] During the process of coarse frequency adjustment, if the frequency of the single-ended data signal Din is greater than the frequency of the second sampling clock signal DClk, the current source circuit 14 increases the number of the first current sources (S11, S12, …, S1m) working in the first current source branch 141 of the current source circuit 14 according to the first frequency control signal CCTW, so that the first current signal I1 output by the first current source branch 141 increases. According to the increased first current signal I1, the voltage-controlled oscillator 155 increases the frequencies of multiple sampling clock signals (Clk1, … Clki, … Clkn) for adjustment, so that the frequencies of the multiple sampling clock signals (Clk1, … Clki, … Clkn) increase rapidly, thereby achieving rapid approximation of the frequency. During the process of coarse frequency adjustment, there are at least two methods for increasing frequency adjustment, which are specifically as follows:

[0137] Method 1:

[0138] The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the first frequency control signal CCTW based on the absolute value of the phase error |ph_err|, and outputs it to the current source circuit 14. For example, the first frequency control signal CCTW is adjusted from the original CCTW<4:0>=00011 to CCTW<4:0>=01111. The current source circuit 14 controls the conduction of an appropriate number of first current sources (S11, S12, …, S1m) to increase according to the received first frequency control signal CCTW<4:0>=01111. For example, there are 5 first current sources (S11, S12, S13, S14, S15) in the first current source branch 141. The currently conducting first current sources in the first current source branch 141 are the first current source S14 and the first current source S15. According to the first frequency control signal CCTW<4:0>=01111, the first current source branch 141 newly conducts the first current source S12 and the first current source S13, and takes the total current output by the first current source S12, the first current source S13, the first current source S14, and the first current source S15 as the first current signal I1, and outputs the first current signal I1 to the voltage controlled oscillator 155 to control and adjust the frequency of the sampling clock signal.

[0139] Method 2:

[0140] The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the first frequency control signal CCTW based on the absolute value |ph_err| of the phase error, and outputs it to the current source circuit 14. For example, there are 5 first current sources (S11, S12, S13, S14, S15) in the first current source branch 141. First, the first frequency control signal CCTW is adjusted from the original CCTW<4:0>=00011 to CCTW<4:0>=00111. That is, the current source circuit 14 controls to turn on one more first current source (S11, S12, S13, S14, S15) according to the received first frequency control signal CCTW<4:0>=00111. For example, the first current source S13 is newly turned on, and the total current output by the first current source S13, the first current source S14, and the first current source S15 is used as the first current signal I1, and the first current signal I1 is output to the voltage-controlled oscillator 155 to control the voltage-controlled oscillator 155 to adjust the frequency of the sampling clock signal; then, the phase error detection module 132 detects the phase of the single-ended data signal Din and the phase of the adjusted sampling clock signal again to obtain the absolute value |ph_err2| of the next phase error. The frequency locking module 134 controls the coefficient adjustment module 135 to adjust the first frequency control signal CCTW to CCTW<4:0>=01111 based on the absolute value |ph_err2| of the next phase error. The current source circuit 14 controls to turn on one more first current source (S11, S12, S13, S14, S15) according to the received first frequency control signal CCTW<4:0>=01111. For example, the first current source S12 is newly turned on, and the total current output by the first current source S12, the first current source S13, the first current source S14, and the first current source S15 is used as the first current signal I1, and the first current signal I1 is output to the voltage-controlled oscillator 155 to control the voltage-controlled oscillator 155 to adjust the frequency of the sampling clock signal until the absolute value |ph_err| of the phase error is less than the first preset value A, indicating that the frequency coarse adjustment process is completed.

[0141] If the frequency of the single-ended data signal Din is less than the frequency of the second sampling clock signal DClk, the current source circuit 14 reduces the number of first current sources (S11, S12, …, S1m) operating in the first current source branch 141 of the current source circuit 14 according to the first frequency control signal CCTW, so that the first current signal I1 output by the first current source branch 141 decreases. Based on the decreased first current signal I1, the voltage-controlled oscillator 155 reduces the frequencies of multiple sampling clock signals (Clk1, …, Clki, …, Clkn) to enable the frequencies of the multiple sampling clock signals (Clk1, …, Clki, …, Clkn) to decrease rapidly, facilitating the rapid catch-up of the frequency of the single-ended data signal Din with the frequency of the second sampling clock signal DClk, thereby achieving rapid frequency approximation. Similarly, during the coarse frequency adjustment process, there are at least two methods for reducing frequency adjustment, which can refer to the principle of the above-mentioned frequency increase adjustment method and will not be repeated here.

[0142] In one embodiment, if the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B and less than the first preset value A, and the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase, the current source circuit 14 increases the number of second current sources operating in the second current source branch 142 based on the second frequency control signal FCTW to increase the first current signal;

[0143] If the absolute value of the phase error |ph_err| is greater than or equal to the second preset value B and less than the first preset value A, and the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase, the number of second current sources operating in the second current source branch 142 is reduced according to the second frequency control signal FCTW to decrease the first current signal.

[0144] When the frequency control signal output by the digital controller 13 is the second frequency control signal FCTW, the second current source branch 142 operates. Under the control of the second frequency control signal FCTW, the second current source branch 142 selectively closes one or more of the fourth switches (K21, K22, …, K2n) so that the second current sources (S21, S22, …, S2n) corresponding to the closed fourth switches (K21, K22, …, K2n) output current signals, and the current signals are output as the first current signal I1 to the voltage-controlled oscillator 155. The voltage-controlled oscillator 155 adjusts the frequency of the output sampling clock signal according to the change of the first current signal I1.

[0145] During the process of fine frequency adjustment, if the frequency of the single-ended data signal Din is greater than the frequency of the second sampling clock signal DClk, the current source circuit 14 increases the number of the second current sources (S21, S22, …, S2n) operating in the second current source branch 142 of the current source circuit 14 according to the second frequency control signal FCTW, so that the first current signal I1 output by the second current source branch 142 increases. According to the increased first current signal I1, the voltage-controlled oscillator 155 adjusts the frequencies of a plurality of sampling clock signals (Clk1, … Clki, … Clkn) to increase them slowly, facilitating the precise adjustment of the frequency of the sampling clock signal Clki at the preset phase, making the frequency of the single-ended data signal Din and the frequency of the sampling clock signal Clki at the preset phase closer, thereby achieving accurate frequency locking. During the process of fine frequency adjustment, there are at least two methods for increasing frequency adjustment, which are as follows:

[0146] Method 1:

[0147] The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW based on the absolute value |ph_err| of the phase error, and outputs it to the current source circuit 14. For example, the second frequency control signal FCTW is adjusted from the original FCTW<4:0>=00101 to FCTW<4:0>=11101. The current source circuit 14 controls the addition of an appropriate number of second current sources (S21, S22, …, S2n) to conduct according to the received second frequency control signal FCTW<4:0>=11101. For example, there are 5 second current sources (S21, S22, S23, S24, S25) in the second current source branch 142, and the currently conducting second current sources in the second current source branch 142 are the second current source S23 and the second current source S25. According to the second frequency control signal FCTW<4:0>=11101, the second current source branch 142 newly adds the second current source S21 and the second current source S22 to conduct, and takes the total current output by the second current source S21, the second current source S22, the second current source S23, and the second current source S25 as the first current signal I1, and outputs the first current signal I1 to the voltage-controlled oscillator 155 to control and adjust the frequency of the sampling clock signal.

[0148] Method 2:

[0149] The frequency locking module 134 in the digital controller 13 controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW based on the absolute value of the phase error |ph_err|, and outputs it to the current source circuit 14. For example, first, the second frequency control signal FCTW is adjusted from the original FCTW<4:0>=00101 to FCTW<4:0>=00111. The current source circuit 14 controls to turn on one more second current source (S21, S22, …, S2n) according to the received second frequency control signal FCTW<4:0>=00111. For example, the second current source S24 is newly turned on, and the total current output by the second current source S23, the second current source S24, and the second current source S25 is used as the first current signal I1, and the first current signal I1 is output to the voltage-controlled oscillator 155 to control the voltage-controlled oscillator 155 to adjust the frequency of the sampling clock signal; then, the phase error detection module 132 detects the phase of the single-ended data signal Din and the phase of the adjusted sampling clock signal again to obtain the absolute value of the next phase error |ph_err2|. The frequency locking module 134 controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW to FCTW<4:0>=10111 based on the absolute value of the next phase error |ph_err2|. The current source circuit 14 controls to turn on one more second current source (S21, S22, …, S2n) in the second current source branch 142 of the current source circuit 14 according to the received second frequency control signal FCTW<4:0>=10111. For example, the second current source S21 is newly turned on, and the total current output by the second current source S21, S23, S24, and S25 is used as the first current signal I1, and the first current signal I1 is output to the voltage-controlled oscillator 155 to control the voltage-controlled oscillator 155 to adjust the frequency of the sampling clock signal until the absolute value of the phase error |ph_err| is less than the second preset value B, indicating that the frequency fine adjustment process is completed. At this time, the frequency is locked and the phase locking link begins.

[0150] If the frequency of the single-ended data signal Din is less than the frequency of the second sampling clock signal DClk, the current source circuit 14 reduces the number of the second current sources (S21, S22, …, S2n) working in the second current source branch 142 of the current source circuit 14 according to the second frequency control signal FCTW, so that the first current signal I1 output by the second current source branch 142 decreases. According to the reduced first current signal I1, the voltage-controlled oscillator 155 reduces and adjusts the frequencies of multiple sampling clock signals (Clk1, … Clki, … Clkn) so that the multiple sampling clock signals (Clk1, … Clki, … Clkn) slowly decrease, thereby achieving accurate frequency locking. During the frequency fine adjustment process, there are at least two methods of frequency reduction adjustment, which can refer to the principle of the above frequency increase adjustment method and will not be repeated here.

[0151] It should be noted that in the embodiments of the present invention, the current value of the current output by the first current sources (S11, S12, …, S1m) is greater than the current value of the current output by the second current sources (S21, S22, …, S2n), and the number m of the first current sources (S11, S12, …, S1m) and the number n of the second current sources (S21, S22, …, S2n) may be equal or unequal, and the embodiments of the present invention do not impose any restrictions on this.

[0152] In the embodiments of the present application, after the coefficient adjustment module 135 receives the first control signal sent by the frequency locking module 134, it determines whether the received phase error ph_err is positive or negative. If the phase error ph_err is positive, it indicates that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current first frequency control signal CCTW and outputs the adjusted first frequency control signal CCTW, and the adjusted first frequency control signal CCTW is used to reduce the number of the first current sources operating in the first current source branch 141;

[0153] If the phase error ph_err is negative, it indicates that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current first frequency control signal CCTW and outputs the adjusted first frequency control signal CCTW, and the adjusted first frequency control signal CCTW is used to increase the number of the first current sources operating in the first current source branch 141.

[0154] After the coefficient adjustment module 135 receives the second control signal sent by the frequency locking module 134, it determines whether the received phase error ph_err is positive or negative. If the phase error ph_err is positive, it indicates that the frequency of the single-ended data signal Din is greater than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current second frequency control signal FCTW and outputs the adjusted second frequency control signal FCTW, and the adjusted second frequency control signal FCTW is used to reduce the number of the second current sources operating in the second current source branch 142;

[0155] If the phase error ph_err is negative, it indicates that the frequency of the single-ended data signal Din is less than the frequency of the sampling clock signal Clki at the preset phase. The coefficient adjustment module 135 adjusts the current second frequency control signal FCTW and outputs the adjusted second frequency control signal FCTW, and the adjusted second frequency control signal FCTW is used to increase the number of the second current sources operating in the second current source branch 142.

[0156] In one embodiment, after the coefficient adjustment module 135 outputs the first frequency control signal CCTW, that is, during coarse adjustment, when the frequency locking module 134 determines that the absolute value |ph_err2| of the next phase error is less than the first preset value A, the first frequency control signal CCTW remains unchanged. In the next cycle of the first divided frequency signal F_Din, it is judged whether the absolute value |ph_err2| of the next phase error is greater than or equal to the second preset value B. When the absolute value |ph_err2| of the next phase error is greater than or equal to the second preset value B, the current second frequency control signal is adjusted, and the adjusted second frequency control signal FCTW is output; when the absolute value |ph_err2| of the next phase error is less than the second preset value B, a switching control signal Mode_Switch is output.

[0157] In the embodiment of the present application, when the frequency locking module 134 determines that the absolute value |ph_err| of the phase error is greater than or equal to the first preset value A, a first control signal is output to the coefficient adjustment module 135. After receiving the first control signal, the coefficient adjustment module 135 determines whether the phase error ph_err is positive or negative, and based on the judgment result, an adjusted first frequency control signal CCTW is output to the first current source branch 141 in the current source circuit 14. The first current output by the current source circuit 14 changes, so that the phase error ph_err output by the phase error detection module 132 changes, that is, the phase error detection module 132 outputs the next phase error ph_err2. The frequency locking module 134 compares the absolute value |ph_err2| of the next phase error with the first preset value A. If the absolute value |ph_err2| of the next phase error is greater than or equal to the first preset value A, the step of outputting the first control signal to the coefficient adjustment module 135 is executed. If the absolute value |ph_err2| of the next phase error is less than the first preset value A, the coarse adjustment ends. At this time, the frequency locking module 134 does not output the first control signal to the coefficient adjustment module 135. Therefore, the first frequency control signal CCTW output by the coefficient adjustment module 135 remains unchanged.

[0158] In one embodiment, after the coarse adjustment is completed, the fine adjustment is entered. After the frequency locking module 134 determines that the absolute value |ph_err2| of the next phase error is less than the first preset value A, it compares the absolute value |ph_err2| of the next phase error with the second preset value B to determine whether the absolute value |ph_err2| of the next phase error is greater than or equal to the second preset value B. If it is greater than or equal to the second preset value B, the frequency locking module 134 outputs a second control signal to the coefficient adjustment module 135. After receiving the second control signal, the coefficient adjustment module 135 determines whether the phase error ph_err is positive or negative, and adjusts the current second frequency control signal FCTW based on the determination result, and outputs the adjusted second frequency control signal FCTW to the second current source branch 142;

[0159] After the second current source branch 142 outputs the adjusted second frequency control signal FCTW, the phase error output by the phase error detection module 132 changes, that is, the phase error detection module 132 outputs the next next phase error ph_err3. After receiving the next next phase error ph_err3, the frequency locking module 134 determines whether the absolute value |ph_err3| of the next next phase error is still greater than or equal to the second preset value B and less than the first preset value A. If so, continue to adjust the current second frequency control signal FCTW until the absolute value of the phase error output by the phase error detection module 132 is less than the second preset value B, and the fine adjustment ends. The frequency locking module 134 outputs a frequency locking signal F_LOCK to the mode switching module 136. After receiving the frequency locking signal F_LOCK, the mode switching module 136 outputs a switching control signal Mode_Switch;

[0160] If the absolute value |ph_err2| of the next phase error is less than the second preset value B, the frequency locking module 134 outputs a frequency locking signal F_LOCK to the mode switching module 136. After receiving the frequency locking signal F_LOCK, the mode switching module 136 outputs a switching control signal Mode_Switch, and outputs a clear signal CLEAR to the clear end of the phase error detection module 132 to control the phase error detection module 132 to be cleared.

[0161] As Figure 9 shown, it is a schematic flowchart of the operation of a digital controller provided by an embodiment of the present application;

[0162] S901: The coefficient adjustment module 135 outputs a first frequency control signal CCTW;

[0163] S902: The frequency locking module 134 determines that based on the absolute value |ph_err2| of the next phase error being less than the first preset value A, it controls the coefficient adjustment module 135 to output the first frequency control signal CCTW unchanged;

[0164] In step 901, the next phase error ph_err2 is output by the phase error detection module 132 after the coefficient adjustment module 135 outputs the first frequency control signal CCTW.

[0165] In one embodiment, after the frequency locking module 134 outputs the first control signal to the coefficient adjustment module 135, it can also output a low-level coarse adjustment signal LOCK to the mode detection module 133 A , the low-level coarse adjustment signal LOCK A indicates that the coefficient adjustment module is performing coarse adjustment; when the frequency locking module 134 controls the coefficient adjustment module 135 to keep the first frequency control signal CCTW unchanged, it can also output a high-level coarse adjustment signal LOCK to the mode detection module 133 A , the high-level coarse adjustment signal LOCK A indicates that the coarse adjustment is completed.

[0166] In the embodiment of the present application, the frequency locking module 134 controls the coefficient adjustment module 135 to keep the first frequency control signal CCTW unchanged, that is, the frequency locking module 134 does not output the first control signal to the coefficient adjustment module 135. After the frequency locking module 134 controls the coefficient adjustment module 135 to keep the first frequency control signal CCTW unchanged, it can also determine that after the current period of the first divided-frequency signal ends, in each period of a preset number of consecutive periods of the first divided-frequency signal F_Din, when it is determined that the absolute value of the phase error is less than the first preset value, the first frequency control signal CCTW is kept unchanged, where the first period of the preset number of consecutive periods is adjacent to the current period of the first divided-frequency signal.

[0167] In a specific implementation, the mode detection module 133 determines whether the received coarse adjustment signal is continuously high-level within a preset number of periods of the first divided-frequency signal F_Din. If so, it sends a third control signal to the frequency locking module. After receiving the third control signal, the frequency locking module 134 sends a coarse adjustment locking signal to the coefficient adjustment module 135. After receiving the coarse adjustment locking signal, the coefficient adjustment module 135 locks the current first frequency control signal CCTW.

[0168] For example, in the first period of the first divided-frequency signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133 A ; in the second period of the first divided-frequency signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133 A; In the third cycle of the first divided-frequency signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133. A ; In the fourth cycle of the first divided-frequency signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133. A ; In the fifth cycle of the first divided-frequency signal F_Din, the frequency locking module 134 outputs a high-level coarse adjustment signal LOCK to the mode detection module 133. A . After the mode detection module 133 continuously receives 5 high-level coarse adjustment signals LOCK A , it outputs a third control signal to the frequency locking module 134.

[0169] S903: In the next cycle of the first divided-frequency signal F_Din, the frequency locking module 134 determines whether the absolute value |ph_err2| of the next phase error is greater than or equal to a second preset value B. If the determination result is yes, execute S904; if the determination result is no, execute S905;

[0170] S904: The frequency locking module 134 controls the coefficient adjustment module 135 to perform fine adjustment, adjusts the current second frequency control signal, and outputs the adjusted second frequency control signal FCTW.

[0171] When the frequency locking module 134 controls the coefficient adjustment module 135 to perform fine adjustment, in the next cycle of the first divided-frequency signal F_Din, after the frequency locking module 134 determines that the absolute value of the next phase error ph_err2 is greater than or equal to the second preset value B, it outputs a second control signal to the coefficient adjustment module 135 to control the coefficient adjustment module 135 to perform fine adjustment. After receiving the second control signal, the coefficient adjustment module 135 adjusts the current second frequency control signal FCTW. The frequency locking module 134 can also output a second control signal to the coefficient adjustment module 135 after receiving the third control signal sent by the mode detection module 133.

[0172] S905: The frequency locking module 134 controls the mode switching module 136 to output a switching control signal Mode_Switch, and outputs a clearing signal CLEAR to the clearing end of the phase error detection module 132 to control the phase error detection module 132 to clear.

[0173] In an embodiment of the present application, within the coarse adjustment mode, it is determined respectively within each period of the first divided-frequency signal F_Din whether the absolute value of the phase error is less than a first preset value. When the absolute value of the phase error is less than the first preset value, the control coefficient adjustment module keeps the first frequency control signal CCTW unchanged within the next period of the first divided-frequency signal F_Din, and controls the coarse adjustment signal LOCK output by the frequency locking module A to be at a high level. When the absolute value of the phase error is greater than or equal to the first preset value, the control coefficient adjustment module adjusts the current first frequency control signal CCTW within the next period of the first divided-frequency signal F_Din, and controls the coarse adjustment signal LOCK output by the frequency locking module A to be at a low level.

[0174] The mode detection module detects the received coarse adjustment signal LOCK A to determine whether it is continuously at a high level within a preset number of periods of the first divided-frequency signal F_Din; if it is continuously at a high level, the frequency locking module is controlled to output a coarse adjustment lock signal to enter the fine adjustment mode; if it is not continuously at a high level, the control coefficient adjustment module adjusts the current first frequency control signal CCTW within the next period of the first divided-frequency signal F_Din to continue the frequency adjustment in the coarse adjustment stage.

[0175] In one embodiment, after the digital controller 13 outputs the second frequency control signal FCTW, when it is determined that the absolute value |ph_err2| of the next phase error is less than the second preset value B, the second frequency control signal FCTW is kept unchanged and a switching control signal is output; when the absolute value |ph_err2| of the next phase error is greater than or equal to the second preset value B, the current second frequency control signal is adjusted and the adjusted second frequency control signal FCTW is output.

[0176] In the embodiment of the present application, when the frequency locking module 134 determines that the absolute value |ph_err| of the phase error is less than the first preset value and greater than or equal to the second preset value, it outputs a second control signal to the coefficient adjustment module 135. After receiving the second control signal, the coefficient adjustment module 135 outputs an adjusted second frequency control signal FCTW to the second current source branch 142 in the current source circuit 14. The current output by the current source circuit 14 changes, so that the phase error output by the phase error detection module 132 changes, that is, the phase error detection module 132 outputs the next phase error ph_err2. The frequency locking module 134 compares the absolute value |ph_err2| of the next phase error with the second preset value B. If the absolute value |ph_err2| of the next phase error is greater than or equal to the second preset value B, the second frequency control signal FCTW is continuously adjusted. If the absolute value |ph_err2| of the next phase error is less than the second preset value B, the current second frequency control signal FCTW is maintained, and the frequency locking module 134 outputs a frequency locking signal F_LOCK. After receiving the frequency locking signal F_LOCK, the mode switching module 136 outputs a switching control signal.

[0177] As Figure 10 shown, it is a schematic flow chart of the operation of another digital controller provided by the embodiment of the present application;

[0178] S1001: The coefficient adjustment module 135 outputs a second frequency control signal FCTW;

[0179] S1002: The frequency locking module 134 determines whether the absolute value |ph_err2| of the next phase error is less than the second preset value B; if the determination result is yes, S1003 is executed; if the determination result is no, S1004 is executed;

[0180] The next phase error ph_err2 is output by the phase error detection module 132 after the coefficient adjustment module 135 outputs an adjusted second frequency control signal FCTW.

[0181] S1003: The frequency locking module 134 controls the second frequency control signal FCTW output by the coefficient adjustment module 135 to remain unchanged, controls the mode switching module 136 to output a switching control signal Mode_Switch, and outputs a clear signal CLEAR to the clear terminal of the phase error detection module 132 to control the phase error detection module 132 to be cleared;

[0182] S1004: Adjust the current second frequency control signal, output an adjusted second frequency control signal FCTW, and return to S1001.

[0183] When the frequency locking module 134 determines that the absolute value of the next phase error |ph_err2| is greater than or equal to the second preset value B, it can also output a low-level fine adjustment signal LOCK to the mode detection module. B When the frequency locking module 134 controls the second frequency control signal FCTW output by the coefficient adjustment module 135 to remain unchanged, it can also output a high-level fine adjustment signal LOCK to the mode detection module 133. B .

[0184] The digital controller 13 can also, after determining the end of the current period of the first divided-frequency signal, keep the second frequency control signal FCTW unchanged in each period of a preset number of consecutive periods of the first divided-frequency signal F_Din, where the absolute value of the phase error |ph_err| is less than the second preset value B, and the first period of the preset number of consecutive periods is adjacent to the current period of the first divided-frequency signal.

[0185] In a specific implementation, the mode detection module 133 determines whether the received fine adjustment signal is continuously high-level within a preset number of periods of the first divided-frequency signal F_Din. If so, it sends a fourth control signal to the frequency locking module. After receiving the fourth control signal, the frequency locking module sends a fine adjustment locking signal to the coefficient adjustment module 135. After receiving the fine adjustment locking signal, the coefficient adjustment module 135 locks the current second frequency control signal FCTW.

[0186] In the embodiment of the present application, within the fine adjustment mode, it is determined respectively in each period of the first divided-frequency signal F_Din whether the absolute value of the phase error is less than the second preset value, where the second preset value is less than the first preset value. When the absolute value of the phase error is less than the second preset value, it controls the coefficient adjustment module 135 to keep the second frequency control signal FCTW unchanged in the next period of the first divided-frequency signal F_Din, and controls the fine adjustment signal LOCK output by the frequency locking module 134 B to be high level. When the absolute value of the phase error is greater than or equal to the second preset value, it controls the coefficient adjustment module 135 to adjust the second frequency control signal FCTW in the next period of the first divided-frequency signal F_Din, and controls the fine adjustment signal LOCK output by the frequency locking module 134 B to be low level.

[0187] The mode detection module 133 detects the received fine adjustment signal LOCK BWhether it is continuously high-level within the periods of a preset number of first divided-frequency signals F_Din; if it is continuously high-level, the frequency locking module is controlled to output a fine-tuning locking signal, and the mode switching module outputs a mode switching control signal to enter the phase locking mode; if it is not continuously high-level, the control coefficient adjustment module adjusts the current second frequency control signal within the next period of the first divided-frequency signal F_Din and continues the frequency adjustment in the fine-tuning stage.

[0188] In one embodiment, the digital controller 13 can also output a switching control signal after receiving an enabling signal, where the enabling signal is used to indicate phase locking.

[0189] Specifically, as Figure 11 shown, it is the flowchart of the operation in the frequency locking stage. The digital controller 13 receives an enabling signal no_link from the outside. If the enabling signal no_link = 1, the digital controller 13 will skip the frequency locking stage and directly output a switching control signal Mode_Switch to the voltage-current converter 154 to enable the phase locking loop to start working and lock the phase; if the enabling signal no_link = 0, the digital controller 13 enters the frequency locking stage. At this time, frequency coarse adjustment is first performed. If the coarse adjustment end signal cctw_finish output by the mode detection module 133 to the frequency locking module 134 is 0, it indicates that the frequency coarse adjustment has not ended, and the frequency locking module 134 outputs a locking signal lock = 0 to the mode switching module 136; if the coarse adjustment end signal cctw_finish = 1, it indicates that the frequency coarse adjustment has ended, and the locking signal lock = 1 is output. Then frequency fine adjustment is performed. If the fine adjustment end signal fctw_finish output by the mode detection module 133 to the frequency locking module 134 is 0, it indicates that the frequency fine adjustment has not ended, and the frequency locking module 134 outputs a locking signal lock = 0 to the mode switching module 136. If the fine adjustment end signal fctw_finish = 1, it indicates that the frequency fine adjustment has ended, and the locking signal lock = 1 is output to enter the phase locking stage.

[0190] In the above solution, after receiving the enabling signal, the digital controller 13 can skip the frequency locking stage and directly enter the phase locking stage, thereby improving the flexibility and universality of the clock data recovery circuit.

[0191] In one embodiment, after generating the phase error, the digital controller can also calculate the phase error based on the error precision selection signal to obtain the phase selection error; and output a frequency control signal or a switching control signal based on the phase selection error.

[0192] Specifically, as Figure 12As shown in the figure, it is a schematic structural diagram of another digital controller provided by an embodiment of the present application. The digital controller 13 further includes an error precision selection module 137. The input end of the error precision selection module 137 is electrically connected to the output end of the phase error detection module 132, and the output end of the error precision selection module 137 is electrically connected to the first input end of the frequency locking module 134 and the first input end of the coefficient adjustment module 135. By selecting different phase selection errors through the error precision selection module 137, the smaller the phase selection error, the more precise the frequency adjustment of the first frequency control signal CCTW and the second frequency control signal FCTW, making the output frequency closer to the input frequency.

[0193] The error precision selection module 137 determines the target error precision based on the error precision selection signal, calculates the phase error ph_err[n + p + a - 1:q + a], and obtains the phase selection error ph_err_SW[n + p + a - 1:0]; the digital controller 13 outputs a frequency control signal or a switching control signal based on the phase selection error ph_err_SW[n + p + a - 1:0].

[0194] Among them, the error precision selection signal is selected by the user based on the register settings. If the error precision selection signal is a digital signal of (q + a) bit, the number of types of error precision is 2 q+a , specifically, the phase selection error = 2 x × the phase error. As shown in Table 1, when q = 2 and a = 0:

[0195] Table 1

[0196]

[0197] Based on the same inventive concept, an embodiment of the present application further provides a display chip. The principle of the display chip to solve the technical problem is similar to the principle of the above clock data recovery circuit to solve the technical problem. The implementation of the display chip can refer to the implementation of the clock data recovery circuit, and the repeated parts will not be described again.

[0198] An embodiment of the present application provides a display chip, including the clock data recovery circuit described in any one of the above.

[0199] Based on the same inventive concept, an embodiment of the present application further provides a display device. The principle of the display device to solve the technical problem is similar to the principle of the above display chip. The implementation of the display device can refer to the implementation of the display chip, and the repeated parts will not be described again.

[0200] An embodiment of the present application provides a display device, including the above display chip.

[0201] The present application provides a clock data recovery circuit, a display chip, and a display device. In the circuit, a differential-to-single-ended circuit converts a differential data signal into a single-ended data signal. A frequency division module divides the single-ended data signal and a sampling clock signal at a preset phase based on first and second frequency division values respectively to generate first and second frequency division signals. A digital controller compares a first phase signal obtained based on the first frequency division signal and a second phase signal obtained based on the second frequency division signal to generate a phase error, and accordingly outputs a frequency control signal or a switching control signal. A current source circuit outputs a first current signal based on the frequency control signal. A clock signal generation module generates a plurality of sampling clock signals based on the first current signal, or generates a second current signal based on the switching control signal and then generates a target clock signal. By the above method, the control signal or the switching control signal is output based on the phase error rather than the frequency error. When the data signal transmission rate is high, a digital controller with high precision is not required, reducing the design difficulty.

[0202] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0203] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0204] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device realizes the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0205] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus, causing a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one process or a plurality of processes and / or boxes Figure 1 in one or more processes and / or boxes Figure 1 steps for implementing the functions specified in one box or a plurality of boxes.

[0206] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit and scope of the application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A clock data recovery circuit, characterized in that, Comprising: A differential-to-single-ended circuit, configured to convert an input differential data signal into a single-ended data signal; A frequency division module, configured to perform frequency division on the single-ended data signal based on a first frequency division value to generate a first frequency division signal, and perform frequency division on a sampling clock signal at a preset phase among a plurality of sampling clock signals based on a second frequency division value to generate a second frequency division signal, wherein the first frequency division value is greater than the second frequency division value; A digital controller, configured to compare a first phase signal and a second phase signal to generate a phase error, wherein the first phase signal is obtained based on the first frequency division signal, and the second phase signal is obtained based on the second frequency division signal; and output a frequency control signal or a switching control signal based on the phase error; A current source circuit, configured to generate a first current signal based on the frequency control signal; A clock signal generation module, configured to generate the plurality of sampling clock signals based on the first current signal, or generate a second current signal under the control of the switching control signal, and generate a target clock signal based on the second current signal; In each period of the first frequency division signal, the digital controller is specifically configured to: Output the switching control signal when determining that an absolute value of the phase error is less than a second preset value; Output the frequency control signal when determining that the absolute value of the phase error is greater than or equal to the second preset value.

2. The circuit according to claim 1, wherein The digital controller is further configured to: Perform phase conversion on the first frequency division signal based on the first frequency division value to obtain the first phase signal, and perform phase conversion on the second frequency division signal based on the second frequency division value to obtain the second phase signal, wherein the first phase signal includes a digital signal of a first bit, and the second phase signal includes a digital signal of a second bit; The digital controller is specifically configured to: Generate the phase error based on the first bit and the second bit.

3. The circuit according to claim 2, characterized in that, The current source circuit includes a first current source branch and a second current source branch, the frequency control signal includes a first frequency control signal and a second frequency control signal, and the digital controller is specifically configured to: Adjust a current first frequency control signal and output an adjusted first frequency control signal when determining that the absolute value of the phase error is greater than or equal to a first preset value; The current source circuit is specifically configured to: Adjust a number of first current sources operating in the first current source branch based on the adjusted first frequency control signal; Adjust a current second frequency control signal and output an adjusted second frequency control signal when determining that the absolute value of the phase error is greater than or equal to the second preset value and less than the first preset value; The current source circuit is specifically configured to: Adjust a number of second current sources operating in the second current source branch based on the adjusted second frequency control signal; Wherein a current value of a current output by a first current source in the first current source branch is greater than a current value of a current output by a second current source in the second current source branch.

4. The circuit according to claim 3, wherein After the digital controller outputs the adjusted first frequency control signal, the digital controller is further configured to: When it is determined that the next phase error is less than the first preset value, keep the first frequency control signal unchanged; Judge whether the absolute value of the next phase error is greater than or equal to the second preset value; When the absolute value of the next phase error is greater than or equal to the second preset value, adjust the current second frequency control signal and output the adjusted second frequency control signal; When the absolute value of the next phase error is less than the second preset value, output the switching control signal.

5. The circuit according to claim 4, wherein After keeping the first frequency control signal unchanged, before judging that the absolute value of the next phase error is greater than or equal to the second preset value in the next cycle of the first divided-frequency signal, the digital controller is further configured to: After determining the end of the current cycle of the first divided-frequency signal, in each of a preset number of consecutive cycles, when it is determined that the phase error is less than the first preset value, keep the first frequency control signal unchanged, where the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first divided-frequency signal.

6. The circuit according to claim 3, wherein The current source circuit is specifically configured to: If the absolute value of the phase error is greater than or equal to the first preset value and the phase error is positive, increase the number of first current sources operating in the first current source branch based on the first frequency control signal; If the absolute value of the phase error is greater than or equal to the first preset value and the phase error is negative, reduce the number of first current sources operating in the first current source branch according to the first frequency control signal.

7. The circuit according to claim 3, characterized in that After the digital controller outputs the second frequency control signal, it is further configured to: When it is determined that the absolute value of the next phase error is less than the second preset value, keep the second frequency control signal unchanged and output the switching control signal; When the absolute value of the next phase error is greater than or equal to the second preset value, adjust the current second frequency control signal and output the adjusted second frequency control signal.

8. The circuit according to claim 7, wherein After keeping the second frequency control signal unchanged, before judging that the absolute value of the next phase error is greater than or equal to the second preset value in the next cycle of the first divided-frequency signal, the digital controller is further configured to: After determining the end of the current cycle of the first divided-frequency signal, in each of a preset number of consecutive cycles, when it is determined that the absolute value of the phase error in each cycle is less than the second preset value, keep the second frequency control signal unchanged, where the first cycle of the preset number of consecutive cycles is adjacent to the current cycle of the first divided-frequency signal.

9. The circuit according to claim 1, wherein After generating the phase error, the digital controller is further configured to: Based on the error precision selection signal, calculate the phase error to obtain a phase selection error; The digital controller is specifically configured to: Based on the phase selection error, output the frequency control signal or the switching control signal.

10. A display chip, characterized in that, Comprising the clock data recovery circuit according to any one of claims 1 to 9.

11. A display device, characterized in that, Comprising the display chip according to claim 10.

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