Unit cell circuit and memory device including the same

Abstract

Disclosed is a unit cell circuit of a memory cell array, the unit cell circuit having a subcell array including a plurality of memory cells, each memory cell being connected to a power line, and an auxiliary circuit connected to the subcell array through the power line, the auxiliary circuit pre-charges the power supply line with the power supply voltage during the standby mode based on the control signal, and blocks the power supply line when the write operation is initiated.

Description

[0001] Cross-references

[0002] This application claims priority to Korean Patent Application No. 10-2023-0137128 filed on October 13, 2023 and Korean Patent Application No. 10-2024-0036077 filed on March 14, 2024, each filed in the Korean Intellectual Property Office (KIPO), the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to memory devices, and more particularly to unit cell circuits and memory devices including the same. Background Art

[0004] System on chip (SoC) can be used in various applications, such as mobile devices like mobile phones, tablets and smart watches, as well as automobiles, smart home systems and medical devices. As technology develops, SoC is expected to be high performance and efficient in terms of energy and area. Operating voltage scaling is a technique for reducing both active power and static power and achieving energy-saving SoC by reducing the operating voltage of SoC.

[0005] However, static random access memory (SRAM) used as cache memory of SoC may present a bottleneck in reducing the operating voltage of SoC due to its high minimum operating voltage. For example, SRAM may have a high minimum operating voltage due to contention within the memory cell during read / write operations. In addition, due to the increasing threshold voltage fluctuations in SRAM cells, the increase in expected yields, and the difficulty in improving the minimum operating voltage due to improvements in the design of the cell itself, the introduction of auxiliary circuits for improving the minimum operating voltage is provided. Summary of the invention

[0006] Embodiments of the present disclosure may address one or more of the above-mentioned fields and provide a unit cell circuit for assisting a write operation and a memory device including the unit cell circuit.

[0007] According to an embodiment of the present disclosure, a unit cell circuit of a memory cell array includes a sub-cell array and an auxiliary circuit, the sub-cell array includes a plurality of memory cells, each memory cell is connected to a power line, the auxiliary circuit is connected to the sub-cell array through the power line, and is configured to precharge the power line with a power voltage based on a control signal during a standby mode, and to block the power line when a write operation is initiated.

[0008] According to an embodiment of the present disclosure, a memory device includes a memory cell array and a row peripheral circuit, the memory cell array includes a plurality of unit cell circuits, the row peripheral circuit is configured to control the plurality of unit cell circuits, wherein each of the plurality of unit cell circuits includes a corresponding sub-cell array and a corresponding auxiliary circuit, the corresponding sub-cell array includes a corresponding plurality of memory cells, and the corresponding auxiliary circuit is connected to the corresponding sub-cell array through a corresponding power line, and is configured to precharge the corresponding power line with a power supply voltage during a standby mode based on the control of the row peripheral circuit, and to block the corresponding power line when a write operation is started.

[0009] According to an embodiment of the present disclosure, a memory row circuit includes: a control logic circuit configured to provide a control signal; and a unit cell circuit including an auxiliary circuit configured to receive the control signal, precharge a power line with a power supply voltage during a standby mode based on the control signal, and block the power line when a write operation is started; and a sub-cell array including a plurality of memory cells, each memory cell being connected to the power line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other embodiments of the present disclosure will become apparent by describing in detail the embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a schematic diagram illustrating a memory device according to an embodiment.

[0012] Figure 2 is a hybrid schematic / graphic diagram illustrating a unit cell circuit according to an embodiment.

[0013] Figure 3 is a circuit diagram showing a unit cell circuit according to an embodiment.

[0014] Figure 4 is a graphical diagram showing an operation waveform of a comparative example.

[0015] Figure 5 It is shown Figure 3 Graphical diagram of the operating waveform.

[0016] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of the row peripheral circuit.

[0017] Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of the row peripheral circuit.

[0018] Figure 8 is a diagram showing a method according to a corresponding embodiment Figure 6 or Figure 7 Circuit diagram of a row decoder.

[0019] Fig. 9 is a diagram showing a method according to an embodiment of the present invention. Figure 6 Circuit diagram of the control logic circuit.

[0020] Fig.10 is a hybrid block / circuit diagram illustrating unit cell circuits and control logic circuits for performing retention mode operations according to an embodiment.

[0021] Fig.11 It is shown Fig.10 Graphical diagram of the operating waveform.

[0022] Fig.12 is a circuit diagram showing an auxiliary circuit according to an embodiment.

[0023] Fig.13 is a circuit diagram showing an auxiliary circuit according to an embodiment.

[0024] Fig.14 is a circuit diagram showing an auxiliary circuit according to an embodiment.

[0025] Fig.15 is a circuit diagram showing an auxiliary circuit according to an embodiment.

[0026] Fig.16 is a circuit diagram showing an auxiliary circuit according to an embodiment.

[0027] Fig.17 is a circuit diagram showing an auxiliary circuit according to an embodiment.

[0028] Fig.18 is a diagram showing a structure of a memory device according to an embodiment.

[0029] Fig.19 is a diagram showing a structure of a memory device according to an embodiment.

[0030] Fig. 20 is a diagram showing a structure of a memory device according to an embodiment.

[0031] Fig.21 is a diagram showing a layout of a memory device according to an embodiment. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure may be described by way of example with sufficient detail and clarity to enable a person skilled in the relevant art to easily implement the described embodiments and other embodiments of the present disclosure.

[0033] Figure 1 A memory device according to an embodiment is shown.

[0034] Reference Figure 1 , the memory device 100 according to the embodiment may include a memory cell array 110 , a row peripheral circuit 120 , a column peripheral circuit 130 , and a control circuit 140 .

[0035] The memory cell array 110 may be connected to the row peripheral circuit 120 through a plurality of word lines WLS1 to WLSn, and may be connected to the column peripheral circuit 130 through a plurality of bit lines BL1 to BLm and a plurality of inversion bit lines BLb1 to BLbm. The memory cell array 110 may include a plurality of memory cells, each of which is accessed through a plurality of word lines WLS1 to WLSn, and a plurality of bit lines BL1 to BLm and a plurality of inversion bit lines BLb1 to BLbm. According to an embodiment, the plurality of memory cells included in the memory cell array 110 may be volatile memory cells, such as static random access memory (SRAM), dynamic random access memory (DRAM), etc. In addition, in an embodiment, the plurality of memory cells included in the memory cell array 110 may include non-volatile memory cells, such as flash memory, resistance random access memory (RRAM), etc. For the purpose of description, the embodiments of the present disclosure will be described mainly with reference to the SRAM cell, without limitation thereto.

[0036] The plurality of memory cells included in the memory cell array 110 may be grouped in units of "k" (where "k" is a natural number), and the grouped memory cells may be defined as sub-cell arrays SCA1 to SCAn. In more detail, each of the sub-cell arrays SCA1 to SCAn may include a plurality of "k" memory cells. For example, if each memory cell has a storage capacity of "1" bit, then each of the sub-cell arrays SCA1 to SCAn may have a storage capacity of "k" bits; and if each memory cell has a storage capacity of "x" bits, then each of the sub-cell arrays SCA1 to SCAn may have a storage capacity of "k" times "x" bits.

[0037] As shown, the memory cell array 110 may be defined as including "m" columns arranged as Col1 to Colm, where "m" is a natural number, and each of the "m" columns Col1 to Colm may be defined as including "n" sub-cell arrays SCA1 to SCAn, where "n" is a natural number. Each of the columns Col1 to Colm is connected by a pair including one of the bit lines BL1 to BLm paired with one of the inversion bit lines BLb1 to BLbm and one of the inversion bit lines BLb1 to BLbm. For example, the first column Col1 may be operated by being connected to the column peripheral circuit 130 via the first bit line BL1 and the first inversion bit line (or bit line bar) BLb1 substantially complementary to the first bit line BL1. In addition, each of the sub-cell arrays SCA1 to SCAn corresponding to a row may be connected to each word line in common.

[0038] According to an embodiment, a plurality of memory cells included in each of the sub-cell arrays SCA1 to SCAn may be connected to power lines SL1 to SLn, respectively. The power lines SL1 to SLn are lines to which a power supply voltage VDD for the operation of each memory cell is applied, and may be configured for each of the sub-cell arrays SCA1 to SCAn, and, for example, "n" power lines SL1 to SLn may be configured. In more detail, a power line may be configured for each sub-cell array through an auxiliary circuit. When the power line is divided for each sub-cell array, the capacitance of the power line may be reduced.

[0039] According to an embodiment, the auxiliary circuits AC1 to ACn may be connected to the subcell arrays SCA1 to SCAn, respectively. In more detail, when "n" subcell arrays SCA1 to SCAn are configured, "n" auxiliary circuits AC1 to ACn may be configured. For convenience, one subcell array among the subcell arrays SCA1 to SCAn and one auxiliary circuit among the auxiliary circuits AC1 to ACn connected to the one subcell array may be referred to as a unit cell circuit. The memory cell array 110 includes a plurality of unit cell circuits. For example, a column Col1 of the memory cell array 110 may include "n" unit cell circuits.

[0040] The auxiliary circuits AC1 to ACn may be connected to the subcell arrays SCA1 to SCAn, respectively, through power lines SL1 to SLn, and may be configured to assist the write operation of each subcell array SCA1 to SCAn. The auxiliary circuits AC1 to ACn may perform various operations depending on the operation of the memory device 100. First, during the standby mode, the auxiliary circuits AC1 to ACn may precharge the power lines SL1 to SLn to the power supply voltage VDD based on the control signal from the row peripheral circuit 120. In this case, the standby mode may be distinguished from the retention mode, which reduces the power of the peripheral circuit and reduces the leakage current of the memory cell by reducing the power supply voltage of the memory cell, and the standby mode may be defined as a mode in which the memory device 100 is ready to perform a read operation or a write operation. In addition, even during a read operation, the auxiliary circuits AC1 to ACn may precharge the power lines SL1 to SLn to the power supply voltage VDD.

[0041] When a write operation is started, the auxiliary circuits AC1 to ACn may block the power lines SL1 to SLn. Based on the auxiliary circuits AC1 to ACn blocking the power lines SL1 to SLn, the voltage of the power lines SL1 to SLn collapses from the power supply voltage VDD precharged during the write operation. As the power supply voltage VDD collapses, the ability to maintain the data previously stored in each memory cell decreases. For example, when the memory cell is an SRAM cell according to the above-described embodiment, the level of the power supply voltage VDD directly provided to the pull-up transistor may decrease, thereby reducing the pull-up performance. As the pull-up performance decreases, the write current path relative to the bit lines BL1 to BLm and the inverted bit lines BLb1 to BLbm can be formed stronger, and thus can help write the final written data into the memory cell.

[0042] According to an embodiment, the auxiliary circuits AC1 to ACn may be configured to form a pull-up current to the power lines SL1 to SLn as the voltage of the power lines SL1 to SLn collapses after the write operation is started. When the pull-up current is formed, the operating voltage of the subcell arrays SCA1 to SCAn may be prevented from excessively collapsing.

[0043] Based on a successful write operation to one of the plurality of memory cells, the voltage of the power supply lines SL1 to SLn will stop collapsing. In more detail, when the write operation is successful, the write current path relative to the bit lines BL1 to BLm and the inverted bit lines BLb1 to BLbm is blocked, so the voltage of the power supply lines SL1 to SLn no longer drops.

[0044] The row peripheral circuit 120 is connected to the memory cell array 110 through a plurality of word lines WLS1 to WLSn and can activate one of the plurality of word lines WLS1 to WLSn based on the row address R_ADDR. Thus, memory cells connected to the activated word line can be selected in the subcell arrays SCA1 to SCAn corresponding to one row.

[0045] According to an embodiment, the row peripheral circuit 120 may be configured to control a unit cell circuit including the above-mentioned auxiliary circuits AC1 to ACn. The row peripheral circuit 120 may control a plurality of auxiliary circuits AC1 to ACn individually, or may control one or more auxiliary circuits AC1 to ACn simultaneously or collectively. The row peripheral circuit 120 may select a word line among a plurality of word lines WLS1 to WLSn, and may activate one of the auxiliary circuits AC1 to ACn corresponding to one of the subcell arrays SCA1 to SCAn connected to the selected word line. Activating the auxiliary circuits AC1 to ACn may mean blocking the power lines SL1 to SLn by the auxiliary circuits AC1 to ACn when a write operation is initiated.

[0046] In addition, the row peripheral circuit 120 may precharge the power lines SL1 to SLn to the power supply voltage VDD through the auxiliary circuits AC1 to ACn during the standby mode. For example, the auxiliary circuits AC1 to ACn may precharge the power lines SL1 to SLn to the power supply voltage VDD based on at least one control signal from the row peripheral circuit 120 during the standby mode.

[0047] The column peripheral circuit 130 may be connected to the memory cell array 110 through a plurality of bit lines, and may activate a pair of bit lines among a plurality of bit lines BL1 to BLm and a plurality of inversion bit lines BLb1 to BLbm based on a column address C_ADDR. The column peripheral circuit 130 may activate a pair of bit lines during a read operation, and may detect a current and / or voltage received through the pair of bit lines, thereby reading a value stored in a memory cell corresponding to the activated word line. In addition, the column peripheral circuit 130 may apply a current and / or voltage to a pair of bit lines based on data to be written during a write operation.

[0048] The control circuit 140 may receive the command CMD and may control the row peripheral circuit 120 and the column peripheral circuit 130 based on the received command CMD. For example, the control circuit 140 may identify a read command or a write command by decoding the command CMD, and may generate a control signal to perform the identified operation. The control circuit 140 may activate or deactivate a plurality of word lines WLS1 to WLSn and / or a plurality of bit lines BL1 to BLm and a plurality of inversion bit lines BLb1 to BLbm at a timing determined based on the control signal.

[0049] According to an embodiment, the memory device 100 may further include a plurality of isolation circuits, such as ISOLC1 and ISOLC2. A plurality of isolation circuits ISOLC1 and ISOLC2 may be configured between some of the subcell arrays SCA1 to SCAn. Like the auxiliary circuits AC1 to ACn, one isolation circuit may be connected to one of the subcell arrays SCA1 to SCAn. Each of the isolation circuits ISOLC1 and ISOLC2 may be configured to isolate the subcell arrays SCA1 to SCAn to prevent data interference or leakage between the subcell arrays. In addition, each of the isolation circuits ISOLC1 and ISOLC2 may be configured so that the connected subcell arrays SCA1 to SCAn share one of the power lines SL1 to SLn.

[0050] According to the above-described embodiment, the memory device 100 of the present disclosure may include a plurality of unit cell circuits, the plurality of unit cell circuits including auxiliary circuits AC1 to ACn and sub-cell arrays SCA1 to SCAn, and the write operation of each of the sub-cell arrays SCA1 to SCAn may be assisted by the auxiliary circuits AC1 to ACn. Specifically, the memory device 100 of the present disclosure blocks the power lines SL1 to SLn by the auxiliary circuits AC1 to ACn when starting the write operation to collapse the power supply voltage VDD and reduce the minimum operating voltage, and thus the write assist performance may be improved compared to always activating the power lines SL1 to SLn. In addition, since the auxiliary circuits AC1 to ACn are not provided in the peripheral circuit, the area overhead caused by the auxiliary circuits AC1 to ACn may also be reduced.

[0051] Figure 2 A unit cell circuit according to an embodiment is shown.

[0052] refer to Figure 2 The unit cell circuit 200 according to the embodiment may be defined as including Figure 1 A subunit array of SCA1-SCAn is selected and from Figure 1 Select one of AC1-ACn corresponding to the auxiliary circuit.

[0053] Figure 2 The unit cell circuit 200 includes a sub-cell array SCA, which in turn includes a plurality of memory cells MC1 to MCk (e.g., "k" memory cells MC1 to MCk), each of which is connected to a power line SL. The sub-cell array SCA is connected to the auxiliary circuit 210 through the power line SL. According to an embodiment, at least the plurality of memory cells MC1 to MCk included in the sub-cell array SCA may be commonly connected to the auxiliary circuit 210 through one power line SL.

[0054] The auxiliary circuit 210 can assist the write operation of the subcell array SCA based on the control signal CON. Figure 1 The row peripheral circuit receives the control signal CON.

[0055] The auxiliary circuit 210 may precharge the power line SL to the power voltage VDD during the standby mode based on the control signal CON.

[0056] When the write operation is started, the auxiliary circuit 210 blocks the power line SL. The voltage of the power line SL (V of SL) collapses from the precharged power voltage VDD to the level of the saturation voltage Vsat. In more detail, the write current paths WCP1 and WCP2 relative to the bit line BL or the bit line inverse logic BLb can be formed from the activated memory cells MC1 to MCk according to the start of the write operation. The write current paths WCP1 and WCP2 may vary depending on the selected memory cell among the plurality of memory cells MC1 to MCk, but may generally be defined as a current path flowing from the power line SL to one of the bit lines via one of the memory cells MC1 to MCk selected.

[0057] The write current paths WCP1 and WCP2 may be formed based on which bit line the data to be written into the activated memory cells MC1 to MCk is to be applied to. For example, when the data to be written is applied to the bit line BL, a first write current path WCP1 may be formed, and when the data to be written is applied to the bit line inverse logic BLb, a second write current path WCP2 may be formed, but is not limited thereto.

[0058] Through the write current paths WCP1 and WCP2, the initial voltage of the power line SL gradually collapses from the power supply voltage VDD toward the saturation voltage Vsat. As the voltage of the power line SL gradually collapses, the pull-up performance of the write current paths WCP1 and WCP2 with respect to the activated memory cells MC1 to MCk decreases, thereby improving the write performance.

[0059] Afterwards, when the write operation for the activated memory cells MC1 to MCk is completed, the formed write current paths WCP1 and WCP2 are blocked again, and the auxiliary circuit 210 can end the blocking of the power line SL based on the control signal CON. Therefore, the voltage of the power line SL rises from the voltage at the end of the collapse (e.g., not less than Vsat) to the power supply voltage VDD.

[0060] According to the above-described embodiment, the unit cell circuit 200 of the present disclosure can have improved write performance using the auxiliary circuit 210, and the auxiliary circuit 210 can reduce the pull-up performance of the memory cells MC1 to MCk by blocking the power line SL. In addition, since the auxiliary circuit 210 is configured inside the unit cell circuit 200, the area overhead can be reduced compared to when the auxiliary circuit 210 is configured in one or more peripheral circuits.

[0061] In addition, when there is an internal resistance including a bit line resistance according to the connection of the bit line and a resistance of the power supply voltage VDD seen from the auxiliary circuit 210, the amount of write current flowing through the write current paths WCP1 and WCP2 is reduced. However, the unit cell circuit 200 of the present disclosure can still have improved write performance because the pull-up performance is reduced by blocking the power supply line SL.

[0062] Figure 3 A unit cell circuit according to an embodiment is shown.

[0063] For the convenience of Figure 3 The unit cell circuit 300 of the present invention is described, and only one memory cell 320 selected from the sub-cell array is shown, but it is not limited to this. In addition, the memory cell 320 shown has a 6T structure composed of six transistors, but the embodiments of the present invention are not limited to this, and the memory cell 320 may have an 8T structure or another structure. The memory cell 320 may include a first pass gate transistor PG1 and a second pass gate transistor PG2 connected to the word line WL, a first pull-up transistor PU1 and a first pull-down transistor PD1 forming an inverter, and a second pull-up transistor PU2 and a second pull-down transistor PD2 forming another inverter.

[0064] The first pass-gate transistor PG1 has a drain connected to the first node N1, a gate connected to the word line WL, and a source connected to the bit line BL. The second pass-gate transistor PG2 has a drain connected to the second node N2, a gate connected to the word line WL, and a source connected to the bit line inverse logic BLb. When the word line WL is activated to select the memory cell 320, the first pass-gate transistor PG1 and the second pass-gate transistor PG2 are turned on. When the word line WL is deactivated, the first pass-gate transistor PG1 and the second pass-gate transistor PG2 are turned off, so that the memory cell 320 maintains the stored data.

[0065] The first pull-up transistor PU1 and the first pull-down transistor PD1 have a drain commonly connected to the first node N1 and a gate commonly connected to the second node N2. The second pull-up transistor PU2 and the second pull-down transistor PD2 have a drain commonly connected to the second node N2 and a gate commonly connected to the first node N1. Therefore, each inverter stores data opposite to each other. For ease of description, it is assumed that data corresponding to a logic high value is stored in the first node N1, but it is not limited thereto. It is further assumed that the write operation is to write data corresponding to a logic low value to the first node N1, but it is not limited thereto.

[0066] The auxiliary circuit 310 is connected to the source of the first pull-up transistor PU1 and the second pull-up transistor PU2 through the power line SL. The auxiliary circuit 310 according to the embodiment may include a pull-up header transistor PUH, a pull-down header transistor PDH, and a stacked transistor STA. However, this is only an embodiment of the present disclosure, and various embodiments associated with the configuration of the auxiliary circuit 310 may be implemented, including but not limited to those described below.

[0067] In an embodiment, the pull-up header transistor PUH has a gate to which a control signal CON is applied, a source to which a power supply voltage VDD is applied, and a drain connected to the source of the stacked transistor STA. The pull-down header transistor PDH can be configured in various ways so that a logic high value voltage is applied to its gate during a write operation. Figure 3 The pull-down header transistor PDH has a gate to which the control signal CON is applied and can be operated by the control signal CON. Since the control signal CON is commonly applied to each gate of the pull-up header transistor PUH and the pull-down header transistor PDH and these transistors have opposite polarity types, one of the pull-up header transistor PUH and the pull-down header transistor PDH can be turned on and the other of the pull-up header transistor PUH and the pull-down header transistor PDH can be turned off.

[0068] The stacked transistor STA may be a PMOS transistor and has a gate to which a ground voltage is applied and a drain connected to the power line SL. In addition, the source of the stacked transistor STA is connected to the drain of the pull-up header transistor PUH and the source of the pull-down header transistor PDH. The stacked transistor STA is always turned on by receiving a ground voltage at its gate and can be operated to enhance the signal characteristics on the power line SL. Therefore, it is determined whether the power supply voltage VDD is applied to the power line SL depending on the header transistor. In an embodiment, the stacked transistor is optional.

[0069] To describe the write operation in detail, first, during the standby mode before the write operation, the logic level of the control signal CON may correspond to a logic low value. In more detail, the pull-up header transistor PUH is turned on, the pull-down header transistor PDH is turned off, and the power supply voltage VDD is precharged on the power supply line SL. In addition, even in the case of a read operation, the logic level of the control signal CON corresponds to a logic low value.

[0070] When the write operation is started, the word line WL is activated, and the logic level of the control signal CON corresponds to a logic high value. According to an embodiment, each of the plurality of memory cells 320 is selected by the word line during the write operation, and the control signal CON may be turned into a logic high value at a second timing that is a certain period of time later than the first timing at which the word line is activated. In this case, in the case where the word line WL is selected but the bit line BL is not selected, since the auxiliary circuit 310 operates later than immediately after the word line WL is activated (which is the most vulnerable time to maintain the stability of the data stored in the memory cell 320), the stability does not have to be degraded.

[0071] Alternatively, according to an embodiment, the second timing at which the control signal CON transitions may be simultaneous with the first timing. Even if the second timing and the first timing are substantially the same, the above stability feature is optional, and thus the control signal CON may transition at the first timing.

[0072] Therefore, the pull-up header transistor PUH is turned off. In addition, since the gate voltage of the pull-down header transistor PDH corresponds to a logic high value and its source voltage is also the precharge supply voltage VDD, the pull-down header transistor PDH is turned off when the write operation is started. The pull-down header transistor PDH operates as a diode after the write operation is started. Therefore, the current Ivdd flowing out from the power supply voltage VDD has a value of substantially "0".

[0073] In the memory cell 320, when the first pull-up transistor PU1 is turned on and each transfer gate transistor is turned on, a write current path WCP is formed through the bit line BL. Therefore, the voltage of the power line SL decreases. As the voltage of the power line SL decreases, the pull-up performance of the first pull-up transistor PU1 for maintaining a logic high value decreases, and thus assists the operation of writing logic low value data into the memory cell 320. Therefore, the write performance with respect to the memory cell 320 can be improved. In addition, since the source voltage of the pull-down header transistor PDH decreases as the voltage of the power line SL collapses, the pull-down header transistor PDH can be gradually turned on.

[0074] When the write operation is successful, the first node N1 changes to a logic low value, and the second node N2 changes to a logic high value. Therefore, the first pull-up transistor PU1 is turned off, and the write current path WCP is blocked. When the write current path WCP is blocked, the voltage on the power line SL stops collapsing. In addition, when the control signal CON changes to a logic low value and the pull-up head transistor PUH is turned on, the voltage of the power line SL is precharged again on the power line SL. During the precharge period, the current Ivdd flows out from the power supply voltage VDD.

[0075] Figure 4 The operation waveform of the comparative example is shown, and Figure 5 Shows Figure 3 In the present disclosure, the comparative examples are some examples in which the auxiliary circuit is configured to always provide the power supply voltage VDD. In addition, Figure 4 and Figure 5 The operating waveform of a cell with low write performance when high sigma "σ" is desired is shown.

[0076] refer to Figure 4 and Figure 5 , before time t1 when the write operation is started, the voltage of the power line SL is precharged to the power supply voltage VDD, and the voltage of the bit line BL is also precharged to the high bit line voltage. At time t1, the bit line BL transitions to a voltage corresponding to the data to be written, and the word line WL is activated. As the bit line BL and the word line WL transition from time t1, the voltage of the first node N1 gradually transitions from a logic low value to a logic high value, and the voltage of the second node N2 gradually transitions from a logic high value to a logic low value.

[0077] Time t2 may be defined as the time at which the logic state of the control signal CON changes. The control signal CON changes from a logic low value to a logic high value at time t2, and time t2 may be a specific period of time after time t1. According to an embodiment, the control signal CON may change to a logic high value at time t1.

[0078] However, Figure 4 The case of is a comparative example assuming that the voltage of the power line SL is always maintained regardless of the transition of the control signal CON, so the voltage drop rate of the power line SL is relatively slow. In more detail, the pull-up performance of the pull-up transistor of the memory cell is slowly reduced, and the voltage of the power line SL does not need to drop to the minimum operating voltage. Finally, in Figure 4 In the comparative example of FIG. 1 , the voltages of the first node N1 and the second node N2 may not transition, so that the write operation may fail.

[0079] On the contrary, in the embodiment according to Figure 5In the case of , the pull-up header transistor PUH and the pull-down header transistor PDH of the auxiliary circuit are initially turned off at time t2, so the power line SL is blocked and a write current path is formed in the memory cell. Therefore, the voltage of the power line SL collapses relatively quickly. Therefore, the minimum operating voltage can be met, and the voltages of the first node N1 and the second node N2 are successfully transformed after time t3, so that the write operation is successful. In addition, since the write current path is blocked depending on the success of the write operation, the voltage of the power line SL is maintained at a specific level.

[0080] After time t4, the bit line BL is precharged again and the word line WL is deactivated. In addition, the control signal CON also changes from a logic high value to a logic low value. Therefore, the power supply voltage VDD is provided to the memory cell from the auxiliary circuit, the voltage of the power supply line SL is precharged to the power supply voltage VDD again, and a current Ivdd is formed.

[0081] According to the above-described embodiments, when high sigma is required, the unit cell circuit of the present disclosure can improve the performance of a write operation by improving the voltage collapse speed of the power line SL and improving the minimum operating voltage.

[0082] Figure 6 and Figure 7 The corresponding embodiment is shown Figure 1 The row peripheral circuit.

[0083] First, refer to Figure 6 , the row peripheral circuit 400 may include a plurality of row decoders RDEC1 to RDECn and a plurality of control logic circuits CLC1 to CLCx. For example, "n" row decoders RDEC1 to RDECn may be configured, and "x" control logic circuits CLC1 to CLCx may be configured (where 'x' is a natural number). For example, "x" may be a natural number less than or equal to "n".

[0084] A plurality of row decoders RDEC1 to RDECn are connected to a plurality of sub-cell arrays SCA1 to SCAn through a plurality of word lines WLS1 to WLSn. One row decoder is connected to one of the sub-cell arrays SCA1 to SCAn and may receive first address information ADDR1. The plurality of row decoders RDEC1 to RDECn may decode the first address information ADDR1 and may select and activate a plurality of word lines WLS1 to WLSn connected to the sub-cell arrays SCA1 to SCAn included in the memory cell array based on the decoded first address information ADDR1.

[0085] A plurality of control logic circuits CLC1 to CLCx control auxiliary circuits AC1 to ACn based on control signals CON1 to CONx. According to an embodiment, one control logic circuit may be connected to two auxiliary circuits to control the two auxiliary circuits based on one control signal, such as, where "x" is substantially equal to "n" / 2. For example, a first control logic circuit CLC1 may be connected to a first auxiliary circuit AC1 and a second auxiliary circuit AC2, and a first control signal CON1 may be applied. Therefore, a plurality of control logic circuits CLC1 to CLCx may simultaneously control two auxiliary circuits corresponding to a plurality of unit cell circuits among a plurality of auxiliary circuits AC1 to ACn. In addition, even if substantially the same control signal CON1 to CONx is applied to two auxiliary circuits AC1 to ACn, a subcell array SCA1 to SCAn corresponding to one word line activated by row decoders RDEC1 to RDECn will operate according to the above-described embodiment.

[0086] The plurality of control logic circuits CLC1 to CLCx may generate control signals CON1 to CONx based on the second address information ADDR2. In this case, the second address information ADDR2 may be defined to select auxiliary circuits AC1 to ACn connected to the subcell arrays SCA1 to SCAn corresponding to the word lines WLS1 to WLSn to be selected.

[0087] Alternatively, one can Figure 7 The configuration shown includes an "n" number of control logic circuits CLC1 to CLCn. In more detail, the number of control logic circuits CLC1 to CLCn may be substantially the same as the number of auxiliary circuits AC1 to ACn. In this case, one control logic circuit is connected to one auxiliary circuit, and one auxiliary circuit may be controlled based on the control signal CON. For example, the first control logic circuit CLC1 may control the first auxiliary circuit AC1 based on the first control signal CON1. ​​In addition, the number and configuration of the control logic circuits are not limited to the above-described embodiments, and the control logic circuits may be implemented in various ways so that one or more control signals are applied to the auxiliary circuits AC1 to ACn connected to the sub-cell array selected by the word lines WLS1 to WLSn.

[0088] According to the above-described embodiments, the row peripheral circuit of the present disclosure can allow an auxiliary circuit configured in a memory cell array to assist a write operation through a control logic circuit.

[0089] Figure 8 It shows the applicable Figure 6 and Figure 7 A row decoder of an embodiment.

[0090] Reference Figure 8, the row decoder 600 according to the embodiment may include a first NOR gate 610, a first NAND gate 620, and a NOT gate 630. The first NOR gate 610 may receive address bit information corresponding to the first address information, and may perform a NOR operation. In this case, the bit information is shown as A_H corresponding to the most significant bit (MSB), A_M corresponding to the middle bit, and A_L corresponding to the least significant bit (LSB), but alternatively or additionally, the first address information may be configured in various ways to select a word line, without limitation thereto.

[0091] The first NAND gate 620 performs a NAND operation on the result of the NOR operation and the clock signal CLK. Therefore, the address bit information can be sampled according to the clock signal CLK. The NOT gate 630 is connected to the output of the first NAND gate 620 and can output a word line signal WL_S for selecting a word line.

[0092] According to an embodiment, the row decoder 600 may further include an auxiliary transistor ATR. The auxiliary transistor ATR may have a drain connected to the output terminal of the NOT gate 630, a source connected to the ground, and a gate to which an inverse logic signal WLUDb of the word line is applied under a driving signal. The auxiliary transistor ATR may be turned on or off depending on the inverse logic signal WLUDb to assist in the execution of a read operation.

[0093] Fig. 9 The invention is shown in accordance with the embodiment Figure 6 A control logic circuit of an embodiment.

[0094] Reference Fig. 9 , the control logic circuit 700 according to the embodiment may include a second NOR gate 710 , a second NAND gate 720 , and a third NAND gate 730 .

[0095] The second NOR gate 710 can receive address bit information corresponding to the second address information and can perform a NOR operation. As an example, the address bit information can include the above-mentioned A_H and A_M. In this case, the control logic circuit 700 is capable of controlling one or more auxiliary circuits. Alternatively, the address bit information can be configured in various ways to select an auxiliary circuit without limitation.

[0096] The second NAND gate 720 can sample the address bit information by performing a NAND operation on the result of the NOR operation and the write clock signal WCLK. The third NAND gate 730 can perform a NAND operation on the NAND operation result of the second NAND gate 720 and the hold signal RETENb to output the control signal CON. Outside the hold mode, the hold signal RETENb has a value of a logic high value. In the hold mode, the hold signal RETENb has a logic value corresponding to a logic low value, and thus the control signal CON always has a logic high value during the hold mode. As described above, the hold mode is achieved by reducing the peripheral circuit (e.g., Figure 1 A mode in which power is removed from the column peripheral circuit (as shown) and power is supplied to the memory cell array while maintaining data stored in the memory cells and reducing leakage power.

[0097] In an alternative embodiment, similar control logic circuits can be applied with minor modifications to Figure 7 embodiments, potentially by omitting the second NOR gate 710 and from Figure 8 The first NOR gate 610 obtains a first input to the second NAND gate 720. A substantially repeated description may be omitted.

[0098] Described above Figure 8 and Fig. 9 The row decoder and control logic circuit are only example circuits. Alternatively, the row decoder and control logic circuit can be configured to respectively perform Figures 1 to 7 The operation and functionality of the embodiments.

[0099] Fig.10 A control logic circuit and a unit cell circuit for performing a hold mode operation according to an embodiment are shown, and Fig.11 Shows Fig.10 The operating waveform.

[0100] Reference Fig.10 and Fig.11, the control logic circuit CLC according to the embodiment may generate a control signal CON based on the second address information ADDR2, the write clock signal WCLK and the hold signal RETENb. The control signal CON may be generated so that when the hold mode starts, the auxiliary circuit 800 blocks the power line SL to the subcell array SCA. In more detail, as described above, the hold signal RETENb may be defined so that the logic level of the control signal CON corresponds to a logic high value during the hold mode. For example, the hold signal RETENb may have a logic low value. Therefore, the control signal CON output from the control logic circuit CLC has a logic high value in the hold mode. According to the embodiment, in the hold mode, all control logic circuits included in the memory device may output control signals having logic high values.

[0101] Additionally, in the retention mode, the corresponding word line is deactivated so that the voltage of the word line corresponds to a logic low value, and the data stored in the memory cell (eg, Figure 3 The voltages of the first and second nodes in will also maintain the stored logic state.

[0102] When a control signal CON corresponding to a logic high value is applied to the gates of the pull-up header transistor PUH and the pull-down header transistor PDH included in the auxiliary circuit 800, the pull-up header transistor PUH is turned off and the pull-down header transistor PDH can operate like a diode, similar to the case of starting a write operation. The stacked transistor STA is always turned on. The pull-down header transistor PDH can be gradually turned on to allow the pull-up current to flow to the power line SL.

[0103] The pull-up current generated by the pull-down header transistor PDH can prevent a voltage drop on the power line SL due to a leakage current relative to the memory cell array including the sub-cell array. For example, the voltage of the power line SL can converge to a level Vsat at which the pull-up current generated by the pull-down header transistor PDH and the leakage current have substantially the same level.

[0104] By preventing the voltage of the power supply line SL from collapsing to the ground level due to the pull-up current, the data retention performance in the retention mode can be improved. Specifically, according to the present disclosure, the leakage current through the auxiliary circuit 800 included in the memory cell array rather than the peripheral circuit can be reduced. In more detail, the auxiliary circuit 800 of the present disclosure can not only assist the writing performance, but also improve the retention performance in the retention mode by reducing the leakage current.

[0105] Next, various embodiments of the auxiliary circuit according to the above-described embodiment are described.

[0106] Figures 12 to 17 An auxiliary circuit according to a respective embodiment is shown.

[0107] refer to Fig.12 According to the embodiment, the auxiliary circuit 900a may include a pull-up header transistor PUH and a pull-down header transistor PDH, but does not need to include any stacked transistors. The pull-up header transistor PUH may have a gate to which a control signal CON is applied, a source to which a power supply voltage VDD is applied, and a drain directly connected to a power supply line SL. The pull-down header transistor PDH may have a gate to which a control signal CON is applied, a drain to which a power supply voltage VDD is applied, and a source directly connected to a power supply line SL. In more detail, by Figure 3 The auxiliary circuit 310 is implemented by omitting the stacked transistor STA. Fig.12 Depending on the common control signal CON, one of the pull-up header transistor PUH and the pull-down header transistor PDH may be turned on, and the other may be turned off.

[0108] According to an embodiment, when a write operation is initiated, the pull-up header transistor PUH is turned off and the pull-down header transistor PDH is turned on, thereby blocking the power line SL and assisting write performance.

[0109] refer to Fig.13 , the auxiliary circuit 900b according to the embodiment may include a first pull-up header transistor PUH1 and a second pull-up header transistor PUH2. The control signal CON is applied to the gate of the first pull-up header transistor PUH1, but the gate of the second pull-up header transistor PUH2 may be connected to the power line SL. In more detail, the power supply voltage VDD is applied to the source of the second pull-up header transistor PUH2, and both its gate and its drain are connected to the power line SL. Therefore, when the control signal CON is a logic low value, the second pull-up header transistor PUH2 is turned off, and when the control signal CON becomes a logic high value when starting a write operation, the second pull-up header transistor PUH2 may block the power line SL, and may then be turned on more gradually.

[0110] refer to Fig.14 According to the embodiment, the auxiliary circuit 900c may include a pull-up header transistor PUH, a pull-down header transistor PDH, and a stacked transistor STA. Except for the pull-down header transistor PDH, the connection relationship of the remaining transistors is the same as Figure 3 The pull-down header transistor PDH may have a structure in which the gate and the drain are connected to each other or both the gate and the drain are connected to the power supply voltage line. In more detail, an operating voltage corresponding to a logic high value (such as VDD) is always applied to the gate of the pull-down header transistor PDH. Finally, during a write operation, such as in Figure 3 In the above description, the pull-down header transistor PDH blocks the power supply line SL and then gradually turns on.

[0111] Reference Fig.15 According to the embodiment, the auxiliary circuit 900d may have Fig.14 Even if the stacked transistor STA is omitted or removed, the operation of the auxiliary circuit 900d that assists the write performance by blocking the power line SL during the write operation or the operation of the pull-down header transistor PDH that prevents the power line SL from extreme collapse in the hold mode is the same as that of the auxiliary circuit 900c. Fig.14 Basically the same.

[0112] refer to Fig.16 and Fig.17 , each of the auxiliary circuits 900e and 900f according to the corresponding embodiments may include a pull-up header transistor PUH, a pull-down header transistor PDH, and a transmission gate header transistor PGH. Like the pull-down header transistor PDH, the transmission gate header transistor PGH may have a gate to which a control signal CON is applied and a drain to which a power supply voltage VDD is applied. The source of the transmission gate header transistor PGH may be connected to the source of the stacked transistor STA, such as Fig.16 As shown in the embodiment 900e; or Fig.17 In more detail, during a write operation, the pull-down header transistor PDH and the pass-gate header transistor PGH together block the power line SL and can be gradually turned on.

[0113] In the above Figures 12 to 15 In the auxiliary circuit of the present invention, the pull-down header transistor PDH can be replaced by a transmission gate header transistor PGH. In addition, the pull-up header transistor PUH, the pull-down header transistor PDH and the transmission gate header transistor PGH can be respectively composed of transistors substantially the same as the pull-up transistor, the pull-down transistor and the transmission gate header transistor PGH included in the memory cell.

[0114] Figures 18 to 20 A memory device according to respective embodiments is described.

[0115] refer to Figures 18 to 20 , the memory devices 1000a to 1000c may be implemented in various ways depending on the configuration of each sub-cell array. For example, the number and arrangement of auxiliary circuits and the number and arrangement of isolation circuits may be configured depending on the number of memory cells included in each sub-cell array.

[0116] Assuming that the memory device has a capacity of 256 bits, for example, when each sub-unit array consists of 64 bits and Fig.18When organized as shown, the memory device 1000a may include four subcell arrays. Auxiliary circuits AC are provided between the first subcell array SCA1 and the second subcell array SCA2, and between the third subcell array SCA3 and the fourth subcell array SCA4, and each auxiliary circuit is connected to each adjacent subcell array. In addition, an isolation circuit ISOLC is connected between the second subcell array SCA2 and the third subcell array SCA3 to support the isolation of the subcell arrays and the split connection of the power supply line SL.

[0117] Alternatively, in a memory device having a capacity of 256 bits, for example, when each sub-unit array consists of 32 bits and Fig.19 When organized as shown, the memory device 1000b may include 8 sub-cell arrays. The auxiliary circuit AC is connected between the first sub-cell array SCA1 and the second sub-cell array SCA2 among the sub-cell arrays defined along the column direction CD, and further the auxiliary circuit AC is connected between the last sub-cell array SCA8 and the second-to-last sub-cell array SCA7. One auxiliary circuit is connected to each sub-cell array. For the remaining sub-cell arrays, the sub-cell arrays with the auxiliary circuit AC connected therebetween in the column direction and the sub-cell arrays with the isolation circuit ISOLC connected therebetween in the column direction can be configured by sequential repetition.

[0118] Alternatively, in a memory device having a 256-bit capacity, for example, when each sub-unit array consists of 16 bits and Fig. 20 When organized as shown, the memory device 1000c may include 16 sub-cell arrays. The auxiliary circuit AC is connected between the first sub-cell array SCA1 and the second sub-cell array SCA2 among the sub-cell arrays defined along the column direction CD, and further, the auxiliary circuit AC is connected between the last sub-cell array SCA16 and the second-to-last sub-cell array SCA15. Other sub-cell arrays may be configured by sequentially repeating the auxiliary circuit AC, the sub-cell arrays, and the isolation circuit ISOLC in the column direction, such as Fig.19 shown.

[0119] According to the above embodiments, in the memory device of the present disclosure, the auxiliary circuit for assisting write performance can be configured in the cell array area of ​​the memory device rather than in the peripheral circuit, thereby reducing the area overhead. In alternative embodiments, the memory device can have any number of bits, which can be divided between the number of sub-cell arrays described in any of the embodiments described above and / or its alternative arrangements, but is not limited thereto.

[0120] Fig.21 Schematic diagram showing the layout of a memory device according to an embodiment. As an example, Fig.21 Shows Fig.16 Auxiliary circuits and Figure 3 The layout of the memory cell is not limited thereto.

[0121] refer to Fig.21 , the memory device according to the embodiment may include an N-type region N well, a gate electrode Gate, an active region ACT, a vertical wiring or CA layer CA, a horizontal wiring or CB layer CB, a wiring layer M1 and a contact CONT. At least some of each region, each layer and each contact may form a memory cell and / or an auxiliary circuit according to the above-described embodiment. The auxiliary circuit is configured with a layout compatible with the memory cell as shown in the figure.

[0122] The layout of the first memory cell MC1 and the second memory cell MC2 may be substantially the same, and the layout of the first auxiliary circuit AC1 and the second auxiliary circuit AC2 may be substantially the same. In addition, the layout of the first memory cell MC1 and the first auxiliary circuit AC1 may be implemented adjacent to each other, and the layout of the second memory cell MC2 and the second auxiliary circuit AC2 may also be implemented adjacent to each other. That is, the layouts of the memory cells and the auxiliary circuits are compatible with each other.

[0123] To form each memory cell, set the Figure 4 The gate electrodes PU1, PU2, PD1, PD2, PG1 and PG2 of the transistors in the embodiment of the present invention are provided, and in order to form each auxiliary circuit, each corresponding to Fig.16 The gate electrodes PUH, PDH, PGH and STA of the transistors in the stack. In this case, PU1, PU2, PD1, PD2, PG1 and PG2 may correspond to the gate electrodes of the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first transmission gate transistor and the second transmission gate transistor in sequence, respectively. In addition, PUH, PDH, PGH and STA may correspond to the gate electrodes of the pull-up header transistor, the pull-down header transistor, the transmission gate header transistor and the stacked transistor in sequence, respectively.

[0124] The wiring layer is connected to the source / drain region and / or the gate electrode through a contact. The wiring layer may correspond to one of the word line WL, the ground corresponding to the ground voltage VSS, the wiring to which the control signal CON is applied, the bit line and the bit line inverse logic BL and BLb, and the power supply line SL, such as Figure 3 and Fig.16 shown.

[0125] According to the embodiment, an n-type region, an active region arranged on the n-type region, a gate electrode arranged on the active region, a CA layer arranged on the gate electrode, a CB layer, a wiring layer corresponding to the bit line and the bit line inverse logic connected to other layers through contacts, a wiring layer to which a ground voltage is applied, a wiring layer corresponding to the word line, and a wiring layer to which a power supply voltage is applied are sequentially arranged along the d3 direction.

[0126] Referring to the first memory cell MC1 and the second memory cell MC2, a plurality of active regions may be arranged to extend along the d1 direction, and gate electrodes PU1, PU2, PD1, PD2, PG1, and PG2 may be arranged on each active region to extend along the d2 direction. A wiring layer corresponding to the ground voltage VSS is connected to the active region where PD1 and PG1 are placed through a CA layer, and a wiring layer corresponding to a word line WL is connected to PG1 through a CB layer. PU1 is connected to PD1.

[0127] PU2 and PD2 are connected to each other, and the wiring layer corresponding to the word line WL is connected to PG2 through the CB layer. The wiring layer corresponding to the ground voltage VSS is connected to PD2 through the CA layer. The wiring layer corresponding to the power supply line SL is connected to PU1 and PU2.

[0128] Looking at the first auxiliary circuit AC1 and the second auxiliary circuit AC2, PGH, STA, PDH, and PUH may be disposed to extend on a plurality of active regions along the d2 direction. The plurality of active regions may be connected to each other through a CA layer extending along the d2 direction.

[0129] A wiring layer corresponding to ground voltage VSS is connected to PGH and STA, and PDH and PUH are connected to each other. A wiring layer to which control signal CON is applied through a CB layer is connected to PDH, and a wiring layer to which power supply voltage VDD is applied is connected to PUH.

[0130] According to the above embodiment, the gate electrodes and CA layers of the first auxiliary circuit AC1 and the second auxiliary circuit AC2 are arranged to extend along the d2 direction so that the source, gate and drain can be shared with each other. The first auxiliary circuit AC1 and the second auxiliary circuit AC2 can be formed in pairs between the memory cells.

[0131] Specifically, the transistors of the auxiliary circuit can be configured to have substantially the same width and / or height as the transistors of the memory cell, or can be configured to have substantially the same gate pitch and / or pattern as the transistors of the memory cell. The pull-up header transistor PUH, the pull-down header transistor PDH, and the stacked transistor STA of the auxiliary circuit can be configured using substantially the same footprint as the pull-up transistors PU1 and PU2 and one pull-down transistor (PD1 or PD2) of the memory cell. In addition, each of the junctions of the pull-up header transistor PUH and the pull-down header transistor PDH can be connected by further adding a CA layer.

[0132] According to the above-described embodiments, in the memory device of the present disclosure, the auxiliary circuit has a layout compatible with the memory cell, so that the auxiliary circuit can be implemented without a separate dummy cell or space. Therefore, the area overhead can be reduced.

[0133] According to an embodiment of the present disclosure, a unit cell circuit for assisting a write operation and a memory device including the unit cell circuit may be provided.

[0134] The above description is a specific embodiment for carrying out the present disclosure. Embodiments in which the design is simply changed or easily changed may be included in the present disclosure as well as in the above-mentioned embodiments. In addition, the technology that is easily changed and implemented by using the above-mentioned embodiments may be included in the present disclosure. Although the present disclosure has been described with reference to the embodiments of the present disclosure, it is clear to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A unit cell circuit of a memory cell array, the unit cell circuit comprising: a subcell array including a plurality of memory cells, each memory cell being connected to a power line; as well as An auxiliary circuit is connected to the subcell array through the power line and is configured to precharge the power line with a power voltage during a standby mode based on a control signal and block the power line at the start of a write operation.

2. The unit cell circuit according to claim 1, in, The memory cell array includes a plurality of unit cell circuits, Wherein, based on the auxiliary circuit blocking the power line during the write operation, the voltage of the power line collapses from the power supply voltage.

3. The unit cell circuit according to claim 2, wherein: Based on the success of the write operation to one of the plurality of memory cells, the voltage of the power supply line stops collapsing.

4. The unit cell circuit according to claim 1, wherein: The auxiliary circuit is configured as follows: After the initiation of the write operation, a pull-up current is formed on the power line based on the collapse of the voltage of the power line.

5. The unit cell circuit according to claim 1, wherein: The auxiliary circuit comprises: a first transistor having a gate configured to receive the control signal, a source configured to receive the power supply voltage, and a drain connected to the power supply line; and The second transistor has a gate configured to receive a logic high voltage during the write operation, a drain configured to receive the power supply voltage, and a source connected to the power supply line.

6. The unit cell circuit according to claim 5, wherein: The control signal is commonly applied to the gate of the first transistor and the gate of the second transistor.

7. The unit cell circuit according to claim 5, wherein: The second transistor has the gate and the drain connected to each other.

8. The unit cell circuit according to claim 1, wherein: The auxiliary circuit comprises: a stacked transistor having a gate configured to receive a ground voltage and a drain connected to the power line; a first transistor having a gate configured to receive the control signal, a source configured to receive the power supply voltage, and a drain connected to the source of the stacked transistor; and A second transistor has a gate configured to receive a logic high voltage during the write operation, a drain configured to receive the power supply voltage, and a source connected to the source of the stacked transistor.

9. The unit cell circuit according to claim 1, wherein: The auxiliary circuit comprises: a first transistor having a gate configured to receive the control signal, a source configured to receive the power supply voltage, and a drain connected to the power supply line; and A third transistor has a gate and a drain connected to the power supply line, and has a source configured to receive the power supply voltage.

10. The unit cell circuit according to claim 1, wherein: The control signal corresponds to a logic low value during the standby mode and corresponds to a logic high value during the write operation.

11. The unit cell circuit according to claim 10, in, each of the plurality of memory cells is selected by a word line during the write operation, and The control signal is turned into a logic high value at a first timing when the word line is activated or at a second timing after a period of time has passed from the first timing.

12. The unit cell circuit according to claim 1, wherein: The power supply line is configured to be used for the sub-unit array through the auxiliary circuit.

13. A memory device comprising: A memory cell array including a plurality of unit cell circuits; as well as a row peripheral circuit configured to control the plurality of unit cell circuits, Wherein, each of the plurality of unit cell circuits comprises: a corresponding sub-cell array including a corresponding plurality of memory cells; and A corresponding auxiliary circuit is connected to the corresponding subcell array through a corresponding power line and is configured to precharge the corresponding power line with a power voltage during a standby mode based on control of the row peripheral circuit and block the corresponding power line at the start of a write operation.

14. The memory device of claim 13, wherein: The row peripheral circuit comprises: a plurality of row decoders configured to select a plurality of word lines connected to the memory cell array based on first address information; and A plurality of control logic circuits are configured to control the auxiliary circuits based on control signals.

15. The memory device of claim 14, wherein: Each of the plurality of control logic circuits is configured to simultaneously control two auxiliary circuits among the plurality of auxiliary circuits corresponding to the plurality of unit cell circuits.

16. The memory device of claim 14, wherein: Each of the plurality of control logic circuits is configured to generate the control signal based on second address information, a write clock signal, and a hold signal.

17. The memory device of claim 16, wherein: The hold signal is defined such that the control signal corresponds to a logic high value in the hold mode.

18. A memory row circuit comprising: a control logic circuit configured to provide a control signal; as well as Unit cell circuit, including: an auxiliary circuit configured to receive the control signal, precharge the power line with the power voltage during the standby mode based on the control signal, and block the power line at the start of the write operation; as well as The sub-cell array includes a plurality of memory cells, each memory cell being connected to the power line.

19. The memory row circuit of claim 18, wherein: The control logic circuit generates the control signal based on address information, a write clock signal, and a hold signal for a hold mode.

20. The memory row circuit of claim 19, wherein: The control signal is generated to cause the auxiliary circuit to block the power line when the hold mode is activated.

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