Sense amplifier, reading circuit and module based on bit line switch and capacitance coupling

Abstract

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier, a reading circuit and a module based on bit line switch and capacitance coupling. The invention discloses a DRAM (Dynamic Random Access Memory) sensitive amplifier based on bit line switch and capacitance coupling. The DRAM sensitive amplifier comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N9, two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2 and two capacitors Cc1-Cc2. The SCSA is designed and matched with corresponding control logic, so that a pre-charging stage, an offset calibration stage, a charge sharing stage, a pre-induction stage and a main induction stage are designed when the SCSA reads a DRAM storage unit, the potential of a bit line BLT or BLB can be correctly changed, and the SCSA reading amplification function is guaranteed. Compared with a traditional DRAM sensitive amplifier, the SCSA provided by the invention has the advantages that the offset voltage index is greatly reduced under the condition that the number of elements is not greatly increased, and the sensing margin is effectively increased.

Description

Technical Field

[0001] The present invention relates to the technical field of DRAM circuit design, and more specifically, to: 1. a DRAM sensitive amplifier (SCSA for short) based on bit line switches and capacitor coupling; 2. a read circuit constructed based on the SCSA; 3. a sensitive amplifier module designed based on the SCSA. Background Art

[0002] DRAM (Dynamic RAM) is a dynamic random access memory that uses a transistor plus a capacitor to store one bit of data, and requires periodic power replenishment to maintain the stored data.

[0003] As the density and capacity of DRAM circuits continue to increase, and the process nodes gradually shrink, the mismatch of MOS tube size, leakage of storage unit data, parasitic capacitance of the bit line itself, coupling noise between bit lines and other problems have become more serious, resulting in a decrease in the effective voltage difference. The DRAM sense amplifier is an important component used to read DRAM storage data - it reads and amplifies the voltage of the bit line to read DRAM storage data. As the effective voltage difference of the DRAM circuit decreases, a DRAM sense amplifier with a smaller offset voltage is required to achieve correct reading and amplification. However, due to the large offset voltage of the existing traditional DRAM sense amplifier, it is easy to cause erroneous amplification and thus errors in reading DRAM data.

[0004] Therefore, how to reduce the offset voltage of the DRAM sense amplifier is an important research direction. At the same time, it is also necessary to ensure that the components contained in the improved DRAM sense amplifier are not too many, so as to ensure that the circuit occupies an excessive area. Summary of the invention

[0005] Based on this, it is necessary to provide a sense amplifier, a read circuit, and a module based on a bit line switch and capacitor coupling to address the problem of large offset voltage of the existing traditional DRAM sense amplifier.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention provides a DRAM sense amplifier based on a bit line switch and capacitor coupling, comprising: 9 NMOS transistors N1-N9, 2 PMOS transistors P1-P2, and 2 capacitors Cc1-Cc2.

[0008] The source of P1 is connected to the control signal SAP1;

[0009] The source of N1 is connected to the control signal SAN1, the drain is connected to the drain of P1, and the gate is connected to the gate of P1;

[0010] The source of P2 is connected to the control signal SAP2;

[0011] The source of N2 is connected to the control signal SAN2, the drain is connected to the drain of P2, and the gate is connected to the gate of P2;

[0012] The gate of N3 is connected to the control signal OC, the drain is connected to the gate of P1, and the source is connected to the drain of P1;

[0013] The gate of N4 is connected to OC, the drain is connected to the gate of P2, and the source is connected to the drain of P2;

[0014] The gate of N5 is connected to the control signal TSE2, the source is connected to the bit line BLB, and the drain is connected to the drain of P1;

[0015] The gate of N6 is connected to the control signal TSE1, the source is connected to the bit line BLT, and the drain is connected to the drain of P2;

[0016] The gate of N7 is connected to the control signal BSE1, the source is connected to BLB, and the drain is connected to the drain of N6;

[0017] The gate of N8 is connected to the control signal BSE2, the source is connected to BLT, and the drain is connected to the drain of N5;

[0018] The gate of N9 is connected to the control signal BLEQ, the source is connected to the input signal VEQ, and the drain is connected to the drain of N6;

[0019] The first end of Cc1 is connected to BLT, and the second end is connected to the gate of P1;

[0020] A first end of Cc2 is connected to BLB, and a second end is connected to the gate of P2;

[0021] Among them, P1 and N1 constitute inverter one, and P2 and N2 constitute inverter two; inverter one and inverter two are cross-coupled through Cc1-Cc2 to form a latch structure.

[0022] The implementation of the DRAM sense amplifier based on bit line switches and capacitive coupling is in accordance with the method or process of an embodiment of the present disclosure.

[0023] In a second aspect, the present invention discloses a reading circuit, comprising: a DRAM storage unit 1, a DRAM storage unit 2, and a DRAM sensitive amplifier based on a bit line switch and capacitor coupling as disclosed in the first aspect.

[0024] DRAM storage cell 1 is used to store 0 or 1. DRAM storage cell 2 is used to store 0 or 1.

[0025] A DRAM sense amplifier based on a bit line switch and capacitor coupling is used to read DRAM storage cell one or DRAM storage cell two.

[0026] The implementation of such a read circuit is in accordance with the method or process of an embodiment of the present disclosure.

[0027] In a third aspect, the present invention discloses a sense amplifier module, which adopts the circuit layout of the DRAM sense amplifier based on bit line switch and capacitive coupling as disclosed in the first aspect.

[0028] The implementation of such a sense amplifier module is based on a method or process of an embodiment of the present disclosure.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. The present invention designs a DRAM sensitive amplifier based on bit line switch and capacitor coupling, and cooperates with corresponding control logic, so that when reading the DRAM storage unit, it designs: pre-charge stage, offset calibration stage, charge sharing stage, pre-sensing stage, and main sensing stage. Among them, in the offset calibration stage, the offset is reduced by storing the flip voltage of the inverter and the voltage difference of the bit line in the capacitor; through the cooperation of the pre-sensing stage and the main sensing stage, the bit line potential can be correctly changed and pulled to the full swing, ensuring the SCSA read amplification function.

[0031] 2. Compared with the traditional DRAM sense amplifier, the SCSA provided by the present invention realizes a significant reduction in the offset voltage index and effectively increases the sensing margin without a large increase in the number of components. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 A circuit diagram of the SCSA disclosed in Embodiment 1 of the present invention;

[0034] Figure 2 Based on Figure 1 Circuit diagram of the reading circuit constructed by SCSA in ;

[0035] Figure 3 for Figure 2 A timing operation diagram of a reading circuit;

[0036] Figure 4 Based on Figure 1 Pinout diagram of the sense amplifier module designed by SCSA;

[0037] Figure 5 A circuit diagram of a read circuit based on an existing conventional DRAM sense amplifier (BLSA) is disclosed for Embodiment 2 of the present invention;

[0038] Figure 6 for Figure 5 A timing operation diagram of a reading circuit;

[0039] Figure 7 for Figure 5 The offset voltage distribution diagram of BLSA in the figure;

[0040] Figure 8 for Figure 1 Figure 2. Distribution of offset voltage of SCSA in Figure 2. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0044] Example 1

[0045] First, see Figure 1 , which is a circuit structure diagram of a DRAM sense amplifier (SCSA) based on bit line switch and capacitor coupling provided in the first embodiment.

[0046] For SCSA, it includes: 9 NMOS tubes N1-N9, 2 PMOS tubes P1-P2, and 2 capacitors Cc1-Cc2.

[0047] like Figure 1As shown, the connection relationship of each component is as follows:

[0048] The source of P1 is connected to the control signal SAP1;

[0049] The source of N1 is connected to the control signal SAN1, the drain is connected to the drain of P1, and the gate is connected to the gate of P1;

[0050] The source of P2 is connected to the control signal SAP2;

[0051] The source of N2 is connected to the control signal SAN2, the drain is connected to the drain of P2, and the gate is connected to the gate of P2;

[0052] The gate of N3 is connected to the control signal OC, the drain is connected to the gate of P1, and the source is connected to the drain of P1;

[0053] The gate of N4 is connected to OC, the drain is connected to the gate of P2, and the source is connected to the drain of P2;

[0054] The gate of N5 is connected to the control signal TSE2, the source is connected to the bit line BLB, and the drain is connected to the drain of P1;

[0055] The gate of N6 is connected to the control signal TSE1, the source is connected to the bit line BLT, and the drain is connected to the drain of P2;

[0056] The gate of N7 is connected to the control signal BSE1, the source is connected to BLB, and the drain is connected to the drain of N6;

[0057] The gate of N8 is connected to the control signal BSE2, the source is connected to BLT, and the drain is connected to the drain of N5;

[0058] The gate of N9 is connected to the control signal BLEQ, the source is connected to the input signal VEQ, and the drain is connected to the drain of N6;

[0059] The first end of Cc1 is connected to BLT, and the second end is connected to the gate of P1;

[0060] A first end of Cc2 is connected to BLB, and a second end of Cc2 is connected to the gate of P2.

[0061] Among them, P1 and N1 constitute inverter one, and P2 and N2 constitute inverter two; inverter one and inverter two are cross-coupled through Cc1-Cc2 to form a latch structure.

[0062] For the convenience of subsequent explanation, the input and output of inverter 1 and inverter 2 can be represented by nodes:

[0063] The input of inverter 1 is node GB (i.e., the gate of P1, the gate of N1, the drain of N3, and the second end of Cc1 are connected to node GB), and the output is node IT (i.e., the drain of P1, the drain of N1, the source of N3, and the drain of N5 are connected to node IT);

[0064] The input of inverter 2 is node GT (i.e., the gate of P2, the gate of N2, the drain of N4, and the second end of Cc2 are connected to node GT), and the output is node IB (the drain of P2, the drain of N2, the source of N4, and the drain of N6 are connected to node IB).

[0065] Secondly, see Figure 2 Based on the above SCSA, a read circuit is constructed, that is, a circuit using the SCSA. The read circuit includes: SCSA, DRAM storage unit 1, and DRAM storage unit 2.

[0066] DRAM storage unit 1 is used to store 0 or 1. DRAM storage unit 2 is used to store 0 or 1. SCSA is used to read DRAM storage unit 1 or DRAM storage unit 2.

[0067] DRAM storage unit 1 and DRAM storage unit 2 may adopt a common 1T1C structure.

[0068] See also Figure 2 DRAM storage unit 1 includes: 1 NMOS tube N11 and 1 capacitor C0. The drain of N11 is connected to BLT, and the gate is connected to the word line WL0; the first end of C0 is connected to the source of N11, and the second end is grounded GND. DRAM storage unit 2 includes: 1 NMOS tube N10 and 1 capacitor C2. The drain of N10 is connected to BLB, and the gate is connected to the word line WL1; the second end of C1 is connected to the source of N10, and the second end is grounded GND.

[0069] It should be noted that WL0 and WL1 cannot be turned on at the same time to prevent damage to the data in the DRAM storage unit.

[0070] The above disclosed reading circuit is used to perform data reading operation, and its working sequence includes: pre-charge (PC) stage, offset calibration (OC) stage, charge sharing (CS) stage, pre-sensing (PS) stage, and main sensing (MS) stage.

[0071] The following is a brief explanation of the principles of each stage:

[0072] 1) In the pre-charge stage:

[0073] BLEQ is set to high level (N9 is turned on), VEQ is set to VDD / 2, OC is set to high level (N3 and N4 are turned on), TSE1, TSE2, BSE1, and BSE2 are set to high level (N5, N6, N7, and N8 are turned on), SAN1, SAN2, SAP1, and SAP2 are set to VDD / 2 (inverter one and inverter two do not work), and BLT and BLB are pre-charged to VDD / 2 (VEQ charges BLT through N9 and N6, VEQ charges BLB through N9 and N7, and BLT and BLB are short-circuited through N8 and N5 to keep them at VDD / 2).

[0074] 2) During the offset calibration phase:

[0075] BLEQ is set to a low level (N9 is disconnected), OC maintains a high level (N3 and N4 are turned on), TSE1, TSE2, BSE1, and BSE2 are set to a low level (N5, N6, N7, and N8 are disconnected), SAN1 and SAN2 are set to a low level, and SAP1 and SAP2 are set to a high level (inverter one and inverter two are working, GB is shorted to IT through N3, and GT is shorted to IB through N4, so that the GB voltage is the flip point voltage of inverter one, and the GT voltage is the flip point voltage of inverter two), the voltage difference between the input terminal (GB) of inverter one and BLT is stored in Cc1, and the voltage difference between the input terminal (GT) of inverter two and BLB is stored in Cc2, thereby reducing the offset.

[0076] 3) In the charge sharing stage:

[0077] BLEQ is kept at a low level (N9 is disconnected), OC is set to a low level (N3 and N4 are disconnected), TSE1, TSE2, BSE1, and BSE2 are kept at a low level (N5, N6, N7, and N8 are disconnected), and SAN1, SAN2, SAP1, and SAP2 are set to VDD / 2 (inverter 1 and inverter 2 do not work);

[0078] 301, if DRAM storage unit 1 is to be read, WL0 is set to a high level (N11 is turned on), and C1 and BLT share charges (C1 is turned on through N11 and BLT).

[0079] 302, if DRAM storage unit 2 is to be read, WL1 is set to a high level (N10 is turned on), and C2 and BLB share charges (C2 is turned on through N10 and BLB).

[0080] 4) In the pre-induction stage:

[0081] 401, if DRAM storage unit 1 is to be read, WL0 is at a high level in the charge sharing stage, then in the pre-sensing stage, WL0 maintains a high level (N11 is turned on), BLEQ maintains a low level (N9 is turned off), OC maintains a low level (N3, N4 are turned off), TSE1, TSE2 are set to a high level (N6, N5 are turned on), BSE1, BSE2 maintain a low level (N7, N8 are turned off), SAN1 is set to a low level, SAP1 is set to a high level, SAN2, SAP2 maintain VDD / 2, so:

[0082] Inverter 1 works and the voltage difference between its input terminal (GB) and output terminal (IT) is enlarged; since IT and BLB are connected through N5, the voltage difference between the input terminal (GB) and BLB of inverter 1 is increased.

[0083] Although the inverter 2 is not working, IB and BLT are connected through N6 so that the two have the same level.

[0084] 402, if DRAM storage unit 2 is to be read, WL1 is at a high level in the charge sharing stage, then in the pre-sensing stage, WL1 maintains a high level (N10 is turned on), BLEQ maintains a low level (N9 is turned off), OC maintains a low level (N3, N4 are turned off), TSE1, TSE2 are set to a high level (N6, N5 are turned on), BSE1, BSE2 maintain a low level (N7, N8 are turned off), SAN2 is set to a low level, SAP2 is set to a high level, SAN1, SAP1 maintain VDD / 2, so:

[0085] The second inverter works and the voltage difference between its input terminal (GT) and output terminal (IB) is enlarged; because IB and BLT are connected through N11, the voltage difference between the input terminal (IB) and BLT of the second inverter is increased.

[0086] Although the inverter 2 is not working, IT and BLB are connected through N5 so that the two have the same level.

[0087] 5) In the main induction stage:

[0088] In general, in the main sensing stage, WL0 and WL1 maintain the same state as the pre-sensing stage, BLEQ maintains a low level (N9 is disconnected), OC maintains a low level (N3 and N4 are disconnected), TSE1 and TSE2 maintain a high level (N6 and N5 are turned on), BSE1 and BSE2 maintain a low level (N7 and N8 are disconnected), SAN1 and SAN2 are set to a low level, and SAP1 and SAP2 are set to a high level (inverter 1 and inverter 2 are working);

[0089] 501, if DRAM storage unit 1 is to be read, and DRAM storage unit 1 stores 1, then in the main sensing stage, WL0 maintains a high level (N11 is turned on), and the cross-coupled inverter 1 and inverter 2 increase the voltage difference (inverter 1 increases the voltage difference between GB and IT, and inverter 2 increases the voltage difference between GT and IB). Then, based on the pre-sensing stage, the BLT voltage is quickly pulled to VDD and the BLB voltage is quickly reduced to 0, so the storage data of DRAM storage unit 1 is obtained by reading the BLT potential.

[0090] 502, if DRAM storage unit 1 is to be read, and DRAM storage unit 1 stores 0, then in the main sensing stage, WL0 maintains a high level (N11 is turned on), and the cross-coupled inverter 1 and inverter 2 increase the voltage difference (inverter 1 increases the voltage difference between GB and IT, and inverter 2 increases the voltage difference between GT and IB). Then, based on the pre-sensing stage, the BLT voltage is quickly reduced to 0 and the BLB voltage is quickly pulled to VDD. Then, the storage data of DRAM storage unit 1 is obtained by reading the BLT potential.

[0091] 503, if DRAM storage unit 2 is to be read, and DRAM storage unit 2 stores 1, then in the main sensing stage, WL1 maintains a high level (N10 is turned on), and the cross-coupled inverters 1 and 2 increase the voltage difference (inverter 1 increases the voltage difference between GB and IT, and inverter 2 increases the voltage difference between GT and IB). Then, based on the pre-sensing stage, the BLB voltage is quickly pulled to VDD and the BLT voltage is quickly reduced to 0. Then, the storage data of DRAM storage unit 2 is obtained by reading the BLB potential.

[0092] 504, if DRAM storage unit 2 is to be read, and DRAM storage unit 2 stores 0, then in the main sensing stage, WL1 maintains a high level (N10 is turned on), and the cross-coupled inverter 1 and inverter 2 increase the voltage difference (inverter 1 increases the voltage difference between GB and IT, and inverter 2 increases the voltage difference between GT and IB). Then, based on the pre-sensing stage, the BLB voltage is quickly reduced to 0 and the BLB voltage is quickly pulled to VDD. Then, the storage data of DRAM storage unit 2 is obtained by reading the BLB potential.

[0093] In order to facilitate the understanding of the above stages, the timing change diagram of each signal at each stage is drawn by taking the reading of DRAM storage unit 1 as an example, as shown in FIG. Figure 3 shown.

[0094] In addition, this embodiment 1 simultaneously discloses a sense amplifier module, which adopts the circuit layout of the DRAM sense amplifier based on bit line switch and capacitor coupling disclosed above. The mode of packaging into a module is easier to promote and apply the above circuit.

[0095] like Figure 4 As shown, the sense amplifier module has 13 pins:

[0096] Among them, pin 1 is used to connect BLT; pin 2 is used to connect BLB; pin 3 is used to connect BLEQ; pin 4 is used to connect VEQ; pin 5 is used to connect SAP1; pin 6 is used to connect SAP2; pin 7 is used to connect SAN1; pin 8 is used to connect SAN2; pin 9 is used to connect TSE1; pin 10 is used to connect TSE2; pin 11 is used to connect BSE1; pin 12 is used to connect TSE2; pin 13 is used to connect OC.

[0097] Example 2

[0098] This embodiment 2 is intended to verify the performance effect of the DRAM sense amplifier based on the bit line switch and capacitive coupling proposed in embodiment 1:

[0099] This embodiment 2 introduces a read circuit constructed by an existing traditional DRAM sense amplifier (BLSA), and performs simulation comparison with the read circuit constructed based on the SCSA proposed in embodiment 1.

[0100] First, the read circuit built based on BLSA is Figure 5 As shown, it includes: BLSA, DRAM storage unit three, and DRAM storage unit four.

[0101] Among them, BLSA includes: 5 NMOS transistors NM1~NM5 and 2 PMOS transistors PM1~PM2. The sources of PM1 and PM2 are connected to the control signal SAP; the sources of N1 and N2 are connected to the control signal SAN; the drain of P1 is connected to the drain of N1, and the gate is connected to the gate of N1; the drain of P2 is connected to the drain of N2, the gate of P1 and the bit line BLT', and the gate is connected to the gate of N2, the drain of P1, and the bit line BLB'; the source of N3 is connected to BLB', the drain is connected to BLT', and the gate is connected to the control signal BLEQ'; the source of N4 is connected to the source of N3, the drain is connected to the input signal VEQ', and the gate is connected to the gate of N3; the source of N5 is connected to the drain of N3, the drain is connected to the drain of N4, and the gate is connected to the gate of N4.

[0102] Among them, PM1 and NM1 constitute inverter three, PM2 and NM2 constitute inverter four, inverter three and inverter four realize cross coupling and form a latch structure.

[0103] The DRAM storage unit 3 includes: an NMOS transistor NM7 and a capacitor CM1. The drain of NM7 is connected to BLT', and the gate is connected to the word line WL3; the first end of CM1 is connected to the source of NM7, and the second end is grounded GND.

[0104] DRAM storage unit 4 includes: an NMOS transistor NM6 and a capacitor CM2. The drain of NM7 is connected to BLB', and the gate is connected to the word line WL4; the first end of CM2 is connected to the source of NM6, and the second end is grounded GND.

[0105] For the reading circuit constructed based on BLSA of the above structure, the working sequence of the data reading operation includes: a pre-charge (PC) phase, a charge sharing (CS) phase, and a main sensing (MS) phase.

[0106] 1) In the pre-charge stage:

[0107] BLEQ' is set to high level (NM3, NM4, NM5 are turned on), VEQ' is set to VDD / 2, SAP and SAN are set to VDD / 2 (inverter three and inverter four are not working), BLT' and BLB' are pre-charged to VDD / 2 (VEQ' charges BLT' through NM5, VEQ' charges BLB' through NM4, and BLT' and BLB' are turned on through NM3).

[0108] 2) In the charge sharing stage:

[0109] BLEQ' is set to low level (NM3, NM4, NM5 are disconnected), SAP and SAN are kept at VDD / 2 (inverter three and inverter four do not work);

[0110] If DRAM storage unit 3 is to be read, WL3 is set to a high level (NM7 is turned on), and CM1 and BLT' share charges (CM1 is connected to BLT' through NM7).

[0111] If DRAM storage unit 4 is to be read, WL4 is set to a high level (NM6 is turned on), and CM2 and BLB' share charges (CM2 is connected to BLB' through NM6).

[0112] 3) In the main induction stage:

[0113] In general, in the main sensing stage, WL3 and WL4 maintain the same state as in the charge sharing stage, BLEQ' remains low (NM3, NM4, and NM5 are disconnected), SAN is set to a low level, and SAP is set to a high level (inverter three and inverter four are working);

[0114] 301, if DRAM storage unit 3 is to be read, and DRAM storage unit 1 stores 0, then in the main sensing stage, WL3 maintains a high level (NM7 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BLT' voltage drops to 0, and the BLB' voltage is pulled to VDD, then the storage data of DRAM storage unit 3 is obtained by reading the BLT' potential.

[0115] 302, if DRAM storage unit 3 is to be read, and DRAM storage unit 1 stores 1, then in the main sensing stage, WL3 maintains a high level (NM7 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BLB' voltage drops to 0, and the BLT' voltage is pulled to VDD, then the storage data of DRAM storage unit 3 is obtained by reading the BLT' potential.

[0116] 303, if DRAM storage unit 4 is to be read, and DRAM storage unit 4 stores 0, then in the main sensing stage, WL4 maintains a high level (NM6 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BLB' voltage drops to 0, and the BLT' voltage is pulled to VDD, then the storage data of DRAM storage unit 4 is obtained by reading the BLB' potential.

[0117] 304, if DRAM storage unit 4 is to be read, and DRAM storage unit 4 stores 1, then in the main sensing stage, WL4 maintains a high level (NM6 is turned on), and the cross-coupled inverters 3 and 4 quickly increase the voltage difference, so that the BLT' voltage drops to 0, and the BLB' voltage is pulled to VDD, then the storage data of DRAM storage unit 4 is obtained by reading the BLB' potential.

[0118] In order to facilitate the understanding of the above stages, the timing change diagram of each signal at each stage is drawn by taking the reading of DRAM storage unit 3 as an example, as shown in FIG. Figure 6 shown.

[0119] Next, simulations are performed on the read circuit constructed based on SCSA of Example 1 and the read circuit constructed based on BLSA described above.

[0120] The simulation conditions are as follows: based on 28nm CMOS process, the aspect ratio of the PMOS tube is 200:30, and the aspect ratio of the NMOS tube is 100:30; the capacitance values ​​of Cc1 and Cc2 are 4fF.

[0121] 500 Monte Carlo simulations were performed at room temperature to obtain the offset voltage distribution at different process corners. The results are shown in Figure 7 , Figure 8 .

[0122] Figure 7 , Figure 8 All of them are normal distribution curves of offset voltage, and the standard deviation is taken as the offset voltage. It can be seen that the offset voltage of SCSA (2.48mV) is much lower than the offset voltage of BLSA (18.01mV), which illustrates the great performance advantage of SCSA proposed in Example 1: the offset voltage index is greatly reduced, and the sensing margin is effectively increased.

[0123] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A DRAM sense amplifier based on bit line switch and capacitive coupling, characterized in that: include: 9 NMOS tubes N1~N9, 2 PMOS tubes P1~P2, 2 capacitors Cc1~Cc2; The source of P1 is connected to the control signal SAP1; The source of N1 is connected to the control signal SAN1, the drain is connected to the drain of P1, and the gate is connected to the gate of P1; The source of P2 is connected to the control signal SAP2; The source of N2 is connected to the control signal SAN2, the drain is connected to the drain of P2, and the gate is connected to the gate of P2; The gate of N3 is connected to the control signal OC, the drain is connected to the gate of P1, and the source is connected to the drain of P1; The gate of N4 is connected to OC, the drain is connected to the gate of P2, and the source is connected to the drain of P2; The gate of N5 is connected to the control signal TSE2, the source is connected to the bit line BLB, and the drain is connected to the drain of P1; The gate of N6 is connected to the control signal TSE1, the source is connected to the bit line BLT, and the drain is connected to the drain of P2; The gate of N7 is connected to the control signal BSE1, the source is connected to BLB, and the drain is connected to the drain of N6; The gate of N8 is connected to the control signal BSE2, the source is connected to BLT, and the drain is connected to the drain of N5; The gate of N9 is connected to the control signal BLEQ, the source is connected to the input signal VEQ, and the drain is connected to the drain of N6; The first end of Cc1 is connected to BLT, and the second end is connected to the gate of P1; A first end of Cc2 is connected to BLB, and a second end is connected to the gate of P2; Among them, P1 and N1 constitute inverter one, and P2 and N2 constitute inverter two; inverter one and inverter two are cross-coupled through Cc1-Cc2 to form a latch structure.

2. A reading circuit, characterized in that: include: DRAM storage unit 1, which is used to store 0 or 1; DRAM storage unit 2, which is used to store 0 or 1; as well as The DRAM sense amplifier based on bit line switch and capacitive coupling as claimed in claim 1 is used to read DRAM storage cell one or DRAM storage cell two.

3. The reading circuit according to claim 2, characterized in that: The DRAM storage unit 1 includes: an NMOS tube N11 and a capacitor C0; The drain of N11 is connected to BLT, and the gate is connected to word line WL0; A first end of C0 is connected to the source of N11, and a second end is grounded GND; The DRAM storage unit 2 includes: an NMOS tube N10 and a capacitor C2; The drain of N10 is connected to BLB, and the gate is connected to word line WL1; The second end of C1 is connected to the source of N10, and the second end is grounded GND; Among them, WL0 and WL1 are not turned on at the same time.

4. The reading circuit according to claim 3, characterized in that: The working sequence of the reading circuit includes a pre-charging stage, an offset calibration stage, a charge sharing stage, a pre-sensing stage, and a main sensing stage.

5. The reading circuit according to claim 4, characterized in that: In the precharge stage, BLEQ is set to a high level, VEQ is set to VDD / 2, OC is set to a high level, TSE1, TSE2, BSE1, and BSE2 are set to a high level, SAN1, SAN2, SAP1, and SAP2 are set to VDD / 2, and BLT and BLB are precharged to VDD / 2.

6. The reading circuit according to claim 5, characterized in that: In the offset calibration stage, BLEQ is set to a low level, OC remains at a high level, TSE1, TSE2, BSE1, and BSE2 are set to a low level, SAN1 and SAN2 are set to a low level, SAP1 and SAP2 are set to a high level, the voltage difference between the input end of inverter one and BLT is stored in Cc1, and the voltage difference between the input end of inverter two and BLB is stored in Cc2.

7. The read circuit according to claim 6, characterized in that: In the charge sharing stage, BLEQ is kept at a low level, OC is set to a low level, TSE1, TSE2, BSE1, BSE2 are kept at a low level, and SAN1, SAN2, SAP1, SAP2 are set to VDD / 2; If WL0 is set to high level, C1 and BLT share charge; If WL1 is set high, C2 and BLB share charge.

8. The reading circuit according to claim 7, characterized in that: If WL0 is high in the charge sharing stage, then in the pre-sensing stage, WL0 maintains a high level, BLEQ maintains a low level, OC maintains a low level, TSE1 and TSE2 are set to a high level, BSE1 and BSE2 maintain a low level, SAN1 is set to a low level, SAP1 is set to a high level, SAN2 and SAP2 maintain VDD / 2, and the voltage difference between the input terminal of the inverter 1 and BLB is increased; If WL1 is at a high level in the charge sharing stage, then in the pre-sensing stage, WL1 remains at a high level, BLEQ remains at a low level, OC remains at a low level, TSE1 and TSE2 are set to a high level, BSE1 and BSE2 remain at a low level, SAN2 is set to a low level, SAP2 is set to a high level, SAN1 and SAP1 remain at VDD / 2, increasing the voltage difference between the input terminal of the inverter 2 and BLT.

9. The reading circuit according to claim 8, characterized in that: In the main sensing stage, WL0 and WL1 remain in the same state as the pre-sensing stage, BLEQ remains at a low level, OC remains at a low level, TSE1 and TSE2 remain at a high level, BSE1 and BSE2 remain at a low level, SAN1 and SAN2 are set to a low level, and SAP1 and SAP2 are set to a high level; If the DRAM storage cell 1 stores 1 and WL0 is at a high level during the main sensing phase, the BLT voltage is pulled to VDD and the BLB voltage drops to 0; If DRAM storage cell 1 stores 0 and WL0 is high in the main sensing phase, the BLT voltage drops to 0 and the BLB voltage is pulled to VDD; If DRAM storage cell 2 stores 1 and WL1 is high in the main sensing phase, the BLB voltage is pulled to VDD and the BLT voltage drops to 0; If DRAM storage cell 2 stores 0 and WL1 is at a high level in the main sensing phase, the BLB voltage drops to 0 and is pulled to VDD.

10. A sensitive amplifier module, characterized in that: A circuit layout of a DRAM sense amplifier based on a bit line switch and capacitive coupling as claimed in claim 1 is adopted.

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