Preparation method of chip packaging structure

Abstract

This application discloses a method for fabricating a chip packaging structure, applicable to the field of semiconductor technology. The method includes providing multiple wafers, each wafer comprising multiple chips; bonding the multiple wafers to form a stacked wafer; dicing the stacked wafers to obtain multiple stacked chips; each stacked chip comprising multiple chips stacked together, each chip originating from a different wafer; the multiple stacked chips including at least one defective chip; and dicing each stacked chip separately to separate the defective chip from each stacked chip. The technical solution of this application aims to improve the utilization rate of qualified chips.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for preparing a chip packaging structure. Background Technology

[0002] In the chip packaging process, there is a problem that qualified chips that have passed the electrical test on the wafer cannot be identified in advance during the wafer-to-wafer bonding process. This leads to the bonding of qualified chips with defective chips, resulting in the waste of qualified chips. Summary of the Invention

[0003] This application proposes a method for preparing a core-encapsulation structure, aiming to improve the utilization rate of qualified cores.

[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0005] On one hand, a method for fabricating a chip packaging structure is proposed. The method includes providing multiple wafers, each wafer including multiple chips, bonding the multiple wafers to form a stacked wafer, cutting the stacked wafers to obtain multiple stacked chips, each stacked chip including multiple chips stacked together, each chip being a chip from a different wafer, the multiple chips of the stacked chip including at least one defective chip, and cutting the multiple stacked chips separately to separate the defective chip from each stacked chip.

[0006] In some embodiments, before bonding multiple wafers, the above preparation method further includes performing electrical tests on the multiple wafers respectively to screen out defective cores from the wafers.

[0007] In some embodiments, after bonding multiple wafers and before dicing the stacked wafers, the above preparation method further includes performing electrical tests on the stacked wafers to screen out defective chips from the stacked wafers.

[0008] In some embodiments, after the stacked wafer is cut, the above preparation method further includes performing electrical tests on the multiple stacked cores to screen out defective cores from the stacked cores.

[0009] In some embodiments, the plurality of stacked granules include a first stacked granule and a second stacked granule. The first stacked granule includes a first defective granule, and the second stacked granule includes a second defective granule. The first defective granule and the second defective granule are granules in the same wafer. The first stacked granule is cut to separate the first defective granule and obtain at least one first granule structure. The first granule structure includes a first surface adjacent to the first defective granule and a second surface distant from the first defective granule. The second stacked granule is cut to separate the second defective granule and obtain at least one second granule structure. The second granule structure includes a third surface adjacent to the second defective granule and a fourth surface distant from the second defective granule. The number of granules in the first granule structure and the second granule structure are equal and correspond one-to-one. The corresponding granules are granules in the same wafer.

[0010] In some embodiments, the above preparation method further includes bonding the second surface of the first core structure and the fourth surface of the second core structure to a carrier, with a gap between the first core structure and the second core structure to form a dielectric layer, the dielectric layer filling the gap, forming a conductive interconnect structure on the first surface of the first core structure and the third surface of the second core structure, removing the carrier, and cutting and separating the first core structure and the second core structure.

[0011] In some embodiments, a melt bonding process is used to bond the second surface of the first core structure and the fourth surface of the second core structure to the substrate, or to bond the second surface of the first core structure and the fourth surface of the second core structure to the substrate.

[0012] In some embodiments, the above-described preparation method further includes bonding the second surface of the first core structure and the fourth surface of the second core structure to the first substrate, with a gap between the first core structure and the second core structure to form a dielectric layer, the dielectric layer filling the gap, forming a protective layer on the first surface of the first core structure and the third surface of the second core structure, bonding the second substrate to the side of the protective layer away from the first core structure and the second core structure, removing the first substrate, forming a conductive interconnect structure on the second surface of the first core structure and the fourth surface of the second core structure, removing the second substrate, and cutting and separating the first core structure and the second core structure.

[0013] In some embodiments, both the first core structure and the second core structure include at least one storage core. After cutting and separating the first core structure and the second core structure, the above preparation method further includes bonding the first core structure to the second core structure.

[0014] In some embodiments, a process selected from laser cutting, mechanical cutting, and plasma etching is used to cut multiple stacked cores separately to separate defective cores from each stacked core.

[0015] The preparation method provided in this application embodiment involves bonding multiple wafers to form a stacked wafer, and then cutting the stacked wafer to obtain multiple stacked cores. Each stacked core includes cores from multiple stacked wafers, that is, each layer of the stacked core includes an independent core. These independent cores include at least one defective core. The defective cores in the multiple stacked cores can be cut and separated by cutting to obtain defective cores and qualified cores with different stacking layers. The qualified cores can be reprocessed and reused by appropriate methods.

[0016] The preparation method provided in this application only requires cutting the stacked cores, which solves the problem of waste of qualified cores caused by bonding qualified cores with defective cores due to the mismatch in core yield at a low cost. Furthermore, it avoids the problem of overall failure of stacked cores due to the presence of defective cores, thereby improving the utilization rate of qualified cores and the packaging yield of core packaging structures.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0019] Figure 1 A flowchart illustrating a method for fabricating a chip packaging structure according to an embodiment of this application;

[0020] Figure 2 for Figure 1 Flowchart of the process steps;

[0021] Figure 3 for Figure 1 A flowchart illustrating the specific implementation process of step S4;

[0022] Figure 4 for Figure 3 A flowchart of the process steps;

[0023] Figure 5 A flowchart illustrating a second method for processing the first core structure and a second core structure, as provided in embodiments of this application;

[0024] Figures 6 to 11 for Figure 5 A flowchart illustrating each step of the process;

[0025] Figure 12 A flowchart for processing the first type of first core structure and the first type of second core structure provided in the embodiments of this application;

[0026] Figures 13-21 for Figure 12 The process flow diagram shows each step. Detailed Implementation

[0027] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0029] In the description of this application, "multiple" means two or more.

[0030] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0031] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "electrical connection" indicates, for example, that two or more components have direct physical or electrical contact, but may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0032] Currently, advanced packaging mainly employs two methods in the fabrication of chip packaging structures: fusion bonding and hybrid bonding.

[0033] Fused bonding requires depositing a film at the bonding interface of the wafers and performing chemical mechanical planarization on the bonding surface to control the surface morphology. However, it can only achieve structural connections and cannot achieve electrical connections between wafers. Subsequently, through-silicon via (TSV) technology is needed to achieve electrical interconnection and outgoing connections between wafers. The process is more complex, and the density of inter-wafer electrical connections in fused bonding is lower than that in hybrid bonding.

[0034] Hybrid bonding enables simultaneous structural and electrical interconnection between wafers. Subsequent electrical connections are achieved simply by linking the upper wafer metal via TSVs, making the process simpler than fused bonding. It also offers higher electrical interconnect density than fused bonding, resulting in superior performance of the final packaged product. However, hybrid bonding requires the use of damascus steel to fabricate the bonding metal plates, demands higher alignment precision during bonding, and involves more complex pre-bonding and bonding processes.

[0035] Currently, advanced packaging is mainly manufactured in fabs. Since advanced packaging technology is relatively outdated compared to fab technology, the process of advanced packaging in fabs is less difficult. In order to maximize compatibility with the conventional processes in fabs, wafer-to-wafer bonding is often used, that is, advanced packaging is done on the whole wafer. The wafer-to-wafer bonding process route is widely used.

[0036] However, in related technologies, wafer-to-wafer bonding packaging methods cannot pre-identify electrically conductive dies on the wafer. This can lead to electrically conductive dies bonding with electrically ineffective dies, causing the overall die packaging structure to fail and resulting in the loss of qualified dies. If the yield on a single wafer is 95%, using wafer-to-wafer bonding, the yield of stacking four wafers is only 81.45%, eight wafers 66.34%, 12 wafers 54.04%, and 16 wafers 44.01%. This significantly reduces the packaging yield of the die packaging structure, resulting in the loss of electrically conductive dies that are opposite to electrically ineffective dies, thus wasting qualified dies.

[0037] To address the aforementioned problems, this application proposes a method for preparing a chip encapsulation structure. Figure 1 A flowchart illustrating a method for fabricating a chip packaging structure for the purposes of this application; Figure 2 for Figure 1 A flowchart of the process.

[0038] like Figure 1 As shown, the preparation method includes the following steps S1 to S4:

[0039] Step S1: Provide multiple wafers, each wafer including multiple chips. Among the multiple chips, there are qualified chips that meet the design requirements and defective chips that do not meet the design requirements. This application's embodiments use a single logic wafer and four dynamic random access memory (DRAM) wafers as examples. The multiple logic chips on the logic wafer can serve as computing units, and the multiple chips on the DRAM wafers can serve as a memory array.

[0040] In some embodiments, before bonding multiple wafers, the above-described fabrication method further includes performing electrical tests on the multiple wafers, namely, a wafer acceptance test (WAT). By setting dicing grooves on the wafers and performing WAT on the wafers, data on the electrical characteristics and process parameters of multiple chips on the wafers are obtained. Then, these data are used to determine whether the multiple chips meet the design requirements. Finally, defective chips that do not meet the design requirements are screened out from the wafers to obtain the accurate location of the defective chips, which facilitates the cutting of defective chips in subsequent processes.

[0041] Step S2: Bond multiple wafers including defective cores. The bonding process can be hybrid bonding or melt bonding. This application embodiment uses hybrid bonding as an example for explanation. The logic wafer and four dynamic random access memory wafers are stacked sequentially by hybrid bonding to form a stacked wafer. Since there are defective cores in multiple wafers, there are also defective cores in the stacked wafer.

[0042] In some embodiments, after bonding multiple wafers to form a stacked wafer, the above-described fabrication method further includes performing an electrical test on the stacked wafer, which is a wafer acceptance test (WAT). By setting dicing grooves on the stacked wafer and performing WAT on the dicing grooves, data on the electrical characteristics and process parameters of multiple chips on the stacked wafer are obtained. Then, based on these data, it is determined whether the multiple chips meet the design requirements. Finally, defective chips that do not meet the design requirements are screened out from the stacked wafer to determine the specific location of the defective chips on the stacked wafer, which facilitates the cutting of defective chips in subsequent processes.

[0043] Step S3: As Figure 2 As shown, the stacked wafers are cut to obtain multiple stacked chips 1. Each stacked chip 1 comprises multiple chips stacked together. Each chip is a chip from one of the multiple different wafers provided in step S1. Specifically, along the Z direction, the stacked chip 1 comprises multiple layers, with only one independent chip per layer. The chips in each layer originate from different wafers and are different chips in total. The multiple chips in the stacked chip 1 include at least one defective chip; that is, there may be one or more defective chips among the multiple chips in the stacked chip 1. This embodiment of the application uses a stacked chip 1 comprising a logic chip 11, a first storage chip 12, a second storage chip 13, a third storage chip 14, and a fourth storage chip 15, with the second storage chip 13 being a defective chip, as an example. The above five chips are arranged as follows... Figure 2 The stacking method shown can form near memory computing (NMC) chips.

[0044] In some embodiments, after dicing the stacked wafer, the above-described fabrication method further includes performing electrical tests on the multiple stacked cores 1, wherein the electrical tests are wafer acceptance tests (WAT). By performing WAT on the stacked cores 1 respectively, data on the electrical characteristics and process parameters of the multiple cores in the stacked cores 1 are obtained. Then, based on these data, it is determined whether the multiple cores meet the design requirements. Finally, defective cores that do not meet the design requirements are screened out from the stacked wafer to determine the specific location of the defective cores in the stacked cores 1, which facilitates the dicing of defective cores in subsequent processes.

[0045] Step S4: As Figure 3 As shown, multiple stacked cores 1 are cut separately to separate defective cores from each stacked core 1. Specifically, the near-memory computing core 1 is cut to separate the second storage core 13 (defective core). For example, the process of cutting the multiple stacked cores 1 separately can employ any of the following processes: laser cutting, mechanical cutting, or plasma cutting, to separate the defective cores from the multiple stacked cores 1. The process of separating defective cores is simple and easy to implement. The cutting process can be selected based on factors such as the thickness and material of the stacked cores 1, resulting in high process feasibility.

[0046] The preparation method provided in this application embodiment involves bonding multiple wafers to form a stacked wafer, and cutting the stacked wafer to obtain multiple stacked cores 1. Each stacked core 1 includes cores from multiple stacked wafers, that is, each layer of the stacked core 1 includes an independent core. These independent cores include at least one defective core. The defective cores in the multiple stacked cores 1 can be cut and separated by cutting to obtain defective cores and qualified cores with different stacking layers. The qualified cores can be reprocessed and reused by appropriate methods.

[0047] The embodiments provided in this application solve the problem of wasted qualified chips due to bonding between qualified and defective chips caused by chip yield mismatch at a lower cost by simply cutting the stacked chip 1. This improves the utilization rate of qualified chips. Furthermore, it avoids the problem of overall failure of the stacked chip 1 due to the presence of defective chips, thus improving the packaging yield of the chip packaging structure.

[0048] Figure 3 for Figure 1 A flowchart illustrating the specific implementation process of step S4; Figure 4 for Figure 3 A flowchart of the process steps; Figure 5 A flowchart illustrating a second method for processing the first core structure and a second core structure, as provided in embodiments of this application; Figures 6 to 11 for Figure 5 A flowchart illustrating each step of the process; Figure 12 A flowchart for processing the first type of first core structure and the first type of second core structure provided in the embodiments of this application; Figures 13-21 for Figure 12 The process flow diagram shows each step.

[0049] In some embodiments, the plurality of stacked cores 1 include a first stacked core and a second stacked core. The first stacked core includes a first defective core, and the second stacked core includes a second defective core. The first defective core and the second defective core are cores in the same wafer, that is, the position of the first defective core in the first stacked core is the same as the position of the second defective core in the second stacked core. It can be understood that the first stacked core and the second stacked core have the same structure, wherein the number of cores included is equal and corresponds one-to-one, and the corresponding cores are cores in the same wafer. The specific process of cutting the plurality of stacked cores 1 in step S4 above is as follows: Figure 3 As shown, the steps include S401 to S402:

[0050] Step S401: As Figure 4 As shown, the first stacked chip is cut to separate the first defective chip and obtain at least one first chip structure A. In the embodiment provided in this application, the second memory chip 13 is a defective chip. After cutting the defective chip, two types of first chip structures A are obtained. The first type of first chip structure A1 includes a logic chip 11 and a first memory chip 12, and the second type of first chip structure A2 includes a third memory chip 14 and a fourth memory chip 15. The first chip structure A includes a first surface 101 close to the second memory chip 13 and a second surface 102 away from the second memory chip 13.

[0051] For the first type of first chip structure A1, the first surface 101 is the side of the first memory chip 12 that is closer to the second memory chip 13, and the second surface 102 is the side of the logic chip 11 that is farther away from the second memory chip 13. For the second type of first chip structure A2, the first surface 101 is the side of the third memory chip 14 that is closer to the second memory chip 13, and the second surface 102 is the side of the fourth memory chip 15 that is farther away from the second memory chip 13.

[0052] Step S402: Cut the second stacked core to separate the second defective core and obtain at least one second core structure. Since the second stacked core has the same structure as the first stacked core, therefore... Figure 4 As shown, cutting the second stacked chips yields two second chip structures B identical to the first stacked structure. The first second chip structure B1 includes a logic chip 11 and a first memory chip 12, and the second second chip structure B2 includes a third memory chip 14 and a fourth memory chip 15. The second chip structure B includes a third surface 103 near the second defective chip and a fourth surface 104 away from the second defective chip. It is understood that in this embodiment, the first first chip structure A1 and the first second chip structure B1 are identical, and the second first chip structure A2 and the second second chip structure B2 are identical.

[0053] Similarly, for the first type of second chip structure B1, the third surface 103 is the side of the first memory chip 12 that is closer to the second memory chip 13, and the fourth surface 102 is the side of the logic chip 11 that is farther away from the second memory chip 13. For the second type of second chip structure B2, the third surface 103 is the side of the third memory chip 14 that is closer to the second memory chip 13, and the fourth surface 104 is the side of the fourth memory chip 15 that is farther away from the second memory chip 13.

[0054] In steps S401 and S402 above, after cutting and separating the defective cores in the first stacked cores and the second stacked cores, qualified first core structure A and second core structure B are obtained, which avoids the waste of qualified cores, improves the utilization rate of qualified cores, and reduces the manufacturing cost of the core packaging structure.

[0055] In some embodiments, after obtaining the first core structure A and the second core structure B, for example, the second first core structure A2 and the second second core structure B2 are first processed, such as... Figure 5 As shown, the above preparation method further includes the following steps S5 to S8:

[0056] Step S5: As Figure 6 As shown, the second surface 102 of the second type of first core structure A2 and the fourth surface 104 of the second type of second core structure B2 are bonded to the substrate 2, with a gap 16 between the second type of first core structure A2 and the second type of second core structure B2. Since the second type of first core structure A2 and the second type of second core structure B2 have the same structure, with the plane XY of the substrate 2 as the reference, along the Z direction, after they are bonded to the first substrate 21, their heights are equal. Equal heights facilitate the subsequent filling of the gap 16 with a dielectric layer.

[0057] In some embodiments, in addition to the second first core structure A2 and the second second core structure B2, other core structures with the same structure as these two core structures can also be bonded together with the second first core structure A2 and the second second core structure B2 on the carrier 2. With the plane XY on which the carrier 2 is located as a reference, the height of the above-mentioned multiple core structures is the same along the direction Z.

[0058] In some embodiments, see Figure 6A fusion bonding process is used to bond the second surface 102 of the first core structure A and the fourth surface 104 of the second core structure B to the carrier 2. Fusion bonding only achieves a structural connection between the carrier 2 and the core structure, thus avoiding the problems of metal contamination and long processing time associated with electrical connections. The carrier 2 can be removed subsequently using wet grinding chemical mechanical polishing (CMP). Alternatively, the second surface 102 of the first core structure A and the fourth surface 104 of the second core structure B can be bonded to the carrier 2. For example, the carrier 2 can be a glass carrier, bonded to the core structure with adhesive. The carrier 2 can be removed subsequently using laser debonding, and the removed carrier 2 can be reused. Both the fusion bonding and adhesive bonding processes described above are relatively simple and easier to implement.

[0059] Step S6: As Figure 7 As shown, a dielectric layer 3 is formed on the first surface 101 of the second type of first core structure A2 and the third surface 103 of the second type of second core structure B2 until the gap 16 is filled, and then as... Figure 8 As shown, the dielectric layer 16 is planarized by physical grinding and chemical mechanical polishing, so that the dielectric layer 16 covers the first surface 101, the third surface 103 and the gap 16.

[0060] Step S7: As Figure 9 As shown, conductive interconnect structures 4 are formed on the second surface 102 of the second type of first core structure A2 and the fourth surface 104 of the second type of second core structure B2 to realize electrical connection and signal transmission between the second type of first core structure A2 and the second type of second core structure B2 and other structures. For example, the conductive interconnect structure 4 includes aluminum pads 41, a passivation layer 42, and a metal layer 43.

[0061] Step S8: As Figure 10 As shown, the second type of first core structure A2 and the second type of second core structure B2 are debonded to the carrier 2, the carrier 2 is removed, and then... Figure 11 As shown, using laser cutting, mechanical cutting, plasma etching, or other methods, the second type of first chip structure A2 and the second type of second chip structure B2 are separated through the dielectric layer 16 to obtain the second type of first chip structure A2 and the second type of second chip structure B2 stacked together with the third memory chip 14 and the fourth memory chip 15. This chip structure can be used as a stacked chip for High Bandwidth Memory (HBM), achieving high bandwidth and low power consumption through the storage chips stacked perpendicularly along the Z direction.

[0062] In some embodiments, the preparation method described in this application can form a stacked HBM chip with two layers of memory chips. In the same production line, each chip can adopt the same design, photomask, process flow, and face-to-back bonding method similar to that of the third memory chip 14 and the fourth memory chip 15 to realize HBM stacked chips with different numbers of layers such as 2, 4, 6, 8, 12, and 16 layers, thereby significantly reducing the production cost of HBM. That is, by using the above process flow, low-cost preparation of chips with multiple stacked layers can be achieved to improve the utilization rate of qualified chips.

[0063] In some embodiments, after obtaining the first core structure A and the second core structure B, for example, the first core structure A1 and the first second core structure B1 are processed, such as... Figure 12 As shown, the above preparation method further includes the following steps S5 to S10:

[0064] Step S5: As Figure 13 As shown, the second surface 102 of the first core structure A1 and the fourth surface 104 of the second core structure B1 are bonded to the first substrate 21. In some embodiments, the second surface 102 of the first core structure A1 and the fourth surface 104 of the second core structure B1 can be connected to the first substrate 21 by fusion bonding or adhesive bonding, which is a relatively simple and easy-to-implement process. There is a gap 16 between the first core structure A1 and the second core structure B1. Since the first core structure A1 and the second core structure B1 have the same structure, with the plane XY on which the first substrate 21 is located as the reference, along the Z direction, the two are bonded to the first substrate 21 at equal heights. Equal heights facilitate the subsequent filling of the gap 16 with a dielectric layer.

[0065] In some embodiments, in addition to the first core structure A1 and the first second core structure B1, other core structures with the same structure as these two core structures may also be bonded together with the first core structure A1 and the first second core structure B1 on the substrate 2. With the plane XY on which the substrate 2 is located as a reference, the height of the above-mentioned multiple core structures is the same along the direction Z.

[0066] Step S6: As Figure 14 As shown, a dielectric layer 3 is formed on the first surface 101 of the first core structure A1 and the third surface 103 of the first second core structure B1 until the gap 16 is filled, and then as... Figure 15 As shown, the dielectric layer 3 is planarized by physical grinding and chemical mechanical polishing, exposing the first surface 101 and the third surface 103.

[0067] Step S7: As Figure 16 As shown, a protective layer 31 is formed on the first surface 101 of the first core structure A1 and the third surface 103 of the first core structure B1. The protective layer 31 is used to protect the first surface 101 of the first core structure A1 and the third surface 103 of the first core structure B1.

[0068] Step S8: As Figure 17 As shown, on the side of the protective layer 31 away from the first core structure A1 and the first second core structure B1, the second carrier 22 is bonded. In some embodiments, the first surface 101 of the first core structure A1 and the first second core structure B1 can be connected to the second carrier 22 by fusion bonding or adhesive bonding, which is a simpler and easier process to implement. Then, as... Figure 18 As shown, the first substrate 21 is removed. Correspondingly, the first substrate 21 connected by fusion bonding can be removed by wet grinding and chemical mechanical polishing, and the first substrate 21 bonded by adhesive can be removed by laser debonding.

[0069] Step S9: As Figure 19 As shown, a dielectric layer 3 is first used to fill the second surface 102 of the first core structure A1 and the fourth surface 104 of the first second core structure B1. Then, a conductive interconnect structure 4 is formed on the side of the dielectric layer 3 away from the second surface 102 and the fourth surface 104 to realize the electrical connection and signal transmission between the first core structure A1 and the first second core structure B1 and other structures. For example, the conductive interconnect structure 4 includes an aluminum pad 41, a passivation layer 42, and a metal layer 43.

[0070] Step S10: As Figure 20 As shown, the second substrate 22 is removed. The second substrate 22, which is fused together, can be removed by wet abrasive chemical mechanical polishing. The second substrate 22, which is bonded with adhesive, can be removed by laser debonding. Then, as... Figure 21 As shown, using laser cutting, mechanical cutting, plasma etching, or other methods, the first first chip structure A1 and the first second chip structure B1 are separated through the dielectric layer 16 to obtain the first first chip structure A1 and the first second chip structure B1 stacked with the logic chip 11 and the first memory chip 12. This chip structure can be used as a stacked chip for near-memory computing (NMC). The logic chip 11 and the first memory chip 12 can be stacked vertically together, and high-speed interconnection can be achieved through through-silicon via (TSV) technology to improve the utilization rate of qualified chips.

[0071] In the embodiments provided in this application, the defective chip is the second storage chip 13. After the above-described process, a chip consisting of a stacked third storage chip 14 and a fourth storage chip 15, as well as a chip consisting of a stacked logic chip 11 and a first storage chip 12, are obtained. For example, when the defective chip is the first storage chip 12 or the third storage chip 14, a single-layer chip such as the logic chip 11 or the fourth storage chip 15 can also be obtained. The preparation method provided in the embodiments of this application can also process single-layer chips, realizing the preparation of stacked chips with multiple layers, and further improving the utilization rate of qualified chips.

[0072] In some embodiments, both the first core structure A and the second core structure B include at least one memory core. In the embodiments of this application, the first first core structure A1 and the first second core structure B1 each include one first memory core 12, and the second first core structure A2 and the second second core structure B2 each include one third memory core 14 and one fourth memory core 15. After cutting and separating the first core structure A and the second core structure B, the above preparation method further includes bonding the first core structure A to the second core structure B. For example, the first first core structure A1 and the first second core structure B1 can be bonded, or the second first core structure A2 and the second second core structure B2 can be bonded, or the first first core structure A1 and the second first core structure A2 can be bonded, or the first second core structure B1 and the second second core structure B2 can be bonded, etc. After bonding the first core structure A to the second core structure B, more diverse stacked cores can be obtained.

[0073] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for preparing a chip encapsulation structure, characterized in that, include: Provide multiple wafers, each wafer comprising multiple dies; The multiple wafers are bonded together to form a stacked wafer; The stacked wafers are cut to obtain multiple stacked granules; the stacked granules include multiple granules stacked together, each granule being a granule from a different wafer, and the multiple granules of the stacked granules include at least one defective granule; The multiple stacked core particles are cut separately to separate the defective core particles in each stacked core particle; The plurality of stacked granules include a first stacked granule and a second stacked granule. The first stacked granule includes a first defective granule, and the second stacked granule includes a second defective granule. The first defective granule and the second defective granule are granules in the same wafer. The first stacked core is cut to separate the first defective core and obtain at least one first core structure, the first core structure including a first surface close to the first defective core and a second surface away from the first defective core. The second stacked core is cut to separate the second defective core and obtain at least one second core structure. The second core structure includes a third surface close to the second defective core and a fourth surface away from the second defective core. The number of cores in the first core structure and the second core structure are equal and correspond one-to-one. The corresponding cores are cores in the same wafer. The first chip structure is bonded to the second chip structure, and both the first chip structure and the second chip structure include at least one memory chip.

2. The preparation method according to claim 1, characterized in that, Before bonding the plurality of wafers, the fabrication method further includes: Electrical tests are performed on the multiple wafers respectively to screen out the defective chips.

3. The preparation method according to claim 1, characterized in that, After bonding the plurality of wafers and before dicing the stacked wafers, the fabrication method further includes: Electrical tests are performed on the stacked wafers to screen out the defective chips.

4. The preparation method according to claim 1, characterized in that, After dicing the stacked wafers, the fabrication method further includes: Electrical tests are performed on the multiple stacked cores to screen out the defective cores.

5. The preparation method according to claim 1, characterized in that, The preparation method further includes: The second surface of the first core structure and the fourth surface of the second core structure are bonded to the substrate, and there is a gap between the first core structure and the second core structure. A dielectric layer is formed, which fills the gap; Conductive interconnect structures are formed on the first surface of the first core structure and on the third surface of the second core structure; Remove the carrier and cut and separate the first core structure and the second core structure.

6. The preparation method according to claim 5, characterized in that, A fusion bonding process is used to bond the second surface of the first core structure and the fourth surface of the second core structure to the carrier. or, The second surface of the first core structure and the fourth surface of the second core structure are bonded to the carrier.

7. The preparation method according to claim 1, characterized in that, The preparation method further includes: The second surface of the first core structure and the fourth surface of the second core structure are bonded to the first substrate, and there is a gap between the first core structure and the second core structure. A dielectric layer is formed, which fills the gap; A protective layer is formed on the first surface of the first core structure and on the third surface of the second core structure; A second substrate is bonded to the side of the protective layer away from the first and second core structures, and the first substrate is removed. Conductive interconnect structures are formed on the second surface of the first core structure and on the fourth surface of the second core structure; Remove the second substrate and cut and separate the first core structure and the second core structure.

8. The preparation method according to claim 1, characterized in that, The multiple stacked core particles are cut using one of the following processes: laser cutting, mechanical cutting, or plasma etching cutting, in order to separate the defective core particles from each stacked core particle.

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