Flip chip packaging method and flip chip

Abstract

The invention relates to the technical field of chip packaging, in particular to a flip chip packaging method and a flip chip. The flip chip packaging method comprises the steps that a chip and a substrate are provided, the active surface of the chip is attached to the upper surface of the substrate, a solder is arranged on the passive surface of the chip, and components located on the two sides of the chip are arranged on the upper surface of the substrate; retaining walls are arranged on the upper surface of the substrate and between the chip and the component; uniformly coating an adhesive on the top surface of the retaining wall; welding a radiating fin on the passive surface of the chip by using the solder, wherein the lower surface of the radiating fin is in contact with the adhesive; and the adhesive is cured, so that the adhesive and the retaining wall form a fence. When the flip chip is manufactured according to the method, the problem that the short circuit failure phenomenon occurs to the element due to the fact that the metal solder is splashed to the element when a product shakes or gas flows is solved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a flip chip packaging method and a flip chip. Background Art

[0002] In the traditional FCBGA process, the heat dissipation structure usually adopts the format of planar heat sink-thermal conductive adhesive-chip. With the development of thermal conductive materials, metal solder with high heat dissipation performance has gradually begun to be widely used in TIM1, including FCBGA, FCLGA and other related heat sink products.

[0003] However, metal solder is a conductor and will melt during high-temperature processes. If the liquid solder splashes onto components due to product shaking or gas flow, it will cause the components to short-circuit and fail. Summary of the invention

[0004] The embodiments of the present application at least provide a flip chip packaging method and a flip chip, which are used to improve the problem that metal solder splashes onto components when the product shakes or gas flows, causing short circuit failure of the components.

[0005] In a first aspect, an embodiment of the present application provides a flip chip packaging method, comprising:

[0006] A chip and a substrate are provided, wherein the active surface of the chip is mounted on the upper surface of the substrate, solder is provided on the passive surface of the chip, and components located on both sides of the chip are provided on the upper surface of the substrate;

[0007] Disposing a retaining wall on the upper surface of the substrate and between the chip and the components;

[0008] Evenly apply adhesive on the top surface of the retaining wall;

[0009] Using the solder to weld a heat sink to the passive surface of the chip, the lower surface of the heat sink is in contact with the adhesive;

[0010] The adhesive is cured so that the adhesive and the retaining wall form a enclosure.

[0011] In an optional embodiment, the retaining wall is formed by a solid structure bonded to the upper surface of the substrate.

[0012] In an optional implementation, the retaining wall is formed by curing DAM glue.

[0013] In an optional implementation, there is a gap between the retaining wall and the chip and the components.

[0014] In an optional implementation, the top surface of the retaining wall is not higher than the passive surface of the chip.

[0015] In an optional implementation, the top surface of the adhesive is higher than the top surface of the solder.

[0016] In an optional implementation, the height of the adhesive is not less than 200 μm.

[0017] In an optional embodiment, the retaining wall is arranged throughout the entire length.

[0018] In an optional embodiment, the enclosure is a U-shaped structure that surrounds the sides and both ends of the component.

[0019] In a second aspect, an embodiment of the present application further provides a flip chip, which is manufactured using the flip chip packaging method described in any one of the first aspects.

[0020] The above technical solution of the present application has the following beneficial technical effects:

[0021] The flip chip packaging method and flip chip of the embodiment of the present application are provided with enclosures on the upper surface of the substrate and between the chip and the components. The enclosures can protect the components and prevent the solder from flowing outward and splashing onto the components under the action of negative pressure or when the product shakes after melting, thereby avoiding the phenomenon of short circuit failure of the components. In addition, since the enclosure includes a retaining wall and an adhesive, the adhesive is located on the top surface of the retaining wall and contacts the heat sink. In this way, on the one hand, the gap between the enclosure and the heat sink can be filled to enhance the protection effect on the components, and on the other hand, the fluidity and elasticity of the adhesive can be used to compensate for the process errors between the components.

[0022] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solutions of the present application. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0024] Figures 1 to 8 A flip chip packaging process provided by an embodiment of the present application is shown;

[0025] Reference numerals:

[0026] 1. Chip; 2. Substrate; 3. Components; 4. Solder; 5. Heat sink; 6. Binder; 7. Enclosure; 71. Retaining wall; 72. Adhesive. DETAILED DESCRIPTION

[0027] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0028] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0029] The term "first" or "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In the description of this application, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0030] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] refer to Figures 1 to 8 , shows a flip chip packaging method, the method comprising the following steps:

[0033] Step 10: Provide a chip 1 and a substrate 2. The active surface of the chip 1 is mounted on the upper surface of the substrate 2. The passive surface of the chip 1 is provided with solder 4. The upper surface of the substrate 2 is provided with components 3 located on both sides of the chip 1.

[0034] Step 20 : Setting a retaining wall 71 on the upper surface of the substrate 2 and between the chip 1 and the component 3 .

[0035] Step 30: evenly apply adhesive 72 on the top surface of retaining wall 71.

[0036] Step 40 , solder the heat sink 5 to the passive surface of the chip 1 using solder 4 , and the lower surface of the heat sink 5 is attached to the upper surface of the substrate 2 through the adhesive 6 , and the lower surface of the heat sink 5 is in contact with the adhesive 72 .

[0037] Step 50 , curing the adhesive 72 , so that the adhesive 72 and the retaining wall 71 form a fence 7 .

[0038] The packaging method of the embodiment of the present application includes the step of setting a barrier 7 on the upper surface of the substrate 2 and between the chip 1 and the component 3. The barrier 7 can protect the component 3 and prevent the solder 4 from flowing outward and splashing onto the component 3 under the action of negative pressure or when the product shakes after melting, so as to avoid the short circuit failure of the component 3. In addition, since the barrier 7 includes a retaining wall 71 and an adhesive 72, the adhesive 72 is located on the top surface of the retaining wall 71 and contacts the heat sink 5. In this way, on the one hand, the gap between the barrier 7 and the heat sink 5 can be filled to improve the protection effect on the component 3, and on the other hand, the fluidity and elasticity of the adhesive can be used to compensate for the process errors between the components.

[0039] In step 10, the active surface of the chip 1 is directly connected to the pads on the substrate 2 through solder balls (usually tin-lead alloy, lead-free solder 4 or other conductive materials). Specifically, the solder balls are located on the pads of the chip 1, which play the role of electrical connection and mechanical fixation. The size and distribution of the solder balls are usually determined by the design of the chip 1 to ensure that each solder ball can be accurately aligned with the corresponding pad on the substrate 2.

[0040] In step 10, the solder 4 is a metal solder 4, which is mainly used to solder the heat sink 5 to the passive surface of the chip 1. Of course, in other embodiments, the solder 4 can also be replaced by thermal conductive glue or thermal conductive paste.

[0041] In step 10, the components 3 on the substrate 2 may be capacitors, such as decoupling capacitors or bypass capacitors, whose main functions are to stabilize the power supply voltage, filter noise, and provide instantaneous current requirements to ensure the stability and reliability of the chip 1 when running at high speed. However, the embodiments of the present application do not make any limitation to this.

[0042] In step 10, the number of components 3 on the substrate 2 may be one or more, and the components 3 may be distributed in different ways. Figure 1 As shown, this embodiment shows that there are multiple components 3, and the multiple components 3 are symmetrically distributed about the center line of the chip 1.

[0043] In step 20 , a retaining wall 71 is disposed between the chip 1 and the component 3 , which mainly serves as a basic structure of the enclosure 7 .

[0044] In step 20, the retaining wall 71 can be formed by curing DAM glue. In this way, it can be suitable for the small and lightweight design of the packaged chip 1. In addition, the cost of DAM glue is low, and the coating and curing process of DAM glue is relatively simple, which can be carried out by dispensing, spraying or screen printing, etc., which is suitable for automated production. Preferably, in an embodiment of the present application, the retaining wall 71 can be formed by curing DAM glue with a high thixotropic coefficient. However, the embodiment of the present application does not impose any restrictions on this. In other embodiments, the retaining wall 71 can also be formed by a solid structure bonded to the upper surface of the substrate 2, such as a solid structure made of materials such as gold, copper, aluminum, and tungsten.

[0045] In step 20, there is a gap between the retaining wall 71 and the chip 1 and the components 3, that is, the retaining wall 71 does not contact the chip 1 and the components 3. In this way, the reliability and functionality of the package can be ensured, and problems caused by excessive contact can be avoided. For example: 1. The DAM glue itself may be an insulating material or have a certain conductivity. If the DAM glue directly contacts the pads or other conductive components of the chip 1, it may cause a short circuit or poor electrical connection. 2. The pads on the surface of the chip 1 are key areas for electrical connection with the substrate 2 or other components. If the DAM glue directly contacts these pads, it may cover the pads, affecting the subsequent welding or bonding process, causing the electrical connection to fail. 3. The coefficients of thermal expansion (CTE) of the chip 1, substrate 2 and DAM glue are usually different. When the temperature changes, the expansion or contraction rates between different materials are different, which may generate mechanical stress. If the DAM glue is in direct contact with the chip 1, this stress may be transmitted to the chip 1, causing cracks in the chip 1 or solder joint failure. 4. Although DAM glue has a certain thermal conductivity, its thermal conductivity is usually not as good as that of metal materials. If DAM glue directly contacts the chip 1, it may affect the heat conduction efficiency and cause poor heat dissipation of the chip 1. Therefore, setting a gap between the retaining wall 71 and the chip 1 and the components 3 can ensure the reliability and functionality of the package and avoid problems caused by excessive contact.

[0046] In step 20, the top surface of the retaining wall 71 is not higher than the passive surface of the chip 1, that is, the height of the retaining wall 71 is not greater than the thickness of the chip 1. In this way, it is possible to avoid the existence of a gap between the solder 4 and the heat sink 5, which affects the heat dissipation effect. Specifically, when mounting the heat sink 5, the adhesive 72 is compressed and deformed so that the bottom surface of the heat sink 5 can contact the solder 4. Since the top surface height of the retaining wall 71 will limit the mounting height of the heat sink 5, when the top surface of the solder 4 is lower than the top surface of the retaining wall 71 after melting, the retaining wall 71 will support the heat sink 5 so that it cannot contact the solder 4. In this case, there will be a gap between the heat sink 5 and the solder 4, which will increase the thermal resistance and affect the heat dissipation effect. Therefore, setting the top surface of the retaining wall 71 not higher than the passive surface of the chip 1 can avoid the existence of a gap between the solder 4 and the heat sink 5, which affects the heat dissipation effect. In this embodiment, the top surface of the retaining wall 71 is flush with the passive surface of the chip 1.

[0047] In step 30, adhesive 72 is disposed on the top surface of retaining wall 71, which is mainly used to increase the height. The overall coating height of adhesive 72 can be selected according to actual conditions. In this embodiment, the overall coating height of adhesive 72 is not less than 200 μm.

[0048] In step 30, the adhesive 72 can be made of the same glue as the adhesive 6 of the heat sink 5. For example, the adhesive 72 and the adhesive 6 of the heat sink 5 are both made of AD glue. In this way, the adhesive 72 and the adhesive 6 of the heat sink 5 can be applied at one time, thereby reducing the number of glue dispensing times, which is beneficial to improving the chip 1 packaging efficiency.

[0049] In step 30, the top surface of the adhesive 72 is higher than the top surface of the solder 4. In this way, it is possible to ensure that the adhesive 72 and the bottom surface of the heat sink 5 are in full contact, avoiding the appearance of a gap that affects the protective effect. Specifically, when mounting the heat sink 5, if the top surface of the solder 4 is higher than the top surface of the adhesive 72, the adhesive 72 may not be able to contact the bottom surface of the heat sink 5, resulting in a gap between the adhesive 72 and the heat sink 5. The gap may cause the liquid solder 4 to pass through and splash onto the component 3, causing the component 3 to short-circuit and fail. Therefore, setting the top surface of the adhesive 72 higher than the top surface of the solder 4 can avoid the appearance of a gap that affects the protective effect.

[0050] In step 40, the bottom surface of the heat sink 5 is attached to the upper surface of the substrate 2 through the adhesive 6. In the specific setting, the adhesive 6 can be applied to the bottom surface of the heat sink 5 first, or the adhesive 6 can be applied to the upper surface of the substrate 2 first, and then the heat sink 5 and the substrate 2 are attached together.

[0051] In step 40, the adhesive 6 of the heat sink 5 and the adhesive 72 of the enclosure 7 can be cured simultaneously. In this way, the curing steps can be reduced, which is conducive to improving the chip 1 packaging efficiency.

[0052] In some embodiments, the enclosure 7 should be arranged throughout the entire length, that is, the retaining wall 71 and the adhesive 72 are arranged throughout the entire length. In this way, a complete enclosure can be formed to prevent the liquid solder 4 from passing through the enclosure 7 and splashing onto the components 3. In addition, such an arrangement also allows the enclosure 7 to provide a continuous conduction path for heat, ensuring uniform heat distribution, avoiding local hot spots, and improving heat dissipation efficiency.

[0053] In some embodiments, the enclosure 7 may be a U-shaped structure, which surrounds the sides and both ends of the component 3, that is, the enclosure 7 surrounds both ends of the component 3 and the side facing the chip 1. In this way, the liquid solder 4 can be prevented from bypassing the enclosure 7 and splashing to both sides of the component 3, which is conducive to improving the protection effect of the enclosure 7. Of course, the shape of the enclosure 7 can be selected according to actual conditions and is not limited to the above-mentioned method.

[0054] In some embodiments, the thickness of the enclosure 7 is not less than 50 μm. Of course, the thickness of the enclosure 7 can be selected according to actual conditions. For example, the thickness of the enclosure 7 can be between 50 μm and 200 μm. Selecting a thinner enclosure 7 can reduce thermal resistance, improve heat conduction efficiency, and help reduce the temperature of the chip 1. In high-reliability applications, the thickness of the enclosure 7 can be increased to between 150 μm and 300 μm to ensure that the package can work stably for a long time in extreme environments. In high-power applications, the thickness of the enclosure 7 can be increased to between 200 μm and 500 μm, which can provide better stress buffering and mechanical protection. At the same time, the thicker enclosure 7 can help absorb more heat and prevent the chip 1 from overheating. Of course, in order to further improve the heat absorption effect and stability of the enclosure 7, the thickness of the enclosure 7 can be increased to more than 500 μm. Preferably, in the embodiment of the present application, the thickness of the enclosure 7 can be between 600 μm and 800 μm.

[0055] The embodiment of the present application also provides a flip chip 1, which is made by the above-mentioned flip chip 1 packaging method. During the packaging process, a barrier 7 is set on the upper surface of the substrate 2 and between the chip 1 and the component 3. The barrier 7 can protect the component 3 and prevent the solder 4 from flowing outward and splashing onto the component 3 under the action of negative pressure or when the product shakes after melting, thereby avoiding the short circuit failure of the component 3. In addition, since the barrier 7 includes a retaining wall 71 and an adhesive 72, the adhesive 72 is located on the top surface of the retaining wall 71 and contacts the heat sink 5. In this way, on the one hand, the gap between the barrier 7 and the heat sink 5 can be filled to enhance the protection effect on the component 3, and on the other hand, the fluidity and elasticity of the adhesive can be used to compensate for the process errors between the components.

[0056] Since a retaining wall 71 is provided on the upper surface of the substrate 2 and between the chip 1 and the component 3, the solder 4 can be prevented from flowing outwards and splashing onto the component 3 under the action of negative pressure or when the product shakes after melting, thereby protecting the component 3 and avoiding short-circuit failure of the component 3.

[0057] like Figure 8As shown, the flip chip 1 includes a substrate 2, a chip 1, a heat sink 5 and a baffle 7. A plurality of components 3 are arranged on the upper surface of the substrate 2, and the plurality of components 3 are symmetrically distributed on both sides of the upper surface of the substrate 2. The chip 1 is located on the upper surface of the substrate 2 and between the plurality of components 3, and the active surface of the chip 1 is mounted on the upper surface of the substrate 2. The heat sink 5 is located above the substrate 2, and the lower surface of the heat sink 5 is bonded and fixed to the upper surface of the substrate 2 by an adhesive 6, and the lower surface of the heat sink 5 is connected to the passive surface of the chip 1 (the side of the chip 1 facing away from the substrate 2) by solder 4. The baffle 7 is located on the upper surface of the substrate 2 and between the chip 1 and the components 3. The baffle 7 includes a baffle wall 71 and an adhesive 72. The baffle wall 71 is arranged on the upper surface of the substrate 2, and the adhesive 72 is arranged on the top surface of the baffle wall 71, and the top surface of the adhesive 72 is in contact with the bottom surface of the heat sink 5.

[0058] One or more embodiments of this specification are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of this application.

[0059] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A flip chip packaging method, characterized in that: include: A chip and a substrate are provided, wherein the active surface of the chip is mounted on the upper surface of the substrate, solder is provided on the passive surface of the chip, and components located on both sides of the chip are provided on the upper surface of the substrate; Disposing a retaining wall on the upper surface of the substrate and between the chip and the components; Evenly apply adhesive on the top surface of the retaining wall; Using the solder to weld a heat sink to the passive surface of the chip, the lower surface of the heat sink is in contact with the adhesive; The adhesive is cured so that the adhesive and the retaining wall form a enclosure.

2. The method according to claim 1, characterized in that The retaining wall is formed by a solid structure bonded to the upper surface of the substrate.

3. The method according to claim 1, characterized in that The retaining wall is formed by curing DAM glue.

4. The method according to claim 3, characterized in that There are intervals between the retaining wall and the chip and the components.

5. The method according to claim 3, characterized in that: The top surface of the retaining wall is not higher than the passive surface of the chip.

6. The method according to claim 1, characterized in that The adhesive top surface is higher than the solder top surface.

7. The method according to claim 1, characterized in that The height of the adhesive is not less than 200 μm.

8. The method according to claim 1, characterized in that: The enclosure is arranged throughout the entire length.

9. The method according to claim 1, characterized in that: The enclosure is a U-shaped structure, which surrounds the side surfaces and both ends of the component.

10. A flip chip, characterized in that: The flip chip packaging method is used to manufacture the device.

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