Semiconductor element packaging structure and preparation method thereof

Abstract

According to the semiconductor element packaging structure and the preparation method thereof, the copper pattern group and the circuit wiring layer are formed in a printing or electroplating mode, so that thick copper with the thickness exceeding 40 microns can be obtained on the two sides of the chip, the limitation that the thick copper with the thickness exceeding 40 microns cannot be prepared through the technology in the prior art is broken through, and the production efficiency is improved. And the heat dissipation effect is also improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor element packaging structure and a preparation method thereof. Background Art

[0002] In the current semiconductor component packaging structure, when there are pins on both sides of the chip, thick copper needs to be provided on both sides of the chip for heat dissipation. However, due to process limitations, the thickness of the thick copper in the current packaging structure is less than 40μm, and the material used for the existing thick copper is copper alloy, which has poor heat dissipation effect. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor element packaging structure and a preparation method thereof, which can break through the 40μm thickness limit of heat dissipation metal and improve the heat dissipation effect.

[0004] In order to solve the above problems, the present invention provides a method for preparing a semiconductor element packaging structure, comprising the following steps:

[0005] Establishing at least one gap-arranged copper pattern group on the temporary substrate by printing or electroplating, each of the copper pattern groups comprising a gap-arranged conductive component group and a first connecting component;

[0006] A chip is attached to each of the first connecting components, each of the chips has a front side and a back side, and each of the chips has at least one pin on the front side and the back side, the front side is arranged toward the first connecting component, and all the pins on the front side are electrically connected to the first connecting component;

[0007] forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, and the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side;

[0008] A circuit wiring layer is formed on the surface of the first plastic packaging layer close to the back side by printing or electroplating, and the circuit wiring layer electrically connects all the pins of each chip located on the back side and the conductive component group at the same time, so that all the pins of each chip located on the back side are led to the front side through the conductive component group;

[0009] forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the circuit wiring layer;

[0010] The temporary substrate is removed.

[0011] Optionally, the thickness of the conductive component group and the first connecting component are both greater than 40 μm, and the thickness of the circuit wiring layer is greater than 40 μm.

[0012] Optionally, the conductive component group includes at least one conductive column, the first connecting component includes at least one first bonding pad, and a specific method of attaching a chip to each of the first connecting components includes:

[0013] Adhere silver paste to the surface of each first solder pad away from the temporary substrate by printing or dispensing to form a first silver paste layer;

[0014] Each of the first connecting components is electrically connected to one of the chips through the first silver paste layer.

[0015] Further, the chip has at least one first pin and at least one second pin, all the first pins are arranged on the front side, all the second pins are arranged on the back side, and each first pin of the chip is arranged opposite to one of the first pads in the corresponding first connecting component and is electrically connected through the first silver paste layer;

[0016] Silver paste is attached to each of the second pins by printing or dispensing to form a second silver paste layer.

[0017] Furthermore, the shape of the conductive column is an inverted "T" shape, and the shape of the conductive column is a rectangle.

[0018] Furthermore, the number of the first pins of each chip is the same as the number of the first pads in the corresponding first connecting component, and the number of the second pins of each chip is the same as the number of the conductive columns in the corresponding first connecting component.

[0019] Furthermore, a distance between the surface of the temporary substrate and the surface of the second silver paste layer away from the back side is smaller than a height of the conductive column.

[0020] Optionally, a specific method for forming a circuit wiring layer includes:

[0021] A circuit wiring layer is formed on the first plastic packaging layer by printing silver paste or copper paste, or by electroplating copper.

[0022] On the other hand, the present invention further provides a semiconductor element packaging structure, comprising a first plastic encapsulation layer and a second plastic encapsulation layer, wherein at least one copper pattern group with a gap arrangement and at least one chip are embedded in the first plastic encapsulation layer, each of the copper pattern groups comprises a conductive component group with a gap arrangement and a first connecting component, each of the first connecting components is covered with a chip, each of the chips has a front side and a back side, and the chip has at least one pin on the front side and the back side, the front side is arranged toward the first connecting component, and all the pins on the front side are electrically connected to the corresponding first connecting component, the first plastic encapsulation layer fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side, the first plastic encapsulation layer forms a circuit wiring layer on the surface close to the back side, the circuit wiring layer electrically connects all the pins of each chip on the back side and the conductive component group at the same time, so that all the pins on the back side of each chip are led to the front side through the conductive component group, and the second plastic encapsulation layer covers the circuit wiring layer;

[0023] Wherein, the copper pattern group and the circuit wiring layer are both formed by printing or electroplating.

[0024] Optionally, the thickness of the conductive component group and the first connecting component are both greater than 40 μm, and the thickness of the circuit wiring layer is greater than 40 μm.

[0025] Compared with the prior art, the present invention has the following unexpected technical effects:

[0026] The present invention provides a semiconductor element packaging structure and a preparation method thereof, the preparation method comprising the following steps: establishing at least one copper pattern group with gaps on a temporary substrate by printing or electroplating, each of the copper pattern groups comprising a conductive component group with gaps and a first connecting component; pasting a chip on each of the first connecting components, each of the chips having a front side and a back side, and the chip having at least one pin on the front side and the back side, the front side being arranged toward the first connecting component, and all the pins on the front side being electrically connected to the first connecting component; forming a first plastic encapsulation layer, the first plastic encapsulation layer filling the conductive component The gap between the group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side; a circuit wiring layer is formed on the surface of the first plastic encapsulation layer close to the back side by printing or electroplating, and the circuit wiring layer simultaneously electrically connects all the pins of each chip located on the back side and the conductive component group, so that all the pins of each chip located on the back side are led to the front side through the conductive component group; a second plastic encapsulation layer is formed, and the second plastic encapsulation layer covers the circuit wiring layer; and the temporary substrate is removed. The present invention forms a copper pattern group and a circuit wiring layer by printing or electroplating, so that thick copper with a thickness of more than 40μm can be obtained on both sides of the chip, breaking through the limitation that the process in the prior art cannot prepare thick copper with a thickness of more than 40μm, and also improves the heat dissipation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1-Figure 12 A schematic structural diagram of each step of a method for preparing a semiconductor element packaging structure provided by an embodiment of the present invention.

[0028] Description of reference numerals:

[0029] 100 - temporary substrate; 101 - copper film layer; 210, 220 - conductive pillars; 231, 232, 241, 242 - first solder pads; 250 - first silver paste layer; 261 - first chip; 262 - second chip; 270 - second silver paste layer; 281, 282 - connecting wires; 310 - first plastic sealing layer; 320 - second plastic sealing layer. DETAILED DESCRIPTION

[0030] A semiconductor element packaging structure and a method for preparing the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0031] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0032] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] This embodiment provides a method for preparing a semiconductor device packaging structure, comprising the following steps:

[0034] Step S1: establishing at least one copper pattern group with gaps on a temporary substrate by printing or electroplating, each of the copper pattern groups comprising a conductive component group with gaps and a first connecting component;

[0035] Step S2: attaching a chip to each of the first connecting components, wherein each of the chips has a front side and a back side, and each of the chips has at least one pin on the front side and the back side, the front side is arranged toward the first connecting component, and all the pins on the front side are electrically connected to the first connecting component;

[0036] Step S3: forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, and the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side;

[0037] Step S4: forming a circuit wiring layer on the surface of the first plastic packaging layer close to the back side by printing or electroplating, wherein the circuit wiring layer electrically connects all the pins of each chip on the back side and the conductive component group, so that all the pins of each chip on the back side are led to the front side through the conductive component group;

[0038] Step S5: forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the circuit wiring layer;

[0039] Step S6: removing the temporary substrate.

[0040] The following combination Figure 1-Figure 12 The method for preparing the semiconductor element packaging structure provided in this embodiment is described in detail.

[0041] See also Figure 1 First, step S1 is performed to establish at least one spaced copper pattern group on the temporary substrate 100 by printing or electroplating, each of the copper pattern groups includes a conductive component group spaced apart and a first connecting component.

[0042] This step specifically includes:

[0043] First, a temporary substrate 100 is provided. The temporary substrate 100 is, for example, square or circular in shape. The temporary substrate 100 may be an iron substrate, and a copper coating is disposed on the surface of the iron substrate. The thickness of the copper coating is 3 μm to 5 μm.

[0044] Next, at least one copper pattern group arranged at intervals is established on the copper coating by using a printing or electroplating process, each of the copper pattern groups can be electrically connected to a chip, the copper pattern group includes a conductive component group arranged at intervals and a first connecting component, the conductive component group includes at least one conductive column, and the first connecting component includes at least one first pad. The conductive column is in the shape of an inverted "T" shape, and the conductive column is in the shape of a rectangle. The conductive column and the first pad are made of pure copper, so that the heat dissipation effect of the thick copper (i.e., the conductive column and the first pad) located on one side of the chip is better than that of the existing copper alloy. The thickness of the conductive component group and the first connecting component is greater than 40μm. Since the printing or electroplating method adopted in this embodiment can prepare thick copper with a thickness of more than 40μm, it breaks through the limitation that the process in the prior art cannot prepare thick copper with a thickness of more than 40μm.

[0045] like Figure 2-Figure 4 As shown, step S2 is then performed to attach a chip to each of the first connecting components, each of the chips having a front side and a back side, and each of the chips having at least one pin on the front side and the back side, the front side being arranged toward the first connecting component, and all of the pins on the front side being electrically connected to the first connecting component.

[0046] This step specifically includes:

[0047] See also Figure 2 First, silver paste is attached to the surface of each first pad away from the temporary substrate by printing or dispensing to form a first silver paste layer 250.

[0048] See also Figure 3Then, a chip is electrically connected to each of the first connection components through the first silver paste layer 250. Each of the chips has a front side and a back side, the front side is arranged toward the first connection component, the chip has at least one first pin and at least one second pin, all the first pins are arranged on the front side, and all the second pins are arranged on the back side. Each first pin of the chip is arranged opposite to one of the first pads in the corresponding first connection component, and is electrically connected through the first silver paste layer 250. The number of the first pins of each chip is the same as the number of the first pads in the corresponding first connection component, and the number of the second pins of each chip is the same as the number of the conductive pillars in the corresponding first connection component.

[0049] In this embodiment, the chip includes a first chip 261 and a second chip 262, each of the first chip 261 and the second chip 262 has two first pins and one second pin, the copper pattern group includes two conductive component groups and two first connecting components, one first connecting component has two first solder pads 231, 232, one conductive component group has a conductive column 210, another first connecting component has two first solder pads 241, 242, and another conductive component group has a conductive column 220, the two first pins of the first chip 261 are respectively connected to the first solder pads 231, 232, and the two first pins of the second chip 262 are respectively connected to a first solder pad 241, 242.

[0050] See also Figure 4 Then, silver paste is attached to each of the second pins by printing or dispensing to form a second silver paste layer 270 .

[0051] Among them, the distance from the surface of the temporary substrate 100 to the surface of the second silver paste layer 270 away from the back side is smaller than the height of the conductive column, so that the conductive column can be exposed first when the first plastic encapsulation layer 310 above the second pin is subsequently ground and removed, thereby avoiding excessive grinding due to the conductive column being too low and causing loss of the second silver paste layer 270.

[0052] like Figure 5-Figure 7 As shown, step S3 is then performed to form a first plastic encapsulation layer 310, wherein the first plastic encapsulation layer 310 fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, and the first plastic encapsulation layer 310 exposes all the pins of the conductive component group and the chip on the back side.

[0053] This step specifically includes:

[0054] See also Figure 5First, a molding material is filled in the gap between the conductive component group and the first connecting component, as well as outside the conductive component group and the first connecting component, and the molding material is cured to form a first molding layer 310. The thickness of the first molding layer 310 is greater than the height of the conductive column, so that the first molding layer 310 can cover the conductive column and the second silver paste layer 270 from the back side.

[0055] The material of the first plastic packaging layer 310 includes, for example, epoxy resin containing 85%-90% silicon dioxide particles and polymer materials.

[0056] Next, in one embodiment, see Figure 6 The thickness of the first plastic encapsulation layer 310 is thinned from the back side by a grinding process to expose the conductive column and the second silver paste layer 270 .

[0057] In this step, since the distance from the surface of the temporary substrate 100 to the surface of the second silver paste layer 270 away from the back side is smaller than the height of the conductive column, part of the conductive column will also be ground away, so that the height of the conductive column after grinding is equal to the distance from the surface of the temporary substrate 100 to the surface of the second silver paste layer 270 away from the back side.

[0058] In another embodiment, see Figure 7 The first plastic encapsulation layer 310 above the second pin and the first plastic encapsulation layer 310 above the conductive column are removed from the back side by laser to expose the conductive column and the second silver paste layer 270 .

[0059] like Figure 8 As shown, step S4 is then performed to form a circuit wiring layer on the surface of the first plastic packaging layer 310 close to the back side by printing or electroplating, and the circuit wiring layer electrically connects all the pins of each chip on the back side and the conductive component group at the same time, so that all the pins of each chip on the back side are led to the front side through the conductive component group.

[0060] The specific steps are as follows: Figure 8 A circuit wiring layer is formed on the surface of the first plastic packaging layer 310 close to the back side by printing silver paste or copper paste, or electroplating copper, and the thickness of the circuit wiring layer is greater than 40 μm.

[0061] Wherein, the circuit wiring layer includes at least one second connection component, each of which is connected to a chip and the first connection component corresponding to the chip at the same time. The second connection component includes at least one connecting wire, each of which is connected to a second pin in the chip and a conductive column in the first connection component corresponding to the chip at the same time. The thickness of all the connecting wires is greater than 40μm, such as 100μm, 200μm, etc. The material of the connecting wire is silver or copper, so that the heat dissipation effect of the thick copper (i.e., the connecting wire) located on one side of the chip is better than that of the existing copper alloy. At the same time, this embodiment adopts printing or electroplating process to prepare thick copper with a thickness of more than 40μm, breaking through the limitation that the process in the prior art cannot prepare copper with a thickness of more than 40μm.

[0062] In this embodiment, the second connection component includes two connection wires 281 and 282 . The connection wire 281 connects the second pin of the first chip 261 and the conductive column 210 . The connection wire 282 connects the second pin of the second chip 262 and the conductive column 220 .

[0063] like Fig. 9 As shown, step S5 is then performed to form a second plastic encapsulation layer 320, wherein the second plastic encapsulation layer 320 covers the circuit wiring layer.

[0064] This step specifically includes: filling the plastic encapsulation material to cover the first plastic encapsulation layer 310 and the circuit wiring layer, and curing the plastic encapsulation material to form the second plastic encapsulation layer 320. The material of the second plastic encapsulation layer 320 includes, for example, epoxy resin, containing 85%-90% silicon dioxide particles and polymer materials.

[0065] like Figure 10-12 As shown, step S6 is then performed to remove the temporary substrate 100 .

[0066] The specific steps of this step are:

[0067] See also Fig.10 In one embodiment, the temporary substrate 100 is selectively etched from the front side by a selective etching process to expose the first plastic encapsulation layer 310 , the conductive column and the first pad on the front side, and also expose a portion of the second plastic encapsulation layer 320 .

[0068] See also Fig.11 In another embodiment, the temporary substrate 100 is removed by an etching process to expose the first plastic encapsulation layer 310, the second plastic encapsulation layer 320, the conductive column and the first pad on the front side.

[0069] See also Fig.12In another embodiment, the iron substrate is first removed by a stripping process and the copper film layer 101 is retained, and then the copper film layer 101 is removed by flash etching (short-time etching) to expose the first plastic encapsulation layer 310, the second plastic encapsulation layer 320, the conductive column and the first solder pad on the front side.

[0070] Finally, the semiconductor element packaging structure is separated through a cutting process.

[0071] See also Figure 1-Figure 12 The present embodiment further provides a semiconductor element packaging structure, comprising a first plastic encapsulation layer 310 and a second plastic encapsulation layer 320, wherein at least one copper pattern group with gaps and at least one chip are embedded in the first plastic encapsulation layer 310, each of the copper pattern groups comprises a conductive component group with gaps and a first connecting component, each of the first connecting components is covered with a chip, each of the chips has a front side and a back side, and each of the chips has at least one pin on the front side and the back side, the front side is arranged toward the first connecting component, and all the pins on the front side are electrically connected to the corresponding first connecting component, and the first The plastic encapsulation layer 310 fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component. The first plastic encapsulation layer 310 exposes the conductive component group and all the pins of the chip on the back side. The first plastic encapsulation layer 310 forms a circuit wiring layer on the surface close to the back side. The circuit wiring layer simultaneously electrically connects all the pins of each chip on the back side and the conductive component group, so that all the pins on the back side of each chip are led to the front side through the conductive component group. The second plastic encapsulation layer 320 covers the circuit wiring layer.

[0072] Wherein, the thickness of the circuit wiring layer is greater than 40 μm, and the thickness of the conductive component group and the first connecting component is greater than 40 μm.

[0073] In summary, the present invention provides a semiconductor element packaging structure and a preparation method thereof, the preparation method comprising the following steps: establishing at least one copper pattern group with gaps on a temporary substrate by printing or electroplating, each of the copper pattern groups comprising a conductive component group with gaps and a first connecting component; pasting a chip on each of the first connecting components, each of the chips having a front side and a back side, and the chip having at least one pin on the front side and the back side, the front side being arranged toward the first connecting component, and all the pins on the front side being electrically connected to the first connecting component; forming a first plastic encapsulation layer, the first plastic encapsulation layer filling the conductive component. The gap between the component group and the first connecting component, and the outside of the conductive component group and the first connecting component, the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side; a circuit wiring layer is formed on the surface of the first plastic encapsulation layer close to the back side by printing or electroplating, and the circuit wiring layer simultaneously electrically connects all the pins of each chip located on the back side and the conductive component group, so that all the pins of each chip located on the back side are led to the front side through the conductive component group; a second plastic encapsulation layer is formed, and the second plastic encapsulation layer covers the circuit wiring layer; and the temporary substrate is removed. The present invention forms a copper pattern group and a circuit wiring layer by printing or electroplating, so that thick copper with a thickness of more than 40μm can be obtained on both sides of the chip, breaking through the limitation that the process in the prior art cannot prepare thick copper with a thickness of more than 40μm, and also improves the heat dissipation effect.

[0074] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0075] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor element packaging structure, characterized in that: The following steps are involved: Establishing at least one gap-arranged copper pattern group on the temporary substrate by printing or electroplating, each of the copper pattern groups comprising a gap-arranged conductive component group and a first connecting component; A chip is attached to each of the first connecting components, each of the chips has a front side and a back side, and each of the chips has at least one pin on the front side and the back side, the front side is arranged toward the first connecting component, and all the pins on the front side are electrically connected to the first connecting component; forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, and the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side; A circuit wiring layer is formed on the surface of the first plastic packaging layer close to the back side by printing or electroplating, and the circuit wiring layer electrically connects all the pins of each chip located on the back side and the conductive component group at the same time, so that all the pins of each chip located on the back side are led to the front side through the conductive component group; forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the circuit wiring layer; The temporary substrate is removed.

2. The method for preparing a semiconductor device packaging structure according to claim 1, wherein: The thickness of the conductive component group and the first connecting component are both greater than 40 μm, and the thickness of the circuit wiring layer is greater than 40 μm.

3. The method for preparing a semiconductor device packaging structure according to claim 1, wherein: The conductive component group includes at least one conductive column, the first connecting component includes at least one first bonding pad, and a specific method of attaching a chip to each of the first connecting components includes: Adhere silver paste to the surface of each first solder pad away from the temporary substrate by printing or dispensing to form a first silver paste layer; Each of the first connecting components is electrically connected to one of the chips through the first silver paste layer.

4. The method for preparing a semiconductor device packaging structure according to claim 3, characterized in that: The chip has at least one first pin and at least one second pin, all the first pins are arranged on the front side, and all the second pins are arranged on the back side, and each first pin of the chip is arranged opposite to one of the first pads in the corresponding first connecting component, and is electrically connected through the first silver paste layer; Silver paste is attached to each of the second pins by printing or dispensing to form a second silver paste layer.

5. The method for preparing a semiconductor device packaging structure according to claim 4, characterized in that: The conductive column has an inverted "T" shape and a rectangular shape.

6. The method for preparing a semiconductor device packaging structure according to claim 4, characterized in that: The number of the first pins of each chip is the same as the number of the first pads in the corresponding first connection component, and the number of the second pins of each chip is the same as the number of the conductive columns in the corresponding first connection component.

7. The method for preparing a semiconductor device packaging structure according to claim 4, characterized in that: A distance between the surface of the temporary substrate and the surface of the second silver paste layer away from the back side is smaller than a height of the conductive pillar.

8. The method for preparing a semiconductor device packaging structure according to claim 1, wherein: The specific method of forming the circuit wiring layer includes: A circuit wiring layer is formed on the first plastic packaging layer by printing silver paste or copper paste, or by electroplating copper.

9. A semiconductor element packaging structure, characterized in that: The invention comprises a first plastic encapsulation layer and a second plastic encapsulation layer, wherein at least one copper pattern group with gap arrangement and at least one chip are embedded in the first plastic encapsulation layer, each of the copper pattern groups comprises a conductive component group with gap arrangement and a first connecting component, each of the first connecting components is covered with a chip, each of the chips has a front side and a back side, and the chip has at least one pin on the front side and the back side, the front side is arranged toward the first connecting component, and all the pins on the front side are electrically connected to the corresponding first connecting component, the first plastic encapsulation layer fills the gap between the conductive component group and the first connecting component, as well as the outside of the conductive component group and the first connecting component, the first plastic encapsulation layer exposes the conductive component group and all the pins of the chip on the back side, the first plastic encapsulation layer forms a circuit wiring layer on the surface close to the back side, the circuit wiring layer electrically connects all the pins of each chip on the back side and the conductive component group at the same time, so that all the pins on the back side of each chip are led to the front side through the conductive component group, and the second plastic encapsulation layer covers the circuit wiring layer; Wherein, the copper pattern group and the circuit wiring layer are both formed by printing or electroplating.

10. The semiconductor device packaging structure according to claim 9, characterized in that: The thickness of the conductive component group and the first connecting component are both greater than 40 μm, and the thickness of the circuit wiring layer is greater than 40 μm.

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