Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate; depositing a first interlayer dielectric layer on one side of the substrate; depositing a sacrificial layer on one side, deviating from the substrate, of the first interlayer dielectric layer; filling a first metal layer in the first interlayer dielectric layer and the sacrificial layer, wherein the first metal layer comprises a plurality of metal structures which are arranged at intervals; forming a plurality of second metal layers on one side, deviating from the first interlayer dielectric layer, of the sacrificial layer; forming a hole extending from the second metal layer to the sacrificial layer through etching; and removing the sacrificial layer, and filling a hole extending from the second metal layer to the sacrificial layer to form an air gap between adjacent metal structures in the first metal layer. According to the invention, the interlayer air gap is formed between the metal layers, the dielectric constant of the metal interconnection process is reduced, the capacitance coupling effect is reduced, the signal transmission RC delay is reduced, the process method is simple, and the size of the air gap is easy to control.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the improvement of process technology, there are more and more wires per unit area, the spacing between wires becomes smaller, the coupling capacitance between wires becomes significant, and a series of problems such as increased crosstalk and delay caused by parasitic capacitance become more prominent. Using low dielectric constant materials to form interlayer dielectrics and forming air gaps in the interlayer dielectrics can effectively reduce the distributed capacitance between interconnects, thereby improving the overall performance of the chip. The current method of introducing air gaps in interlayer dielectrics is to place a polymer material (Thermal Degradable Polymer) that can be decomposed at a certain temperature as a sacrificial material in the interlayer dielectric, and its thermal decomposition temperature is about 350°C. The sacrificial material is removed by annealing in the later process. However, the process of this method is relatively complicated, and the process is difficult to control, and the air gap formed is difficult to reach the target size.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In response to the problems in the prior art, the purpose of the present application is to provide a method for preparing a semiconductor structure and a semiconductor structure, by forming an interlayer air gap between metal layers, reducing the dielectric constant of the metal interconnection process, thereby reducing the capacitive coupling effect and reducing the RC delay of signal transmission. The process method is simple and the size of the air gap is easy to control.

[0005] The present invention provides a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] Depositing a first interlayer dielectric layer on one side of the substrate;

[0008] Depositing a sacrificial layer on a side of the first interlayer dielectric layer facing away from the substrate;

[0009] Filling a first metal layer in the first interlayer dielectric layer and the sacrificial layer, wherein the first metal layer includes a plurality of metal structures arranged at intervals;

[0010] forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer;

[0011] forming a hole extending from the second metal layer to the sacrificial layer by etching;

[0012] The sacrificial layer is removed, and holes extending from the second metal layer to the sacrificial layer are filled to form air gaps between adjacent metal structures in the first metal layer.

[0013] In some embodiments, the sacrificial layer is a silicon oxynitride layer.

[0014] In some embodiments, before depositing the first interlayer dielectric layer on one side of the substrate, the following steps are also included:

[0015] An etch stop layer is deposited on one side of the substrate.

[0016] In some embodiments, the interlayer dielectric layer is a low dielectric constant material dielectric layer.

[0017] In some embodiments, forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer comprises the following steps:

[0018] An etch stop layer, a second interlayer dielectric layer and a second metal layer are cyclically deposited on a side of the sacrificial layer away from the interlayer dielectric layer until the amount of the second metal layer reaches a target amount.

[0019] In some embodiments, a ratio of a thickness of the sacrificial layer to a thickness of the first interlayer dielectric layer is between 1:9 and 1:4.

[0020] In some embodiments, removing the sacrificial layer includes: using high temperature phosphoric acid and wet etching to remove the sacrificial layer.

[0021] In some embodiments, the step of forming a hole extending from the second metal layer to the sacrificial layer by etching comprises the following steps:

[0022] A hole extending from the second metal layer to the sacrificial layer is formed by dry etching using carbon tetrafluoride gas.

[0023] In some embodiments, filling the hole extending from the second metal layer to the sacrificial layer comprises the following steps:

[0024] A silicon dioxide layer is deposited in the hole extending from the second metal layer to the sacrificial layer by a plasma enhanced chemical vapor deposition process.

[0025] An embodiment of the present application also provides a semiconductor structure obtained by the semiconductor structure preparation method, wherein the semiconductor structure includes a substrate and multiple metal layers, the metal layers are located on one side of the substrate, and an air gap is formed between the metal structures of at least one of the metal layers.

[0026] The semiconductor structure preparation method and semiconductor structure provided in this application have the following advantages:

[0027] The present application forms an interlayer air gap between metal layers to reduce the dielectric constant of the metal interconnection process, thereby reducing the capacitive coupling effect and reducing the RC delay of signal transmission, and the process method is simple. When forming a sacrificial layer, a first interlayer dielectric layer of a certain thickness is first deposited to control the thickness of the sacrificial layer so that it is not too large, so as to avoid the air gap formed after removing the sacrificial layer being too large and affecting the mechanical properties of the semiconductor structure and even the semiconductor device. By controlling the thickness ratio of the sacrificial layer and the first interlayer dielectric layer, the size of the air gap can be controlled as needed, thereby making it easier to control the size of the air gap so that it reaches the target air gap size.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present application;

[0031] Figure 2 is a schematic diagram of providing a substrate according to an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of depositing an etch stop layer and a first interlayer dielectric layer on one side of a substrate according to an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of depositing a sacrificial layer on a side of a first interlayer dielectric layer facing away from a substrate according to an embodiment of the present application;

[0034] Figure 5 It is a schematic diagram of filling a first metal layer in a first interlayer dielectric layer and a sacrificial layer according to an embodiment of the present application;

[0035] Figure 6 is a schematic diagram of forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer according to an embodiment of the present application;

[0036] Figure 7is a schematic diagram of etching to form a hole extending from the second metal layer to the sacrificial layer and removing the sacrificial layer in one embodiment of the present application;

[0037] Figure 8 is a schematic diagram of filling a hole extending from the second metal layer to the sacrificial layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.

[0039] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.

[0040] In order to reduce RC delay and capacitive coupling effect, an air gap can be formed in the metal layer of the semiconductor structure. RC delay (Resistance-Capacitance Delay) refers to the signal transmission delay phenomenon caused by the presence of resistance (R) and capacitance (C) in electronic circuits. In the prior art, a polymer material that can be decomposed at a certain temperature is placed in the interlayer dielectric as a sacrificial material, and its thermal decomposition temperature is about 350°C. The sacrificial material is removed by annealing in the later process. However, the process of this method is relatively complicated, and the process is difficult to control, and the air gap formed is difficult to reach the target size.

[0041] like Figure 1 As shown, the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0042] S100: providing a substrate;

[0043] The substrate is, for example, a structure after completing a CT process (semiconductor packaging process technology), and the substrate at least includes a silicon substrate, in which a plurality of conductive members formed of metal tungsten are arranged;

[0044] When an air gap is formed in the first metal layer on the substrate, the surface of the substrate has no metal layer; when an air gap is formed in the nth (n>1) metal layer on the substrate, the substrate includes a silicon substrate and n-1 metal layers formed on the surface of the silicon substrate, and the first metal layer formed in the following step S400 is the nth metal layer;

[0045] S200: depositing a first interlayer dielectric layer on one side of the substrate;

[0046] An interlayer dielectric layer refers to an insulating material located between different metal layers in a multi-layer electronic device; the "first" in the "first interlayer dielectric layer" is only to distinguish it from other interlayer dielectric layers subsequently deposited thereon, and the "first interlayer dielectric layer" specifically refers to the interlayer dielectric layer (ILD) corresponding to the metal layer below which an air gap needs to be formed;

[0047] S300: depositing a sacrificial layer on a side of the first interlayer dielectric layer facing away from the substrate;

[0048] A sacrificial layer is a temporary material layer used in semiconductor manufacturing. Its main function is to assist in the manufacture of some complex microstructures or nanostructures. It is selectively removed at a specific stage of the manufacturing process to form the desired structure or gap.

[0049] In this embodiment, the sacrificial layer is a silicon oxynitride SiON layer. The sacrificial layer is used to replace a portion of the interlayer dielectric layer, and after the sacrificial layer is subsequently removed, an air gap of a target size can be formed at the location of the sacrificial layer;

[0050] S400: filling a first metal layer in the first interlayer dielectric layer and the sacrificial layer, wherein the first metal layer includes a plurality of metal structures arranged at intervals;

[0051] The first metal layer is, for example, a copper layer, and a TaN / Ta structure is formed on the sidewall of each metal structure. The TaN (tantalum nitride) / Ta (tantalum) structure mainly plays the role of diffusion barrier, improving electrical contact and improving structural stability. This structure can effectively prevent the diffusion of metal atoms between different metal layers, ensuring good electrical and mechanical properties between metal layers;

[0052] The "first" in the "first metal layer" here is only to distinguish it from the metal layer that is subsequently deposited thereon. The first metal layer is the metal layer that needs to form an air gap, and is not necessarily the first metal layer on the silicon substrate. As mentioned above, when an air gap needs to be formed on the nth metal layer, the nth metal layer is filled after the n-1th metal layer has been formed on the silicon substrate.

[0053] S500: forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer;

[0054] The "second" in the "second metal layer" is only used to distinguish it from the metal layer that needs to form an air gap, and does not necessarily mean that the second metal layer and the first metal layer must have different materials or structures; the number of the "second metal layers" can be selected as needed, for example, forming another second metal layer, or forming three metal layers, etc.;

[0055] S600: forming a hole extending from the second metal layer to the sacrificial layer by etching;

[0056] Here, “extending from the second metal layer to the sacrificial layer” means extending downward from the top surface height of the second metal layer to the bottom surface height of the sacrificial layer;

[0057] S700: removing the sacrificial layer, and filling the holes extending from the second metal layer to the sacrificial layer to form air gaps between adjacent metal structures in the first metal layer;

[0058] By removing the sacrificial layer, gaps are left between the metal structures of the first metal layer, forming air gaps between the metal structures, and vertical holes extending from the second metal layer to the sacrificial layer are filled to avoid affecting the mechanical properties of the semiconductor structure. Insulating materials, such as silicon dioxide materials, are used to fill the holes.

[0059] The present application forms an interlayer air gap between metal layers to reduce the dielectric constant of the metal interconnection process, thereby reducing the capacitive coupling effect and reducing the RC delay of signal transmission, and the process method is simple. When forming a sacrificial layer, a first interlayer dielectric layer of a certain thickness is first deposited to control the thickness of the sacrificial layer so that it is not too large, so as to avoid the air gap formed after removing the sacrificial layer being too large and affecting the mechanical properties of the semiconductor structure and even the semiconductor device. By controlling the thickness ratio of the sacrificial layer and the first interlayer dielectric layer, the size of the air gap can be controlled as needed, thereby making it easier to control the size of the air gap so that it reaches the target air gap size.

[0060] In this embodiment, the interlayer dielectric layer is a low dielectric constant material dielectric layer, and the low dielectric constant material refers to a material with a relatively low dielectric constant. Generally, the dielectric constant is less than or equal to 3.9, such as a silicon dioxide material. Optionally, the interlayer dielectric layer is a silicon dioxide dielectric layer. The low dielectric constant material dielectric layer is conducive to isolating the metal layer, preventing electrical short circuits, and reducing the capacitance between adjacent metal layers, reducing signal transmission delay and crosstalk.

[0061] In this embodiment, the step S100: before depositing the first interlayer dielectric layer on one side of the substrate, further includes the following steps:

[0062] An etch stop layer is deposited on one side of the substrate. The etch stop layer is, for example, a silicon carbide nitride SiCN layer. The main function of the etch stop layer (ESL) is to accurately control the depth of etching during the etching process, and to stop etching when the etching reaches the layer, thereby protecting the underlying material, or accurately manufacturing a structure with a specific thickness or shape.

[0063] In this embodiment, the step S500 of forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer comprises the following steps:

[0064] An etch stop layer, a second interlayer dielectric layer and a second metal layer are cyclically deposited on the side of the sacrificial layer away from the interlayer dielectric layer until the number of the second metal layers reaches the target number. Each second metal layer includes one or more metal structures, and a TaN / Ta structure is formed on the sidewall of each metal structure.

[0065] The "second" in the "second interlayer dielectric layer" is only to distinguish it from the first interlayer dielectric layer with a reduced thickness below the first metal layer, and the second interlayer dielectric layer and the first interlayer dielectric layer can be made of the same material, such as low dielectric constant materials such as silicon dioxide. The thickness of the second interlayer dielectric layer can be equal to the sum of the thickness of the first interlayer dielectric layer and the sacrificial layer, but other sizes can also be used, which are selected and set according to the product performance requirements of the semiconductor device.

[0066] In this embodiment, the thickness of the sacrificial layer is smaller than the thickness of the first interlayer dielectric layer.

[0067] In this embodiment, the ratio of the thickness of the sacrificial layer to the thickness of the first interlayer dielectric layer is between 1:9 and 1:4. Taking a 65nm semiconductor device as an example, the thickness of the etch stop layer is about 400A, the full thickness of each interlayer dielectric layer is about 1000A, and the thickness of the sacrificial layer accounts for about 10% to 20% of the full thickness of each interlayer dielectric layer, so that the thickness of the sacrificial layer is about 100 to 200A. Therefore, the thickness of the first interlayer dielectric layer is the full thickness of the interlayer dielectric layer minus the thickness of the sacrificial layer, which is 900 to 800A.

[0068] In this embodiment, the step S600 of forming a hole extending from the second metal layer to the sacrificial layer by etching includes the following steps:

[0069] A hole extending from the second metal layer to the sacrificial layer is formed by dry etching using CF4 gas. Dry etching removes material by chemically reacting a gaseous etchant with the etched material without using a liquid etchant. This method can accurately control the shape, size and depth of the etching.

[0070] In this embodiment, in the step S700, removing the sacrificial layer includes: using high-temperature phosphoric acid to remove the sacrificial layer by wet etching. Specifically, the sacrificial layer is removed by wet etching using hot phosphoric acid H3PO4. As the temperature increases, the etching rate of phosphoric acid increases significantly. The high temperature of the high-temperature phosphoric acid here is, for example, 155-165°C. In this temperature range, phosphoric acid has a good corrosion effect on silicon oxynitride. However, the present application is not limited to this, and the specific temperature selection may vary due to different production process requirements, equipment conditions, and emphasis on corrosion rate and selectivity.

[0071] In this embodiment, in step S700, filling the hole extending from the second metal layer to the sacrificial layer includes the following steps:

[0072] A silicon dioxide layer is deposited in the hole extending from the second metal layer to the sacrificial layer by a plasma enhanced chemical vapor deposition process.

[0073] Plasma-Enhanced Chemical Vapor Deposition (PECVD) is a chemical vapor deposition process. It uses plasma to enhance the activity of the reaction gas, thereby achieving the deposition of high-quality thin film materials at a lower temperature. Due to the limitation of CVD's hole filling ability, if the hole width is large, there may be a gap in the center of the hole. The hole width can be controlled to fill the hole, reduce the size of the gap or even eliminate the gap, so as to further enhance the mechanical properties of the semiconductor structure.

[0074] Combine the following Figures 2 to 6 The specific implementation process of the preparation method of the semiconductor structure in a specific example is introduced. It is understandable that the structure shown in the drawings and the following description are only examples and are not intended to limit the scope of protection of the present application. The shapes and sizes of the various film layers shown in the drawings are only examples and are not intended to limit the scope of protection of the present application. In different implementations, the shapes and sizes of the various film layers can be adaptively selected and adjusted according to the structural requirements and process requirements of the semiconductor device, and all fall within the scope of protection of the present application.

[0075] Figure 2 FIG. 1 is a schematic diagram of providing a substrate according to an embodiment of the present application. Figure 2 As shown, corresponding to step S200, a substrate 100 is first provided, and the substrate 100 is a substrate after the CT process is completed, and at least includes a silicon substrate, in which a conductive member of metal tungsten is formed. When an air gap is formed in the first metal layer on the substrate, there is no metal layer on the surface of the substrate, and when an air gap is formed in the nth (n>1) metal layer on the substrate, the substrate includes the silicon substrate and the n-1 metal layer that has been formed on the surface of the silicon substrate. Figure 2 In the example, it is taken that an air gap needs to be formed in the first metal layer, but the present application is not limited thereto.

[0076] Figure 3 FIG. 1 is a schematic diagram of depositing an etch stop layer and a first interlayer dielectric layer on one side of a substrate according to an embodiment of the present application. Figure 3 As shown, corresponding to step S200, an etch stop layer 200 is first deposited on one side of the substrate 100, and then a first interlayer dielectric layer 300 is deposited on the side of the etch stop layer 200 away from the substrate 100. The etch stop layer 200 is, for example, a silicon carbide nitride layer. The first interlayer dielectric layer 300 is a low dielectric constant dielectric layer, such as a silicon dioxide dielectric layer.

[0077] Figure 4 FIG. 1 is a schematic diagram of depositing a sacrificial layer on a side of the first interlayer dielectric layer facing away from the substrate according to an embodiment of the present application. Figure 4As shown, corresponding to step S300, a sacrificial layer 400 is deposited on the side of the first interlayer dielectric layer 300 away from the substrate 100. The sacrificial layer 400 is, for example, a silicon oxynitride layer. The thickness ratio of the sacrificial layer 400 to the first interlayer dielectric layer 300 is between 1:9 and 1:4.

[0078] Figure 5 FIG. 1 is a schematic diagram of filling a first metal layer in a first interlayer dielectric layer and a sacrificial layer according to an embodiment of the present application. Figure 5 As shown, corresponding to step S400: a first metal layer 510 is filled in the first interlayer dielectric layer 300 and the sacrificial layer 400, wherein the first metal layer 510 includes a plurality of metal structures arranged at intervals. Figure 5 3 metal structures are shown in the figure by way of example, but the present application is not limited thereto. The first metal layer 510 is, for example, a copper layer. A TaN / Ta structure 520 is formed on the sidewall of each metal structure.

[0079] Figure 6 Schematic diagram of forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer according to an embodiment of the present application. Figure 6 As shown, corresponding to step S500, an etch stop layer, a second interlayer dielectric layer 600 and a second metal layer 700 are cyclically deposited on the side of the sacrificial layer 400 away from the interlayer dielectric layer until the amount of the second metal layer 700 reaches the target amount. Figure 6 In the example of depositing three layers of second metal layer 700, the present application is not limited thereto. The second metal layer 700 is, for example, a copper layer. Each second metal layer 700 includes one or more metal structures, and a TaN / Ta structure is formed on the sidewall of each metal structure. The etching stop layer is, for example, a silicon carbide nitride layer. The second interlayer dielectric layer 600 is a low dielectric constant dielectric layer, for example, a silicon dioxide layer.

[0080] Figure 7 It is a schematic diagram of etching to form a hole extending from the second metal layer to the sacrificial layer and removing the sacrificial layer according to an embodiment of the present application. Figure 8 Schematic diagram of filling a hole extending from the second metal layer to the sacrificial layer in one embodiment of the present application. Corresponding to steps S600 and S700, a hole 800 extending from the second metal layer 700 to the sacrificial layer is first formed by etching, and then the sacrificial layer is removed by wet etching using high-temperature phosphoric acid to form an air gap 900 of a target size between the metal structures of the first metal layer. Then, the hole 800 extending from the second metal layer 700 to the sacrificial layer is filled. Here, an insulating material, such as a silicon dioxide material, is used to fill the hole. Therefore, an air gap between the metal structures of the first metal layer can be formed by etching a hole connected to the sacrificial layer downward from the upper metal layer of the first metal layer, and then removing the sacrificial layer using hot phosphoric acid.

[0081] The embodiment of the present application also provides a semiconductor structure, which is obtained by the method for preparing the semiconductor structure, and the semiconductor structure includes a substrate and a plurality of metal layers, wherein the metal layers are located on one side of the substrate, and an air gap is formed between the metal structures of at least one of the metal layers. Since the semiconductor structure is obtained by the method for preparing the semiconductor structure, it also has corresponding technical effects, and an air gap of a target size is formed in the metal layer where the air gap needs to be formed without affecting the mechanical properties of the semiconductor structure, thereby reducing the dielectric constant of the metal interconnection process, reducing the capacitive coupling effect, and reducing the RC delay of signal transmission.

[0082] In summary, the semiconductor structure preparation method and semiconductor structure provided in this application have the following advantages:

[0083] The present application forms an interlayer air gap between metal layers to reduce the dielectric constant of the metal interconnection process, thereby reducing the capacitive coupling effect and reducing the RC delay of signal transmission, and the process method is simple. When forming a sacrificial layer, a first interlayer dielectric layer of a certain thickness is first deposited to control the thickness of the sacrificial layer so that it is not too large, so as to avoid the air gap formed after removing the sacrificial layer being too large and affecting the mechanical properties of the semiconductor structure and even the semiconductor device. By controlling the thickness ratio of the sacrificial layer and the first interlayer dielectric layer, the size of the air gap can be controlled as needed, thereby making it easier to control the size of the air gap so that it reaches the target air gap size.

[0084] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; Depositing a first interlayer dielectric layer on one side of the substrate; Depositing a sacrificial layer on a side of the first interlayer dielectric layer facing away from the substrate; Filling a first metal layer in the first interlayer dielectric layer and the sacrificial layer, wherein the first metal layer includes a plurality of metal structures arranged at intervals; forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer; forming a hole extending from the second metal layer to the sacrificial layer by etching; The sacrificial layer is removed, and holes extending from the second metal layer to the sacrificial layer are filled to form air gaps between adjacent metal structures in the first metal layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The sacrificial layer is a silicon oxynitride layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before depositing the first interlayer dielectric layer on one side of the substrate, the method further includes the following steps: An etch stop layer is deposited on one side of the substrate.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The interlayer dielectric layer is a low dielectric constant material dielectric layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: Forming a plurality of second metal layers on a side of the sacrificial layer away from the first interlayer dielectric layer comprises the following steps: An etch stop layer, a second interlayer dielectric layer and a second metal layer are cyclically deposited on a side of the sacrificial layer away from the interlayer dielectric layer until the amount of the second metal layer reaches a target amount.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The ratio of the thickness of the sacrificial layer to the thickness of the first interlayer dielectric layer is between 1:9 and 1:

4.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: Removing the sacrificial layer includes: using high temperature phosphoric acid and wet etching to remove the sacrificial layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming a hole extending from the second metal layer to the sacrificial layer by etching comprises the following steps: A hole extending from the second metal layer to the sacrificial layer is formed by dry etching using carbon tetrafluoride gas.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of filling the hole extending from the second metal layer to the sacrificial layer comprises the following steps: A silicon dioxide layer is deposited in the hole extending from the second metal layer to the sacrificial layer by a plasma enhanced chemical vapor deposition process.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9, wherein the semiconductor structure comprises a substrate and a plurality of metal layers, wherein the metal layers are located on one side of the substrate, and an air gap is formed between metal structures of at least one of the metal layers.

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