Package structure and method for forming the same

Abstract

A package structure and a method for forming a package structure are provided. The package structure includes a chip-containing structure bonded to the redistribution structure through a plurality of first solder bumps. The package structure also includes a memory-containing structure bonded to the interposer chip. The interposer chip is bonded to the redistribution structure through a plurality of second solder bumps. The package structure also includes a substrate, and the redistribution structure is over the substrate.

Description

Technical Field

[0001] Embodiments of the present application relate to package structures and methods for forming package structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have produced semiconductor devices with more sophisticated components and / or higher integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased, while component size (i.e., the smallest component that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] The chip package not only provides protection for the semiconductor device from environmental pollutants, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures that occupy less space or are lower in height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies.These relatively new packaging technologies for semiconductor dies face manufacturing challenges. Summary of the invention

[0005] Some embodiments of the present application provide a packaging structure, including: a substrate; a redistribution structure located above the substrate; a chip-containing structure joined to the redistribution structure via a plurality of first solder bumps; an interposer chip joined to the redistribution structure via a plurality of second solder bumps; and a memory-containing structure joined to the interposer chip.

[0006] Other embodiments of the present application provide a packaging structure, including: a first chip-containing structure bonded to a redistribution structure; an interposer chip bonded to the redistribution structure, wherein the interposer chip has active devices; and a second chip-containing structure bonded to the interposer chip.

[0007] Some other embodiments of the present application provide a method for forming a package structure, comprising: forming a redistribution structure above a carrier substrate; bonding a first chip-containing structure to the redistribution structure; bonding a second chip-containing structure to an interposer chip, wherein the interposer chip has active devices; and bonding the interposer chip to the redistribution structure. In some embodiments, the method for forming a package structure further comprises: providing a heat diffusion cap above the first chip-containing structure and the second chip-containing structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figures 1A to 1F are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0010] Figures 2A to 2G are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0011] Figure 3 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0012] Figure 4 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0013] Figure 5 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0014] Figure 6 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0015] Figure 7 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0016] Figure 8 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0017] Fig. 9 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0018] Fig. 10A is a cross-sectional view of a portion of a package structure according to some embodiments.

[0019] Fig. 10B is a cross-sectional view of a portion of a package structure according to some embodiments.

[0020] Fig.11 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0021] Fig.12 is a cross-sectional view of a portion of a package structure according to some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] Those skilled in the art will understand the term "substantially" in the description (such as "substantially flat" or "substantially coplanar"). In some embodiments, the adjective substantially can be removed. Where applicable, the term "substantially" may also include embodiments with "complete", "completely", "all", etc. Where applicable, the term "substantially" may also relate to 90% or more of the specified content, such as 95% or more, particularly 99% or more, including 100%. In addition, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor deviations from the specified arrangement, and may include, for example, deviations of up to 10 degrees. The word "substantially" does not exclude "completely", for example, a composition that is "substantially free of" Y may be completely free of Y.

[0025] Terms such as "about" in conjunction with specific distances or dimensions should be interpreted as not excluding minor deviations from the specific distances or dimensions and may include deviations of, for example, up to 10%. The term "about" in connection with a numerical value x may mean x±5% or x±10%.

[0026] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Additional components may be added to the semiconductor device structure and / or the packaging structure. For different embodiments, some of the components described below may be replaced or eliminated. Although some embodiments are discussed with operations implemented in a specific order, these operations may be implemented in another logical order.

[0027] Embodiments of the present disclosure may relate to three-dimensional (3D) packages or 3D-IC devices. Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be implemented on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of known good dies to increase yield and reduce costs.

[0028] Figures 1A to 1F is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. Figure 1A As shown in , a carrier substrate 100 is provided or received. The carrier substrate 100 is used as a support substrate during the manufacturing process. In some embodiments, the carrier substrate 100 is a temporary support carrier and will be removed later.

[0029] The carrier substrate 100 may be made of or include a dielectric material, a semiconductor material, one or more other suitable materials, or a combination thereof. In some embodiments, the carrier substrate 100 is a dielectric substrate, such as a glass wafer. In some other embodiments, the carrier substrate 100 is a semiconductor substrate, such as a silicon wafer. The semiconductor substrate may be made of or include silicon, germanium, silicon germanium, another suitable semiconductor material, or a combination thereof.

[0030] like Figure 1A As shown in , according to some embodiments, a redistribution structure RDL is formed over a carrier substrate 100. The redistribution structure RDL may include a plurality of conductive features surrounded by a plurality of insulating layers. The insulating layers may include a plurality of polymer-containing insulating layers.

[0031] The insulating layer of the redistribution structure RDL can be made of or include one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), epoxy-based resin, another suitable polymer material, or a combination thereof. In some embodiments, the polymer material is photosensitive. Therefore, a photolithography process can be used to form an opening with a desired pattern in the insulating layer. These openings can be used to include some of the conductive components.

[0032] The conductive components of the redistribution structure RDL may include conductive wires, conductive vias and / or conductive pads. The conductive components may be made of copper, cobalt, tin, titanium, gold, platinum, aluminum, tungsten, one or more other suitable materials or combinations thereof or include copper, cobalt, tin, titanium, gold, platinum, aluminum, tungsten, one or more other suitable materials or combinations thereof. The conductive components may be formed using an electroplating process, a chemical plating process, another applicable process or a combination thereof. The formation of the conductive components may also involve one or more etching processes and one or more planarization processes.

[0033] like Figure 1B As shown in , according to some embodiments, a plurality of chip structures (or chip-containing structures) are arranged above the redistribution structure RDL. In some embodiments, before the chip structures are arranged, a test operation is performed on the redistribution structure RDL to ensure the quality and reliability of the redistribution structure RDL.

[0034] In some embodiments, the chip structure (or chip-containing structure) 102A is bonded to the redistribution structure RDL through a conductive connector 104A. The conductive connector 104A may include a solder bump. The solder bump may include tin and other materials, such as copper, silver, gold, aluminum, lead, another suitable material, or a combination thereof. In some embodiments, the conductive connector 104A is a lead-free solder bump.

[0035] In some embodiments, the chip structure 102A is a logic control chip structure including a plurality of logic control device elements. The chip structure 102A may include a semiconductor substrate portion 106, a device portion 108, and an interconnect structure 107A. The semiconductor substrate portion 106 may include silicon or other elemental semiconductor materials, such as germanium. In some embodiments, the semiconductor substrate portion 106 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or combinations thereof.

[0036] In some other embodiments, the semiconductor substrate portion 106 includes a compound semiconductor. For example, the compound semiconductor includes a X1 Ga X2 In X3 AsY1 P Y2 N Y3 Sb Y4 One or more III-V compound semiconductors of a defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. Each of them is greater than or equal to zero, and they are added together to equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrates including II-VI compound semiconductors may also be used.

[0037] A plurality of device elements are formed in and / or on the device portion 108. Examples of various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs)), or another suitable element. Various processes may be used to form various device elements, including deposition, etching, implantation, photolithography, annealing, and / or other suitable processes.

[0038] In some embodiments, interconnect structure 107A is formed on device portion 108 for providing electrical connection to device elements. Interconnect structure 107A may be a front-side interconnect structure. Interconnect structure 107A includes a plurality of conductive components surrounded by a plurality of dielectric layers. The conductive components may include conductive contacts, conductive wires, and conductive vias. The formation of interconnect structure 107A may involve a plurality of deposition processes, a plurality of patterning processes, and a plurality of planarization processes.

[0039] The device elements in the device portion 108 of the chip structure 102A can be interconnected through the interconnect structure 107A to form multiple integrated circuit devices, such as cache elements, global buffer elements, accumulator elements, local buffer elements, activation elements, pooling elements, input and / or output elements, etc.

[0040] The chip structure 102A can be a single semiconductor die, an integrated chip system (SoIC), and / or a package including one or more semiconductor dies that are sealed or protected. For an integrated chip system, multiple semiconductor dies (or chiplets) are stacked and bonded together to form electrical connections between these semiconductor dies. In some embodiments, the semiconductor die is a system-on-chip (SoC) chip that includes multiple functions. In some embodiments, the back side of the semiconductor die faces up, wherein the front side of the semiconductor die faces the redistribution structure RDL.

[0041] In some embodiments, a heat conducting layer 130A is formed on the chip structure 102A. Figure 1BAs shown in . The heat conductive layer 130A is used as a thermal interface material. The heat conductive layer 130A can be made of a polymer material including silicone resin or epoxy resin or include a polymer material including silicone resin or epoxy resin. The heat conductive layer 130A can also include particles dispersed in the polymer material. The particles can be made of dielectric particles such as aluminum oxide and / or zinc oxide, metal particles such as gold and / or silver, other suitable particles or combinations thereof or include dielectric particles such as aluminum oxide and / or zinc oxide, metal particles such as gold and / or silver, other suitable particles or combinations thereof.

[0042] In some other embodiments, the heat conducting layer 130A is made of or includes a solid material or a liquid material. The solid material may include tin (Sn), indium (In), bismuth (Bi), another suitable material, an alloy thereof, or a combination thereof. The liquid material may include gallium (Ga), an alloy thereof, or a resin material containing gallium (Ga) or an alloy thereof.

[0043] like Figure 1B As shown in , according to some embodiments, the chip structure (or chip-containing structure) 102B is bonded to the interposer chip 120 through a plurality of conductive connectors 112. The interposer chip 120 is further bonded to the redistribution structure RDL through a plurality of conductive connectors 104B. The conductive connectors 104B and 112 may include solder bumps. The solder bumps may include tin and other materials, such as copper, silver, gold, aluminum, lead, another suitable material, or a combination thereof. In some embodiments, the conductive connectors 104B and 112 are lead-free solder bumps. In some embodiments, each of the conductive connectors 104B is wider than each of the conductive connectors 112. In some embodiments, the spacing between the conductive connectors 104B is wider than the spacing between the conductive connectors 112.

[0044] In some embodiments, the chip structure 102B is a memory-containing chip structure, which includes a plurality of memory device elements. In some embodiments, the chip structure 102B includes a memory device, such as a dynamic random access memory (DRAM) device, a high bandwidth memory (HBM) device, etc. In some embodiments, the memory device element is a non-volatile memory element, such as a static random access memory (SRAM) element, a resistive random access memory (RRAM) element, a magnetoresistive random access memory (MRAM) element, etc.

[0045] A plurality of device elements are formed in the device portion 110 of the chip structure 102B. Examples of various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs)), or another suitable element. Various processes may be used to form various device elements, including deposition, etching, implantation, photolithography, annealing, and / or other suitable processes.

[0046] The chip structure 102B may be a single semiconductor die, a system on an integrated chip (SoIC), and / or a package including one or more semiconductor dies that are sealed or protected. For a system on an integrated chip, multiple semiconductor dies (or chiplets) are stacked and bonded together to form electrical connections between the semiconductor dies. In some embodiments, multiple memory dies are stacked to form a high bandwidth memory (HBM) chip structure.

[0047] In some embodiments, the interposer chip 120 includes a plurality of through substrate vias (TSVs) 122, such as Figure 1B As shown in . TSV 122 may be used to form an electrical connection between chip structure 102B and redistribution structure RDL. One or more dielectric layers may be formed to laterally surround each of TSV 122 to prevent short circuits between TSV 122.

[0048] In some embodiments, the interposer chip 120 includes one or more active devices 121 formed therein. The active devices 121 may be used to provide electrical communication between some devices of the chip structure 102A and some devices of the chip structure 102B. In some embodiments, one of the active devices is electrically connected to one or more memory devices of the chip structure 102B and one or more logic devices of the chip structure 102A through some of the conductive features of the redistribution structure RDL.

[0049] In some embodiments, the active device 121 formed in the interposer chip 120 includes an analog-to-digital converter (ADC) element, etc. The ADC element can be used to convert the analog signal from the chip structure 102B into a digital signal. Afterwards, the digital signal can be further transmitted to the chip structure 102A through the redistribution structure RDL for further operation. Due to the assistance of the active device 121 formed in the interposer chip 120 located nearby, a large number of electrical signals are operated by the active device 121 of the interposer chip 120, and are not directly transmitted to the chip structure 102A. Therefore, the operating speed is greatly improved. The heat generated during operation is also significantly reduced, which causes low operating temperature and high performance.

[0050] In some embodiments, a heat conducting layer 130B is formed on the chip structure 102B, such as Figure 1BAs shown in . The heat conductive layer 130B is used as a thermal interface material. The heat conductive layer 130B can be made of a polymer material including silicone resin or epoxy resin or include a polymer material including silicone resin or epoxy resin. The heat conductive layer 130B can also include particles dispersed in the polymer material. The particles can be made of dielectric particles such as aluminum oxide and / or zinc oxide, metal particles such as gold and / or silver, other suitable particles or combinations thereof or include dielectric particles such as aluminum oxide and / or zinc oxide, metal particles such as gold and / or silver, other suitable particles or combinations thereof.

[0051] In some other embodiments, the heat conducting layer 130B is made of or includes a solid material or a liquid material. The solid material may include tin (Sn), indium (In), bismuth (Bi), another suitable material, their alloys, or a combination thereof. The liquid material may include gallium (Ga), their alloys, or a resin material containing gallium (Ga) or their alloys.

[0052] like Figure 1C As shown in FIG. 1 , according to some embodiments, a protection layer 140 is formed over the redistribution structure RDL to laterally surround and protect the chip structures 102A and 102B and the interposer chip 120. In some embodiments, the protection layer 140 is in physical contact with the redistribution structure RDL.

[0053] In some embodiments, the protective layer 140 is made of or includes an insulating material such as a molding material. The molding material may include a polymer material such as an epoxy-based resin in which a filler is dispersed. The filler may include fibers (such as silica fibers and / or carbon-containing fibers), particles (such as silica particles and / or carbon-containing particles), or a combination thereof.

[0054] In some embodiments, a molding material, such as a liquid molding material, is introduced or injected to cover the redistribution structures RDL, the chip structures 102A and 102B, and the interposer chip 120. In some embodiments, a thermal process is then used to cure the liquid molding material and convert it into the protection layer 140.

[0055] In some embodiments, a planarization process is performed on the protective layer 140 to improve the planarity of the protective layer 140. For example, the planarization process may include a grinding process, a CMP process, a dry polishing process, one or more other applicable processes, or a combination thereof. In some embodiments, after the planarization process, the top surface of the protective layer 140 is substantially flush with the surfaces of the thermal conductive layers 130A and 130B.

[0056] like Figure 1DAs shown in FIG. 1 , according to some embodiments, a heat diffusion cap 150 is disposed over the protection layer 140 and the thermal conductive layers 130A and 130B. The heat diffusion cap 150 may help improve heat dissipation of the chip structures 102A and 102B to improve operation and reliability of the chip structures 102A and 102B.

[0057] The thermal diffusion cover 150 can be made of or include copper, nickel, aluminum, gold, silver, steel, another suitable material, or a combination thereof. In some embodiments, the thermal diffusion cover 150 has a body made of or including copper. The thermal diffusion cover 150 can also have one or more other layers coated on the body. For example, these layers can include an inner layer made of nickel and one or more outer layers made of gold and / or silver.

[0058] like Figure 1E As shown in , according to some embodiments, Figure 1D The structure shown in FIG. 1 is turned upside down and attached to a carrier tape 152. Thereafter, according to some embodiments, the carrier substrate 100 is removed, as shown in FIG. Figure 1E As shown in . Therefore, the surface of the redistribution structure RDL, which was originally covered by the carrier substrate 100 , is exposed.

[0059] Thereafter, according to some embodiments, a plurality of conductive connectors 160 are formed over the exposed surface of the redistribution structure RDL, such as Figure 1E . Conductive connector 160 may include solder bumps. Solder bumps may include tin and other materials, such as copper, silver, gold, aluminum, lead, other suitable materials, or combinations thereof. In some embodiments, conductive connector 160 is a lead-free solder bump. In some embodiments, each of conductive connector 160 is wider than each of conductive connectors 104A and 104B. In some embodiments, the spacing between conductive connectors 160 is wider than the spacing between conductive connectors 104A or 104B.

[0060] In some embodiments, a singulation process (eg, sawing, etc.) is then used to separate Figure 1E The structure shown in is cut into a plurality of package structures. According to some embodiments, after the sawing process, one of the package structures is picked up from the carrier tape 152 and turned upside down, such as Figure 1F The structure is then bonded to a substrate 170 via a conductive connector 160, as shown in FIG. Figure 1F In some other embodiments, the heat diffusion cap 150 is disposed over the chip structures 102A and 102B after being bonded to the substrate 170 .

[0061] However, the embodiments of the present disclosure are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the sawing process is not performed to separate the Figure 1E The structure in the wafer level package is separated into a plurality of smaller die packages. The entirety of the wafer level package structure can be directly integrated into a large package structure without cutting. In addition, in some embodiments, the heat diffusion cap 150 can be attached after the singulation process.

[0062] Substrate 170 may be a circuit substrate (or packaging substrate). In some embodiments, substrate 170 includes a core portion. Substrate 170 may also include a plurality of insulating layers and a plurality of conductive components. The conductive components may be used to route electrical signals between opposite sides of substrate 170. The insulating layers may be made of or include one or more polymer materials. The conductive components may be made of or include copper, aluminum, cobalt, tungsten, gold, one or more other suitable materials, or a combination thereof.

[0063] The core portion of substrate 170 may include an organic material, such as a material that can be easily laminated. In some embodiments, the core portion may include a single-sided or double-sided copper clad laminate, epoxy, resin, fiberglass, molding compound, plastic (such as polyvinyl chloride (PVC), acrylonitrile, butadiene and styrene (ABS), polypropylene (PP), polyethylene (PE), polystyrene (PS), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyphenylene sulfide (PPS)), one or more other suitable elements, or a combination thereof. Conductive vias may extend through the core portion to provide electrical connections between elements disposed on either side of the core portion.

[0064] In some embodiments, substrate 170 further includes a bonding structure 172. In some embodiments, bonding structure 172 is a solder bump. In some embodiments, bonding structure 172 is used to bond to another component such as a printed circuit board.

[0065] In some embodiments, the bonding structures 172 are lead-free solder bumps. In some embodiments, each of the bonding structures 172 is wider than each of the conductive connectors 160. In some embodiments, the spacing between the bonding structures 172 is wider than the spacing between the conductive connectors 160.

[0066] like Figure 1F As shown in FIG. 1 , in some embodiments, the operating heat generated during the operation of chip structures 102A and 102B is significantly reduced due to the assistance of active devices 121 formed in interposer chip 120 , thereby greatly improving the performance and reliability of the package structure.

[0067] Many variations and / or modifications may be made to the embodiments of the present disclosure.In some other embodiments, one or more local interconnect chips are used to improve the interconnection between chip structures 102A and 102B.

[0068] Figures 2A to 2G is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. Figure 2A As shown in Figure 1A According to some embodiments, a redistribution structure RDL1 is formed over a carrier substrate 100. The material and formation method of the redistribution structure RDL1 may be the same as Figure 1A The redistribution structures RDL shown in FIG. 1 are the same as or similar to those Figure 1A Those of the redistribution structure RDL shown in .

[0069] like Figure 2B As shown in , according to some embodiments, a local interconnect chip 202 (e.g., a local silicon interconnect (LSI), etc.) is disposed above the redistribution structure RDL1. The local interconnect chip 202 may be used to receive electrical signals from other chip structures to be disposed later and / or to transmit electrical signals to other chip structures to be disposed later. In some embodiments, the local interconnect chip 202 does not have active devices formed therein. In some other embodiments, the local interconnect chip 202 includes active devices and / or passive devices formed therein.

[0070] In some embodiments, the local interconnect chip 202 includes a semiconductor substrate portion 204 and a plurality of conductive features 206. In some embodiments, the conductive features 206 include through-substrate vias. In some embodiments, the local interconnect chip 202 also includes conductive lines that provide electrical connections between some of the through-substrate vias. In some embodiments, one or more dielectric layers are formed to laterally surround the conductive features 206 to prevent short circuits between the conductive features 206.

[0071] like Figure 2C As shown in FIG. 1 , according to some embodiments, a protection layer 240 is formed over the redistribution structure RDL1 to laterally surround the local interconnect chip 202. The material and formation method of the protection layer 240 may be the same as Figure 1C The protective layer 140 shown in FIG. 1 is the same as or similar to that of Figure 1C Those of the protective layer 140 shown in .

[0072] like Figure 2D As shown in FIG. 2 , according to some embodiments, a redistribution structure RDL2 is formed over the protection layer 240 and the local interconnection chip 202. The material and formation method of the redistribution structure RDL2 may be the same as Figure 1A The redistribution structures RDL shown in FIG. 1 are the same as or similar to those Figure 1A Some of the conductive features of the redistribution structure RDL2 are electrically connected to some of the conductive features 206 of the local interconnect chip 202 .

[0073] like Figure 2E As shown in Figure 1B According to some embodiments, the chip structure 102A and the interposer chip 120 carrying the chip structure 102B are bonded to the redistribution structure RDL2. In some embodiments, the top surfaces of the chip structures 102A and 102B are substantially flush. In some embodiments, the top surfaces of the thermal conductive layers 130A and 130B are substantially flush.

[0074] In some embodiments, local interconnect chip 202 extends across adjacent sidewalls of chip structures 102A and 102B, such as Figure 2E . In some embodiments, local interconnect chip 202 extends across the gap between chip structures 102A and 102B. In some embodiments, local interconnect chip 202 extends across the gap between chip structure 102A and interposer chip 120. In some embodiments, electrical communication between chip structure 102A and interposer chip 120 (and chip structure 102B thereon) is improved due to local interconnect chip 202.

[0075] like Figure 2F As shown in FIG. 1 , according to some embodiments, a protection layer 140 is formed over the redistribution structure RDL2 to laterally surround and protect the interposer chip 120 and the chip structures 102A and 102B. The material and formation method of the protection layer 140 may be the same as Figure 1C The protective layer 140 shown in FIG. 1 is the same as or similar to that of Figure 1C Those of the protective layer 140 shown in .

[0076] Afterwards, similar to Figure 1D According to some embodiments, the thermal diffusion cover 150 is disposed above the thermally conductive layers 130A and 130B, such as Figure 2F The heat diffusion cover 150 extends across the opposite sidewalls of the chip structure 102A, the opposite sidewalls of the second chip structure 102B, and the opposite sidewalls of the interposer chip 120. Figure 1F As discussed, a singulation process may be performed to separate the individual package structures.The heat diffusion cap 150 may be attached before or after the singulation process.

[0077] like Figure 2G As shown in Figure 1E to Figure 1FAccording to some embodiments, the carrier substrate 100 is removed and the redistribution structure RDL1 is bonded to the substrate 270 through a plurality of conductive connectors 260. The conductive connectors 260 may be connected to the substrate 270. Figure 1E to Figure 1F The conductive connector 160 shown in FIG. Figure 1E to Figure 1F The conductive connector 160 is shown in FIG.

[0078] The substrate 270 may be Figure 1F The substrate 170 shown in FIG. Figure 1F . Similar to substrate 170, substrate 270 includes a plurality of bonding structures 272. In some embodiments, bonding structures 272 are solder bumps. In some embodiments, bonding structures 272 are used to bond with another component such as a printed circuit board.

[0079] In some embodiments, chip structure 102B is substantially as wide as interposer chip 120. However, embodiments of the present disclosure are not limited thereto. Many variations and / or modifications may be made to embodiments of the present disclosure. In some other embodiments, chip structure 102B and interposer chip 120 have different widths.

[0080] Figure 3 1 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, interposer chip 120 is wider than chip structure 102B. In some embodiments, dummy chip 302 is disposed above interposer chip 120. In some embodiments, dummy chip 302 has no active devices. Dummy chip 302 is spaced apart from chip structure 102B. In some embodiments, a top surface of dummy chip 302 is substantially flush with a top surface of chip structure 102B.

[0081] In some embodiments, a protection layer 304 is formed over the interposer chip 120 to laterally surround and protect the dummy chip 302 and the chip structure 102B. The material and formation method of the protection layer 304 may be the same as or similar to those of the protection layer 140. The protection layer 304 fills the gap between the dummy chip 302 and the chip structure 102B.

[0082] Fig. 10A and Fig. 10B is a cross-sectional view of a portion of a package structure according to some embodiments. Fig. 10A A cross-sectional view of a dummy chip 302 is shown in accordance with some embodiments. Fig. 10B A cross-sectional view of a dummy chip 302 according to some other embodiments is shown.

[0083] In some embodiments, the dummy chip 302 includes a semiconductor block, such as a silicon block. Figure 3 and Fig. 10AIn some other embodiments, a plurality of thermal vias 1002 are formed in the dummy chip 302. The thermal vias 1002 can help reduce the stress of the dummy chip 302 and help improve the heat dissipation of the package structure. Therefore, the performance and reliability of the package structure can be improved.

[0084] In some embodiments, the thermal via 1002 is in direct contact with the dummy chip 302. No dielectric layer is formed between the dummy chip 302 and the thermal via 1002. The thermal via 1002 may be made of or include copper, aluminum, tungsten, cobalt, another suitable material, or a combination thereof.

[0085] In some embodiments, the chip structure 102A and the interposer chip 120 are bonded to a redistribution structure including a plurality of polymer-containing insulating layers and a plurality of conductive components. However, the embodiments of the present disclosure are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the chip structure 102A and the interposer chip 120 are bonded to a semiconductor interposer.

[0086] Figure 4 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, chip structure 102A and interposer chip 120 carrying chip structure 102B are bonded to semiconductor interposer 402. Semiconductor interposer 402 may include semiconductor substrate 404 and a plurality of conductive features 406.

[0087] The semiconductor substrate 404 may be made of or include silicon. The conductive features 406 may include through substrate vias (TSVs) penetrating the semiconductor substrate 404. In some embodiments, one or more dielectric layers surrounding the conductive features 406 are used to prevent short circuits between the conductive features 406.

[0088] In some embodiments, an interconnect structure is formed over opposing surfaces of the semiconductor substrate 404. The interconnect structure may include a plurality of dielectric layers and a plurality of conductive features.

[0089] In some embodiments, chip structure 102B is bonded to interposer chip 120 via tin-containing solder bumps. However, embodiments of the present disclosure are not limited thereto. Many variations and / or modifications may be made to embodiments of the present disclosure. In some other embodiments, chip structure 102B is bonded to interposer chip 120 via dielectric-to-dielectric bonding and metal-to-metal bonding.

[0090] Figure 5is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, the interposer chip 120 further includes a plurality of metal bonding structures 504 and a dielectric bonding structure 502 surrounding the metal bonding structures 504. In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process is used to ensure that the top surfaces of the metal bonding structures 504 and the top surfaces of the dielectric bonding structures 502 are substantially coplanar. The planarization process can help provide the interposer chip 120 with a highly planarized bonding surface.

[0091] In some embodiments, the chip structure 102B further includes a plurality of metal bonding structures 508 and a dielectric bonding structure 506 surrounding the metal bonding structures 508. In some embodiments, a planarization process such as a CMP process is used to ensure that the top surfaces of the metal bonding structures 508 and the top surfaces of the dielectric bonding structures 506 are substantially coplanar. The planarization process can help provide the chip structure 102B with a highly planarized bonding surface.

[0092] In some embodiments, chip structure 102B is placed directly on interposer chip 120. Therefore, dielectric bonding structures 502 and 506 are in direct contact with each other and bonded to each other. Metal bonding structures 504 and 508 are in direct contact with each other.

[0093] As mentioned above, before placing chip structure 102B, a planarization process is performed to provide a highly planarized bonding surface for chip structure 102B and interposer chip 120. In some embodiments, there is no gap between dielectric bonding structures 502 and 506. In some embodiments, there is no gap between metal bonding structures 504 and 508. In some embodiments, a thermal operation is then used to enhance the bonding between metal bonding structures 504 and 508. The temperature of the thermal operation can be in a range from about 100 degrees Celsius to about 700 degrees Celsius.

[0094] Due to the dielectric-to-dielectric bonding and the metal-to-metal bonding, the electrical connection between the chip structure 102B and the interposer chip 120 is significantly improved. The performance and reliability of the package structure are also improved.

[0095] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 6 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 6 As shown in Figure 2G In some embodiments, similar to the packaging structure shown in Figure 5In the embodiment shown in , the chip structure 102B and the interposer chip 120 are directly bonded together via dielectric-to-dielectric bonding (eg, bonding between dielectric bonding structures 502 and 506 ) and metal-to-metal bonding (eg, bonding between metal bonding structures 504 and 508 ).

[0096] Figure 7 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, Figure 7 Shows Figure 6 104B. In some embodiments, the interposer chip 120 includes an interconnect structure 702 having a plurality of dielectric layers and a plurality of conductive features. The conductive features of the interconnect structure 702 form an electrical connection between the TSV 122 and the conductive connector 104B. In some embodiments, the metal bonding structure 504 of the interposer chip 120 is electrically connected to the TSV 122.

[0097] In some embodiments, the interposer chip 120 further includes a plurality of dummy metal bonding pads 704 laterally surrounded by the dielectric bonding structure 502. In some embodiments, the dummy metal bonding pads 704 are not electrically connected to other device elements.

[0098] In some embodiments, the chip structure 102B further includes a plurality of conductive vias 508V and a plurality of metal bonding pads 508P. The conductive vias 508V and the metal bonding pads 508P together form a plurality of metal bonding structures. In some embodiments, the metal bonding pads 508P are electrically connected to device elements (such as memory device elements) of the chip structure 102B through the conductive vias 508V.

[0099] In some embodiments, the chip structure 102B further includes a plurality of pseudo metal bonding pads 706P and pseudo conductive vias 706V that are laterally surrounded by the dielectric bonding structure 506. The pseudo metal bonding pads 706P and the pseudo conductive vias 706V together form a plurality of pseudo metal bonding structures. In some embodiments, the pseudo metal bonding pads 706P are not electrically connected to other device components. The pseudo metal bonding pads 704 and 706P are used to enhance the bonding between the interposer chip 120 and the chip structure 102B. In some embodiments, the pseudo metal bonding pads 704 and 706P are not used for signal transmission.

[0100] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 8 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 8 As shown in Figure 3 In some embodiments, similar to the packaging structure shown in Figure 5In the embodiment shown in , the chip structure 102B and the interposer chip 120 are directly bonded together through dielectric-to-dielectric bonding (e.g., bonding between dielectric bonding structures 502 and 506) and metal-to-metal bonding (e.g., bonding between metal bonding structures 504 and 508). In some embodiments, the dummy chip 302 is directly bonded to some of the dielectric bonding structures 502 and the metal bonding structures 504 of the interposer chip 120.

[0101] Many variations and / or modifications may be made to the embodiments of the present disclosure. Fig. 9 is a cross-sectional view of a portion of a package structure according to some embodiments. Fig. 9 As shown in Figure 4 In some embodiments, similar to the packaging structure shown in Figure 5 In the embodiment shown in , the chip structure 102B and the interposer chip 120 are directly bonded together via dielectric-to-dielectric bonding (eg, bonding between dielectric bonding structures 502 and 506 ) and metal-to-metal bonding (eg, bonding between metal bonding structures 504 and 508 ).

[0102] In some embodiments, there is a dummy chip 302 formed between the interposer chip 120 and the thermal diffusion cover 150. However, the embodiments of the present disclosure are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, two or more dummy chips are disposed next to the chip structure 102B.

[0103] Fig.11 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, dummy chips 302A and 302B are formed next to chip structure 102B. In some embodiments, similar to Fig. 10B In the embodiment shown in FIG. 1 , a plurality of thermal conductive vias 1002 are formed in the dummy chips 302A and 302B. The dummy chips 302A and 302B can further improve the heat dissipation of the package structure.

[0104] In some embodiments, chip structure 102A and / or chip structure 102B include a semiconductor substrate portion. However, the embodiments of the present disclosure are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, chip structure 102A and / or chip structure 102B do not have a semiconductor substrate portion.

[0105] Fig.12 is a cross-sectional view of a portion of a package structure according to some embodiments. Fig.12 As shown in Figure 6In some embodiments, the chip structure 102A includes interconnect structures 107A and 107B formed on opposite surfaces of the device portion 108. The interconnect structures 107A and 107B can be used as a front-side interconnect structure and a back-side interconnect structure, respectively. In some embodiments, the chip structure 102A does not include a semiconductor substrate portion. Therefore, heat dissipation of device elements in the device portion 108 can become easier. The performance and reliability of the package structure are improved.

[0106] Embodiments of the present disclosure form a packaging structure having a first chip-containing structure and an interposer chip carrying a second chip-containing structure. The first chip-containing structure and the interposer chip are bonded to a redistribution structure, which may be a polymer-containing redistribution structure or a semiconductor interposer. The interposer chip may include one or more active devices. The active devices may be used to provide electrical communication between some devices (such as logic devices) of the first chip-containing structure and some devices (such as memory devices) of the second chip-containing structure. Due to the assistance of the active devices formed in the interposer chip, a large number of electrical signals are operated by the active devices of the interposer chip instead of being directly transmitted to the first chip-containing structure. Therefore, the operating speed is greatly improved. The heat generated during operation is also significantly reduced, which causes a low operating temperature. Therefore, the performance and reliability of the packaging structure are greatly improved.

[0107] According to some embodiments, a package structure is provided. The package structure includes a chip-containing structure bonded to a redistribution structure through a plurality of first solder bumps. The package structure also includes a memory-containing structure bonded to an interposer chip. The interposer chip is bonded to the redistribution structure through a plurality of second solder bumps. The package structure also includes a substrate, and the redistribution structure is located above the substrate.

[0108] According to some embodiments, a package structure is provided. The package structure includes a first chip-containing structure bonded to a redistribution structure and an interposer chip bonded to the redistribution structure. The interposer chip has active devices. The package structure also includes a second chip-containing structure bonded to the interposer chip. The active devices of the interposer chip provide electrical communication between the first chip-containing structure and the second chip-containing structure.

[0109] According to some embodiments, a method for forming a package structure is provided. The method includes: forming a redistribution structure above a carrier substrate; and bonding a first chip-containing structure to the redistribution structure. The method also includes: bonding a second chip-containing structure to an interposer chip, and the interposer chip has active devices. The method also includes: bonding the interposer chip to the redistribution structure. The active devices of the interposer chip provide electrical communication between the first chip-containing structure and the second chip-containing structure.

[0110] Some embodiments of the present application provide a packaging structure, including: a substrate; a redistribution structure located above the substrate; a chip-containing structure joined to the redistribution structure via a plurality of first solder bumps; an interposer chip joined to the redistribution structure via a plurality of second solder bumps; and a memory-containing structure joined to the interposer chip.

[0111] In some embodiments, the interposer chip includes an active device. In some embodiments, the active device provides electrical communication between the chip-containing structure and the memory-containing structure. In some embodiments, the interposer chip includes a plurality of substrate through-vias. In some embodiments, the redistribution structure includes a plurality of conductive components surrounded by a plurality of polymer-containing insulating layers. In some embodiments, the package structure further includes: a thermal diffusion cover extending across opposite sidewalls of the chip-containing structure and opposite sidewalls of the memory-containing structure; a first thermally conductive layer located between the thermal diffusion cover and the chip-containing structure; and a second thermally conductive layer located between the thermal diffusion cover and the memory-containing structure. In some embodiments, the package structure further includes: a molding layer located between the thermal diffusion cover and the redistribution structure, wherein the molding layer laterally surrounds the chip-containing structure, the memory-containing structure, and the interposer chip. In some embodiments, the memory-containing structure has a plurality of first metal bonding structures and a first dielectric bonding structure laterally surrounding the first metal bonding structure, the surface of the first metal bonding structure and the surface of the first dielectric bonding structure are substantially coplanar, the interposer chip has a plurality of second metal bonding structures and a second dielectric bonding structure laterally surrounding the second metal bonding structure, the surface of the second metal bonding structure and the surface of the second dielectric bonding structure are substantially coplanar, the first metal bonding structure and the second metal bonding structure are in direct contact with each other, and the first dielectric bonding structure and the second dielectric bonding structure are in direct contact with each other. In some embodiments, the packaging structure further includes: a dummy chip located above the interposer chip, wherein the dummy chip has no active devices, and the top of the dummy chip is substantially flush with the top of the memory-containing structure. In some embodiments, the packaging structure further includes: a plurality of thermal vias located within the dummy chip.

[0112] Other embodiments of the present application provide a packaging structure, including: a first chip-containing structure bonded to a redistribution structure; an interposer chip bonded to the redistribution structure, wherein the interposer chip has active devices; and a second chip-containing structure bonded to the interposer chip.

[0113] In some embodiments, the interposer chip is wider than the second chip-containing structure. In some embodiments, the package structure further comprises: a heat diffusion cover extending across opposite sidewalls of the first chip-containing structure, opposite sidewalls of the second chip-containing structure, and opposite sidewalls of the interposer chip; and a protective layer located between the heat diffusion cover and the redistribution structure, wherein the protective layer laterally surrounds the first chip-containing structure, the second chip-containing structure, and the interposer chip. In some embodiments, the second chip-containing structure has a plurality of first metal bonding structures and a first dielectric bonding structure laterally surrounding the first metal bonding structure, the surface of the first metal bonding structure and the surface of the first dielectric bonding structure are substantially coplanar, the interposer chip has a plurality of second metal bonding structures and a second dielectric bonding structure laterally surrounding the second metal bonding structure, the surface of the second metal bonding structure and the surface of the second dielectric bonding structure are substantially coplanar, the first metal bonding structure and the second metal bonding structure are directly bonded together, and the first dielectric bonding structure and the second dielectric bonding structure are directly bonded together. In some embodiments, the packaging structure also includes: a second redistribution structure located below the redistribution structure; a local interconnect chip located between the redistribution structure and the second redistribution structure, wherein the local interconnect chip extends across a gap between the first chip-containing structure and the interposer chip; and a molding layer located between the redistribution structure and the second redistribution structure, wherein the molding layer laterally surrounds the local interconnect chip.

[0114] Some other embodiments of the present application provide a method for forming a package structure, comprising: forming a redistribution structure above a carrier substrate; bonding a first chip-containing structure to the redistribution structure; bonding a second chip-containing structure to an interposer chip, wherein the interposer chip has active devices; and bonding the interposer chip to the redistribution structure. In some embodiments, the method for forming a package structure further comprises: providing a heat diffusion cap above the first chip-containing structure and the second chip-containing structure.

[0115] In some embodiments, the method further comprises: removing the carrier substrate; and bonding the redistribution structure to the substrate through a plurality of tin-containing solder bumps. In some embodiments, the method further comprises: before forming the redistribution structure, forming a lower redistribution structure above the carrier substrate; disposing a local interconnect chip above the lower redistribution structure; forming a molding layer above the lower redistribution structure to laterally surround the local interconnect chip; and forming the redistribution structure above the molding layer and the local interconnect chip. In some embodiments, the second chip-containing structure has a plurality of first metal bonding structures and a first dielectric bonding structure laterally surrounding the first metal bonding structure, the surface of the first metal bonding structure and the surface of the first dielectric bonding structure are substantially coplanar, the interposer chip has a plurality of second metal bonding structures and a second dielectric bonding structure laterally surrounding the second metal bonding structure, the surface of the second metal bonding structure and the surface of the second dielectric bonding structure are substantially coplanar, the first metal bonding structure and the second metal bonding structure are directly bonded together, and the first dielectric bonding structure and the second dielectric bonding structure are directly bonded together.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A packaging structure, comprising: substrate; a redistribution structure located above the substrate; A chip-containing structure bonded to the redistribution structure via a plurality of first solder bumps; an interposer chip bonded to the redistribution structure via a plurality of second solder bumps; as well as The memory structure is bonded to the interposer chip.

2. The packaging structure according to claim 1, wherein: The interposer chip includes active devices.

3. The packaging structure according to claim 2, wherein: The active device provides electrical communication between the chip-containing structure and the memory-containing structure.

4. The packaging structure according to claim 1, wherein: The interposer chip includes a plurality of through substrate vias.

5. The packaging structure according to claim 1, wherein: The redistribution structure includes a plurality of conductive features surrounded by a plurality of polymer-containing insulating layers.

6. The package structure according to claim 1, further comprising: a heat diffusion cover extending across opposite sidewalls of the chip-containing structure and opposite sidewalls of the memory-containing structure; a first heat-conducting layer, located between the heat diffusion cover and the chip-containing structure; as well as A second heat conducting layer is located between the heat diffusion cover and the memory containing structure.

7. The packaging structure according to claim 6, further comprising: A molding layer is located between the heat diffusion cover and the redistribution structure, wherein the molding layer laterally surrounds the chip-containing structure, the memory-containing structure and the interposer chip.

8. The package structure according to claim 1, wherein: The memory-containing structure has a plurality of first metal bonding structures and a first dielectric bonding structure laterally surrounding the first metal bonding structures, a surface of the first metallic bonding structure and a surface of the first dielectric bonding structure are substantially coplanar, The interposer chip has a plurality of second metal bonding structures and a second dielectric bonding structure laterally surrounding the second metal bonding structures. a surface of the second metallic bonding structure and a surface of the second dielectric bonding structure are substantially coplanar, The first metal bonding structure and the second metal bonding structure are in direct contact with each other, and The first dielectric bonding structure and the second dielectric bonding structure are in direct contact with each other.

9. A packaging structure, comprising: A first chip-containing structure bonded to a redistribution structure; an interposer chip bonded to the redistribution structure, wherein the interposer chip has active devices; as well as The second chip-containing structure is bonded to the interposer chip.

10. A method for forming a package structure, comprising: forming a redistribution structure over a carrier substrate; bonding a first chip-containing structure to the redistribution structure; bonding a second chip-containing structure to an interposer chip, wherein the interposer chip has active devices; and The interposer chip is bonded to the redistribution structure.

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