A package stacking structure of SOC and memory chip

Abstract

This invention discloses a packaging and stacking structure for a System-on-a-Chip (SoC) and a memory chip, which improves speed and capacity, reduces size, and achieves thinness, high density, and high speed. It includes: a PCB board; an SoC chip module comprising several SoC chips and a first molding compound; an LPDDR chip module comprising several memory chips, an adapter board, and a second molding compound; a UFS chip module comprising a main control chip, several stacked flash memory chips, a flash memory chip substrate, and a third molding compound; and a composite substrate.

Description

Technical Field

[0001] This invention relates to the technical field of chip packaging, specifically to a packaging stacking structure for a System-on-a-Chip (SoC) and a memory chip. Background Technology

[0002] As mobile terminal products such as smartphones become thinner, lighter, denser, and have higher capacity and speed requirements, the existing mobile phone SoC chip and memory chip are two independent products. These chips are soldered onto the PCB board using SMT technology. This will cause delays and affect the response speed of mobile terminals such as smartphones. Therefore, there is an urgent need to develop a new packaging structure that can reduce size and thinness while improving speed and capacity, so as to enable it to have high density and high speed. Summary of the Invention

[0003] To address the aforementioned issues, this invention provides a packaging and stacking structure for SOC and memory chips that improves speed and capacity, reduces size, and achieves thinness, high density, and high speed.

[0004] A packaged stacking structure for a System-on-a-Chip (SoC) and a memory chip, characterized in that it comprises:

[0005] PCB board;

[0006] SOC chip module, which includes several SOC chips and a first molding compound;

[0007] An LPDDR chip module includes several memory chips, an adapter board, and a second plastic package.

[0008] The UFS chip module includes a main control chip, several stacked flash memory chips, a flash memory chip substrate, and a third molding compound.

[0009] And a sealed substrate;

[0010] One surface of the encapsulated substrate is connected to a plurality of memory chips via the second molding compound. The other surface, formed by the combination of the plurality of memory chips, is provided with the adapter board. The central region of the other surface of the encapsulated substrate is connected to the corresponding SOC chip bump of the SOC chip. The outer periphery of the other surface of the encapsulated substrate is connected to the first protruding solder ball of the PCB board. The surface of the adapter board facing away from the memory chips is provided with a second protruding solder ball. The exposed surface of the flash memory chip substrate is connected to the second protruding solder ball. A main control chip and a plurality of stacked flash memory chips are encapsulated within the third molding compound of the flash memory chip substrate.

[0011] Its further features are:

[0012] The first opening is pre-set on the encapsulation substrate using the TMV process. Then, the SOC chip module and LPDDR chip module are encapsulated on the encapsulation substrate using a double-sided molding process. After that, the TMV process is used to create the second and third openings on the double sides of the entire structure, so that the entire structure has channels or lines for connection with the PCB board and flash memory chip substrate. The chips in the SOC chip module and LPDDR chip module are interconnected, thereby improving the response speed of the mobile terminal.

[0013] Several memory chips include stacked memory chip groups arranged in two columns. The two stacked memory chip groups have the same height, and the memory chips in each stacked memory chip group are stacked in a staggered manner and connected by gold wires.

[0014] The main control chip is located on one side of the surface area of ​​the flash memory chip substrate, and a plurality of stacked flash memory chips are located on the other side of the surface area of ​​the flash memory chip substrate. The flash memory chips of the plurality of stacked flash memory chips are stacked in a staggered manner and connected by gold wires.

[0015] The adapter board is supported on a surface of equal height formed by two stacked memory chip groups. The adapter board is connected to one of the stacked memory chip groups by gold wire. The flash memory chip substrate is provided with a fourth opening through TMV process. The lines in the fourth opening are connected to the raised second solder ball of the adapter board, indirectly connecting the main control chip and several stacked flash memory chips to the PCB board.

[0016] Preferably, the raised second solder ball is provided with a second opening at the corresponding position of the second molding compound to ensure a reliable connection between the raised second solder ball and the corresponding line of the flash memory chip substrate;

[0017] The encapsulated substrate connects the SOC chip module and the LPDDR chip module to the raised first solder ball on the PCB board through the lines set by the first and third openings, ensuring the interconnection of the two sets of chips.

[0018] By employing this invention, the SOC chip and the memory chips of the LPDDR chip module are encapsulated using a double-sided molding process. After molding, double-sided TMV openings are made, and then the UFS chip module is SMT soldered onto the adapter board of the LPDDR chip module. Finally, the entire structure is SMT soldered onto the PCB board, realizing the PoP structure of the SOC and Memory products, improving product operating speed and reducing size. Furthermore, several SOC chips and memory chips from the LPDDR chip module are encapsulated on both sides of the encapsulation substrate using a double-sided molding process, interconnecting the chips within the SOC chip module and the LPDDR chip module, thereby improving the response speed of the mobile terminal. In summary, it improves speed and capacity, reduces size, and achieves thinness, high density, and high speed. Attached Figure Description

[0019] Figure 1 This is a simplified schematic diagram of the packaging structure corresponding to the present invention;

[0020] The names corresponding to the serial numbers in the diagram are as follows:

[0021] PCB board 10, raised first solder ball 11, SOC chip module 20, SOC chip 21, first molding compound 22, SOC chip bump 23, LPDDR chip module 30, stacked memory chipset 301, first gold wire 302, third gold wire 303, memory chip 31, adapter board 32, second molding compound 33, raised second solder ball 34, UFS chip module 40, second gold wire 401, fourth opening 402, main control chip 41, flash memory chip 42, flash memory chip substrate 43, third molding compound 44, encapsulated substrate 50, first opening 51, second opening 52, third opening 53. Detailed Implementation

[0022] A packaging stacking structure for a SoC and a memory chip, see Figure 1 It includes a PCB board 10, a SOC chip module 20, an LPDDR chip module 30, a UFS chip module 40, and a composite substrate 50.

[0023] A raised first solder ball 11 is provided on the outer periphery of the upper surface of the PCB board 10;

[0024] SOC chip module 20 includes several SOC chips 21 and a first molding compound 22. Each group of SOC chips 21 is provided with an SOC chip bump 23.

[0025] The LPDDR chip module 30 includes several memory chips 31, an adapter board 32, and a second molding compound 33;

[0026] UFS chip module 40 includes a main control chip 41, a plurality of stacked flash memory chips 42, a flash memory chip substrate 43, and a third molding compound 44;

[0027] Before encapsulation, the encapsulated substrate 50 is pre-formed with a first opening 51 using the TMV process. The first opening 51 contains corresponding circuits and plating. One surface of the encapsulated substrate 50 is encapsulated and connected to several memory chips 31 through a second molding compound 33, and the second molding compound also encapsulates an adapter board 32. The other surface formed by the combination of several memory chips 31 is provided with the adapter board 32. The central area of ​​the other surface of the encapsulated substrate 50 is encapsulated with several SOC chips through a first molding compound. Each group of SOC chips is connected to the corresponding circuit or plating of the encapsulated substrate 50 via a corresponding SOC chip bump 23. The outer periphery of the other surface of the encapsulated substrate 50 is connected to the raised first solder ball 11 of the PCB board 10. The surface of the adapter board 32 facing away from the memory chip 31 is provided with a raised second solder ball 34. The exposed surface of the flash memory chip substrate 43 is connected to the raised second solder ball 34. The third molding compound 44 of the flash memory chip substrate 43 encapsulates a main control chip 41 and several stacked flash memory chips 42.

[0028] In specific implementation, the first opening 51 is pre-set on the encapsulation substrate 50 using the TMV process. Then, the part of the SOC chip module 20 and the LPDDR chip module 30 without the plastic encapsulation body is encapsulated on the encapsulation substrate 50 using a double-sided plastic encapsulation method. Then, the TMV process is used to open the double sides of the entire mechanism to form the second opening 52 and the third opening 53, so that the entire mechanism has a channel or line to connect with the PCB board 10 and the flash memory chip substrate 43, and the chips in the SOC chip module 20 and the LPDDR chip module 30 are interconnected, thereby improving the response speed of the mobile terminal.

[0029] The plurality of memory chips 31 include stacked memory chip groups 301 arranged in two columns. The two stacked memory chip groups 301 have the same height, and the memory chips 31 in each stacked memory chip group 301 are stacked in a staggered manner and connected by a first gold wire 302.

[0030] The main control chip 41 is located on one side of the surface area of ​​the flash memory chip substrate 43, and a plurality of stacked flash memory chips 42 are located on the other side of the surface area of ​​the flash memory chip substrate 43. The flash memory chips of the plurality of stacked flash memory chips 42 are stacked in a staggered manner and connected by a second gold wire 401.

[0031] The adapter board 32 is supported on the same height surface formed by two stacked memory chip groups 301. The adapter board 32 is connected to one of the stacked memory chip groups 301 through the third gold wire 303. The flash memory chip substrate 43 is provided with a fourth opening 402 through TMV process. The lines in the fourth opening 402 are connected to the raised second solder ball 34 of the adapter board 32, and the main control chip 41 and several stacked flash memory chips 42 are indirectly connected to the PCB board 10.

[0032] In specific implementation, the second opening 52 corresponds to the corresponding position of the raised second solder ball 34 and the second molding compound, ensuring a reliable connection between the raised second solder ball 34 and the corresponding line of the flash memory chip substrate 43;

[0033] The sealing substrate 50 connects the SOC chip module 20 and the LPDDR chip module 30 to the raised first solder ball 11 on the PCB board 10 through the lines set by the first opening 51 and the third opening 53, ensuring the interconnection of the two sets of chips.

[0034] Its manufacturing principle is as follows: The memory chip and SOC chip of the LPDDR chip module are interconnected through a multi-layer encapsulation substrate, and the first encapsulation body and the second encapsulation body are formed through double-sided molding process, so that the two form an integrated structure. Then, holes are opened on the surface of the encapsulation substrate and the second encapsulation body through TMV process, so that the integrated structure has channels or lines for connection with PCB board and flash memory chip substrate.

[0035] The UFS chip module is also packaged independently. The flash memory chip substrate is opened through TMV process, and then the UFS chip module 40 is SMT soldered on the exposed second solder ball of the adapter board. Then, the SOC chip module 20, LPDDR chip module 30, UFS chip module 40 and encapsulation substrate 50 are combined to form an overall structure and are SMT soldered on the first solder ball 11 of the PCB board to realize the PoP structure of SOC and memory products.

[0036] The SOC chip and the memory chip of the LPDDR chip module are encapsulated using double-sided plastic encapsulation. After encapsulation, double-sided TMV openings are made. Then, the UFS chip module is SMT soldered from the adapter board of the LPDDR chip module. Finally, the entire structure is SMT soldered to the PCB board to realize the PoP structure of the SOC and Memory products, improve the product's operating speed, and reduce its size.

[0037] Several SOC chips and memory chips from LPDDR chip modules are encapsulated on both sides of a composite substrate using a double-sided molding process. The chips within the SOC chip module and the LPDDR chip module are interconnected, thereby improving the response speed of the mobile terminal.

[0038] Furthermore, the LPDDR chip module and the UFS chip module are packaged independently, resulting in higher packaging and testing yields. Combining the two products into a finished product yields even higher yields. At the same time, the UFS chips corresponding to the UFS chip module will not be lost. The two modules are packaged and tested independently before being mixed and packaged, resulting in higher packaging yields and thus reducing costs.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0040] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A packaging and stacking structure for a System-on-a-Chip (SOC) and a memory chip, characterized in that, It includes: PCB board; SOC chip module, which includes several SOC chips and a first molding compound; An LPDDR chip module includes several memory chips, an adapter board, and a second plastic package. The UFS chip module includes a main control chip, several stacked flash memory chips, a flash memory chip substrate, and a third molding compound. And a sealed substrate; One surface of the encapsulated substrate is connected to a plurality of memory chips via the second molding compound. The other surface formed by the combination of the plurality of memory chips is provided with the adapter board. The central area of ​​the other surface of the encapsulated substrate is connected to the corresponding SOC chip bump of the SOC chip. The outer periphery of the other surface of the encapsulated substrate is connected to the first protruding solder ball of the PCB board. The surface of the adapter board facing away from the memory chips is provided with a second protruding solder ball. The exposed surface of the flash memory chip substrate is connected to the second protruding solder ball. A main control chip and a plurality of stacked flash memory chips are encapsulated in the third molding compound of the flash memory chip substrate. The encapsulation substrate has a first opening pre-set using the TMV process. Then, the SOC chip module and LPDDR chip module are encapsulated on the encapsulation substrate using a double-sided encapsulation method. After that, the TMV process is used to create a second and a third opening on the double sides of the entire structure, so that the entire structure has channels or lines for connection with the PCB board and flash memory chip substrate, and interconnects the chips in the SOC chip module and LPDDR chip module.

2. The SOC and memory chip packaging stacking structure according to claim 1, characterized in that: The memory chips include stacked memory chip groups arranged in two columns. The two stacked memory chip groups have the same height, and the memory chips in each stacked memory chip group are staggered and connected by gold wires.

3. The SOC and memory chip packaging stacking structure according to claim 2, characterized in that: The main control chip is located on one side of the surface area of ​​the flash memory chip substrate, and a plurality of stacked flash memory chips are located on the other side of the surface area of ​​the flash memory chip substrate. The flash memory chips of the plurality of stacked flash memory chips are stacked in a staggered manner and connected by gold wires.

4. The SOC and memory chip packaging stacking structure according to claim 3, characterized in that: The adapter board is supported on a surface of equal height formed by two stacked memory chip groups. The adapter board is connected to one of the stacked memory chip groups by gold wires. The flash memory chip substrate is provided with a fourth opening through TMV process. The lines in the fourth opening are connected to the second protruding solder ball of the adapter board, indirectly connecting the main control chip and several stacked flash memory chips to the PCB board.

5. The SOC and memory chip packaging stacking structure according to claim 1, characterized in that: The raised second solder ball has a second opening at the corresponding position of the second molding compound.

6. The packaging and stacking structure of a SOC and a memory chip according to claim 1, characterized in that: The sealing substrate connects the SOC chip module and the LPDDR chip module to the raised first solder ball on the PCB board through the lines set by the first opening and the third opening.

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