Chip packaging structure and manufacturing method thereof

Abstract

The invention provides a chip packaging structure. The chip packaging structure comprises a first chip, a second chip, a plurality of first mixed bonding pads, a first insulating layer, a first patterned conductive layer, a second patterned conductive layer, a plurality of first conductive through hole structures and a plurality of second conductive through hole structures, the first chip is electrically connected with the second chip through the first TSV. The first chip is bonded on the second chip through the first hybrid bonding pad. The first insulating layer wraps the first chip and the second chip. The first patterned conductive layer and the second patterned conductive layer are respectively disposed on the first upper surface and the first lower surface of the first insulating layer. The first conductive through hole structure is electrically connected with the first patterned conductive layer and the second patterned conductive layer. The second conductive through hole structure is electrically connected with the first chip and the first patterned conductive layer. The chip packaging structure has the advantages of very low profile, low cost, high density, high performance and the like.

Description

Technical Field

[0001] The invention relates to a packaging structure and a manufacturing method thereof, in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] Driven by artificial intelligence and 5G / 6G, high-performance computing (HPC) has become more popular in recent years and is widely used in advanced network and server applications, especially in artificial intelligence (AI) related products that require high data rates, increasing bandwidth, and decreasing latency. However, the current build-up package substrate cannot meet the above requirements because only one chip is embedded in the build-up structure, thus failing to meet the requirements of high density and high performance. Summary of the invention

[0003] The present invention is directed to a chip packaging structure having the advantages of very low profile, low cost, high density and high performance.

[0004] The present invention also provides a method for manufacturing a chip packaging structure, which is used to manufacture the above-mentioned chip packaging structure.

[0005] According to an embodiment of the present invention, a chip packaging structure includes a first chip, a second chip, a plurality of first hybrid bonding pads, a first insulating layer, a first patterned conductive layer, a second patterned conductive layer, a plurality of first conductive via structures, and a plurality of second conductive via structures. The first chip has a plurality of first through silicon vias (TSV). The second chip is directly configured on the first chip, wherein the first chip is electrically connected to the second chip through the first through silicon via. The first hybrid bonding pad is formed between the first chip and the second chip. The first chip is bonded to the second chip through the first hybrid bonding pad. The first insulating layer covers the first chip and the second chip, and has a first upper surface and a first lower surface opposite to each other. The first patterned conductive layer is configured on the first upper surface of the first insulating layer. The second patterned conductive layer is configured on the first lower surface of the first insulating layer. The first conductive via structure penetrates the first insulating layer and electrically connects the first patterned conductive layer and the second patterned conductive layer. The second conductive via structure is configured in the first insulating layer and electrically connects the first chip and the first patterned conductive layer.

[0006] In the chip packaging structure according to the embodiment of the present invention, the first chip has a first surface, and the second chip has a second surface, and the first surface directly contacts the second surface.

[0007] In the chip packaging structure according to an embodiment of the present invention, the chip packaging structure further includes a build-up layer structure and a core substrate. The core substrate includes a core layer and a plurality of third conductive via structures. The core layer is disposed between the build-up layer structure and the second patterned conductive layer. The third conductive via structure penetrates the core layer and electrically connects the build-up layer structure and the second patterned conductive layer.

[0008] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned build-up structure includes a third chip, a fourth chip, a plurality of second hybrid bonding pads, a second insulating layer, a third patterned conductive layer, a fourth patterned conductive layer, a plurality of fourth conductive via structures, and a plurality of fifth conductive via structures. The third chip has a plurality of second through silicon vias. The fourth chip is directly configured on the third chip, wherein the third chip is electrically connected to the fourth chip through the second through silicon vias. The second hybrid bonding pad is formed between the third chip and the fourth chip. The third chip is bonded to the fourth chip through the second hybrid bonding pad. The second insulating layer covers the third chip and the fourth chip, and has a second upper surface and a second lower surface opposite to each other. The third patterned conductive layer is configured on the second upper surface of the second insulating layer. The fourth patterned conductive layer is configured on the second lower surface of the second insulating layer and directly contacts the core layer. The third conductive via structure is electrically connected to the second patterned conductive layer and the fourth patterned conductive layer. The fourth conductive via structure penetrates the second insulating layer and is electrically connected to the third patterned conductive layer and the fourth patterned conductive layer. The fifth conductive via structure is configured in the second insulating layer and is electrically connected to the third chip and the third patterned conductive layer.

[0009] In the chip packaging structure according to an embodiment of the present invention, the above-mentioned build-up structure includes a second insulating layer, a first patterned circuit layer, a second patterned circuit layer, a third patterned circuit layer, a plurality of fourth conductive via structures, a plurality of fifth conductive via structures, and a plurality of sixth conductive via structures. The second insulating layer has a second upper surface and a second lower surface opposite to each other. The first patterned circuit layer is arranged on the second upper surface of the second insulating layer and directly contacts the core layer. The third conductive via structure is electrically connected to the second patterned conductive layer and the first patterned circuit layer. The second patterned circuit layer is arranged in the second insulating layer. The third patterned circuit layer is arranged on the second lower surface of the second insulating layer. The fourth conductive via structure is arranged in the second insulating layer and is electrically connected to the first patterned circuit layer and the second patterned circuit layer. The fifth conductive via structure is arranged in the second insulating layer and is electrically connected to the second patterned circuit layer and the third patterned circuit layer. The sixth conductive via structure is arranged in the second insulating layer and is electrically connected to the first patterned circuit layer and the third patterned circuit layer.

[0010] In the chip packaging structure according to the embodiment of the present invention, the thickness of the core substrate is greater than the thickness of the build-up layer structure.

[0011] In the chip packaging structure according to the embodiment of the present invention, the chip packaging structure further includes a die attach film (DAF) disposed between the second chip and the second patterned conductive layer. The second chip is fixed on the second patterned conductive layer through the die attach film.

[0012] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. A first chip and a second chip are provided. The first chip has a plurality of first through silicon vias. A plurality of first hybrid bonding pads are formed between the first chip and the second chip. The first chip is bonded to the second chip through the first hybrid bonding pad, and the first chip is electrically connected to the second chip through the first through silicon via. The first chip and the second chip are bonded to a first metal layer. A second metal layer and a first insulating layer located on the second metal layer are provided. The second metal layer and the first insulating layer are pressed onto the first metal layer. The first insulating layer covers the first chip and the second chip, wherein the first insulating layer has a first upper surface and a first lower surface opposite to each other. A drilling process is performed to form a plurality of first openings penetrating the second metal layer and the first insulating layer to expose a portion of the first metal layer, and a plurality of second openings penetrating the second metal layer and a portion of the first insulating layer to expose a portion of the first chip. A first patterned conductive layer is formed on the first upper surface of the first insulating layer. A second patterned conductive layer is formed on the first lower surface of the first insulating layer. A plurality of first conductive via structures are formed in the first opening. The first conductive via structure is electrically connected to the first patterned conductive layer and the second patterned conductive layer. A plurality of second conductive via structures are formed in the second opening. The second conductive via structure is electrically connected to the first chip and the first patterned conductive layer.

[0013] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the manufacturing method of the chip packaging structure further includes forming a chip bonding film on the first metal layer before bonding the first chip and the second chip on the first metal layer. The second chip is fixed on the first metal layer through the chip bonding film.

[0014] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the manufacturing method of the chip packaging structure further includes providing a build-up layer structure. Providing a core substrate. The core substrate includes a core layer and a plurality of third conductive via structures penetrating the core layer. Joining the build-up layer structure and the second patterned conductive layer on the core substrate. The core layer is disposed between the build-up layer structure and the second patterned conductive layer. The third conductive via structure electrically connects the build-up layer structure and the second patterned conductive layer.

[0015] Based on the above, in the design of the chip packaging structure of the present invention, the first chip is electrically connected to the second chip through the first silicon via, and the first chip is bonded to the second chip through the first hybrid bonding pad, and the first insulating layer covers the first chip and the second chip. In other words, there is no bump between the first chip and the second chip, and the first chip and the second chip are embedded in the first insulating layer, so the chip packaging structure of the present invention can have a very low profile, lower cost, higher density and higher performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1E is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;

[0017] Figure 2 is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0018] Figure 3 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0019] Description of Reference Numerals

[0020] 100a, 100b, 100c: chip packaging structure;

[0021] 110: first chip;

[0022] 110': third chip;

[0023] 111: upper surface;

[0024] 112: pad;

[0025] 113: lower surface;

[0026] 115: first silicon through-hole;

[0027] 115': second silicon through-hole;

[0028] 120: second chip;

[0029] 120': the fourth chip;

[0030] 121: upper surface;

[0031] 123: lower surface;

[0032] 130: a first hybrid bonding pad;

[0033] 130': second hybrid bonding pad;

[0034] 140: chip bonding film;

[0035] 150: first insulating layer;

[0036] 150': second insulating layer;

[0037] 151: first upper surface;

[0038] 151': second upper surface;

[0039] 153: first lower surface;

[0040] 153': second lower surface;

[0041] 160: a first patterned conductive layer;

[0042] 160': a third patterned conductive layer;

[0043] 165: a first conductive via structure;

[0044] 165': fourth conductive via structure;

[0045] 168: a second conductive via structure;

[0046] 168': fifth conductive via structure;

[0047] 170: a second patterned conductive layer;

[0048] 170': fourth patterned conductive layer;

[0049] 180: core layer;

[0050] 185: a third conductive via structure;

[0051] 191: fourth conductive via structure;

[0052] 192: a first patterned circuit layer;

[0053] 193: a fifth conductive via structure;

[0054] 194: a second patterned circuit layer;

[0055] 195: a sixth conductive via structure;

[0056] 196: a third patterned circuit layer;

[0057] 198: second insulating layer;

[0058] 198a: second upper surface;

[0059] 198b: second lower surface;

[0060] BL1, BL2: build-up structure;

[0061] C: core substrate;

[0062] M1: first metal layer;

[0063] M2: second metal layer;

[0064] S: surface;

[0065] T1: first opening;

[0066] T2: Second opening. DETAILED DESCRIPTION

[0067] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0068] The embodiments of the present invention can be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings of the present invention are not drawn to scale, and in fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0069] Figures 1A to 1E FIG. 1 is a cross-sectional view of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. According to the method for manufacturing a chip packaging structure of this embodiment, first, please refer to Figure 1A , providing a first chip 110 and a second chip 120. The first chip 110 includes a plurality of pads 112, and has an upper surface 111 and a lower surface 113 opposite to each other, and a plurality of first silicon through vias 115. The pads 112 are disposed on the upper surface 111, and the first silicon through vias 115 are separated from each other, penetrate the first chip 110, and connect the upper surface 111 and the lower surface 113. The second chip 120 has an upper surface 121 and a lower surface 123 opposite to each other. Here, the first chip 110 and the second chip 120 may be, for example, logic chips, memory chips, chipsets (chiplets) or other system-on-chips (SOCs), etc., but are not limited thereto.

[0070] Next, please refer to Figure 1A, a plurality of first hybrid bonding pads 130 are formed between the first chip 110 and the second chip 120, wherein the first chip 110 is bonded to the second chip 120 through the first hybrid bonding pads 130, and the first chip 110 is electrically connected to the second chip 120 through the first through silicon vias 115. The first hybrid bonding pads 130 are formed by silicon dioxide to silicon dioxide (SiO2-to-SiO2) bonding at room temperature and by metal to metal bonding during annealing, such as the metal pads on the first chip 110 directly bonded to the metal pads on the second chip 120, which means that there is no bump between the first chip 110 and the second chip 120. Here, the lower surface 113 (i.e., the first surface) of the first chip 110 directly contacts the upper surface 121 (i.e., the second surface) of the second chip 120. That is, the first chip 110 is directly disposed and directly contacts the second chip 120, and the edge of the first chip 110 is, for example, flush with the edge of the second chip 120. In one embodiment, the orthographic projection of the pad 112 of the first chip 110 on the second chip 120 is, for example, partially overlapped with the first hybrid bonding pad 130 and / or does not overlap with the first hybrid bonding pad 130.

[0071] Next, please refer to Figure 1B A first metal layer M1 and a chip bonding film 140 disposed on the first metal layer M1 are provided. Here, the first metal layer M1 is, for example, copper foil, but is not limited thereto. The size of the first metal layer M1 is, for example, larger than the size of the chip bonding film 140.

[0072] Next, please refer to Figure 1B , the first chip 110 and the second chip 120 are bonded on the first metal layer M1 , wherein the second chip 120 is fixed on the first metal layer M1 via a chip bonding film 140 . Here, the edge of the chip bonding film 140 is cut flush with the edge of the second chip 120 and the first chip 110 .

[0073] Next, please refer to Figure 1C , providing a second metal layer M2 and a first insulating layer 150 located on the second metal layer M2. Here, the second metal layer M2 is, for example, copper foil, but not limited thereto. The edge of the second metal layer M2 is, for example, cut flush with the edge of the first insulating layer 150, and the thickness of the first insulating layer 150 is, for example, greater than the thickness of the second metal layer M2.

[0074] Next, please also refer to Figure 1C as well as Figure 1D, the second metal layer M2 and the first insulating layer 150 are pressed on the first metal layer M1 by heat pressing, wherein the first insulating layer 150 is located between the first metal layer M1 and the second metal layer M2, and the first insulating layer 150 covers the first chip 110 and the second chip 120. In other words, the first chip 110 and the second chip 120 are buried in the first insulating layer 150, that is, the first chip 110 and the second chip 120 are surrounded by the first insulating layer 150. Here, the first insulating layer 150 has a first upper surface 151 and a first lower surface 153 opposite to each other.

[0075] Next, please refer to Figure 1D , a drilling process such as laser drilling or mechanical drilling is performed to form a plurality of first openings T1 penetrating the second metal layer M2 and the first insulating layer 150 to expose a portion of the first metal layer M1, and a plurality of second openings T2 penetrating the second metal layer M2 and a portion of the first insulating layer 150 to expose a portion of the first chip 110. The first openings T1 expose a portion of the surface S of the first metal layer M1, and the second openings T2 expose the pads 112 of the first chip 110.

[0076] Afterwards, please also refer to Figure 1D as well as Figure 1E , forming a first patterned conductive layer 160 on the first upper surface 151 of the first insulating layer 150; forming a second patterned conductive layer 170 on the first lower surface 153 of the first insulating layer 150; forming a plurality of first conductive through-hole structures 165 in the first opening T1; and forming a plurality of second conductive through-hole structures 168 in the second opening T2.

[0077] In detail, a metal material layer is formed on the first upper surface 151 of the first insulating layer 150 by electroplating, wherein the metal material layer covers the second metal layer M2 and fills the first opening T1 and the second opening T2, thereby forming a first conductive via structure 165 located in the first opening T1 and a second conductive via structure 168 located in the second opening T2. Next, a patterning process is performed on the metal material layer and the second metal layer M2 thereunder, thereby forming a first patterned conductive layer 160 located on the first upper surface 151 of the first insulating layer 150; and a patterning process is performed on the first metal layer M1, thereby forming a second patterned conductive layer 170 located on the first lower surface 153 of the first insulating layer 150, wherein the patterning process described above is, for example, an etching process. Here, the first conductive via structure 165 electrically connects the first patterned conductive layer 160 and the second patterned conductive layer 170. The second conductive via structure 168 electrically connects the pad 112 of the first chip 110 and the first patterned conductive layer 160. So far, the manufacturing of the chip packaging structure 100a has been completed.

[0078] In terms of structure, please refer to Figure 1E In this embodiment, the chip package structure 100a includes a first chip 110, a second chip 120, a first hybrid bonding pad 130, a first insulating layer 150, a first patterned conductive layer 160, a second patterned conductive layer 170, a first conductive via structure 165, and a second conductive via structure 168. The first chip 110 has a first through silicon via 115. The second chip 120 is directly disposed on the first chip 110, wherein the first chip 110 is electrically connected to the second chip 120 through the first through silicon via 115. The first hybrid bonding pad 130 is formed between the first chip 110 and the second chip 120, wherein the first chip 110 is bonded to the second chip 120 through the first hybrid bonding pad 130. The first insulating layer 150 covers the first chip 110 and the second chip 120, and has a first upper surface 151 and a first lower surface 153 opposite to each other. The first patterned conductive layer 160 is disposed on the first upper surface 151 of the first insulating layer 150. The second patterned conductive layer 170 is disposed on the first lower surface 153 of the first insulating layer 150. The first conductive via structure 165 penetrates the first insulating layer 150 and electrically connects the first patterned conductive layer 160 and the second patterned conductive layer 170. The second conductive via structure 168 is disposed in the first insulating layer 150 and electrically connects the first chip 110 and the first patterned conductive layer 160. In addition, the chip package structure 100a of the present embodiment further includes a chip bonding film 140, which is disposed between the second chip 120 and the second patterned conductive layer 170, wherein the second chip 120 is fixed on the second patterned conductive layer 170 through the chip bonding film 140.

[0079] Since the first chip 110 of the present embodiment is electrically connected to the second chip 120 through the first through silicon via 115, and the first chip 110 is bonded to the second chip 120 through the first hybrid bonding pad 130, and the first insulating layer 150 covers the first chip 110 and the second chip 120. In other words, there is no bump between the first chip 110 and the second chip 120, and the first chip 110 and the second chip 120 are embedded in the first insulating layer 150, the chip package structure 100a of the present embodiment can have a very low profile, lower cost, higher density and higher performance.

[0080] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiments, and the following embodiments will not be repeated.

[0081] Figure 2is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention. Figure 1E as well as Figure 2 The chip package structure 100b of the present embodiment is similar to the chip package structure 100a described above, but the main difference between the two is that in the present embodiment, the chip package structure 100b further includes a build-up structure BL1 and a core substrate C. The core substrate C includes a core layer 180 and a plurality of third conductive via structures 185. The core layer 180 is disposed between the build-up structure BL1 and the second patterned conductive layer 170. The third conductive via structure 185 penetrates the core layer 180 and electrically connects the build-up structure BL1 and the second patterned conductive layer 170. Here, the thickness of the core substrate C may be, for example, greater than the thickness of the build-up structure BL1, but is not limited thereto.

[0082] For more details, please refer to Figure 2 In the present embodiment, the build-up structure BL1 includes a third chip 110', a fourth chip 120', a plurality of second hybrid bonding pads 130', a second insulating layer 150', a third patterned conductive layer 160', a fourth patterned conductive layer 170', a plurality of fourth conductive via structures 165', and a plurality of fifth conductive via structures 168'. The third chip 110' has a plurality of second through silicon vias 115'. The fourth chip 120' is directly disposed on the third chip 110', wherein the third chip 110' is electrically connected to the fourth chip 120' through the second through silicon vias 115'. The second hybrid bonding pad 130' is formed between the third chip 110' and the fourth chip 120', wherein the third chip 110' is bonded to the fourth chip 120' through the second hybrid bonding pad 130'. The second insulating layer 150' covers the third chip 110' and the fourth chip 120', and has a second upper surface 151' and a second lower surface 153' opposite to each other. The third patterned conductive layer 160' is disposed on the second upper surface 151' of the second insulating layer 150'. The fourth patterned conductive layer 170' is disposed on the second lower surface 153' of the second insulating layer 150' and directly contacts the core layer 180. The third conductive via structure 185 electrically connects the second patterned conductive layer 170 and the fourth patterned conductive layer 170'. The fourth conductive via structure 165' penetrates the second insulating layer 150' and electrically connects the third patterned conductive layer 160' and the fourth patterned conductive layer 170'. The fifth conductive via structure 168' is disposed in the second insulating layer 150' and electrically connects the third chip 110' and the third patterned conductive layer 160'. Here, the build-up structure BL1 is embodied in the same manner as the chip package structure 100a of Figure 1, that is, the build-up structure BL1 of this embodiment is a structural layer embedded therein for hybrid bonding of multiple chips.

[0083] In terms of process, please also refer to Figure 1E as well as Figure 2 , completed Figure 1E After the chip package structure 100a is fabricated, another identical structure can be provided as a build-up structure BL1. Afterwards, a core substrate C is provided, wherein the core substrate C includes a core layer 180 and a third conductive via structure 185 penetrating the core layer 180. Finally, the build-up structure BL1 and the second patterned conductive layer 170 are bonded on the core substrate C, wherein the core layer 180 is disposed between the build-up structure BL1 and the second patterned conductive layer 170, and the third conductive via structure 185 electrically connects the build-up structure BL1 and the second patterned conductive layer 170. At this point, the fabrication of the chip package structure 100b has been completed.

[0084] Figure 3 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention. Figure 1E as well as Figure 3 The chip package structure 100c of the present embodiment is similar to the chip package structure 100a described above, but the main difference between the two is that in the present embodiment, the chip package structure 100c further includes a build-up structure BL2 and a core substrate C. The core substrate C includes a core layer 180 and a plurality of third conductive via structures 185. The core layer 180 is disposed between the build-up structure BL1 and the second patterned conductive layer 170. The third conductive via structure 185 penetrates the core layer 180 and electrically connects the build-up structure BL2 and the second patterned conductive layer 170. Here, the thickness of the core substrate C may be, for example, greater than the thickness of the build-up structure BL2, but is not limited thereto.

[0085] For more details, please refer to Figure 3In the present embodiment, the build-up structure BL2 includes a first patterned circuit layer 192, a second patterned circuit layer 194, a third patterned circuit layer 196, a second insulating layer 198, a plurality of fourth conductive via structures 191, a plurality of fifth conductive via structures 193, and a plurality of sixth conductive via structures 195. The second insulating layer 198 has a second upper surface 198a and a second lower surface 198b opposite to each other. The first patterned circuit layer 192 is disposed on the second upper surface 198a of the second insulating layer 198 and directly contacts the core layer 180. The third conductive via structure 185 is electrically connected to the second patterned conductive layer 170 and the first patterned circuit layer 192. The second patterned circuit layer 194 is disposed in the second insulating layer 198. The third patterned circuit layer 196 is disposed on the second lower surface 198b of the second insulating layer 198. The fourth conductive via structure 191 is disposed in the second insulating layer 198 and electrically connects the first patterned circuit layer 192 and the second patterned circuit layer 194. The fifth conductive via structure 193 is disposed in the second insulating layer 198 and electrically connects the second patterned circuit layer 194 and the third patterned circuit layer 196. The sixth conductive via structure 195 is disposed in the second insulating layer 198 and electrically connects the first patterned circuit layer 192 and the third patterned circuit layer 196. Here, the build-up structure BL2 is embodied as a circuit structure layer.

[0086] In terms of process, please also refer to Figure 1E as well as Figure 3 , completed Figure 1E After the chip package structure 100a in the embodiment is fabricated, a build-up structure BL2 is provided. Next, a core substrate C is provided, wherein the core substrate C includes a core layer 180 and a third conductive via structure 185 penetrating the core layer 180. Afterwards, the build-up structure BL2 and the core substrate C are bonded, so that the core layer 180 and the third conductive via structure 185 directly contact the first patterned circuit layer 192 of the build-up structure BL2. Finally, the second patterned conductive layer 170 of the chip package structure 100a is bonded on the core substrate C, wherein the core layer 180 is located between the build-up structure BL2 and the second patterned conductive layer 170, and the third conductive via structure 185 electrically connects the build-up structure BL2 and the second patterned conductive layer 170. At this point, the manufacture of the chip package structure 100c has been completed.

[0087] In summary, based on the above, in the design of the chip packaging structure of the present invention, the first chip is electrically connected to the second chip through the first silicon via, and the first chip is bonded to the second chip through the first hybrid bonding pad, and the first insulating layer covers the first chip and the second chip. In other words, there is no bump between the first chip and the second chip, and the first chip and the second chip are embedded in the first insulating layer, so the chip packaging structure of the present invention can have a very low profile, lower cost, higher density and higher performance.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A first chip having a plurality of first through silicon vias; A second chip is directly configured on the first chip, wherein the first chip is electrically connected to the second chip through the plurality of first through silicon vias; A plurality of first hybrid bonding pads are formed between the first chip and the second chip, and the first chip is bonded to the second chip through the plurality of first hybrid bonding pads; A first insulating layer, covering the first chip and the second chip, and having a first upper surface and a first lower surface opposite to each other; A first patterned conductive layer is disposed on the first upper surface of the first insulating layer; a second patterned conductive layer, disposed on the first lower surface of the first insulating layer; A plurality of first conductive via structures, penetrating the first insulating layer and electrically connecting the first patterned conductive layer and the second patterned conductive layer; as well as A plurality of second conductive via structures are disposed in the first insulating layer and electrically connect the first chip and the first patterned conductive layer.

2. The chip packaging structure according to claim 1, characterized in that: The first chip has a first surface, and the second chip has a second surface, and the first surface directly contacts the second surface.

3. The chip packaging structure according to claim 1, characterized in that: Also includes: Added layer structure; as well as The core substrate includes a core layer and a plurality of third conductive via structures, wherein the core layer is disposed between the build-up layer structure and the second patterned conductive layer, and the plurality of third conductive via structures penetrate the core layer and electrically connect the build-up layer structure and the second patterned conductive layer.

4. The chip packaging structure according to claim 3, characterized in that: The build-up structure comprises: A third chip having a plurality of second through silicon vias; a fourth chip, directly configured on the third chip, wherein the third chip is electrically connected to the fourth chip through the plurality of second through silicon vias; A plurality of second hybrid bonding pads are formed between the third chip and the fourth chip, and the third chip is bonded to the fourth chip through the plurality of second hybrid bonding pads; A second insulating layer covers the third chip and the fourth chip and has a second upper surface and a second lower surface opposite to each other; a third patterned conductive layer, disposed on the second upper surface of the second insulating layer; a fourth patterned conductive layer, disposed on the second lower surface of the second insulating layer and directly contacting the core layer, wherein the plurality of third conductive via structures electrically connect the second patterned conductive layer and the fourth patterned conductive layer; a plurality of fourth conductive via structures, penetrating the second insulating layer and electrically connecting the third patterned conductive layer and the fourth patterned conductive layer; and A plurality of fifth conductive via structures are disposed in the second insulating layer and electrically connect the third chip and the third patterned conductive layer.

5. The chip packaging structure according to claim 3, characterized in that: The build-up structure comprises: A second insulating layer having a second upper surface and a second lower surface opposite to each other; A first patterned circuit layer is disposed on the second upper surface of the second insulating layer and directly contacts the core layer, and the plurality of third conductive via structures electrically connect the second patterned conductive layer and the first patterned circuit layer; A second patterned circuit layer is disposed in the second insulating layer; a third patterned circuit layer, disposed on the second lower surface of the second insulating layer; a plurality of fourth conductive via structures, disposed in the second insulating layer and electrically connecting the first patterned circuit layer and the second patterned circuit layer; a plurality of fifth conductive via structures, disposed in the second insulating layer and electrically connecting the second patterned circuit layer and the third patterned circuit layer; and A plurality of sixth conductive via structures are disposed in the second insulating layer and electrically connected to the first patterned circuit layer and the third patterned circuit layer.

6. The chip packaging structure according to claim 3, characterized in that: The thickness of the core substrate is greater than the thickness of the build-up layer structure.

7. The chip packaging structure according to claim 1, characterized in that: Also includes: The chip bonding film is disposed between the second chip and the second patterned conductive layer, wherein the second chip is fixed on the second patterned conductive layer through the chip bonding film.

8. A method for manufacturing a chip packaging structure, characterized in that: include: Providing a first chip and a second chip, wherein the first chip has a plurality of first through silicon vias; forming a plurality of first hybrid bonding pads between the first chip and the second chip, wherein the first chip is bonded to the second chip through the plurality of first hybrid bonding pads, and the first chip is electrically connected to the second chip through the plurality of first through silicon vias; Bonding the first chip and the second chip on a first metal layer; Providing a second metal layer and a first insulating layer located on the second metal layer; Laminating the second metal layer and the first insulating layer on the first metal layer, wherein the first insulating layer covers the first chip and the second chip, wherein the first insulating layer has a first upper surface and a first lower surface opposite to each other; Performing a drilling process to form a plurality of first openings penetrating the second metal layer and the first insulating layer to expose a portion of the first metal layer, and a plurality of second openings penetrating the second metal layer and a portion of the first insulating layer to expose a portion of the first chip; forming a first patterned conductive layer on the first upper surface of the first insulating layer; forming a second patterned conductive layer on the first lower surface of the first insulating layer; forming a plurality of first conductive via structures in the plurality of first openings, wherein the plurality of first conductive via structures electrically connect the first patterned conductive layer and the second patterned conductive layer; as well as A plurality of second conductive via structures are formed in the plurality of second openings, wherein the plurality of second conductive via structures electrically connect the first chip and the first patterned conductive layer.

9. The method for manufacturing a chip packaging structure according to claim 8, characterized in that: Also includes: Before bonding the first chip and the second chip to the first metal layer, a chip bonding film is formed on the first metal layer, and the second chip is fixed to the first metal layer through the chip bonding film.

10. The method for manufacturing a chip packaging structure according to claim 8, characterized in that: Also includes: Providing a layered structure; Providing a core substrate, the core substrate comprising a core layer and a plurality of third conductive through-hole structures penetrating the core layer; as well as The build-up structure and the second patterned conductive layer are bonded on the core substrate, the core layer is disposed between the build-up structure and the second patterned conductive layer, and the plurality of third conductive via structures electrically connect the build-up structure and the second patterned conductive layer.

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