Semiconductor device and method of forming semiconductor device

Abstract

In an embodiment, a semiconductor device may include a first structure including a first surface and a second surface opposite the first surface. The first structure may include a first substrate and a first through substrate via (TSV) exposed from a second surface of the first substrate. The first TSV has a first width. The semiconductor device may further include a second TSV exposed from the second surface of the first structure, the second TSV having a second width less than the first width. The semiconductor device may further include a guard ring surrounding each of the first TSV and the second TSV. In addition, the semiconductor device may include a second structure bonded to a first surface of the first structure, the first surface including a first bonding pad. The embodiment of the invention also provides a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is caused by the repeated reduction of the minimum component size, which allows more components to be integrated into a given area. With the growth of the demand for shrinking electronic devices, there has been a demand for smaller and more creative packaging technologies for semiconductor dies. An example of such a packaging system is the stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present disclosure provide a semiconductor device, which includes: a first structure, including a first surface and a second surface opposite to the first surface, wherein the first structure includes: a first substrate; a first through substrate via (TSV) exposed from the second surface of the first substrate, the first TSV having a first width; a second TSV exposed from the second surface of the first structure, the second TSV having a second width smaller than the first width; a guard ring surrounding each of the first TSV and the second TSV; and a second structure bonded to the first surface of the first structure, the first surface including a first bonding pad.

[0004] Some other embodiments of the present disclosure provide a method for forming a semiconductor device, the method comprising: forming a first structure, the first structure comprising a first surface and a second surface opposite to the first surface, wherein forming the first structure comprises: forming a first interconnect structure above a first substrate, the first interconnect structure comprising an active metallization pattern and a guard ring; forming a first through substrate via (TSV) passing through the first interconnect structure and the first substrate, the guard ring surrounding the first TSV in the first interconnect structure; and forming a first bonding pad above the first interconnect structure, the first bonding pad being connected to the first TSV and the active metallization pattern of the first interconnect structure, the first bonding pad being located on a first surface of the first structure; forming a second structure, the second structure comprising a first surface and a second surface opposite to the first surface; bonding the first surface of the first structure to the first surface of the second structure; after bonding, forming a second TSV from the second surface of the first structure to the first interconnect structure, the second TSV having a width smaller than the first TSV; exposing the first TSV at the second surface of the first structure; and forming a second bonding pad on the second surface of the first structure, the second bonding pad being electrically coupled to the first TSV and the second TSV.

[0005] Another embodiment of the present disclosure provides a method for forming a semiconductor device, the method comprising: forming a first structure, wherein forming the first structure comprises: forming a first interconnect structure over a first substrate, the first interconnect structure comprising a metallization pattern; forming a first through substrate via (TSV) passing through the first interconnect structure and the first substrate; and forming a first bonding pad over the first interconnect structure, and the first bonding pad is connected to the first TSV and the metallization pattern of the first interconnect structure; bonding the first structure to a second structure; after bonding, forming a second TSV from the first substrate of the first structure to the first interconnect structure, the second TSV having a width smaller than the first TSV; thinning the first substrate, wherein the thinning exposes the first TSV; and forming a second bonding pad on the first structure, the second bonding pad being electrically coupled to the first TSV and the second TSV. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9Cross-sectional and plan views are shown of intermediate stages in forming a die in accordance with an embodiment.

[0008] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 A cross-sectional view is shown of an intermediate stage in forming a stacked package in accordance with some embodiments.

[0009] Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25 , Fig.26 , Fig.27A , Fig.27B , Fig.28A and Fig.28B Cross-sectional views and plan views of various packages are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] The embodiments discussed herein may be discussed in a specific context, namely, devices / structures having through substrate vias (TSVs) of different sizes. For example, a device may have larger TSVs (e.g., wider in a cross-sectional view) for power and ground, and smaller TSVs (e.g., narrower in a cross-sectional view) for signal transmission. The disclosed devices and methods provide solutions that allow power and signal transmission, thereby enabling multi-layer stacking and providing more flexible designs.

[0013] The size of TSV, also known as TSV critical dimension (CD), affects the performance of TSV. Large TSV CD is suitable for face-to-face (F2F) power transmission due to its low resistance, while small TSV CD is suitable for face-to-back (F2B) die-to-die (D2D) communication due to its small pitch. However, both large TSV CD and small TSV CD have their drawbacks. Large TSV CD causes high RC delay for signal communication, and small TSV CD causes high IR drop for power transmission. These issues limit the design of system-on-integrated circuit (SoIC) stacking, whether in F2F or F2B configuration.

[0014] The disclosed devices and methods overcome these challenges by incorporating different TSV CDs into a single solution for power and signal transmission. This approach allows multi-layer stacking beyond just two-layer stacking, providing more flexible design. Within a single layer, at least two different TSV CDs are formed to enable different SoIC stacking combinations, such as F2F and multiple F2B multi-layer stacking.

[0015] The disclosed devices and methods provide multiple advantages. They provide a more user-friendly design with less TSV area consumption. They provide an all-in-one solution for TSV, making them an ideal solution for various packaging types. In addition, they ensure high signal bandwidth, high-speed interconnection and high-density integration, suitable for computing and high-power applications, such as artificial intelligence (AI) applications or deep learning.

[0016] Furthermore, the teachings of the present disclosure apply to any device or package having TSVs in a stacked package arrangement. Other embodiments contemplate other applications, such as different package types or different configurations, which will be readily apparent to one of ordinary skill in the art after reading the present disclosure. It should be noted that the embodiments discussed herein do not necessarily illustrate every component or part that may be present in the structure. For example, multiple components may be omitted from a figure, such as when a discussion of one of the components may be sufficient to convey aspects of the embodiment. Furthermore, the method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0017] Figure 1, Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 A cross-sectional view is shown of an intermediate stage in the formation of die or wafer 20 in accordance with some embodiments.

[0018] Figure 1 A cross-sectional view of an integrated circuit die 20 is shown in accordance with some embodiments. Although structure 20 is described as a die in the following description, structure 20 may be a wafer 20 and not singulated after the formation steps.

[0019] The integrated circuit die 20 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 20 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0020] The integrated circuit die 20 can be formed in a wafer, which may include different device regions, which are singulated in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 20 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 20 includes a substrate 22, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The substrate 22 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 22 has an active surface (e.g., Figure 1 upward-facing surface) and non-active surfaces (e.g. Figure 1 The active surface is sometimes called the front side, and the inactive surface is sometimes called the back side.

[0021] Device 21 may be formed at the front surface of substrate 22. Device 21 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc., or a combination thereof. An interlayer dielectric (ILD) (not shown separately) is located above the front surface of substrate 22. The ILD surrounds device 21 and may cover device 21. The ILD may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0022] A conductive plug (not shown separately) extends through the ILD to electrically and physically couple the device 21. For example, when the device 21 is a transistor, the conductive plug can couple the gate and source / drain regions of the transistor. The conductive plug can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof.

[0023] The active surface of substrate 22 includes portions 22A between substrate 22 and dummy metallization pattern 28 and guard ring 30. These portions 22A may be patterned portions of substrate 22, or may be structures formed on top of substrate 22. These portions extend to the same height of substrate 22 as the front-end processing. In some embodiments, the front-end processing ends after the gate, ILD, and conductive plug are formed.

[0024] The interconnect structure 24 is located above the ILD and the conductive plug. The interconnect structure 24 can be formed by, for example, metallization patterns 26, 28, 30 in the dielectric layer 23 located on the ILD. In these embodiments, the metallization patterns 26, 28, 30 are formed in the middle process and the back end of the line process. The metallization patterns 26, 28, 30 include metal lines and vias formed in one or more low-k dielectric layers 23. The metallization patterns can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, etc.

[0025] The metallization patterns 26, 28, 30 include active metallization patterns 26, guard rings 30, and optional dummy metallization patterns 28. The active metallization patterns 26 of the interconnect structure 24 interconnect the devices to form an integrated circuit. The active metallization patterns 26 are electrically coupled to the devices through conductive plugs. The dummy metallization patterns 28 are electrically isolated from the devices of the die 20.

[0026] like Figure 1 As shown, the guard ring 30 is formed around the TSV region 27. The guard ring 30 may be an independent guard ring 30 around adjacent TSV regions 27, or a single guard ring 30 (eg, Figure 1The dummy metallization pattern 28 (shown between the regions 27 in the middle) can be formed between adjacent regions 27. A dummy metallization pattern 28 (if present) can be formed adjacent to a guard ring 30 or an active metallization pattern 26. The dummy metallization pattern 28 and the guard ring 30 are formed simultaneously, and the dummy metallization pattern 28 and the guard ring 30 are formed by the same process as the active metallization pattern 26. The guard ring 30 can reduce the leakage current between the subsequently formed TSV and other structures in the substrate 22 and the interconnect structure 24. In addition, the TSV can introduce mechanical stress, and the guard ring 30 can provide stress relief during the manufacture and operation of the device. In addition, the guard ring 30 can provide electrical isolation between the TSV and nearby active devices and metallization patterns. The dummy metallization pattern 28 is included to provide a more uniform pattern density in the interconnect structure 24, which, for example, helps to achieve planarization and process consistency, such as during a chemical mechanical polishing (CMP) process.

[0027] In some embodiments, guard ring 30 surrounds each TSV region 27 , and dummy metallization pattern 28 surrounds guard ring 30 and is not between TSV regions 27 . In some embodiments, dummy metallization pattern 28 may be located between TSV regions 27 .

[0028] After forming the interconnect structure 24, as shown in FIG. Figure 2 As shown, a mask 32 is formed and patterned on the interconnect structure 24. In some embodiments, the mask 32 is a photoresist and can be formed by spin coating, etc., and the mask 32 can be exposed to light for patterning. The pattern of the photoresist corresponds to the through-substrate via (TSV) 44 (see, for example, FIG. 1 ) that is subsequently formed in the TSV region 27. Figure 6 ). At least one opening is patterned through the photoresist 32 to expose the interconnect structure 24. In some embodiments, before the mask 32, a stop layer (not shown), such as a chemical mechanical polishing (CMP) stop layer, is deposited over the top surface of the interconnect structure 24. The CMP stop layer can be used to prevent the subsequent CMP process from removing too much material by resisting the subsequent CMP process and / or by providing a detectable stop point for the subsequent CMP process. In some embodiments, the CMP stop layer may include one or more dielectric material layers. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), oxycarbides (such as SiOC, etc.), carbonitrides (such as SiCN, etc.), carbides (such as SiC, etc.), combinations thereof, etc., and suitable dielectric materials may be formed using spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), etc., or combinations thereof.

[0029] exist Figure 3In the embodiment of the present invention, the remaining mask 32 is used as a mask during the etching process to remove the exposed and underlying substrate 22 and portions of the dielectric layer 23 of the interconnect structure 24. A single etching process can be used to etch the opening 34 in the TSV region 27 of the interconnect structure 24 and the substrate 22, or a first etching process can be used to etch the interconnect structure 24 and a second etching process can be used to etch the substrate 22. In some embodiments, the opening 34 is formed using a plasma dry etching process and a reactive ion etching (RIE) process (such as a deep RIE (DRIE) process). In some embodiments, the DRIE process includes an etching cycle and a passivation cycle, wherein the etching cycle uses, for example, SF6, and the passivation cycle uses, for example, C4F8. The use of a DRIE process with a passivation cycle and an etching cycle can achieve a highly anisotropic etching process. In some embodiments, the etching process can be any acceptable etching process, such as by wet etching or dry etching.

[0030] like Figure 4 As shown, after the opening 34 is formed, the photoresist 32 is removed. The photoresist 32 may be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like.

[0031] Further in Figure 4 In the embodiment of the present invention, a liner layer 38 is conformally deposited on the interconnect structure 24 and on the bottom surface and sidewalls of the opening 34. In some embodiments, the liner layer 38 includes one or more dielectric material layers and can be used to physically and electrically isolate the subsequently formed through-hole from the substrate 22. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), combinations thereof, etc. The liner layer 38 may be formed using CVD, PECVD, ALD, etc., or combinations thereof.

[0032] In subsequent steps, Figure 4 As shown, a seed layer 40 is formed on the pad layer 38. In some embodiments, the seed layer 40 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer 40 includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). In some embodiments, before forming the seed layer 40, a barrier layer (not shown) can be formed on the pad layer 38. The barrier layer can include Ti, TiN, etc. or a combination thereof.

[0033] exist Figure 5 In the embodiment, a conductive material 42 is formed on the seed layer 40, and the conductive material 42 fills the opening 34. The conductive material 42 may be formed by plating, such as electroplating including electrochemical plating, chemical plating, etc. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc.

[0034] After forming conductive material 42, an annealing process is then performed. The annealing process may be performed to prevent subsequent extrusion of the conductive material of TSV 44 (sometimes referred to as TSV oozing). TSV oozing is caused by a coefficient of thermal expansion (CTE) mismatch between conductive material 42 and substrate 22, and may cause damage to structures above the TSV (e.g., metallization patterns).

[0035] After the annealing process, a planarization process is performed to remove portions of the conductive material 42, the seed layer 40, and the liner layer 38 outside the opening 34 to form a TSV 44. Figure 6 As shown. After the planarization process, the top surface of the topmost dielectric layer of TSV 44 and interconnect structure 24 is coplanar within process variations. The planarization process can be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, the upper portion of TSV 44 (formed in interconnect structure 24) has a greater width than the lower portion of TSV 44 (formed in substrate 22). In some embodiments, the width of TSV 44 passing through interconnect structure 24 and substrate 22 is constant. In some embodiments, TSV 44 is formed to have a width W1. In some embodiments, width W1 is less than 15μm. In some embodiments, TSV 44 is formed to have a pitch P1. In some embodiments, pitch P1 is in the range of (1xW1) to (2xW1). In some embodiments, pitch P1 is in the range of 4μm to 10μm.

[0036] See also Figure 7 ,exist Figure 6 The interconnect structure 50 is formed above the structure. The interconnect structure 50 includes a dielectric layer 52, a metallization pattern and a via 54, and a top metal 56. Figure 7 5. The interconnect structure 50 is connected to the active metallization pattern 26 and TSV 44 of the interconnect structure 24 through the metallization pattern and via formed in the dielectric layer 52. The metallization pattern and via can be formed by similar processes and materials as the interconnect structure 24, and will not be described again here. In some embodiments, there is more than one layer of top metal 56, such as two top metal layers.

[0037] In some embodiments, dielectric layer 52 is the same material as dielectric layer 23 of interconnect structure 24, for example, a low-k dielectric. In other embodiments, dielectric layer 52 is formed of a silicon-containing material (which may or may not include oxygen). For example, dielectric layer 52 may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc.

[0038] The metallization pattern and the via 54 and the top metal 56 can be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, a combination thereof, etc. Examples of forming the metallization pattern and the via 54 and the top metal 56 by a damascene process include etching the dielectric layer 52 to form an opening, depositing a conductive barrier layer into the opening, plating a metal material (such as copper or a copper alloy), and performing planarization to remove excess portions of the metal material. In other embodiments, the formation of the dielectric layer 52, the metallization pattern and the via 54 and the top metal 56 may include forming the dielectric layer 52, patterning the dielectric layer 52 to form an opening, forming a metal seed layer (not shown), forming a patterned plating mask (such as a photoresist) to cover some portions of the metal seed layer while exposing other portions, plating the metallization pattern and the via 54 and the top metal 56, removing the plating mask, and etching undesired portions of the metal seed layer. The metallization pattern and the via 54 and the top metal 56 may be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof. In some embodiments, the top metal 56 is thicker than the metallization pattern, such as three times thicker, five times thicker, or any suitable thickness ratio to the metallization layer.

[0039] Figure 7 It is further shown that a passivation layer 58 is formed over the dielectric layer 52 and the top metal 56. In some embodiments, the passivation layer 58 is formed of the same material as the dielectric layer 52. In some embodiments, the passivation layer 58 can be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc. or a combination thereof. The passivation layer 58 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The passivation layer 58 can have a top surface that is level within process variations.

[0040] although Figure 7 TSVs 44 are shown connected directly to the interconnect structure 50 , but in some embodiments, one or more TSVs 44 may be connected directly to active metallization patterns 26 in the interconnect structure 24 .

[0041] exist Figure 8 In the embodiment, dielectric layers 72, 74 and 76 are formed over passivation layer 58. Figure 8Three dielectric layers 72, 74, and 76 are shown, but more or less than three dielectric layers may be formed. Dielectric layer 72 is separated from top metal structure 56 by passivation layer 58. Dielectric layer 72 provides a flat top surface to form dielectric layers 74 and 76, and dielectric layer 72 may be considered a planarized dielectric layer 72. Dielectric layer 74 may provide an etch stop function during subsequent formation of bonding pads and bonding vias, and may be considered an etch stop layer 74. Dielectric layer 76 may provide a dielectric bonding function and may be considered a bonding dielectric layer 76.

[0042] In some embodiments, dielectric layers 72, 74, and 76 are formed of a silicon-containing material. For example, dielectric layers 72, 74, and 76 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, or a combination thereof.

[0043] Figure 8 Further shown are bonding pad vias 86 and bonding pads 88 formed in dielectric layers 72, 74, and 76. Bonding pad vias 86 and bonding pads 88 are connected to top metal 56. Bonding pad vias 86 and bonding pads 88 may be formed using any suitable process, such as a single damascene process, a dual damascene process, combinations thereof, etc. A dual damascene process will be described.

[0044] In some embodiments, a photoresist (not shown) is formed and patterned on the dielectric layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the opening for the bonding pad 88. In addition, the dielectric layer 76 is patterned using the patterned photoresist as a mask to form an opening, wherein the patterning process stops on the dielectric layer 74. The exposed portion of the dielectric layer 76 can be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0045] The photoresist is removed and can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Next, a photoresist (not shown) is formed and patterned on the patterned dielectric layer 76 and in the openings through the dielectric layer 76. The photoresist can be formed by spin coating, etc. and can be exposed to light for patterning. The pattern of the photoresist corresponds to the opening for the bonding pad via 86. The patterned photoresist is used as a mask to pattern the dielectric layers 74 and 72 to form openings, wherein the patterning process exposes portions of the top metal 56. The exposed portions of the dielectric layers 74 and 72 can be removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching.

[0046] The photoresist is removed, and a barrier layer 84, a bonding pad via 86, and a bonding pad 88 are formed in the opening. Before forming the bonding pad via 86 and the bonding pad 88, a barrier layer 84 may be formed in the opening. In some embodiments, the barrier layer 84 may include Ti, TiN, etc., or a combination thereof. The bonding pad via 86 and the bonding pad 88 may be formed by a process and material similar to the top metal 56 and the via 54, and are not repeated here. For example, the bonding pad 88 may be formed of or include copper. Adjacent bonding pads 88 have a spacing P2. In some embodiments, the spacing P2 is as small as 3.0 μm. In some embodiments, the spacing P2 is in the range of 3.0 μm to 9.0 μm.

[0047] The top surface of the bond pad 88 is coplanar (within process variations) with the top surface of the uppermost dielectric layer 76. Planarization is achieved by a chemical mechanical polishing (CMP) process or a mechanical grinding process.

[0048] exist Fig. 9 In the embodiment of the present invention, the integrated circuit die 20 is thinned by thinning the substrate 22 before the subsequent singulation process. The thinning may be performed by a planarization process such as a mechanical grinding process or a CMP process. The thinning process exposes the TSVs 44 and the liner layer 38. After thinning, the TSVs 44 provide electrical connections from the back side of the substrate 22 to the front side of the substrate 22 (e.g., the interconnect structures 24 and 50 and the bonding pads 88).

[0049] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 A cross-sectional view is shown of an intermediate stage in forming a package-on-package 100 in accordance with some embodiments.

[0050] exist Fig.10 In the embodiment, a plurality of integrated circuit dies 20A are attached to a carrier substrate 90. The integrated circuit dies 20A are similar to the integrated circuit dies 20 described above and are not described again herein. Fig. 9 After processing, the integrated circuit die 20 is attached to a carrier substrate 90. In some embodiments, the integrated circuit die 20 is attached to a carrier substrate 90. Fig. 9 The substrate thinning step is performed, and the unthinned substrate (eg, TSVs 44 are not exposed) is attached to a carrier substrate 90.

[0051] like Fig.10As shown, an integrated circuit die 20A is placed in each of the packaging regions 100A and 100B. Figures 10 to 21 Two packaging regions 100A and 100B are shown, but more or fewer packaging regions are contemplated. The stacked package is formed in wafer form, which may include different packaging regions (e.g., 100A and 100B) that are singulated in subsequent steps to form multiple stacked packages.

[0052] The carrier substrate 90 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 90 may be a wafer so that a plurality of structures 20A may be simultaneously attached to the carrier substrate 90. The structures 20A may be attached by an adhesive film (not shown) between the structures 20 and the carrier substrate 90.

[0053] In some embodiments, a release layer (not shown) is formed on the carrier substrate 90, and the structure 20A and the adhesive film (if present) are attached to the release layer. The release layer can be formed of a polymer-based material, which can be removed from the above structure to be formed in a subsequent step together with the carrier substrate 90. In some embodiments, the release layer is a thermal release material based on epoxy resin, which loses its adhesiveness when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer can be an ultraviolet (UV) glue that loses its adhesiveness when exposed to ultraviolet light. The release layer can be dispensed as a liquid and cured, can be a laminated film laminated to the carrier substrate 90, or can be the like. The top surface of the release layer can be flat and substantially flat within process variations.

[0054] exist Fig.10 In the embodiment of the present invention, a gap filling process is performed to seal the die 20A in the encapsulant 96. After being formed, the encapsulant 96 seals the die 20A. The encapsulant 96 may include an oxide. Alternatively, the encapsulant 96 may be a molding compound, a molded underfill, a resin, an epoxy resin, etc. The encapsulant 96 may be applied by compression molding, transfer molding, etc., and the encapsulant 96 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0055] After depositing the encapsulant 96, a planarization process is performed to make the front side surface of the integrated circuit die 20A flush with the top surface of the encapsulant 96 and expose the bonding pads 88 and the dielectric layer 76. After the planarization process, the surfaces of the bonding pads 88, the dielectric layer 76, and the encapsulant 96 are coplanar within process variations. The planarization process can be, for example, a chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the bonding pads 88 and the dielectric layer 76 are already exposed, the planarization can be omitted.

[0056] Integrated circuit die 20A may be referred to as a layer of dies in a stacked package. For example, die 20A may be referred to as a first layer or bottom layer of a stacked package.

[0057] exist Fig.11 , the next layer of the integrated circuit die 20B is bonded to the first layer of the integrated circuit die 20A. The bonding of the integrated circuit die 20B to the integrated circuit die 20A can be achieved by direct bonding, wherein a metal-to-metal direct bond (between the respective bonding pads 88) and a dielectric-to-dielectric bond (such as a Si-O-Si bond between the surface dielectric layers 76 of the integrated circuit dies 20A and 20B) are formed. In this embodiment, in each packaging area 100A and 100B, a single die 20B is bonded to a single die 20A. However, in other embodiments, there can be multiple dies 20B bonded to the same die 20A. The multiple dies 20B bonded to the same die 20A can be the same or different from each other to form a homogeneous structure or a heterogeneous structure.

[0058] Die 20A is disposed face-up so that the front side of die 20A faces die 20B and the back side of die 20A faces away from die 20B. Die 20A is bonded to die 20B at interface 108. Fig.11 As shown, the direct bonding process directly bonds the topmost dielectric layer 76 of die 20B to the topmost dielectric layer 76 of die 20A at interface 108 by fusion bonding. In an embodiment, the bond between the topmost dielectric layer 76 of die 20B and the topmost dielectric layer 76 of die 20A can be an oxide-to-oxide bond. The direct bonding process also directly bonds the bonding pad 88 of die 20A to the bonding pad 88 of die 20B at interface 108 by direct metal-to-metal bonding. Therefore, the physical connection through the bonding pad 88 provides an electrical connection between die 20A and die 20B.

[0059] As an example, the direct bonding process begins by aligning die 20B with corresponding die 20A, for example, by aligning bonding pads 88. When die 20A and die 20B are aligned, bonding pads 88 can overlap corresponding bonding pads 88. Next, the direct bonding includes a pre-bonding step in which die 20B is contacted with die 20B. The direct bonding process continues with an anneal, for example, at a temperature between 150° C. and 400° C. for 0.5 hours to 3 hours, so that the copper in bonding pads 88 diffuses into each other and thus forms a direct metal-to-metal bond. The bonding of the layers of die 20B to the layers of die 20A forms a gap 110 between adjacent die 20B.

[0060] Next, if Fig.12As shown, a gap fill process is performed to fill gap 110 and seal die 20B in encapsulant 120. After formation, encapsulant 120 seals die 20B and is located on encapsulant 96. Encapsulant 120 is similar to encapsulant 96 described above and will not be described again here. After formation, encapsulant 120 seals die 20B.

[0061] exist Fig.13 and Fig.14 In the embodiment, encapsulant 120 is removed from over the back side of die 20B and planarized. Fig.13 In the embodiment of the present invention, the encapsulant 120 is removed from the back side of the die 20B to expose the back side of the die 20B. This step may include a photolithography and etching process to pattern the encapsulant 120.

[0062] exist Fig.14 In the process, a planarization process is performed to make the backside surface of the integrated circuit die 20B flush with the top surface of the encapsulant 120 and to ensure that the backside of the die 20B is exposed. After the planarization process, the surfaces of the substrate 22 of the die 20B and the encapsulant 120 are coplanar within process variations. The planarization process can be, for example, a CMP, a grinding process, etc. In some embodiments, planarization can be omitted, for example, if the encapsulant 120 and the backside of the die 20B are already coplanar.

[0063] exist Fig.15 In the embodiment of the present invention, a stack of layers 130, 132, and 134 is formed over encapsulant 120 and the back side of die 20B. In some embodiments, the layer stack includes stop layer 130 on encapsulant 120 and the back side of die 20B, dielectric layer 132 on stop layer 130, and mask layer 134 on dielectric layer 132. In some embodiments, stop layer 130 and dielectric layer 132 may be omitted, and only mask layer 134 is present.

[0064] In some embodiments, a stop layer 130 (such as a chemical mechanical polishing (CMP) stop layer 130) is deposited over the encapsulant 120 and the back side of the die 20B. The CMP stop layer 130 can be used to prevent a subsequent CMP process from removing too much material by resisting the subsequent CMP process and / or by providing a detectable stopping point for the subsequent CMP process. In some embodiments, the CMP stop layer 130 can include one or more dielectric material layers. Suitable dielectric materials can include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), oxycarbides (such as SiOC, etc.), carbonitrides (such as SiCN, etc.), carbides (such as SiC, etc.), combinations thereof, etc., and suitable dielectric materials can be formed using spin coating, CVD, PECVD, ALD, etc., or combinations thereof.

[0065] In some embodiments, dielectric layer 132 is deposited over CMP stop layer 130. Dielectric layer 132 can be used to transfer the pattern of mask layer 134 to the underlying layer. In some embodiments, dielectric layer 132 can include one or more dielectric material layers. Suitable dielectric materials can include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), combinations thereof, etc., and suitable dielectric materials can be formed using spin coating, CVD, PECVD, ALD, etc., or combinations thereof.

[0066] In some embodiments, mask layer 134 is formed on dielectric layer 132 (if present). In some embodiments, mask layer 134 is photoresist and can be formed by spin coating or the like.

[0067] exist Fig.16 In the process, the mask layer 134, the dielectric layer 132, the CMP stop layer 130, the substrate 22 of the die 20B, and the interconnect structure 24 of the die 20B are patterned. This patterning process exposes the metallization patterns in the interconnect structure of the die 20B, such as the top metal 56 of the die 20B.

[0068] The mask layer 134 may be a photoresist and may be exposed to light for patterning. The pattern of the mask layer 134 corresponds to the through substrate vias (TSVs) 144 to be formed later (see, e.g., Fig.18 and Fig.19 ). At least one opening is patterned through the mask layer 134 to expose underlying layers.

[0069] Further in Fig.16 , the remaining mask 134 is used as a mask during the etching process to remove the exposed and underlying dielectric layer 132, CMP stop layer 130, substrate 22, and portions of dielectric layer 23 of interconnect structure 24, thereby forming opening 136. A single etching process can be used to etch through dielectric layer 132, CMP stop layer 130, substrate 22, and opening 136 of dielectric layer 23 of interconnect structure 24. In some embodiments, multiple etching processes are used to form opening 136. For example, different etching processes can be used to etch through different corresponding layers / structures. In some embodiments, opening 136 is formed using a plasma dry etching process and a reactive ion etching (RIE) process (such as a deep RIE (DRIE) process). In some embodiments, the DRIE process includes an etching cycle and a passivation cycle, wherein the etching cycle uses, for example, SF6, and the passivation cycle uses, for example, C4F8. The use of a DRIE process with a passivation cycle and an etching cycle can achieve a highly anisotropic etching process. In some embodiments, the etching process can be any acceptable etching process, such as by wet etching or dry etching.

[0070] exist Fig.17 In the embodiment of the present invention, a conductive material 140 is formed in the opening 136 and over the mask 134. In some embodiments, the mask 134 is removed before the conductive material 140 is formed.

[0071] Before forming the conductive material 140, a liner layer (not shown) and a seed layer (not shown) are formed in the opening 136. The liner layer may be conformally deposited on the mask layer 134 and on the bottom surface and sidewalls of the opening 136. In some embodiments, the liner layer includes one or more dielectric material layers and may be used to physically and electrically isolate the subsequently formed through-holes from the substrate 22. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, etc.), nitrides (such as SiN, etc.), oxynitrides (such as SiON, etc.), combinations thereof, etc. The liner layer may be formed using CVD, PECVD, ALD, etc., or combinations thereof.

[0072] In a subsequent step, a seed layer is formed over the pad layer. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). In some embodiments, before forming the seed layer, a barrier layer (not shown) can be formed on the pad layer. The barrier layer can include Ti, TiN, etc., or a combination thereof.

[0073] Further in Fig.17 In the process, a conductive material 140 is formed on the seed layer, and the conductive material 140 fills the opening 136. The conductive material 140 may be formed by plating, such as electroplating including electrochemical plating, chemical plating, etc. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc.

[0074] After forming the conductive material 140, an annealing process is then performed. The annealing process may be performed to prevent subsequent extrusion of the conductive material of the TSV 144 (sometimes referred to as TSV bulging). TSV bulging is caused by a coefficient of thermal expansion (CTE) mismatch between the conductive material 140 and the substrate 22, and may cause damage to structures (e.g., metallization patterns) beneath the TSV.

[0075] After the annealing process, a planarization process is performed to remove portions of the conductive material 140, the seed layer, the liner layer, the mask layer 134, and the dielectric layer 132 outside the opening 136 to form the TSV 144. Fig.18 After the planarization process, the top surfaces of the TSV 144 and the CMP stop layer 130 are coplanar within process variations. The planarization process may be, for example, CMP, a grinding process, or the like.

[0076] exist Fig.19 In the process, CMP stop layer 130 is removed, and substrate 22 is thinned to expose TSV 44. CMP stop layer 130 and the thinning process may be performed by a planarization process, such as CMP, a grinding process, etc. After the planarization process, TSV 144, the surface of TSV 44, and the backside surface of substrate 22 are coplanar within process variations. In some embodiments, after the thinning process, the surface of TSV 144 and TSV 44 protrudes from the backside surface of substrate 22.

[0077] In some embodiments, the upper portion of TSV 144 (formed in substrate 22) has a greater width than the lower portion of TSV 144 (formed in interconnect structure 24). In some embodiments, the width of TSV 144 passing through interconnect structure 24 and substrate 22 is constant. In some embodiments, TSV 144 is formed to have a width W2. In some embodiments, the width W2 of TSV 144 is less than the width W1 of TSV 44. In some embodiments, the width W2 is as small as 0.1 μm. In some embodiments, the ratio of width W1 / W2 is in the range of 1.5 to 70.

[0078] exist Fig. 20 , a backside bonding pad structure is formed. Dielectric layers 150 and 152 and bonding pad vias 156 and bonding pads 158 are formed above and on die 20B and TSVs 44 and 144. Dielectric layers 150 and 152 can be similar to dielectric layers 72, 74, and 76 described above, and are not repeated here. Bonding pad vias 156 and bonding pads 158 can be similar to bonding pad vias 86 and bonding pads 88 described above, and are not repeated here. The backside bonding pad structure can include some redistribution layers.

[0079] exist Fig.21 , the previously described steps of bonding new layers of die 20 are repeated twice for die 20C and die 20D. These die layers may be formed as described above and are not repeated here. Die 20D may be referred to as the top die layer, and die 20D in this layer may not include TSVs. As shown, die 20A (e.g., bottom die 20A) does not include TSVs 144, but in some embodiments, die 20A includes TSVs 144.

[0080] Fig.21 The structure may undergo further processing, such as removing carrier substrate 90, forming conductive connectors on TSVs 44 in die 20A, and singulating stacked package 100 along scribe lines between regions 100A and 100B. Conductive connectors (not shown) allow external connections to be made to the singulated stacked package 100.

[0081] The larger TSVs 44 are most efficient for power transmission, and the smaller TSVs 144 are used for signal communication between components of the stacked package 100. For example, the larger TSVs 44 may be power lines or ground lines of the stacked package 100, and the smaller TSVs 144 may be signal lines between different components of the stacked package 100. By merging different TSVCDs into a single solution for power transmission and signal transmission, the disclosed embodiments allow for multi-layer stacking beyond just two layers of stacking, and provide a more flexible design. In addition, using the most efficient smaller TSVs for signal transmission can reduce TSV area consumption.

[0082] Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25 , Fig.26 , Fig.27A , Fig.27B , Fig.28A and Fig.28B Cross-sectional views and plan views of various packages are shown in accordance with some embodiments.

[0083] Fig.22A and Fig. 22B 2 shows a cross-sectional view and a plan view of a stacked package 200 according to some embodiments. Figures 1 to 21 , and will not be repeated here. In this embodiment, TSV144 is clustered in the central area of ​​layers 20B and 20C, and TSV 44 surrounds the clustering area. In addition, in this embodiment, layers 20A, 20B, and 20C are wafer-level structures rather than die-level structures. These wafers have been directly bonded together to form a stacked package 200. Although this embodiment has a three-layer structure, more or fewer layers are considered within the scope of the present disclosure. For example, one or more layers of a wafer can be bonded to wafer 20C.

[0084] in addition, Fig.22A An under bump metallization (UBM) 210 and conductive connectors 220 are shown on the wafer 20A. They form external connections for the stacked package 200. The UBM 210 is electrically coupled to the TSVs 44 in the wafer 20A.

[0085] According to some embodiments of the present disclosure, UBM 210 is formed by a plating process, wherein each UBM includes a seed layer (not shown) and a plated metal material located above the seed layer. The seed layer can be formed using, for example, PVD. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, etc. (such as electroplating or chemical plating, etc.). The seed layer and the plated metal material can be formed of the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching and / or dry etching. The remaining portion of the seed layer and the conductive material form the UBM.

[0086] Conductive connector 220 is formed on UBM 210. Conductive connector 220 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by chemical nickel plating chemical palladium immersion gold technology (ENEPIG), etc. Conductive connector 220 can include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, conductive connector 220 can be formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed so that the material is formed into a desired bump shape. In another embodiment, conductive connector 220 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and the metal cap layer may be formed by a plating process.

[0087] Fig.23A and Fig. 23B 2 shows a cross-sectional view and a plan view of a stacked package 250 according to some embodiments. This embodiment is similar to Fig.22A and Fig. 22B In this embodiment, layers 20B and 20C are die-level structures, and layer 20A is a wafer-level structure. For example, Fig.23A and Fig. 23BThis is referred to as chip-on-wafer-on-chip structure 250. Although this embodiment has a three-layer structure, more or fewer layers are contemplated within the scope of the present disclosure. For example, one or more layers of a wafer / die may be bonded to die 20C.

[0088] Fig.24A and Fig. 24B A cross-sectional view and a plan view of a stacked package 260 are shown in accordance with some embodiments. This embodiment is similar to Fig.23A and Fig. 23B In this embodiment, all layers 20A, 20B and 20C are core-level structures. For example, Fig.24A and Fig. 24B This is referred to as chip-on-chip-on-chip structure 260. Although this embodiment has a three-layer structure, more or fewer layers are contemplated within the scope of the present disclosure. For example, one or more layers of a wafer / die may be bonded to die 20C.

[0089] Fig.25 A cross-sectional view of a stacked package 270 is shown in accordance with some embodiments. This embodiment is similar to Fig.23A and Fig. 23B In this embodiment, layer 20C is a die-level structure, and layers 20A and 20B are wafer-level structures. For example, Fig.25 This is referred to as chip-on-wafer-on-wafer structure 270. Although this embodiment has a three-layer structure, more or fewer layers are contemplated within the scope of the present disclosure. For example, one or more layers of a wafer / die may be bonded to die 20C.

[0090] Fig.26 A cross-sectional view of a stacked package 280 is shown in accordance with some embodiments. This embodiment is similar to Fig.25 In this embodiment, layers 20A and 20C are wafer-level structures, and layer 20B is a die-level structure. For example, Fig.26 This is referred to as a chip-on-wafer-on-wafer structure 280. Although this embodiment has a three-layer structure, more or fewer layers are contemplated within the scope of the present disclosure. For example, one or more layers of wafers / dies may be bonded to wafer 20C.

[0091] Fig.27A and Fig.27B 2 shows a cross-sectional view and a plan view of a stacked package 300 according to some embodiments. Fig.24A and Fig. 24B In this embodiment, the conductive connecting member 220 is used to connect Fig.24A and Fig. 24B The stacked package 260 in FIG. 1 is attached to the interposer 310. Although this embodiment has a three-layer structure in the stacked package 260, more or fewer layers are contemplated within the scope of the present disclosure. Although this embodiment shows the stacked package 260, Figure 21 to Figure 26 Any of the stacked packages in can be applied to this embodiment.

[0092] The interposer 310 may be, for example, an organic interposer, a redistribution structure, etc. The interposer 310 may include a plurality of redistribution layers formed in a plurality of dielectric layers (not shown separately). The redistribution layer may include conductive lines, conductive vias, conductive pads, etc. The redistribution layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The interposer 310 may also include other conductive components, such as metallization patterns, through-holes, etc. In some embodiments, the dielectric layer may include a polymer, such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB)-based polymer, etc. In other embodiments, the dielectric layer may include other suitable dielectric materials, such as silicon oxide, etc. Any suitable process may be used to form the redistribution layer, such as deposition, plating, inlay, dual inlay, etc. In some embodiments, the interposer 310 is substantially free of active and passive devices. In some cases, the use of the interposer 310 may reduce manufacturing costs and package size. In some embodiments, the die 314 is attached to the interposer 310 by a conductive connector 316. The conductive connector 316 may be similar to the conductive connector 220 described above and will not be described again herein.

[0093] In some embodiments, die 314 may be a chip, a chiplet, a surface mount device, etc. Die 314 may include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. In some embodiments, die 314 is a passive device. In some embodiments, die 314 is bonded to interposer 310 via conductive connector 316.

[0094] In some embodiments, interposer 310 includes local interconnect 312. Local interconnect 312 may be, for example, a chip, a chiplet, a local silicon interconnect (LSI), an interconnect structure, etc., which provides additional electrical interconnect within interposer 310. For example, local interconnect 312 may provide an electrical connection (e.g., a bridge connection) between adjacent semiconductor devices (such as between stacked package 260 and die 314). Accordingly, conductive connectors 316 and 220 may be electrically coupled to local interconnect 312. Local interconnect 312 may include conductive features (e.g., conductive lines, vias, pads, etc.) formed in a dielectric layer. Conductive features may be formed using suitable techniques, such as damascene, dual damascene, etc. For example, in some cases, local interconnect 312 may include an interconnect structure located on a substrate, which may have a through substrate via (TSV) therein, although other local interconnects 312 are also possible. Local interconnect 312 may or may not include passive devices or active devices. Fig.27A and Fig.27B The local interconnects 312 shown in FIG. 5 are illustrative examples, and the local interconnects 312 may have a different arrangement, number, configuration, or size than that shown.

[0095] The interposer 310 also includes a redistribution structure 320 and a conductive connector 330 to allow external connections to the interposer 310 and the attached components. In some embodiments, the redistribution structure 320 includes a redistribution layer and / or a UBM as previously described, and the description is not repeated here. The conductive connector 330 can be similar to the conductive connector 220 described above, and the description is not repeated here.

[0096] Fig.28A and Fig.28B A cross-sectional view and a plan view of a stacked package 350 are shown in accordance with some embodiments. This embodiment is similar to Fig.27A and Fig.27B In this embodiment, the conductive connecting member 330 is used to connect Fig.27A and Fig.27B The package 300 in FIG. 1 is attached to the substrate 360. Although this embodiment shows a stacked package 260, Figure 21 to Figure 26 Any of the stacked packages in can be applied to this embodiment.

[0097] exist Fig.28A and Fig.28B In the embodiment, the conductive connecting member 330 is used to connect Fig.27A and Fig.27BThe package assembly is attached to a substrate 360 ​​(such as a package substrate 360) to form a package structure 350. The package substrate 360 ​​includes a substrate core 362, which can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, etc. can also be used. In addition, the substrate core 362 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In another embodiment, the substrate core 362 is an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively other printed circuit board (PCB) materials or films. Laminated films such as Ajinomoto laminated film (ABF) or other laminated materials can be used for the substrate core 362.

[0098] The substrate core 362 may include active devices and passive devices (not shown). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements of the system design. The devices may be formed using any suitable method.

[0099] The substrate core 362 may also include metallization layers and vias, and bonding pads located above the metallization layers and vias. The metallization layers may be formed above the active and passive devices and are designed to connect the devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the vias interconnect the layers of conductive materials, and the metallization layers may be formed by any suitable process (such as deposition, inlay, etc.). In some embodiments, the substrate core 362 is substantially free of active and passive devices.

[0100] The conductive connectors 330 are reflowed to attach the interposer 310 to the bonding pads on the package substrate 360. The conductive connectors 330 connect the package assembly 300 to the package substrate 360 ​​including the metallization layer of the substrate core 362. Thus, the package substrate 360 ​​is electrically connected to the stacked package 260. In some embodiments, passive devices (e.g., SMDs) can be attached to the package substrate 360, for example, to the bonding pads.

[0101] In some embodiments, an underfill (not shown) is formed between the package component 300 and the package substrate 360 ​​to surround the conductive connector 330. The underfill may be formed by a capillary flow process after the package component is attached, or may be formed by any suitable deposition method before the package component is attached.

[0102] In some embodiments, conductive connector 366 is formed on the underside of package substrate 360, which is opposite package assembly 300. Conductive connector 366 may be similar to conductive connector 220 described above, and will not be described again herein.

[0103] Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of 3D packages or 3DICs, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods for intermediate verification of known good dies to improve yield and reduce costs.

[0104] The embodiments discussed herein may be discussed in a specific context, namely, devices / structures having through substrate vias (TSVs) of different sizes. For example, a device may have larger TSVs (e.g., wider in a cross-sectional view) for power and ground, and smaller TSVs (e.g., narrower in a cross-sectional view) for signal transmission. The disclosed devices and methods provide solutions that allow power and signal transmission, thereby enabling multi-layer stacking and providing more flexible designs.

[0105] The size of TSV, also known as TSV critical dimension (CD), affects the performance of TSV. Large TSV CD is suitable for face-to-face (F2F) power transmission due to its low resistance, while small TSV CD is suitable for face-to-back (F2B) die-to-die (D2D) communication due to its small pitch. However, both large TSV CD and small TSV CD have their drawbacks. Large TSV CD causes high RC delay for signal communication, and small TSV CD causes high IR drop for power transmission. These issues limit the design of system-on-integrated circuit (SoIC) stacking, whether in F2F or F2B configuration.

[0106] The disclosed devices and methods overcome these challenges by incorporating different TSV CDs into a single solution for power and signal transmission. This approach allows multi-layer stacking beyond just two-layer stacking, providing more flexible design. Within a single layer, at least two different TSV CDs are formed to enable different SoIC stacking combinations, such as F2F and multiple F2B multi-layer stacking.

[0107] The disclosed devices and methods provide multiple advantages. They provide a more friendly design with less TSV area consumption. They provide an all-in-one solution for TSV, making them an ideal solution for various packaging types. In addition, they ensure high signal bandwidth, high-speed interconnection and high-density integration, suitable for computing and high-power applications, such as artificial intelligence (AI) applications or deep learning.

[0108] In an embodiment, a device may include a first structure including a first surface and a second surface opposite to the first surface. The first structure may include a first substrate and a first through substrate via (TSV) exposed from the second surface of the first substrate. The first TSV may have a first width. The device may also include a second TSV exposed from the second surface of the first structure, wherein the second TSV has a second width less than the first width. The device may also include a guard ring surrounding each of the first TSV and the second TSV. In addition, the device may include a second structure bonded to the first surface of the first structure, wherein the first surface has a first bonding pad.

[0109] The embodiments may also include one or more of the following features. The device may include an active metallization pattern connected to an active device in the first structure. The first surface may be located on a first side of the substrate, and the first interconnect structure may be located on the first side of the substrate. The guard ring and the active metallization pattern may be located in the first interconnect structure, and the second bonding pad may be located on the second side of the substrate. The second bonding pad may be electrically coupled to the first TSV and the second TSV. The device may include a third structure bonded to the second bonding pad of the first structure. The first structure and the second structure may be bonded in a face-to-face configuration or a face-to-face configuration. The first structure and the third structure are bonded in a face-to-face configuration. Each of the first structure, the second structure, and the third structure may be a semiconductor wafer or a semiconductor die. The device may include an interposer bonded to the third structure, wherein the third structure is located between the first structure and the interposer. The device may also include a first die bonded to the interposer, wherein the interposer may include a local interconnect embedded in the interposer. The local interconnect may be coupled to the first die and the third structure. The first TSV may be a power line or a ground line, and the second TSV may be a communication line between the first structure and the second structure.

[0110] In an embodiment, a method may include forming a first structure including a first surface and a second surface opposite to the first surface. Forming the first structure may include forming a first interconnect structure above a first substrate, wherein the first interconnect structure has an active metallization pattern and a guard ring. The method may also include forming a first TSV passing through the first interconnect structure and the first substrate, wherein the guard ring surrounds the first TSV in the first interconnect structure. In addition, the method may include forming a first bonding pad above the first interconnect structure, and the first bonding pad is connected to the first TSV and the active metallization pattern of the first interconnect structure. The first bonding pad may be located on the first surface of the first structure. The method may also include forming a second structure including a first surface and a second surface opposite to the first surface. After bonding the first surface of the first structure to the first surface of the second structure, the method may include forming a second TSV from the second surface of the first structure to the first interconnect structure. The second TSV has a width less than the first TSV. The method may also include exposing the first TSV at the second surface of the first structure, and forming a second bonding pad on the second surface of the first structure. The second bonding pad may be electrically coupled to the first TSV and the second TSV.

[0111] The embodiments may also include one or more of the following features. The method may include forming a third structure including a first surface and a second surface opposite to the first surface, and bonding the second surface of the first structure to the first surface of the third structure using a second bonding pad. The first structure and the third structure may be semiconductor dies, and the second structure may be a semiconductor wafer. The method may include bonding the second surface of the third structure to an interposer, wherein the third structure is located between the first structure and the interposer. The method may also include bonding the first die to the interposer, wherein the interposer has a local interconnect embedded in the interposer. The local interconnect may be coupled to the first die and the third structure. The first structure and the second structure may be bonded in a face-to-face configuration or a face-to-back configuration. The first structure and the third structure are bonded in a face-to-back configuration.

[0112] In an embodiment, a method may include forming a first structure. Forming the first structure may include forming a first interconnect structure above a first substrate, wherein the first interconnect structure has a metallization pattern. The method may also include forming a first TSV passing through the first interconnect structure and the first substrate. In addition, the method may include forming a first bonding pad above the first interconnect structure, and the first bonding pad is connected to the first TSV and the metallization pattern of the first interconnect structure. The first bonding pad may be located on a first surface of the first structure. The method may also include bonding the first structure to the second structure. After bonding, the method may include forming a second TSV from the first substrate through the first structure to the first interconnect structure. The second TSV may have a width less than the first TSV. The method may also include thinning the first substrate, the thinning exposing the first TSV. In addition, the method may include forming a second bonding pad on the first wafer, wherein the second bonding pad is electrically coupled to the first TSV and the second TSV.

[0113] The embodiments may also include one or more of the following features. The method may include bonding a second bonding pad of the first wafer to a third structure having a TSV. The second structure may include a semiconductor die.

[0114] Some embodiments of the present application provide a semiconductor device, including: a first structure, including a first surface and a second surface opposite to the first surface, wherein the first structure includes: a first substrate; a first substrate through-hole exposed from the second surface of the first substrate, the first substrate through-hole having a first width; a second substrate through-hole exposed from the second surface of the first structure, the second substrate through-hole having a second width smaller than the first width; a guard ring surrounding each of the first substrate through-hole and the second substrate through-hole; and a second structure bonded to the first surface of the first structure, the first surface including a first bonding pad.

[0115] In some embodiments, the first structure further comprises: an active metallization pattern connected to an active device in the first structure; a substrate, the first surface being located on a first side of the substrate; a first interconnect structure being located on the first side of the substrate, the guard ring and the active metallization pattern being located in the first interconnect structure; and a second bonding pad being located on the second side of the substrate, the second bonding pad being electrically coupled to the first through-substrate via and the second through-substrate via. In some embodiments, the semiconductor device further comprises: a third structure bonded to the second bonding pad of the first structure. In some embodiments, the first structure and the second structure are bonded in a face-to-face configuration. In some embodiments, the first structure and the third structure are bonded in a face-to-back configuration. In some embodiments, each of the first structure, the second structure, and the third structure is a semiconductor wafer. In some embodiments, each of the first structure, the second structure, and the third structure is a semiconductor die. In some embodiments, the semiconductor device further comprises: an interposer bonded to the third structure, the third structure being located between the first structure and the interposer. In some embodiments, the semiconductor device further comprises: a first die bonded to the interposer, wherein the interposer comprises a local interconnect embedded in the interposer, the local interconnect being coupled to the first die and the third structure. In some embodiments, the first through-substrate via is a power line or a ground line, wherein the second through-substrate via is a communication line between the first structure and the second structure.

[0116] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first structure, the first structure comprising a first surface and a second surface opposite to the first surface, wherein forming the first structure comprises: forming a first interconnect structure over a first substrate, the first interconnect structure comprising an active metallization pattern and a guard ring; forming a first substrate through-hole passing through the first interconnect structure and the first substrate, the guard ring surrounding the first substrate through-hole in the first interconnect structure; and forming a first bonding pad over the first interconnect structure, the first bonding pad being connected to the first substrate through-hole and the active metallization pattern of the first interconnect structure, the first bonding pad being located on the first surface of the first structure; forming a second structure, the second structure comprising a first surface and a second surface opposite to the first surface; bonding the first surface of the first structure to the first surface of the second structure; after bonding, forming a second substrate through-hole from the second surface of the first structure to the first interconnect structure, the second substrate through-hole having a width smaller than the first substrate through-hole; exposing the first substrate through-hole at the second surface of the first structure; and forming a second bonding pad on the second surface of the first structure, the second bonding pad being electrically coupled to the first substrate through-hole and the second substrate through-hole.

[0117] In some embodiments, the method further comprises: forming a third structure, the third structure comprising a first surface and a second surface opposite to the first surface; and bonding the second surface of the first structure to the first surface of the third structure using the second bonding pad. In some embodiments, the first structure and the second structure are bonded in a face-to-face configuration. In some embodiments, the first structure and the third structure are bonded in a face-to-back configuration. In some embodiments, the first structure and the third structure are semiconductor dies, and wherein the second structure is a semiconductor wafer. In some embodiments, the method further comprises: bonding the second surface of the third structure to an interposer, the third structure being located between the first structure and the interposer. In some embodiments, the method further comprises: bonding the first die to the interposer, the interposer comprising a local interconnect embedded in the interposer, the local interconnect coupled to the first die and the third structure.

[0118] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first structure, wherein forming the first structure comprises: forming a first interconnect structure above a first substrate, the first interconnect structure comprising a metallization pattern; forming a first substrate through-hole passing through the first interconnect structure and the first substrate; and forming a first bonding pad above the first interconnect structure, and the first bonding pad is connected to the first substrate through-hole and the metallization pattern of the first interconnect structure; bonding the first structure to a second structure; after bonding, forming a second substrate through-hole passing through the first substrate of the first structure to the first interconnect structure, the second substrate through-hole having a width smaller than the first substrate through-hole; thinning the first substrate, wherein the thinning exposes the first substrate through-hole; and forming a second bonding pad on the first structure, the second bonding pad being electrically coupled to the first substrate through-hole and the second substrate through-hole.

[0119] In some embodiments, the method further comprises bonding the second bonding pad of the first structure to a third structure, the third structure comprising a through substrate via. In some embodiments, the second structure comprises a semiconductor die.

[0120] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A first structure comprising a first surface and a second surface opposite to the first surface, wherein the first structure comprises: a first substrate; a first substrate through-hole exposed from the second surface of the first substrate, the first substrate through-hole having a first width; a second through-substrate via exposed from the second surface of the first structure, the second through-substrate via having a second width smaller than the first width; a guard ring surrounding each of the first through substrate via and the second through substrate via; and A second structure is bonded to the first surface of the first structure, the first surface including a first bonding pad.

2. The semiconductor device according to claim 1, wherein The first structure also includes: an active metallization pattern connected to active devices in the first structure; a substrate, the first surface being located on a first side of the substrate; a first interconnect structure located on the first side of the substrate, the guard ring and the active metallization pattern being located in the first interconnect structure; and A second bonding pad is located on a second side of the substrate, the second bonding pad being electrically coupled to the first through substrate via and the second through substrate via.

3. The semiconductor device according to claim 2, further comprising: A third structure is bonded to the second bonding pad of the first structure.

4. The semiconductor device according to claim 3, wherein: The first structure and the second structure are joined in a face-to-face configuration.

5. The semiconductor device according to claim 4, wherein: The first structure and the third structure are joined in a face-to-back configuration.

6. The semiconductor device according to claim 3, wherein: Each of the first structure, the second structure, and the third structure is a semiconductor wafer.

7. The semiconductor device according to claim 3, wherein: Each of the first structure, the second structure, and the third structure is a semiconductor die.

8. The semiconductor device according to claim 3, further comprising: The interposer is bonded to the third structure, and the third structure is located between the first structure and the interposer.

9. A method of forming a semiconductor device, comprising: forming a first structure, the first structure comprising a first surface and a second surface opposite to the first surface, wherein forming the first structure comprises: forming a first interconnect structure over a first substrate, the first interconnect structure comprising an active metallization pattern and a guard ring; forming a first through-substrate via passing through the first interconnect structure and the first substrate, the guard ring surrounding the first through-substrate via in the first interconnect structure; and forming a first bonding pad over the first interconnect structure and connected to the first through substrate via and the active metallization pattern of the first interconnect structure, the first bonding pad being located on the first surface of the first structure; forming a second structure comprising a first surface and a second surface opposite to the first surface; Bonding the first surface of the first structure to the first surface of the second structure; after bonding, forming a second through-substrate via from the second surface of the first structure to the first interconnect structure, the second through-substrate via having a width smaller than the first through-substrate via; exposing the first through-substrate via at the second surface of the first structure; and A second bonding pad is formed on the second surface of the first structure, the second bonding pad being electrically coupled to the first through substrate via and the second through substrate via.

10. A method of forming a semiconductor device, comprising: forming a first structure, wherein forming the first structure comprises: forming a first interconnect structure over a first substrate, the first interconnect structure comprising a metallization pattern; forming a first through-substrate via passing through the first interconnect structure and the first substrate; and forming a first bonding pad over the first interconnect structure and connected to the first through substrate via and the metallization pattern of the first interconnect structure; bonding the first structure to a second structure; After bonding, forming a second substrate through-hole via from the first substrate of the first structure to the first interconnect structure, the second substrate through-hole having a width smaller than the first substrate through-hole; thinning the first substrate, wherein the thinning exposes the first substrate through-holes; and A second bonding pad is formed on the first structure, the second bonding pad being electrically coupled to the first through substrate via and the second through substrate via.

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