Semiconductor structure, forming method thereof and contact structure

Abstract

A structure according to an embodiment of the present disclosure includes: a bottom metal member; a semiconductor substrate disposed over the bottom metal feature; an interconnect structure disposed over the semiconductor substrate; a top metal feature over the interconnect structure; and a via structure extending from a bottom surface of the top metal feature through the interconnect structure and the semiconductor substrate to contact a top surface of the bottom metal feature. The via structure includes a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnect structure. The bottom portion and the top portion taper toward the top metal member. The bottom portion includes a first taper angle and the top portion includes a second taper angle less than the first taper angle. The embodiment of the invention also relates to a semiconductor structure, a forming method thereof and a contact structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor structure, a method for forming the same, and a contact structure. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] In addition to smaller device sizes in each generation, packaging technology is also constantly evolving to further improve the performance of IC devices. For example, three-dimensional (3D) packaging technology was introduced to vertically stack multiple IC devices. Through-substrate vias (TSVs) are commonly used in 3D device packages because they are configured to route electrical signals from one side of the silicon substrate of an IC chip to the other side thereof. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor structure, comprising: a bottom metal component; a semiconductor substrate, disposed above the bottom metal component; an interconnection structure, disposed above the semiconductor substrate; a top metal component, located above the interconnection structure; and a through-hole structure, extending from a bottom surface of the top metal component through the interconnection structure and the semiconductor substrate to contact a top surface of the bottom metal component, wherein the through-hole structure comprises a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnection structure, wherein the bottom portion and the top portion gradually taper toward the top metal component, wherein the bottom portion comprises a first taper angle, and the top portion comprises a second taper angle smaller than the first taper angle.

[0005] Other embodiments of the present application provide a contact structure, comprising: a dielectric layer; a top metal component disposed in the dielectric layer; an interconnect structure disposed above the dielectric layer and the top metal component, the interconnect structure comprising a guard ring structure; a substrate located above the interconnect structure; and a through-hole structure extending through the substrate and the interconnect structure to contact the top metal component, wherein the through-hole structure comprises a bottom portion surrounded by the guard ring structure and a top portion disposed above the bottom portion, wherein the top portion is suspended above the guard ring structure.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: providing an intermediate structure, including: a metal component, arranged in a dielectric layer, an interconnect structure, arranged above the metal component and the dielectric layer, and a substrate, arranged above the interconnect structure; forming a guide opening through the substrate and the interconnect structure to expose the top surface of the metal component; depositing a polymer plug in the guide opening; forming a patterned hard mask above the intermediate structure and the polymer plug, the patterned hard mask including a pattern opening surrounding the polymer plug; using the patterned hard mask as an etching mask to etch the substrate, the polymer plug and the interconnect structure to form a through-hole opening to expose the metal component; forming a dielectric liner above the sidewall of the through-hole opening; depositing a barrier layer above the dielectric liner; depositing a metal plug above the barrier layer; depositing an etch stop layer (ESL) above the metal plug and the substrate; and planarizing the etch stop layer until the etch stop layer and the top surface of the metal plug are coplanar. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart illustrating an embodiment of a method of forming a device structure and a via structure therethrough according to various aspects of an embodiment of the present disclosure.

[0009] Figures 2 to 17 It is the experience according to various aspects of the embodiments of the present disclosure Figure 1 A partial cross-sectional view of a WIP structure during the method of operation.

[0010] Figures 18 to 20 A partial cross-sectional view of a device structure according to various alternative embodiments of the present disclosure is shown.

[0011] Fig.21 and Fig. 22 A partial cross-sectional view of an IC device package including a through-via structure according to embodiments of the present disclosure is shown in accordance with various aspects of embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The disclosed embodiments relate generally to integrated circuit devices, and more particularly, to interconnect structures for integrated circuit devices.

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0016] The interconnect structure electrically couples the various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on the substrate so that the various components can operate as specified by the design requirements. The interconnect structure includes a combination of a dielectric layer and a conductive layer configured to provide electrical signal routing. The conductive layer includes through holes and contact components that provide vertical connections and wires that provide horizontal connections. In some embodiments, the interconnect structure may have eight (8) to twenty (20) levels of metal layers (or metallization layers) that are vertically interconnected by through holes or contact components. The interconnect structure routes signals between components of the IC device and / or distributes signals (e.g., clock signals, voltage signals, and / or ground signals) to components. In order to allow multiple IC chips to be stacked vertically in a 3D package, it is desirable to provide vertical interconnects extending through the interconnect structure and / or the substrate to facilitate the various device structures. Such a vertical interconnect may be referred to as a through silicon via or through substrate via (TSV) because it extends in whole or in part through the semiconductor substrate. The term TSV in the embodiments of the present disclosure broadly encompasses a through-hole structure that provides direct signal routing from the front side of a substrate to the back side of a substrate, or vice versa.

[0017] As IC devices become more complex and the interconnect structures include more and more metallization layers, TSVs may have high aspect ratios. The resistance associated with high aspect ratio TSVs may begin to play a role in device performance. Conceptually, the resistance associated with TSVs can be reduced by increasing the size of the TSVs or by using more conductive materials. Both routes present challenges. For example, TSVs and protection structures around TSVs compete for spacing with functional devices and routing metal features. Increasing the size of TSVs may displace functional devices and degrade device performance. In addition, some existing TSVs are already formed of sufficiently conductive materials.

[0018] The present disclosure provides a TSV structure with reduced total resistance. The exemplary TSV according to the present disclosure extends through a semiconductor substrate and an interconnect structure disposed above the semiconductor substrate. The exemplary TSV includes a first portion in the semiconductor substrate and a second portion in the interconnect structure. The first portion tapers toward the interconnect structure, and the second portion tapers away from the semiconductor substrate. Although the first portion and the second portion taper in the same direction, the first portion tapers at a larger taper angle than the second portion. In other words, the TSV widens in the semiconductor substrate. The wider first portion allows the TSV to have reduced contact resistance without interfering with active devices formed on the semiconductor substrate.

[0019] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 FIG. 2 is a diagram showing various aspects of a work-in-progress (WIP) structure 200 ( Figures 2 to 17100 is a flowchart of a method 100 for forming a contact structure on a substrate (shown in FIG. 100 ). The method 100 is merely an example and is not intended to limit the disclosed embodiments to those explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 17 Describing method 100, Figures 2 to 17 1 is a partial cross-sectional view of a WIP structure 200 at different manufacturing stages according to various embodiments of the method 100. Because the WIP structure 200 will be manufactured into a tube die, the WIP structure 200 may be referred to as a tube die 200 herein as the context requires. For the avoidance of doubt, Figures 2 to 20 The X, Y and Z directions are perpendicular to each other. Throughout the embodiments of the present disclosure, the same reference numerals represent the same components unless otherwise explicitly described.

[0020] refer to Figure 1 and Figure 2 , method 100 includes block 102, where a WIP structure 200 is provided. Figure 2, the WIP structure 200 includes a substrate 202 and an interconnect structure 206. The substrate 202 includes a front side 202F and a back side 202B. The interconnect structure 206 is disposed over the front side 202F of the substrate 202. In one embodiment, the substrate 202 is a semiconductor substrate formed of silicon (Si). Alternatively or additionally, the substrate 202 may include: another element semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Alternatively, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor substrate on insulator can be manufactured using isolation by implantation of oxygen (SIMOX), wafer bonding and / or other suitable methods. The substrate 202 may include various doped regions (not shown), depending on the design requirements of the die 200. In some embodiments, the substrate 202 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant, such as boron (e.g., BF2), other p-type dopants, or a combination thereof. In some embodiments, the substrate 202 includes an n-type doped region (e.g., an n-type well) doped with an n-type dopant, such as phosphorus (P), arsenic (As), other n-type dopants, or a combination thereof. In some embodiments, the substrate 202 includes a doped region formed with a combination of a p-type dopant and an n-type dopant. The various doped regions may be formed directly on and / or in the substrate 202, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and / or other suitable doping processes may be implemented to form the various doped regions. In some embodiments, the substrate 202 in the WIP structure 200 may have a thickness between about 5 μm and about 60 μm. It should be noted that when the WIP structure 200 is first formed, the substrate 202 may have a much greater thickness (i.e., between about 750 μm and about 800 μm). To accommodate the formation of the via structure, the substrate 202 is thinned to a thickness between about 5 μm and about 60 μm.

[0021] A plurality of transistors are formed on the front side 202F. Figure 2204 is shown in the figure to represent multiple transistors. Transistor 204 can be a planar transistor or a multi-gate transistor, such as a fin FET (FinFET) or a gate-all-around (GAA) transistor. GAA transistors can include channel regions of various shapes, including nanowires, nanorods, or nanosheets, which can be collectively referred to as nanostructures. GAA transistors can also be referred to as multi-bridge channel (MBC) transistors or gate-all-around transistors (SGTs). Figure 2 The transistor 204 representatively shown in FIG. 2 is a FinFET, which includes a fin structure ( Figure 2 The fin structure may be formed by a substrate 202, which may be a silicon (Si) substrate, or an epitaxial layer formed on the substrate 202. Although the transistor 204 is Figure 2 Although shown as a FinFET in EMBODIMENT 2 and subsequent figures, it should be understood that transistor 204 may also be a planar device or a GAA transistor.

[0022] Although not explicitly shown, the gate structure 204G includes an interface layer that interfaces with the fin structure, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0023] The gate electrode layer of the gate structure 204G may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof.

[0024] The source / drain component 204SD may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain component 204SD is n-type, it may include silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As). When the source / drain component 204SD is p-type, it may include silicon germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron difluoride (BF2). In some optional embodiments not explicitly shown in the figures, the source / drain component 204SD may include multiple layers. In one example, the source / drain component 204SD may include a lightly doped first epitaxial layer above the source / drain region of the fin structure, a heavily doped second epitaxial layer above the lightly doped first epitaxial layer, and a capping epitaxial layer disposed above the heavily doped second epitaxial layer. The first epitaxial layer has a lower dopant concentration or a smaller germanium content (when germanium is present) than the second epitaxial layer to reduce lattice mismatch defects. The second epitaxial layer has the highest dopant concentration or the highest germanium content (when germanium is present) to reduce resistance and increase strain on the channel. The capping epitaxial layer may have a smaller dopant concentration and germanium content (when germanium is present) than the second epitaxial layer to increase etching resistance.

[0025] The interconnect structure 206 may include eight (8) to twenty (20) metal layers. Each of the metal layers includes an etch stop layer (ESL) and an intermetallic dielectric (IMD) layer disposed on the ESL. The ESL may share the same composition and may include silicon nitride or silicon oxynitride. The IMD layer may share the same composition and may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of low-k dielectric materials include carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide. In some embodiments, the interconnect structure 206 in the WIP structure 200 may have a thickness between about 0.5 μm and about 3.5 μm.

[0026] Each of the metal layers in the interconnect structure 206 includes a plurality of vertically extending vias and horizontally extending metal lines. The vias and metal lines function to connect a plurality of transistors on the substrate 202, such as transistor 204. In addition to the vias and metal lines, the interconnect structure 206 also includes a guard ring structure 210. Figure 2 In some embodiments shown in , the guard ring structure 210 includes a plurality of ring layers in the metal layer. Each of the plurality of ring layers includes a lower portion and an upper portion disposed above the lower portion. As used herein, a ring refers to a structure that continuously extends around a space to form a closed loop. Figure 2 As shown in , each of the multiple ring layers is a closed ring on the XY plane, and the multiple ring layers are stacked vertically to define a through-hole penetration interval in the interconnect structure 206. In order to prevent metal contamination during the formation of a guide opening or a through-hole opening through the through-hole penetration interval, the through-hole penetration interval is free of metal. In one embodiment, the guard ring structure 210 has a circular shape when viewed along the Z direction. In some optional embodiments, the guard ring structure 210 can be a rectangular, square, hexagonal, octagonal or other polygonal shape when viewed along the Z direction. In the depicted embodiment, the guard ring structure 210 includes a first width W1. When the guard ring structure 210 is circular, the first width W1 represents the outer diameter of the guard ring structure 210.

[0027] exist Figure 2In some embodiments shown in, the guard ring structure 210 has a smooth inner wall. This arrangement is not insignificant. It can be observed that any protrusion or groove in the inner wall of the guard ring structure 210 can enhance the stress acting on the guard ring structure 210 or the structure near and outside the guard ring structure 210. The through hole, metal line and guard ring structure 210 in the interconnect structure 206 may include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al) and / or other suitable materials. In one embodiment, they may include copper (Cu). In some embodiments, in order to prevent electromigration from metal materials or oxygen diffusion from dielectric components into metal materials, through holes, metal lines and ring layers may each include a barrier layer to interface with ESL and IMD layers.

[0028] exist Figure 2 In some embodiments shown in , the WIP structure 200 also includes a first passivation layer 214, a first ESL 216 above the first passivation layer 214, a second passivation layer 218, and a second ESL 220 above the second passivation layer 218. In some embodiments, the first passivation layer 214 and the second passivation layer 218 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The first ESL 216 and the second ESL 220 may include silicon nitride or silicon oxynitride. In Figure 2 In some embodiments shown in , the WIP structure 200 includes a first top metal component 224 and a second top metal component 226 disposed in a first ESL 216, a second passivation layer 218, and a second ESL 220. In some instances, the first top metal component 224 and the second top metal component 226 may include copper (Cu), aluminum (Al), or an alloy of aluminum and copper. To prevent electromigration, the first top metal component 224 and the second top metal component 226 may be separated from the first ESL 216, the second passivation layer 218, and the second ESL 220 by a first barrier layer 223 and a second barrier layer 225, respectively. The first barrier layer 223 and the second barrier layer 225 may include titanium nitride (TiN) or tantalum nitride (TaN). In Figure 2 In the embodiment shown in , the first top metal feature 224 is configured to be coupled to a TSV extending through the guard ring structure 210 , and the second top metal feature 226 is electrically coupled to the top metal line 212 of the interconnect structure 206 through a plurality of contact vias.

[0029] refer to Figure 1 , Figure 2 and Figure 3 , the method 100 includes a frame 104, wherein a guide opening 244 is formed through the substrate 202 and the interconnect structure 206. To form the guide opening 244, a first masking layer 240 is formed over the back side 202B of the substrate 202. The first masking layer 240 may include a bottom anti-reflective coating (BARC) layer, a photoresist layer, silicon oxide, or silicon nitride. In one embodiment, the first masking layer 240 may be a photoresist layer having a thickness between about 5 μm and about 15 μm. The first masking layer 240 may be deposited using spin coating or flowable chemical vapor deposition (FCVD). Then, the deposited first masking layer 240 undergoes a pre-exposure baking process, exposure to radiation reflected from a photomask or transmitted through the photomask, a post-exposure baking process, and a development process to form a first patterned mask 240. The first patterned mask 240 has a first opening 242. In some examples, the first opening 242 has a second width W2. When the first opening 242 is substantially circular in the top view, the second width W2 represents the diameter of the first opening 242. The first patterned mask 240 is then applied as an etching mask to etch the substrate 202, the interconnect structure 206, the first passivation layer 214, and the first barrier layer 223. The etching process for frame 104 can be an anisotropic dry etching process (e.g., a reactive ion etching (RIE) process). In some examples, the exemplary dry etching process can implement an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. When the guide opening 244 reaches the top surface of the first top metal component 224, the etching is terminated at frame 104. After the guide opening 244 is formed, the first patterned mask 240 is selectively removed by ashing or selective etching. In some examples, the guide opening 244 shares the same second width W2 as the first opening 242. When the guide opening 244 is substantially circular in top view, the second width W2 represents the diameter of the guide opening 244. Figure 3 As shown in FIG. 2 , the guide opening 244 vertically penetrates the guard ring structure 210 and exposes a portion of the first top metal component 224. To ensure that the guide opening 244 penetrates the guard ring structure 210, the second width W2 is smaller than the first width W1.

[0030] refer to Figure 1 and Figure 4, method 100 includes block 106, in which a sacrificial plug 246 is formed in guide opening 244. Sacrificial plug 246 is formed of an organic polymer including carbon (C), hydrogen (H), oxygen (O), nitrogen (N), or a combination thereof. In some embodiments, sacrificial plug 246 may include poly(methyl methacrylate) (PMMA), poly(methyl acrylate) (PMA), polymaleimide (PMAI), or a copolymer thereof. To form sacrificial plug 246, a material for sacrificial plug 246 is deposited over WIP structure 200 and guide opening 244 by spin coating. After curing the deposited material by exposure to ultraviolet (UV) radiation, exposure to water, or annealing, the cured material for sacrificial plug 246 is etched back until back side 202B of substrate 202 is exposed, as shown. Figure 4 At this time, a sacrificial plug 246 is formed in the guide opening 244. The sacrificial plug 246 protects the first top metal feature 224 in a subsequent etching process.

[0031] refer to Figure 1 and Figure 5 , the method 100 includes a block 108, in which a second patterned mask 250 is formed over the WIP structure 200. To form the second patterned mask 250, a second masking layer 250 is deposited over the back side 202B of the substrate 202. The second masking layer 250 may include a bottom anti-reflective coating (BARC) layer, a photoresist layer, silicon oxide, or silicon nitride. In one embodiment, the second masking layer 250 may be a photoresist layer having a thickness between about 5 μm and about 15 μm. The second masking layer 250 may be deposited using spin coating or FCVD. The deposited second masking layer 250 then undergoes a pre-exposure bake process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure bake process, and a development process to form a Figure 5 The second patterned mask 250 shown in FIG. The second patterned mask 250 has a second opening 252. Figure 5 In some embodiments shown in , the second opening 252 has a third width W3. When the second opening 252 is substantially circular in the top view, the third width W3 represents the diameter of the second opening 252. The third width W3 is greater than the second width W2. In some examples, the ratio of the second width W2 to the third width W3 can be between about 1.1 and about 3. When the ratio of the second width W2 to the third width W3 is greater than 1.5, the second opening 252 can overlap at least partially with the outer contour of the guard ring structure 210.

[0032] refer to Figure 1 and Figure 6, the method 100 includes a block 110, wherein the substrate 202, the interconnect structure 206, and the sacrificial plug 246 are etched using the second patterned mask 250 as an etch mask to form a through-hole opening 254. The second patterned mask 250 is then applied as an etch mask to etch the substrate 202, the interconnect structure 206, the sacrificial plug 246, the first passivation layer 214, and the first barrier layer 223. In the block, the etching process includes an isotropic etching process. The isotropic etching process may be a wet isotropic etching process or a dry isotropic etching process. An exemplary wet isotropic etching process may include using dilute hydrofluoric acid (DHF), hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), deionized water (H2O), or a mixture thereof. An exemplary dry isotropic etching process may include using sulfur hexafluoride (SF6) gas. The isotropic etching process in block 110 simultaneously widens the guide opening 244 as it etches into the sacrificial plug 246, the IMD layer, and the ESL in the interconnect structure 206. Thus, the via opening 254 may include a first portion that is primarily below the substrate 202 and a second portion that is primarily within the substrate 202. Figure 6 In the embodiment, both the first portion and the second portion taper downward toward the first top metal component 224. The first portion includes a taper angle that is greater than the taper angle of the second portion. Figure 6 As shown in , a first portion of the via opening 254 remains surrounded by the guard ring structure 210. A second portion of the via opening 254 may extend directly over at least a portion of the guard ring structure 210. After forming the via opening 254, the second patterned mask 250 is selectively removed by ashing or selective etching. Because the via opening 254 includes a first portion and a second portion of different widths, the via opening 254 may be referred to as a dual damascene opening.

[0033] refer to Figure 1 and Figure 7 , the method 100 includes block 112, where a dielectric liner 256 is deposited over the WIP structure 200 and the via opening 254. In some embodiments, the dielectric liner 256 includes silicon nitride or silicon oxide. In an exemplary process, a material layer for the dielectric liner 256 is first deposited over the WIP structure 200 and the via opening 254 by atomic layer deposition (ALD) or CVD. In one embodiment, the material layer is deposited using ALD. An anisotropic etch back process is then performed to remove the material layer on the top-facing surface of the substrate 202 and the first top metal feature 224 to form Figure 72. The dielectric liner 256 is shown in FIG. The dielectric liner 256 covers the sidewalls of the via opening 254. The anisotropic etching process in block 112 may include using an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof.

[0034] refer to Figure 1 and Figures 8 to 10 , the method 100 includes block 114, where a barrier layer 260 is deposited over the dielectric liner 256. Figures 8 to 10 In some embodiments shown in FIG. 2 , the barrier layer 260 is not deposited to cover the first top metal feature 224. To achieve this, a self-assembled monolayer (SAM) 258 is selectively deposited on the exposed surface of the first top metal feature 224, such as Figure 8 In one embodiment, SAM 258 may include tetrakis(dimethylamino)titanium (TDMAT). In some optional embodiments, SAM 258 may be formed by a molecule including a head group (or anchor) and a tail group. In some instances, the head group may include phosphorus (P), sulfur (S) or silicon (Si), and in some instances, they may be in the form of a phosphate, sulfate or silane-based substance. The tail group may include a carbon chain, such as a carbon chain including olefins and alkynes. In some instances, the molecule forming SAM 258 (or the head group of the molecule for SAM 258) may include ODPA (octadecylphosphonic acid), organic sulfur or thiol (e.g., dodecanethiol, alkanethiols). In some other embodiments, the molecule forming SAM 258 may include (3-aminopropyl) triethoxysilane (APTES). In some examples, the SAM 258 may be attached to a conductive layer, such as the first top metal feature 224, but not substantially attached to a surface of the substrate 202 or the dielectric liner 256 formed of a semiconductor material or a dielectric material. Fig. 9 , after depositing SAM 258 to cover first top metal feature 224, barrier layer 260 is deposited over WIP structure 200. Because the precursor of barrier layer 260 has a low affinity for SAM 258 (i.e., SAM 258 repels the precursor of barrier layer 260), SAM 258 acts as a barrier or blocking layer for barrier layer 260. In some embodiments, barrier layer 260 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), or a combination thereof. In some alternative embodiments, SAM 258 is not deposited over first top metal feature 224, and barrier layer 260 is deposited over the top surface of first top metal feature 224, such as Fig.18 and Fig.19 as shown in .

[0035] refer to Figure 1 and Fig.11 , the method 100 includes a frame 116, in which a metal fill layer 262 is formed over the via opening 254. The metal fill layer 262 may include copper (Cu), aluminum (Al), cobalt (Co), a copper alloy, tantalum (Ta), titanium (Ti), or tungsten (W). In one embodiment, the barrier layer 260 includes titanium nitride (TiN), and the metal fill layer 262 includes copper (Cu). The metal fill layer 262 is deposited using electroplating, physical vapor deposition (PVD), CVD, chemical plating, or a suitable method. In one embodiment, the metal fill layer 262 is formed using electroplating. In this embodiment, after the barrier layer 260 is formed, a seed layer (not shown) may be deposited over the WIP structure 200 (including over the surface of the barrier layer 260) using PVD or a suitable process. Then, the metal fill layer 262 may be deposited over the seed layer using electroplating. In an embodiment using electroplating, the seed layer may include copper (Cu), titanium (Ti), or a combination thereof, and the metal fill may include copper (Cu). The seed layer may be considered to be part of the metal fill layer 262. After the metal fill layer 262 is deposited over the WIP structure 200 and in the via opening 254, a planarization process, such as CMP, may be performed to provide a substantially coplanar top surface. Fig.11 As shown in , the planarization process can etch the substrate 202 at a higher rate, so that the metal filling layer 262 and the barrier layer 260 rise above the top surface of the substrate 202. At this time, a via structure 264 is formed. The via structure 264 includes a dielectric liner 256, a barrier layer 260 and a metal filling layer 262. The via structure 264 can be called a dual damascene via structure.

[0036] refer to Figure 1 , Fig.12 and Fig.13 , the method 100 includes block 118, in which an etch stop layer (ESL) 270 is formed over the substrate 202. In block 118, the ESL 270 is deposited over the WIP structure 200 by ALD or CVD. After depositing the ESL 270, the WIP structure 200 is planarized so that the top surfaces of the via structure 264 and the ESL 270 are coplanar, as shown in FIG. Fig.13 Because the via structure 264 rises above the top surface of the substrate 202, the top surface of the substrate 202 remains covered by the ESL 270. The planarization in block 118 may include a chemical mechanical polishing (CMP) process.

[0037] refer to Figure 1 and Figures 13 to 20, the method 100 includes block 120, wherein further processing is performed. Such further processing may include: depositing a backside dielectric layer 272 ( Fig.13 ); patterning the backside dielectric layer 272 to form a contact opening 280 ( Fig.14 and Fig.15 and forming a contact member 286 ( Fig.16 and Fig.17 ). Fig.13 After planarization in block 118, a backside dielectric layer 272 is deposited over the top surface of the via structure 264 and the substrate 202. The backside dielectric layer 272 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the backside dielectric layer 272 may be deposited using spin coating, FCVD, or CVD.

[0038] Reference now Fig.14 . A third patterned mask 276 is formed over the backside dielectric layer 272. The third patterned mask 276 includes a third opening 278 to expose a portion of the backside dielectric layer 272. In order to form the third patterned mask 276, a third masking layer 276 is deposited over the backside dielectric layer 272. The third masking layer 276 may include a bottom anti-reflective coating (BARC) layer, a photoresist layer, silicon oxide, or silicon nitride. In one embodiment, the third masking layer 276 may be a photoresist layer having a thickness between about 5 μm and about 15 μm. The third masking layer 276 may be deposited using spin coating or FCVD. The deposited third masking layer 276 then undergoes a pre-exposure baking process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure baking process, and a developing process to form a Fig.14 The third patterned mask 276 is shown in FIG. The third patterned mask 276 has a third opening 278. Fig.14 In some embodiments shown in , the third opening 278 has a fourth width W4. When the third opening 278 is substantially circular in top view, the fourth width W4 represents the diameter of the third opening 278. The fourth width W4 is greater than the third width W3 to ensure that the through-hole structure 264 is fully engaged with the contact feature to be formed in the opening formed using the third opening 278. Fig.15. A third pattern mask 276 is applied as an etching mask to etch the backside dielectric layer 272 to form a contact opening 280. The etching process for forming the contact opening 280 may include using an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), a chlorine-containing gas (e.g., Cl2 and / or BCl3), a bromine-containing gas (e.g., HBr), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. The contact opening 280 may also have a fourth width W4, like the third opening 278.

[0039] Reference now Fig.16 and Fig.17 . A barrier layer 282 is deposited over the WIP structure 200 (including over the contact opening 280). The barrier layer 282 may include titanium nitride (TiN) or tantalum nitride (TaN) and may be deposited using CVD or metal organic CVD (MOCVD). After the barrier layer 282 is deposited, a seed layer (not explicitly shown) is deposited using PVD. The seed layer may include titanium (Ti) or copper (Cu). A metal fill 284 is then deposited over the barrier layer 282 using electrochemical plating (ECP). The metal fill 284 may include copper (Cu), aluminum (Al), or an alloy of aluminum and copper. In some embodiments, the metal fill 284 over the contact opening 280 may be thicker, such as Fig.16 As shown in . Fig.17 A planarization process, such as a CMP process, is performed to remove excess material. At this time, a contact component 286 is formed. The contact component 286 includes a barrier layer 282 and a metal filling layer 284.

[0040] like Fig.17As shown in , the via structure 264 includes a first portion 262-1 substantially disposed in the interconnect structure 206 and the first passivation layer 214 and a second portion 262-2 substantially disposed in the substrate 202. The via structure 264 includes a first dimension D1 at its interface with the first top metal component 224, a second dimension D2 at the interface between the first portion 262-1 and the second portion 262-2, and a third dimension D3 at the interface between the via structure 264 and the contact component 286. In some examples, the third dimension D3 is between about 2 μm and about 4 μm. In some embodiments, the second dimension D2 is greater than or equal to the first dimension D1, and the third dimension D3 is greater than or equal to the second dimension D2. The via structure 264 has a foot angle α with the top surface of the top metal component 224. The via structure 264 also has a transition angle β across the interface between the first portion 262-1 and the second portion 262-2. The ratio of the second dimension D2 to the first dimension D1 can be between 1.05 and 1.25. The ratio of the third dimension D3 to the second dimension D2 can be between about 1 and 3. In some embodiments, the footing angle α can be between about 70° and about 90°. That is, the footing angle α is an acute angle. The transition angle β can be between about 180° and about 200°. That is, the transition angle β is greater than a right angle (i.e., 180°). In some examples, the aspect ratio of the through hole structure 264 can be between about 5 and about 15. Fig.17 In some embodiments shown in FIG. 1 , the interface between the first portion 262-1 and the second portion 262-2 is located at the interface between the interconnect structure 206 and the substrate 202. Due to the use of SAM 258 in block 114, the barrier layer 260 does not extend between the first top metal feature 224 and the via structure 264. Fig.17 In some embodiments shown in , the second portion 262-2 widens so much away from the interface between the first portion 262-1 and the second portion 262-2 that the second portion 262-2 overhangs part or all of the guard ring structure 210. That is, along the Z direction, the vertical projection area of ​​the second portion 262-2 partially or completely overlaps the vertical projection area of ​​the guard ring structure 210.

[0041] Figures 18 to 20 An exemplary alternative embodiment is shown. Fig.18 An embodiment is shown in which the SAM 258 is not deposited to block the first top metal feature 224. Thus, the barrier layer 260 extends between the first top metal feature 224 and the via structure 264. Fig.19 An embodiment is shown in which the interface between the first portion 262 - 1 and the second portion 262 - 2 is moved away from the interconnect structure 206 and is completely located in the substrate 202 . Fig. 20An embodiment is shown in which the SAM 258 is not deposited to block the first top metal feature 224 and the interface between the first portion 262-1 and the second portion 262-2 is moved away from the interconnect structure 206. According to an embodiment of the present disclosure, the interface between the first portion 262-1 and the second portion 262-2 should be located at the interface between the interconnect structure 206 and the substrate 202, or be completely disposed in the substrate 202 to prevent damage to or interference with the front end of line (FEOL) devices.

[0042] Fig.21 2 is a partial cross-sectional view of an IC device package 400 including a die 200. The die 200 formed by the WIP structure 200 includes a substrate 202 and an interconnect structure 206. A transistor 204 (one is shown for representation) is formed over the substrate 202. The die 200 may be surrounded and protected by a molding material 290. The die 200 is bonded to the die 420 by direct bonding. The bonding pads on the die 200 (such as bonding pad 288) are aligned with the bonding pads on the die 420 (such as bonding pad 426) and bonded to the bonding pads on the die 420. The dielectric layers around the bonding pads on the die 200 and 420 are also in contact and bonded together. The die 420 is bonded to the die 440 by direct bonding. The die 420 is surrounded by a molding material 430. The die 200 includes a solder component 295 to interface with a package substrate, an interposer, or a printed circuit board (PCB) substrate. The via structure 264 includes a first portion ( Fig.17 262-1) and a second portion ( Fig.17 262-2 in FIG. 262-2). The second portion tapers toward the interconnect structure 206. The first portion is surrounded by a guard ring structure 210. The interface between the first portion and the second portion is located either at the interface between the substrate 202 and the interconnect structure 206 or in the substrate 202. The solder component 295 is closer to the first portion than the second portion.

[0043] Fig. 22 5 is a partial cross-sectional view of an IC device package 500 including a die 510 bonded to a die 520 and a die 530. The die 520 and 530 are arranged side by side and bonded to a carrier substrate 540. The die 510 includes a substrate 502 and an interconnect structure 506 disposed on the substrate 202. The die 510 includes a through-hole structure 550 extending through a portion of the substrate 502 and the interconnect structure 506. Each of the through-hole structures 550 includes a first portion disposed in the interconnect structure 506 and a second portion disposed in the substrate 502. The first portion is formed by a hole similar to Fig.17The first portion is surrounded by the guard ring of the guard ring structure 210 shown in FIG. The second portion tapers toward the interconnect structure 506. The interface between the first portion and the second portion is located either at the interface between the substrate 502 and the interconnect structure 506 or in the substrate 502. The die 510 includes a solder component 560, which may be a microbump. Fig.21 Unlike the through-hole structure 264 in FIG. 5 , the second portion is closer to the solder feature 560 than the first portion.

[0044] In one exemplary aspect, embodiments of the present disclosure relate to a structure. The structure includes: a bottom metal component; a semiconductor substrate disposed above the bottom metal component; an interconnect structure disposed above the semiconductor substrate; a top metal component located above the interconnect structure; and a via structure extending from a bottom surface of the top metal component through the interconnect structure and the semiconductor substrate to contact a top surface of the bottom metal component. The via structure includes a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnect structure. The bottom portion and the top portion taper toward the top metal component. The bottom portion includes a first taper angle, and the top portion includes a second taper angle that is less than the first taper angle.

[0045] In some embodiments, the structure further comprises: an etch stop layer (ESL) disposed between the semiconductor substrate and the bottom metal component. The bottom surface of the bottom metal component is coplanar with the bottom surface of the ESL. In some embodiments, the bottom portion of the through-hole structure is completely disposed under the interconnect structure. In some embodiments, the through-hole structure is spaced apart from the semiconductor substrate and the interconnect structure by a dielectric liner. In some instances, the dielectric liner comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the structure further comprises: a barrier layer sandwiched between the through-hole structure and the dielectric liner. In some embodiments, the barrier layer comprises titanium, tantalum, tantalum nitride, or titanium nitride.

[0046] In another exemplary aspect, embodiments of the present disclosure relate to a contact structure. The contact structure includes: a dielectric layer; a top metal component disposed in the dielectric layer; an interconnect structure disposed above the dielectric layer and the top metal component, the interconnect structure including a guard ring structure; a substrate disposed above the interconnect structure; and a via structure extending through the substrate and the interconnect structure to contact the top metal component. The via structure includes a bottom portion surrounded by the guard ring structure and a top portion disposed above the bottom portion. The top portion is suspended above the guard ring structure.

[0047] In some embodiments, the bottom portion and the top portion taper toward the top metal component, and the bottom portion includes a first taper angle, and the top portion includes a second taper angle greater than the first taper angle. In some embodiments, the contact structure further includes: an etch stop layer (ESL) located above the substrate, and the top surfaces of the through-hole structure and the ESL are coplanar. In some embodiments, the contact structure further includes: a barrier layer sandwiched between the ESL and the through-hole structure.

[0048] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: providing an intermediate structure, the intermediate structure including: a metal component disposed in a dielectric layer, an interconnect structure disposed above the metal component and the dielectric layer, and a substrate disposed above the interconnect structure; forming a guide opening through the substrate and the interconnect structure to expose a top surface of the metal component; depositing a polymer plug in the guide opening; forming a patterned hard mask over the intermediate structure and the polymer plug, the patterned hard mask including a pattern opening surrounding the polymer plug; using the patterned hard mask as an etching mask to etch the substrate, the polymer plug, and the interconnect structure to form a through-hole opening to expose the metal component; forming a dielectric liner over a sidewall of the through-hole opening; depositing a barrier layer over the dielectric liner; depositing a metal plug over the barrier layer; depositing an etch stop layer (ESL) over the metal plug and the substrate; and planarizing the ESL until the top surfaces of the ESL and the metal plug are coplanar.

[0049] In some embodiments, the interconnect structure includes a guard ring structure, and the guide opening extends through the guard ring structure. In some embodiments, a portion of the metal plug is suspended above the guard ring structure. In some embodiments, etching the substrate, the polymer plug, and the interconnect structure includes using an isotropic etching process. In some embodiments, the isotropic etching process is a wet etching process including the use of dilute hydrofluoric acid (DHF), hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), deionized water (H2O), or a mixture thereof. In some embodiments, the isotropic etching process is a dry etching process including the use of sulfur hexafluoride (SF6) gas. In some instances, forming a dielectric liner includes using atomic layer deposition (ALD). In some embodiments, the method further includes: after forming the dielectric liner, anisotropically etching the intermediate structure to expose the metal component; and before depositing the barrier layer, depositing a self-assembled monolayer (SAM) layer above the exposed metal component. The SAM layer prevents the barrier layer from being deposited above the metal component. In some embodiments, the method further includes: after depositing the barrier layer, removing the SAM layer to expose the metal component.

[0050] Some embodiments of the present application provide a semiconductor structure, comprising: a bottom metal component; a semiconductor substrate, disposed above the bottom metal component; an interconnection structure, disposed above the semiconductor substrate; a top metal component, located above the interconnection structure; and a through-hole structure, extending from a bottom surface of the top metal component through the interconnection structure and the semiconductor substrate to contact a top surface of the bottom metal component, wherein the through-hole structure comprises a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnection structure, wherein the bottom portion and the top portion gradually taper toward the top metal component, wherein the bottom portion comprises a first taper angle, and the top portion comprises a second taper angle smaller than the first taper angle.

[0051] In some embodiments, the semiconductor structure further comprises: an etch stop layer (ESL) disposed between the semiconductor substrate and the bottom metal component, wherein the bottom surface of the bottom metal component is coplanar with the bottom surface of the etch stop layer. In some embodiments, the bottom portion of the through-hole structure is completely disposed below the interconnect structure. In some embodiments, the through-hole structure is spaced apart from the semiconductor substrate and the interconnect structure by a dielectric liner. In some embodiments, the dielectric liner comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the semiconductor structure further comprises: a barrier layer sandwiched between the through-hole structure and the dielectric liner. In some embodiments, the barrier layer comprises titanium, tantalum, tantalum nitride, or titanium nitride.

[0052] Other embodiments of the present application provide a contact structure, comprising: a dielectric layer; a top metal component disposed in the dielectric layer; an interconnect structure disposed above the dielectric layer and the top metal component, the interconnect structure comprising a guard ring structure; a substrate located above the interconnect structure; and a through-hole structure extending through the substrate and the interconnect structure to contact the top metal component, wherein the through-hole structure comprises a bottom portion surrounded by the guard ring structure and a top portion disposed above the bottom portion, wherein the top portion is suspended above the guard ring structure.

[0053] In some embodiments, the bottom portion and the top portion taper toward the top metal feature, wherein the bottom portion comprises a first taper angle and the top portion comprises a second taper angle greater than the first taper angle. In some embodiments, the contact structure further comprises: an etch stop layer (ESL) located above the substrate, wherein the top surfaces of the via structure and the etch stop layer are coplanar. In some embodiments, the contact structure further comprises: a barrier layer sandwiched between the etch stop layer and the via structure.

[0054] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: providing an intermediate structure, including: a metal component, arranged in a dielectric layer, an interconnect structure, arranged above the metal component and the dielectric layer, and a substrate, arranged above the interconnect structure; forming a guide opening through the substrate and the interconnect structure to expose the top surface of the metal component; depositing a polymer plug in the guide opening; forming a patterned hard mask above the intermediate structure and the polymer plug, the patterned hard mask including a pattern opening surrounding the polymer plug; using the patterned hard mask as an etching mask to etch the substrate, the polymer plug and the interconnect structure to form a through-hole opening to expose the metal component; forming a dielectric liner above the sidewall of the through-hole opening; depositing a barrier layer above the dielectric liner; depositing a metal plug above the barrier layer; depositing an etch stop layer (ESL) above the metal plug and the substrate; and planarizing the etch stop layer until the etch stop layer and the top surface of the metal plug are coplanar.

[0055] In some embodiments, the interconnect structure includes a guard ring structure, wherein the guide opening extends through the guard ring structure. In some embodiments, a portion of the metal plug overhangs the guard ring structure. In some embodiments, etching the substrate, the polymer plug, and the interconnect structure includes using an isotropic etching process. In some embodiments, the isotropic etching process is a wet etching process including using dilute hydrofluoric acid (DHF), hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), deionized water (H2O), or a mixture thereof. In some embodiments, the isotropic etching process is a dry etching process including using sulfur hexafluoride (SF6) gas. In some embodiments, forming the dielectric liner includes using atomic layer deposition (ALD). In some embodiments, the method further includes: after forming the dielectric liner, anisotropically etching the intermediate structure to expose the metal component; and before depositing the barrier layer, depositing a self-assembled monolayer (SAM) layer above the exposed metal component, wherein the self-assembled monolayer layer prevents the barrier layer from being deposited above the metal component. In some embodiments, the method further comprises, after depositing the barrier layer, removing the self-assembled monolayer layer to expose the metal feature.

[0056] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising: Bottom metal parts; a semiconductor substrate disposed above the bottom metal component; an interconnect structure disposed above the semiconductor substrate; a top metal component located above the interconnect structure; as well as a via structure extending from a bottom surface of the top metal feature through the interconnect structure and the semiconductor substrate to contact a top surface of the bottom metal feature, The through-hole structure includes a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnect structure. wherein the bottom portion and the top portion taper toward the top metal component, Wherein, the bottom portion includes a first taper angle, and the top portion includes a second taper angle smaller than the first taper angle.

2. The semiconductor structure according to claim 1, further comprising: an etch stop layer disposed between the semiconductor substrate and the bottom metal component, Wherein, a bottom surface of the bottom metal component is coplanar with a bottom surface of the etching stop layer.

3. The semiconductor structure according to claim 2, wherein: The bottom portion of the via structure is disposed completely below the interconnect structure.

4. The semiconductor structure according to claim 2, wherein: The via structure is spaced apart from the semiconductor substrate and the interconnect structure by a dielectric liner.

5. The semiconductor structure according to claim 4, wherein: The dielectric liner includes silicon oxide, silicon nitride, or a combination thereof.

6. The semiconductor structure according to claim 4, further comprising: A barrier layer is interposed between the via structure and the dielectric liner.

7. The semiconductor structure according to claim 6, wherein: The barrier layer includes titanium, tantalum, tantalum nitride or titanium nitride.

8. A contact structure comprising: Dielectric layer; a top metal component disposed in the dielectric layer; an interconnect structure disposed above the dielectric layer and the top metal component, the interconnect structure comprising a guard ring structure; a substrate located above the interconnect structure; as well as a via structure extending through the substrate and the interconnect structure to contact the top metal feature, The through hole structure includes a bottom portion surrounded by the guard ring structure and a top portion disposed above the bottom portion. Wherein, the top portion is suspended above the protection ring structure.

9. The contact structure according to claim 8, in, The bottom portion and the top portion taper toward the top metal component, Wherein, the bottom portion includes a first taper angle, and the top portion includes a second taper angle greater than the first taper angle.

10. A method of forming a semiconductor structure, comprising: Provides intermediate structures, including: A metal component disposed in a dielectric layer, an interconnect structure disposed over the metal feature and the dielectric layer, and a substrate disposed above the interconnect structure; forming a guide opening through the substrate and the interconnect structure to expose a top surface of the metal feature; depositing a polymer plug in the guide opening; forming a patterned hard mask over the intermediate structure and the polymer plug, the patterned hard mask comprising a pattern opening surrounding the polymer plug; etching the substrate, the polymer plug, and the interconnect structure using the patterned hard mask as an etch mask to form a via opening to expose the metal feature; forming a dielectric liner over sidewalls of the via opening; depositing a barrier layer over the dielectric liner; depositing a metal plug over the barrier layer; depositing an etch stop layer over the metal plug and the substrate; and The etch stop layer is planarized until top surfaces of the etch stop layer and the metal plug are coplanar.

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