Semiconductor structure and forming method thereof
By reducing the area of the interconnect structure in a fully depleted silicon transistor and achieving vertical electrical connection through conductive plugs, the problems of short channel effect and gate leakage are solved, and the integration and performance of the device are improved.
Patent Information
- Application Number
- CN202311331009.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-13
- Publication Date
- 2025-04-15
AI Technical Summary
The existing fully depleted silicon transistor technology has short channel effect and gate leakage problems, resulting in high power consumption and insufficient performance.
By forming a first interconnection structure on the second surface of the first substrate and forming a first device layer on the first surface surface, the area of the interconnection structure is reduced; at the same time, the first substrate and the storage wafer are electrically connected through a first conductive plug to achieve a vertical electrical connection, reducing the chip area and improving the integration degree.
It effectively reduces the area of the interconnect structure, reduces the horizontal direction area of the chip, improves the integration and performance of the device, and solves the problems of short channel effect and gate leakage.
Smart Images
Figure CN119833523A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] As advanced semiconductor manufacturing processes have been fully transformed into below 28 nanometers, traditional process devices have problems such as too small feature size, too thin gate oxide layer, easy occurrence of short channel effect and gate leakage. Modern semiconductor manufacturing processes have developed two major routes: Fin Field-Effect Transistor (FINFET) and Fully Depleted Silicon-On-Insulator (FDSOI) technology.
[0003] Compared with bulk silicon-based metal-oxide semiconductor field effect transistors or fin field effect transistors, fully depleted silicon-on-insulator transistors can save up to 35% of power consumption and improve peak performance by 50% while maintaining the same performance. They also have small drain / source parasitic capacitance, lower device delay and dynamic power consumption, and threshold voltage that does not depend on gate bias, making them more suitable for low-power applications. In addition, fully depleted silicon-on-insulator transistors have a flexible and adjustable back bias that can greatly improve chip performance.
[0004] However, there are still many problems with the current fully depleted silicon-on-insulator transistor technology. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of a fully depleted silicon-on-insulator transistor.
[0006] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a storage wafer, the storage wafer comprising a second substrate, having a third surface and a fourth surface relative to each other, and comprising a second device layer located on the third surface; providing a first substrate, comprising a first semiconductor layer, a buried oxide layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the surface of the buried oxide layer, the first substrate comprising a first surface and a second surface relative to each other, the first surface being the surface of the second semiconductor layer; forming a first device layer on the surface of the first surface; bonding the third surface to the first device layer; forming a well region in the first semiconductor layer; forming a first conductive plug penetrating the first substrate, the first device layer and the storage wafer in the first substrate, the first device layer and the storage wafer; forming a first interconnect structure on the surface of the second surface, the first interconnect structure being electrically connected to the well region.
[0007] Optionally, it also includes: providing a logic wafer, the logic wafer including: a third substrate, the third substrate including a fifth surface and a sixth surface opposite to each other; a third device layer located on the fifth surface, the third device layer having a first metal layer; bonding the storage wafer and the logic wafer to form a combined wafer.
[0008] Optionally, the method for forming the storage wafer includes: forming a second device layer on the third surface; forming a third dielectric layer on the surface of the second device layer; and forming a third interconnect structure in the third dielectric layer.
[0009] Optionally, the method for forming the logic wafer includes: forming a third device layer on the fifth surface; and forming a first metal layer in the third device layer.
[0010] Optionally, the method for bonding the logic wafer and the storage wafer includes: thinning the fourth side of the storage wafer; forming a bonding oxide layer on the surface of the third device layer of the logic wafer; and bonding the fourth side of the storage wafer and the bonding oxide layer to form a combined wafer.
[0011] Optionally, the method for thinning the storage wafer includes: thinning the second substrate from the fourth surface toward the third surface to 50 μm to 200 μm.
[0012] Optionally, the first device layer includes: a second dielectric layer, a first gate located in the second dielectric layer on the surface of the second semiconductor layer, and a second interconnect structure located in the second dielectric layer.
[0013] Optionally, the second semiconductor layer on both sides of the first gate further includes a first source and a first drain.
[0014] Optionally, after bonding the storage wafer and the logic wafer, a third conductive plug is formed in the second dielectric layer, the third conductive plug is located on the surface of one or more of the first gate, the first source and the first drain, and the third conductive plug is electrically connected to the second interconnect structure.
[0015] Optionally, before forming the well region, the method further includes: bonding the third surface to the first device layer; thinning the second surface of the first substrate; and performing ion implantation on the thinned first semiconductor layer of the first substrate to form a well region; the ion implantation parameters include: an ion implantation energy range of 1500KeV to 3000KeV; an ion implantation dose range of 2E13atoms / cm 2 ~5E15atoms / cm 2 .
[0016] Optionally, the method for thinning the first substrate includes: thinning the first substrate from the second surface toward the first surface until the distance from the second surface to the buried oxide layer is in the range of 0.5 μm to 3 μm.
[0017] Optionally, before forming the first conductive plug and after forming the well region, the method further includes: forming a first isolation structure penetrating the first substrate in the first substrate, wherein the first isolation structure is connected to the first source and the first drain.
[0018] Optionally, after forming the first isolation structure and before forming the first interconnect structure, the method further includes: forming a second conductive plug penetrating the first substrate and the first device layer.
[0019] Optionally, after forming the first conductive plug and before forming the first interconnect structure, the method further includes: forming a first dielectric layer on the second surface; and forming the first interconnect structure in the first dielectric layer.
[0020] Optionally, the method further includes: forming an external connection layer on the surface of the first dielectric layer, wherein the external connection layer is electrically connected to the first interconnection structure.
[0021] Optionally, the first conductive plug is electrically connected to the first metal layer and the first interconnect structure; and the second conductive plug is electrically connected to the first interconnect structure.
[0022] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a first substrate, including a first semiconductor layer, a buried oxide layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the surface of the buried oxide layer, the first substrate including a first surface and a second surface relative to each other, the first surface being the surface of the second semiconductor layer; a well region located in the first semiconductor layer; a first device layer located on the surface of the first surface; a first interconnect structure located on the surface of the second surface, the first interconnect structure being electrically connected to the well region; a storage wafer bonded to the first device layer, the storage wafer including a second substrate, having a third surface and a fourth surface relative to each other, including a second device layer located on the third surface, the third surface being bonded to the first device layer; a first conductive plug located in the first substrate, the first device layer and the storage wafer, the first conductive plug being electrically connected to the first conductive plug.
[0023] Optionally, it further includes: a second conductive plug penetrating the first substrate and the first device layer, the second conductive plug being electrically connected to the first interconnect structure.
[0024] Optionally, it further includes: a first dielectric layer located on the second surface, the first interconnection structure located in the first dielectric layer; and an external connection layer located on the surface of the first dielectric layer, the external connection layer being electrically connected to the first interconnection structure.
[0025] Optionally, the first device layer includes: a second dielectric layer, a first gate located in the second dielectric layer on the surface of the second semiconductor layer, and a second interconnect structure located in the second dielectric layer, wherein the second interconnect structure is electrically connected to the second conductive plug.
[0026] Optionally, the second semiconductor layer on both sides of the first gate further includes a first source and a first drain.
[0027] Optionally, the method further includes: a third conductive plug located on a surface of one or more of the first gate, the first source and the first drain, wherein the third conductive plug is electrically connected to the second interconnect structure.
[0028] Optionally, the storage wafer further includes: a third dielectric layer located on the surface of the second device layer, the third dielectric layer having a third interconnect structure therein, the third dielectric layer being bonded to the first device layer, and the third interconnect structure being electrically connected to the second interconnect structure.
[0029] Optionally, it also includes: a logic wafer bonded to the storage wafer, the logic wafer including: a third substrate, the third substrate including a fifth surface and a sixth surface relative to each other; a third device layer located on the fifth surface, the third device layer having a first metal layer, and the third device layer bonded to the fourth surface.
[0030] Optionally, the first conductive plug is also electrically connected to the first metal layer.
[0031] Optionally, it also includes: a first isolation structure penetrating the first substrate, the first isolation structure being connected to the first source and the first drain.
[0032] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0033] In the semiconductor structure of the technical solution of the present invention, on the one hand, the first device layer and the first interconnection structure are distributed on two opposite sides of the first substrate, the first device layer is located on the surface of the buried oxide layer, and the first interconnection structure is located on the surface of the well region, thereby reducing the area occupied by the first interconnection structure in a direction parallel to the surface of the first substrate; on the other hand, the first substrate and the storage wafer are electrically connected through the first conductive plug, so that the wafers are electrically connected in the vertical direction, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device.
[0034] In the method for forming a semiconductor structure of the technical solution of the present invention, on the one hand, a first interconnection structure is formed on the surface of the second surface of the first substrate, and a first device layer is formed on the surface of the first surface of the first substrate, the first device layer and the first interconnection structure are distributed on two opposite sides of the first substrate, the first device layer is located on the surface of the buried oxide layer, and the first interconnection structure is located on the surface of the well region, thereby reducing the area occupied by the first interconnection structure in a direction parallel to the surface of the first substrate; on the other hand, the first substrate and the storage wafer are electrically connected through the first conductive plug, so that the wafers are electrically connected in the vertical direction, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figures 1 to 12 It is a cross-sectional schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] As described in the background art, the existing fully depleted silicon-on-insulator transistor technology still has many problems.
[0037] In an embodiment of a fully depleted silicon-on-insulator, a back bias control terminal is led out from the wafer and is in the same plane as the gate, source, and drain, thereby increasing the area of the chip in the horizontal direction.
[0038] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same. On the one hand, a first interconnection structure is formed on the surface of the second surface of the first substrate, and a first device layer is formed on the surface of the first surface of the first substrate, the first device layer and the first interconnection structure are distributed on two opposite sides of the first substrate, the first device layer is located on the surface of the buried oxide layer, and the first interconnection structure is located on the surface of the well region, thereby reducing the area occupied by the first interconnection structure in a direction parallel to the surface of the first substrate; on the other hand, the first substrate and the storage wafer are electrically connected through the first conductive plug, so that the wafers are electrically connected in the vertical direction, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device.
[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0040] Figures 1 to 12 It is a cross-sectional schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.
[0041] Please refer to Figure 1, providing a storage wafer 104, the storage wafer 104 includes: a second substrate 100, having a third surface and a fourth surface opposite to each other; and a second device layer 101 located on the third surface.
[0042] The material of the second substrate 100 includes: silicon, silicon germanium, and silicon carbide.
[0043] The second substrate 100 has a second source (not shown) and a second drain (not shown).
[0044] The second device layer 101 includes: a second gate (not shown). The second substrate 100 on both sides of the second gate has a second source and a second drain.
[0045] The storage wafer 104 further includes: a third dielectric layer 102 formed on the surface of the second device layer 101 ; and a third interconnect structure 103 formed in the third dielectric layer 102 .
[0046] The material of the third dielectric layer 102 includes silicon oxide.
[0047] The material of the third interconnect structure 103 includes copper.
[0048] The third interconnect structure 103 is electrically connected to a second interconnect structure 118 formed subsequently.
[0049] The third interconnect structure 103 is electrically connected to the subsequently formed second interconnect structure 118, so that the subsequently formed first device layer 115 is electrically connected to the storage wafer 104 in the vertical direction, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device.
[0050] The method for forming the storage wafer 104 includes: forming a second device layer 101 on the third surface; forming a third dielectric layer 102 on the surface of the second device layer 101 ; and forming a third interconnect structure 103 in the third dielectric layer 102 .
[0051] The memory wafer 104 is subsequently bonded to the logic wafer 105 along the vertical direction, which reduces the area of the chip in the horizontal direction and improves the integration of the device.
[0052] Please refer to Figure 2 , providing a logic wafer 105, the logic wafer 105 includes: a third substrate 106, the third substrate 106 includes a fifth surface and a sixth surface opposite to each other; a third device layer 107 located on the fifth surface, the third device layer 107 has a first metal layer 108 therein.
[0053] The method for forming the logic wafer 105 includes: forming a third device layer 107 on the fifth surface; and forming a first metal layer 108 in the third device layer 107 .
[0054] The material of the third substrate 106 includes: silicon, silicon germanium, and silicon carbide.
[0055] The third substrate 106 has a third source (not shown) and a third drain (not shown).
[0056] The third device layer 107 includes: a third gate (not shown). A third source and a third drain are provided in the third substrate 106 on both sides of the third gate.
[0057] The material of the first metal layer 108 includes copper.
[0058] The logic wafer 105 is subsequently bonded to the storage wafer 104 along the vertical direction, which reduces the area of the chip in the horizontal direction and improves the integration of the device.
[0059] The first metal layer 108 is electrically connected to the first conductive plug 122 formed subsequently. The first device layer 115 formed subsequently is electrically connected to the storage wafer 104 and the logic wafer 105 in the vertical direction through the first conductive plug 122, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device.
[0060] The memory wafer 104 and the logic wafer 105 are bonded together to form a combined wafer 109. Figures 3 to 5 .
[0061] Please refer to Figure 3 , thinning the fourth surface of the storage wafer 104.
[0062] Specifically, in this embodiment, the method for thinning the memory wafer 104 includes: thinning the second substrate 100 from the fourth surface toward the third surface to 50 μm to 200 μm.
[0063] The thinning process is used to improve the heat dissipation performance of the wafer and reduce the power consumption of the wafer.
[0064] Please refer to Figure 4 , a bonding oxide layer 110 is formed on the surface of the third device layer 107 of the logic wafer 105 .
[0065] The bonding oxide layer 110 is formed by a chemical vapor deposition method.
[0066] The thickness range of the bonding oxide layer 110 is:
[0067] The material of the bonding oxide layer 110 includes silicon oxide.
[0068] The bonding oxide layer 110 is used to adjust the bonding force.
[0069] The bonding oxide layer 110 is used for subsequent bonding connection between the logic wafer 105 and the memory wafer 104 .
[0070] Please refer to Figure 5 , bonding the fourth surface of the storage wafer 104 to the bonding oxide layer 110 to form a combined wafer 109 .
[0071] The bonding parameters include: bonding time: 5s to 20s; bonding force 1000mN to 3000mN.
[0072] The logic wafer 105 and the storage wafer 104 are bonded and connected in the vertical direction, which reduces the area of the chip in the horizontal direction and improves the integration of the device.
[0073] Please refer to Figure 6 , providing a first substrate 111, including a first semiconductor layer 112, a buried oxide layer 113 located on the surface of the first semiconductor layer 112, and a second semiconductor layer 114 located on the surface of the buried oxide layer 113, the first substrate 111 includes a first surface and a second surface opposite to each other, the first surface is the surface of the second semiconductor layer 114.
[0074] The first semiconductor layer 112 provides a structural basis for the subsequent formation of a well region 120 .
[0075] The thickness range of the buried oxide layer 113 is:
[0076] The material of the buried oxide layer 113 includes silicon oxide.
[0077] The formation process of the buried oxide layer 113 includes: chemical vapor deposition.
[0078] The buried oxide layer 113 is located on the entire surface of the first semiconductor layer 112, so that the device layer 115 subsequently formed on the first surface has the same height at all locations along a direction parallel to the first surface, thereby avoiding a large height difference between different circuit modules.
[0079] The second semiconductor layer 114 includes a first source electrode (not shown) and a first drain electrode (not shown).
[0080] Please refer to Figure 7 , forming a first device layer 115 on the surface of the first surface.
[0081] Specifically, in this embodiment, the first device layer 115 includes: a second dielectric layer 116 , a first gate 117 located in the second dielectric layer 116 on the surface of the second semiconductor layer 114 , and a second interconnect structure 118 located in the second dielectric layer 116 .
[0082] The material of the second dielectric layer 116 includes silicon oxide.
[0083] Specifically, in this embodiment, the second semiconductor layer 114 on both sides of the first gate 117 further includes a first source (not shown) and a first drain (not shown).
[0084] The material of the second interconnect structure 118 includes copper.
[0085] The second interconnect structure 118 is also electrically connected to the third interconnect structure 103 after the third surface of the storage wafer 104 is subsequently bonded to the first device layer 115 .
[0086] The first device layer 115 is subsequently bonded to the third surface of the storage wafer 104 in the vertical direction, which reduces the area of the chip in the horizontal direction and improves the integration of the device. The first device layer 115 and the first interconnection structure 125 formed subsequently are distributed on two opposite sides of the first substrate 111, the first device layer 115 is located on the surface of the buried oxide layer 113, and the first interconnection structure 125 is located on the surface of the well region 120 formed subsequently, which reduces the area occupied by the first interconnection structure 125 formed subsequently in the direction parallel to the surface of the first substrate 111.
[0087] Specifically, in this embodiment, before forming the second interconnect structure 118 and after forming the second dielectric layer 116, it also includes: forming a third conductive plug 119 in the second dielectric layer 116, the third conductive plug 119 is located on the surface of one or more of the first gate 117, the first source and the first drain, and the third conductive plug 119 is electrically connected to the second interconnect structure 118.
[0088] Specifically, in this embodiment, the third conductive plug 119 electrically connects the second interconnect structure 118 with the first gate 117 , the first source and the first drain in a vertical direction, thereby improving the integration of the device.
[0089] The material of the third conductive plug 119 includes tungsten.
[0090] Please refer to Figure 8After forming the first device layer 115 , the third surface is bonded to the first device layer 115 ; the second surface of the first substrate 111 is thinned; and ion implantation is performed on the thinned first semiconductor layer 112 of the first substrate 111 to form a well region 120 .
[0091] Specifically, in this embodiment, the ion implantation parameters of the well region 120 include: ion implantation energy range: 1500KeV to 3000KeV; ion implantation dose range: 2E13atoms / cm 2 ~5E15atoms / cm 2 .
[0092] The well region 120 is electrically connected to a first interconnect structure 125 formed subsequently. The first device layer 115 is located on the surface of the buried oxide layer 113, and the first interconnect structure 125 formed subsequently is located on the surface of the well region 120, which reduces the area occupied by the first interconnect structure 125 formed subsequently in a direction parallel to the surface of the first substrate 111.
[0093] The thinning method of the first substrate 111 includes: thinning the first substrate from the second surface toward the first surface until the distance from the second surface to the buried oxide layer is in the range of 0.5 μm to 3 μm.
[0094] The thinning process is used to improve the heat dissipation performance of the wafer and reduce the power consumption of the wafer.
[0095] The first device layer 115 is bonded to the third surface of the storage wafer 104 in the vertical direction, which reduces the area of the chip in the horizontal direction and improves the integration of the device.
[0096] Please refer to Fig. 9 After the well region 120 is formed, a first isolation structure 121 penetrating the first substrate 111 is formed in the first substrate 111 , and the first isolation structure 121 is connected to the first source and the first drain.
[0097] Specifically, in this embodiment, the depth of the first isolation structure 121 ranges from 0.5 μm to 3 μm.
[0098] The function of the first isolation structure 121 is to separate the well regions corresponding to the first gates 117 to avoid electrical crosstalk between adjacent first gates 117 and between the first gates 117 and other devices in the device layer 115 .
[0099] Please refer to Fig.10 After forming the first isolation structure 121 , a first conductive plug 122 is formed that penetrates the first substrate 111 , the first device layer 115 , and the storage wafer 104 .
[0100] The method for forming the first conductive plug 122 includes: forming a first mask layer (not shown) on the surface of the well region 120, wherein the first mask layer exposes a portion of the surface of the well region 120; using the first mask layer as a mask, etching the first substrate 111, the first device layer 115, the third dielectric layer 102, the second device layer 101 and the second substrate 100 until a portion of the surface of the third device layer 107 is exposed to form a first opening (not shown); and forming the first conductive plug 122 in the first opening.
[0101] The material of the first conductive plug 122 includes copper.
[0102] The size of the first opening along a direction parallel to the surface of the second substrate 100 ranges from 2 μm to 8 μm.
[0103] The first conductive plug 122 is electrically connected to the first metal layer 108 and the subsequently formed first interconnect structure 125. The first substrate 111 is electrically connected to the storage wafer 104 through the first conductive plug 122, so that each wafer is electrically connected in the vertical direction, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device.
[0104] Specifically, in this embodiment, the method further includes: forming a second conductive plug 123 penetrating the first substrate 111 and the first device layer 115 .
[0105] The method for forming the second conductive plug 123 includes: forming a second mask layer (not shown) on the surface of the well region 120, the second mask layer exposing a portion of the surface of the well region 120; using the second mask layer as a mask, etching the first substrate 111 and the first device layer 115 until a portion of the surface of the third interconnect structure 103 is exposed to form a second opening (not shown); and forming the second conductive plug 123 in the second opening.
[0106] The material of the second conductive plug 123 includes copper.
[0107] The size of the second opening along a direction parallel to the surface of the first substrate 111 ranges from 2 μm to 8 μm.
[0108] The second conductive plug 123 is electrically connected to the first interconnect structure 125 formed subsequently, which reduces the area of the chip in the horizontal direction and improves the integration of the device.
[0109] Please refer to Fig.11After forming the first conductive plug 122 , a first dielectric layer 124 is formed on the second surface; and the first interconnect structure 125 is formed in the first dielectric layer 124 .
[0110] The material of the first dielectric layer 124 includes silicon oxide.
[0111] The material of the first interconnect structure 125 includes copper.
[0112] The first device layer 115 and the first interconnect structure 125 are distributed on two opposite sides of the first substrate 111. The first device layer 115 is located on the surface of the buried oxide layer 113, and the first interconnect structure 125 is located on the surface of the well region 120, thereby reducing the area occupied by the first interconnect structure 125 along the direction parallel to the surface of the first substrate 111.
[0113] The first interconnect structure 125 is electrically connected to the first conductive plug 122 and the second conductive plug 123, so that the first device layer 115 is electrically connected to the storage wafer 104 and the logic wafer 105 in the vertical direction, so that there is no height difference on the wafer surface of the same circuit module, while reducing the area of the chip in the horizontal direction, thereby improving the integration of the device.
[0114] The first interconnect structure 125 is electrically connected to the subsequently formed external connection layer 126 , and the subsequently formed external connection layer 126 is connected to the first interconnect structure 125 from the second surface without passing through the buried oxide layer 113 , thereby simplifying the process.
[0115] Please refer to Fig.12 After forming the first interconnect structure 125 , an external connection layer 126 is formed on the surface of the first dielectric layer 124 , and the external connection layer 126 is electrically connected to the first interconnect structure 125 .
[0116] The material of the external connection layer 126 includes aluminum.
[0117] The external connection layer 126 is electrically connected to the first interconnect structure 125 . The external connection layer 126 is connected from the second surface without passing through the buried oxide layer 113 , thereby simplifying the process.
[0118] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, comprising: a first substrate 111, comprising a first semiconductor layer 112, a buried oxide layer 113 located on the surface of the first semiconductor layer 112, and a second semiconductor layer 114 located on the surface of the buried oxide layer 113, the first substrate 111 comprising a first surface and a second surface relative to each other, the first surface being the surface of the second semiconductor layer 114; a well region 120 located in the first semiconductor layer 112; a first device layer 115 located on the surface of the first surface; a first interconnect structure 125 located on the surface of the second surface, the first interconnect structure 125 being electrically connected to the well region 120; a storage wafer 104 bonded to the first device layer 115, the storage wafer 104 comprising a second substrate 100, having a third surface and a fourth surface relative to each other, comprising a second device layer 101 located on the third surface, the third surface being bonded to the first device layer 115; a first conductive plug 122 located in the first substrate 111, the first device layer 115 and the storage wafer 104, the first conductive plug 122 being electrically connected to the first conductive plug 122.
[0119] The semiconductor structure includes: a first substrate 111, including a first semiconductor layer 112, a buried oxide layer 113 located on the surface of the first semiconductor layer 112, and a second semiconductor layer 114 located on the surface of the buried oxide layer 113, the first substrate 111 includes a first surface and a second surface opposite to each other, the first surface is the surface of the second semiconductor layer 114.
[0120] The thickness range of the buried oxide layer 113 is:
[0121] The material of the buried oxide layer 113 includes silicon oxide.
[0122] The second semiconductor layer 114 includes a first source electrode (not shown) and a first drain electrode (not shown).
[0123] The semiconductor structure includes a well region 120 located in the first semiconductor layer 112 .
[0124] The ion implantation parameters of the well region 120 include: ion implantation energy range: 1500KeV~3000KeV; ion implantation dose range: 2E13atoms / cm 2 ~5E15atoms / cm 2 .
[0125] The semiconductor structure includes: a first device layer 115 located on the surface of the first surface.
[0126] The first device layer 115 includes a second dielectric layer 116 , a first gate 117 located in the second dielectric layer 116 on the surface of the second semiconductor layer 114 , and a second interconnect structure 118 located in the second dielectric layer 116 . The second interconnect structure 118 is electrically connected to the second conductive plug 123 .
[0127] The material of the second dielectric layer 116 includes silicon oxide.
[0128] The material of the second interconnect structure 118 includes copper.
[0129] The second interconnect structure 118 is electrically connected to the third interconnect structure 103. The second semiconductor layer 114 on both sides of the first gate 117 further includes a first source (not shown) and a first drain (not shown).
[0130] The semiconductor structure includes a third conductive plug 119 located on the surface of one or more of the first gate 117 , the first source (not shown) and the first drain (not shown), and the third conductive plug 119 is electrically connected to the second interconnect structure 118 .
[0131] The material of the third conductive plug 119 includes tungsten.
[0132] The semiconductor structure includes: a first isolation structure 121 penetrating the first substrate 111, the first isolation structure 121 being connected to the first source and the first drain. Specifically, in this embodiment, the depth of the first isolation structure 121 ranges from 0.5 μm to 3 μm.
[0133] The semiconductor structure includes a memory wafer 104 bonded to a first device layer 115. The memory wafer 104 includes a second substrate 100 having a third surface and a fourth surface opposite to each other, including a second device layer 101 on the third surface, and the third surface is bonded to the first device layer 115.
[0134] The material of the second substrate 100 includes: silicon, silicon germanium, and silicon carbide.
[0135] The second substrate 100 has a second source (not shown) and a second drain (not shown).
[0136] The second device layer 101 includes: a second gate (not shown). The second substrate 100 on both sides of the second gate has a second source and a second drain.
[0137] The storage wafer 104 further includes: a third dielectric layer 102 located on the surface of the second device layer 101 ; and a third interconnect structure 103 located in the third dielectric layer 102 .
[0138] The material of the third dielectric layer 102 includes silicon oxide.
[0139] The material of the third interconnect structure 103 includes copper.
[0140] The semiconductor structure includes: a logic wafer 105 bonded to the memory wafer 104. The logic wafer 105 includes: a third substrate 106, the third substrate 106 includes a fifth surface and a sixth surface opposite to each other; a third device layer 107 located on the fifth surface, the third device layer 107 having a first metal layer 108 therein.
[0141] The material of the third substrate 106 includes: silicon, silicon germanium, and silicon carbide.
[0142] The third substrate 106 has a third source (not shown) and a third drain (not shown).
[0143] The third device layer 107 includes: a third gate (not shown). A third source and a third drain are provided in the third substrate 106 on both sides of the third gate.
[0144] The material of the first metal layer 108 includes copper.
[0145] The semiconductor structure includes: a bonding oxide layer 110 located on the surface of the third device layer 107 .
[0146] The thickness range of the bonding oxide layer 110 is:
[0147] The material of the bonding oxide layer 110 includes silicon oxide.
[0148] The semiconductor structure includes: a first conductive plug 122 located in the first substrate 111 , the first device layer 115 , and the storage wafer 104 , and the first conductive plug 122 is electrically connected to the first interconnect structure 125 .
[0149] The size of the first conductive plug 122 along a direction parallel to the surface of the second substrate 100 ranges from 2 μm to 8 μm.
[0150] The semiconductor structure includes a second conductive plug 123 penetrating the first substrate 111 and the first device layer 115 .
[0151] The material of the second conductive plug 123 includes copper.
[0152] The size of the second conductive plug 123 along a direction parallel to the surface of the first substrate 111 ranges from 2 μm to 8 μm.
[0153] The semiconductor structure includes: a first interconnect structure 125 located on the surface of the second surface, and the first interconnect structure 125 is electrically connected to the well region 120 .
[0154] The semiconductor structure includes a first dielectric layer 124 located on the second surface.
[0155] The material of the first dielectric layer 124 includes silicon oxide.
[0156] The material of the first interconnect structure 125 includes copper.
[0157] The semiconductor structure includes an external connection layer 126 located on the surface of the first dielectric layer 124 , and the external connection layer 126 is electrically connected to the first interconnection structure 125 .
[0158] The material of the external connection layer 126 includes aluminum.
[0159] The semiconductor structure includes: a combined wafer 109 , which is a bonding structure of a memory wafer 104 and a logic wafer 105 .
[0160] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A first substrate comprises a first semiconductor layer, a buried oxide layer located on a surface of the first semiconductor layer, and a second semiconductor layer located on a surface of the buried oxide layer, wherein the first substrate comprises a first surface and a second surface opposite to each other, and the first surface is a surface of the second semiconductor layer; a well region located in the first semiconductor layer; a first device layer located on a surface of the first surface; a first interconnect structure located on a surface of the second surface, the first interconnect structure being electrically connected to the well region; A storage wafer bonded to the first device layer, the storage wafer comprising a second substrate having a third surface and a fourth surface opposite to each other, comprising a second device layer located on the third surface, the third surface being bonded to the first device layer; A first conductive plug is located in the first substrate, the first device layer and the storage wafer, and the first conductive plug is electrically connected to the first interconnect structure.
2. The semiconductor structure according to claim 1, wherein: Also includes: A second conductive plug penetrates the first substrate and the first device layer, and the second conductive plug is electrically connected to the first interconnect structure.
3. The semiconductor structure according to claim 1, wherein: Also includes: a first dielectric layer located on the second surface, wherein the first interconnect structure is located in the first dielectric layer; An external connection layer is located on the surface of the first dielectric layer, and the external connection layer is electrically connected to the first interconnection structure.
4. The semiconductor structure according to claim 2, wherein: The first device layer includes: a second dielectric layer, a first gate located in the second dielectric layer on the surface of the second semiconductor layer, and a second interconnection structure located in the second dielectric layer, wherein the second interconnection structure is electrically connected to the second conductive plug.
5. The semiconductor structure according to claim 4, characterized in that: The second semiconductor layer at both sides of the first gate also has a first source and a first drain.
6. The semiconductor structure according to claim 5, characterized in that: Also includes: A third conductive plug is located on a surface of one or more of the first gate, the first source, and the first drain, and the third conductive plug is electrically connected to the second interconnect structure.
7. The semiconductor structure according to claim 4, characterized in that: The storage wafer further includes: a third dielectric layer located on the surface of the second device layer, the third dielectric layer having a third interconnect structure therein, the third dielectric layer being bonded to the first device layer, and the third interconnect structure being electrically connected to the second interconnect structure.
8. The semiconductor structure according to claim 7, characterized in that: Also includes: A logic wafer bonded to the memory wafer, the logic wafer comprising: a third substrate, the third substrate comprising a fifth surface and a sixth surface opposite to each other; A third device layer is located on the fifth surface, wherein the third device layer has a first metal layer, and the third device layer is bonded to the fourth surface.
9. The semiconductor structure according to claim 8, characterized in that: The first conductive plug is also electrically connected to the first metal layer.
10. The semiconductor structure according to claim 5, characterized in that: Also includes: A first isolation structure penetrates the first substrate, and the first isolation structure is connected to the first source and the first drain.
11. A method for forming a semiconductor structure, characterized in that: include: Providing a memory wafer, the memory wafer comprising a second substrate having a third surface and a fourth surface opposite to each other, and comprising a second device layer located on the third surface; Providing a first substrate, comprising a first semiconductor layer, a buried oxide layer located on a surface of the first semiconductor layer, and a second semiconductor layer located on a surface of the buried oxide layer, wherein the first substrate comprises a first surface and a second surface opposite to each other, and the first surface is a surface of the second semiconductor layer; forming a first device layer on the surface of the first surface; bonding the third surface to the first device layer; forming a well region in the first semiconductor layer; forming a first conductive plug penetrating the first substrate, the first device layer and the storage wafer in the first substrate, the first device layer and the storage wafer; A first interconnect structure is formed on the surface of the second surface, wherein the first interconnect structure is electrically connected to the well region.
12. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: Providing a logic wafer, the logic wafer comprising: a third substrate, the third substrate comprising a fifth surface and a sixth surface opposite to each other; A third device layer is located on the fifth surface, wherein the third device layer has a first metal layer; the memory wafer and the logic wafer are bonded together to form a combined wafer.
13. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the storage wafer comprises: forming a second device layer on the third surface; forming a third dielectric layer on the surface of the second device layer; and forming a third interconnection structure in the third dielectric layer.
14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming a logic wafer includes: forming a third device layer on the fifth surface; and forming a first metal layer in the third device layer.
15. The method for forming a semiconductor structure according to claim 12, wherein: The method for bonding the logic wafer and the storage wafer includes: thinning the fourth surface of the storage wafer; forming a bonding oxide layer on the surface of the third device layer of the logic wafer; and bonding the fourth surface of the storage wafer and the bonding oxide layer to form a combined wafer.
16. The method for forming a semiconductor structure according to claim 15, wherein: The method for thinning the memory wafer comprises: thinning the second substrate from the fourth surface toward the third surface to 50 μm to 200 μm.
17. The method for forming a semiconductor structure according to claim 12, wherein: The first device layer includes: a second dielectric layer, a first gate located in the second dielectric layer on the surface of the second semiconductor layer, and a second interconnection structure located in the second dielectric layer.
18. The method for forming a semiconductor structure according to claim 17, wherein: The second semiconductor layer at both sides of the first gate also has a first source and a first drain.
19. The method for forming a semiconductor structure according to claim 18, wherein: After bonding the storage wafer and the logic wafer, a third conductive plug is formed in the second dielectric layer, the third conductive plug is located on the surface of one or more of the first gate, the first source and the first drain, and the third conductive plug is electrically connected to the second interconnect structure.
20. The method for forming a semiconductor structure according to claim 19, wherein: Before forming the well region, the method further includes: bonding the third surface to the first device layer; thinning the second surface of the first substrate; and performing ion implantation on the first semiconductor layer of the thinned first substrate to form a well region. The ion implantation parameters include: an ion implantation energy range of 1500KeV to 3000KeV; an ion implantation dose range of 2E13atoms / cm 2 ~5E15atoms / cm 2 .
21. The method for forming a semiconductor structure according to claim 20, wherein: The thinning method of the first substrate comprises: thinning the first substrate from the second surface toward the first surface until the distance from the second surface surface to the buried oxide layer is in the range of 0.5 μm to 3 μm.
22. The method for forming a semiconductor structure according to claim 20, wherein: Before forming the first conductive plug and after forming the well region, the method further includes: forming a first isolation structure penetrating the first substrate in the first substrate, wherein the first isolation structure is connected to the first source and the first drain.
23. The method for forming a semiconductor structure according to claim 22, wherein: After forming the first isolation structure and before forming the first interconnect structure, the method further includes: forming a second conductive plug penetrating the first substrate and the first device layer.
24. The method for forming a semiconductor structure according to claim 23, wherein: After forming the first conductive plug and before forming the first interconnect structure, the method further includes: forming a first dielectric layer on the second surface; and forming the first interconnect structure in the first dielectric layer.
25. The method for forming a semiconductor structure according to claim 24, wherein: Also includes: An external connection layer is formed on the surface of the first dielectric layer, and the external connection layer is electrically connected to the first interconnection structure.
26. The method for forming a semiconductor structure according to claim 25, wherein: The first conductive plug is electrically connected to the first metal layer and the first interconnect structure; and the second conductive plug is electrically connected to the first interconnect structure.