Vertical cavity surface emitting laser and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a vertical cavity surface emitting laser and a preparation method thereof.The laser comprises an n-face electrode layer, a substrate layer, a buffer layer and an n-DBR layer which are sequentially arranged from bottom to top, and a SiO2 insulating layer located on the periphery is arranged above the n-DBR layer; an n-lower oxidation limiting structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation limiting structure layer, a p-DBR layer, a contact layer and a p-surface electrode layer which form a cylindrical table are sequentially arranged at the center of the SiO2 insulating layer from bottom to top. According to the invention, by adopting a symmetrical oxidation limiting structure, more current carriers are limited in oxidation holes, the output power and the electro-optical conversion efficiency can be improved, and the number and distribution of transverse modes can be regulated and controlled.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical cavity surface emitting laser and a preparation method thereof, which improves the photoelectric performance of the vertical cavity surface emitting laser through a symmetrical oxidation confinement structure. Background Art

[0002] Vertical Cavity Surface Emitting Laser (VCSEL) is a semiconductor laser that emits laser light perpendicular to the device surface. Due to its special chip structure, VCSEL has the advantages of low threshold, low power consumption, single longitudinal mode, circular spot, easy coupling with optical fiber, on-wafer testability, easy arraying, and low manufacturing cost. It has been widely used in the fields of intelligent sensing, optical interconnection, optical communication, optical storage, quantum precision measurement, etc.

[0003] VCSEL was first proposed by Japanese scientist Iga in 1977. After more than 30 years of development, VCSEL has been commercialized on a large scale and has formed device types such as GaAs-based VCSEL, InP-based VCSEL, antimonide VCSEL, and GaN-based VCSEL. Among them, GaAs-based VCSEL is the most mature and widely used VCSEL product. There are two main reasons for this: (1) AlGaAs material has a natural lattice match with GaAs substrate, and the refractive index difference is large, so it is easy to grow a distributed Bragg reflector (DBR) structure with high reflectivity and low defect density; (2) AlGaAs material with a high Al content can form an oxidation-limited structure through a wet oxidation process, which has a significant effect on reducing the loss of VCSEL devices and is a key technology to promote the industrialization of GaAs-based VCSEL.

[0004] Thanks to the in-depth and systematic research on AlGaAs materials, the wet oxidation process of GaAs-based VCSELs is now very mature, so the oxidation confinement structure has become the most widely used current limitation and light field limitation method. The oxidation confinement layer of GaAs-based VCSELs is generally placed between the first pair of P-DBRs close to the active area. This structure can limit the diffusion of carriers and light fields, and confine most carriers and photons within the oxidation holes, but a large number of carriers and photons still diffuse outside the oxidation holes and cannot form effective stimulated radiation. Some researchers have also set up double oxidation confinement layers in P-DBRs to reduce the parasitic capacitance of VCSELs and increase the modulation bandwidth, but this structure lacks current limitation on the N side, and the output power and electro-optical conversion efficiency are low. Summary of the invention

[0005] The technical problems to be solved by the present invention are: (1) GaAs-based VCSELs with a p-type single oxide confinement layer structure have no current confinement on the n-side, and electron diffusion is relatively serious; (2) The carrier confinement capability is relatively weak, which is not conducive to improving the carrier injection efficiency; (3) The light field confinement effect is relatively poor, especially the high-order transverse modes are often outside the oxide hole, unable to form effective mode gain, thereby reducing the output power.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a vertical cavity surface emitting laser, comprising an n-surface electrode layer, a substrate layer, a buffer layer, and an n-DBR layer arranged in sequence from bottom to top, a SiO2 insulating layer located on the periphery is arranged above the n-DBR layer, and an n-lower oxidation confinement structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation confinement structure layer, a p-DBR layer, a contact layer, and a p-surface electrode layer are arranged in sequence from bottom to top in the center of the SiO2 insulating layer to form a cylindrical platform;

[0007] The n-underoxidation restriction structure layer includes at least one periodic n-underoxidation restriction structure, wherein the n-underoxidation restriction structure is sequentially arranged from bottom to top. z1 GaAs high refractive index layer, n-Al 0.98 GaAs oxide confinement layer and n-Al 0.9 GaAs low refractive index layer, the n-Al 0.98 A first aluminum oxide layer is formed on the periphery of the GaAs oxide confinement layer by a wet oxidation process;

[0008] The p-upper oxidation restriction structure layer includes at least one period of p-upper oxidation restriction structure, and the p-upper oxidation restriction structure includes p-Al 0.9 GaAs low refractive index layer, p-Al 0.98 GaAs oxide confinement layer and p-Al z2 GaAs high refractive index layer, the p-Al 0.98 A second aluminum oxide layer is formed on the periphery of the GaAs oxide restriction layer by a wet oxidation process, and z1 and z2 represent the Al components in the corresponding materials, respectively.

[0009] The n-Al 0.98 The thickness of the GaAs oxide restriction layer is 30 nm. 0.98 The thickness of the GaAs oxide confinement layer is 30 nm.

[0010] The n-Al 0.98 The doping concentration of the GaAs oxide confinement layer is 1×10 18 cm -3 , doped with Si; the p-Al 0.98The doping concentration of the GaAs oxide confinement layer is 1×10 18 cm -3 , doped with C.

[0011] The n-Al z1 GaAs high refractive index layer and n-Al 0.98 An n-AlGaAs transition layer is also provided between the GaAs oxidation restriction layers, and its Al composition changes linearly from z1 to 0.9;

[0012] The p-Al 0.98 GaAs oxide confinement layer and p-Al z A p-AlGaAs transition layer is also arranged between the GaAs high refractive index layers, and its Al composition changes linearly from 0.9 to z2.

[0013] The n-side electrode layer includes gold and nickel layers arranged in sequence from bottom to top;

[0014] The substrate layer is an n-GaAs substrate with a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si;

[0015] The buffer layer is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si;

[0016] The lower space layer is an AlGaAs lower space layer with a thickness of 114.1 nm and no doping;

[0017] The upper space layer is an AlGaAs upper space layer 09, with a thickness of 114.1 nm;

[0018] The contact layer is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C;

[0019] The p-side electrode layer includes titanium, platinum and gold layers arranged in sequence from bottom to top.

[0020] The z1=z2.

[0021] The p-side electrode layer is annular, its center coincides with the center of the n-lower oxidation restriction structure layer, and its inner diameter is larger than that of the n-Al 0.98 GaAs oxide confinement layer and p-Al 0.98 Radius of the GaAs oxide confinement layer.

[0022] The n-DBR layer consists of 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al0.9 GaAs low refractive index layers are periodically overlapped; among them, n-Al z3 The thickness of the GaAs high refractive index layer is λ / 4n H1 –20nm, z3 satisfies: 1.424+1.247z3>1240 / (λ-50); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n L1 –20nm; λ is the emission wavelength of VCSEL, n H1 n-Al z3 The refractive index of the GaAs high refractive index layer, n L1 n-Al 0.9 The refractive index of the GaAs low refractive index layer;

[0023] Each layer of n-Al z3 On top of the GaAs high refractive index layer, a 20nm n-AlGaAs transition layer is set, and the Al composition in the transition layer changes linearly from z3 to 0.9; similarly, each layer of n-Al 0.9 On top of the GaAs low refractive index layer, a 20nm n-AlGaAs transition layer is set, and the Al composition changes linearly from 0.9 to z3;

[0024] The p-DBR layer consists of 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z4 GaAs high refractive index layers are periodically overlapped; among them, p-Al z4 The thickness of the GaAs high refractive index layer is λ / 4n H2 –20nm, z4 satisfies: 1.424+1.247z4>1240 / (λ-50); p-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n L2 –20nm; λ is the emission wavelength of VCSEL, n H2 n-Al z4 The refractive index of the GaAs high refractive index layer, n L2 n-Al 0.9 The refractive index of the GaAs low refractive index layer;

[0025] Each layer of p-Al z On top of the GaAs high refractive index layer, a 20nm AlGaAs transition layer is set, and the Al composition changes linearly from z to 0.9; similarly, each p-Al 0.9 A 20nm p-AlGaAs transition layer is set on the GaAs low refractive index layer, and the Al composition changes linearly from 0.9 to z; each p-Al zA 20nm p-AlGaAs transition layer is set on the GaAs high refractive index layer, and the Al composition changes linearly from z4 to 0.9; the top p-Al z A 30nm p-AlGaAs transition layer is set on the GaAs high refractive index layer. The Al composition changes linearly from z4 to 0, and the doping concentration increases from 3×10 18 cm -3 Linear Gradient to 2×10 19 cm -3 ; z3 and z4 represent the Al components in the corresponding materials respectively.

[0026] In the vertical cavity surface emitting laser, z3=z4.

[0027] In addition, the present invention also provides a method for preparing a vertical cavity surface emitting laser, comprising an epitaxial growth step and a chip process step; the epitaxial growth step adopts metal organic chemical vapor deposition technology to perform epitaxial growth, comprising the following steps:

[0028] Step 1: Select a (001) surface n-type GaAs substrate and place it on a graphite tray in a MOCVD reaction chamber;

[0029] Step 2: In a hydrogen atmosphere, introduce arsine (AsH3), raise the temperature of the graphite tray to 680°C under the protection of AsH3, and bake at high temperature to remove impurities and oxide layers on the surface of the substrate;

[0030] Step 3: lower the temperature to 640°C, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of the GaAs buffer layer by adjusting the TMGa flow rate, control the V / III ratio to 60 by adjusting the AsH3 flow rate, control the doping concentration by adjusting the SiH4 flow rate, and grow an n-GaAs buffer layer;

[0031] Step 4: Maintaining the growth temperature at 640°C and the V / III ratio at 60, trimethylaluminum (TMAl) was introduced and its flow rate was gradually changed from 0 to Al z GaAs growth required flow rate to form an AlGaAs transition layer on top of the n-GaAs buffer layer;

[0032] Step 5: Keep the growth temperature at 640℃, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, and adjust the SiH4 flow rate to make the doping concentration 2×10 18 cm -3 , Al in the growth n-DBR z3 GaAs high refractive index layer;

[0033] Step 6: Maintaining the growth temperature at 640°C and the V / III ratio at 60, the TMGa and TMAl flows were linearly ramped to Al 0.9 The flow rate required for GaAs growth to form Al z3 AlGaAs transition layer on top of GaAs high refractive index layer;

[0034] Step 7: Keep the growth temperature at 640℃, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, and adjust the SiH4 flow rate to make the doping concentration 2×10 18 cm -3 , Al in the growth n-DBR 0.9 GaAs low refractive index layer;

[0035] Step 8: Keep the growth temperature at 640℃, V / III ratio at 60, and linearly change the flow rate of TMGa and TMAl to Al z3 The flow rate required for GaAs growth to form Al 0.9 An AlGaAs transition layer on top of a GaAs low refractive index layer;

[0036] Step 9: Repeat steps 5 to 8 to form 40 pairs of doping concentrations of 2×10 18 cm -3 n-DBR;

[0037] Step 10: Adjust the SiH4 flow rate to make the doping concentration 1×10 18 cm -3 , repeat steps 5 to 8 again to form three pairs of doping concentrations of 1×10 18 cm -3 n-DBR;

[0038] Step 11: Use the growth parameters in step 5, but shorten the growth time to grow n-Al in the n-lower oxide confinement structure. z1 GaAs high refractive index layer;

[0039] Step 12: Repeat step 6 to form n-Al z1 AlGaAs transition layer on top of GaAs high refractive index layer;

[0040] Step 13: Maintaining the growth temperature at 640°C and the V / III ratio at 60, the TMGa and TMAl flows were switched to Al 0.98 The flow rate required for GaAs growth is adjusted to make the doping concentration 1×10 18 cm -3 , grow n-Al in n-lower oxide confinement structure 04 0.98 GaAs lower oxide restriction layer 05;

[0041] Step 14: Maintain the growth temperature at 640°C, V / III ratio at 60, and switch the TMGa and TMAl flows to Al 0.9 The flow rate required for GaAs growth is adjusted to make the doping concentration 1×10 18 cm -3 , grow n-Al in n-oxidation confinement structure 0.9 GaAs low refractive index layer;

[0042] Step 15: maintaining the growth temperature at 640°C and the V / III ratio at 60, cutting off the SiH4 supply, linearly changing the flow rates of TMGa and TMAl to the flow rates required for the growth of the AlGaAs quantum barrier layer, and growing the AlGaAs lower space layer;

[0043] Step 16: Keep the growth temperature at 640°C, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, grow the AlGaAs quantum barrier layer, cut off the TMGa and TMAl sources after the growth is completed, and pause the growth for 5 seconds;

[0044] Step 17: maintaining the growth temperature at 640°C and the V / III ratio at 60, introducing TMGa, TMAl and TMIn sources, and adjusting the flow rates of TMGa, TMAl and TMIn sources to make the growth rate of the InGaAlAs quantum well layer 0.2nm / s, growing the quantum well layer, and after the growth is completed, cutting off the TMGa, TMAl and TMIn sources, and pausing the growth for 5s;

[0045] Step 18: Repeat steps 16 to 17 for multiple cycles to form a quantum well active region;

[0046] Step 19: Repeat step 16 to complete the last AlGaAs quantum barrier layer of the quantum well active region;

[0047] Step 20: Keep the growth temperature at 640°C and the V / III ratio at 60, introduce TMGa and TMAl sources, set the initial flow rate to the flow rate required for the growth of the AlGaAs quantum barrier layer, and then linearly change to Al 0.9 The flow rate required for GaAs growth forms the upper space layer of AlGaAs;

[0048] Step 21: Keep the growth temperature at 640°C, lower the V / III ratio to 40, keep the TMGa and TMAl flow rates unchanged, introduce carbon tetrabromide as the C doping source, and adjust the carbon tetrabromide flow rate to make the doping concentration 1×10 18 cm -3 , growing p-Al in a p-upper oxidation confinement structure 0.9 GaAs low refractive index layer;

[0049] Step 22: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the TMGa and TMAl flows were switched to Al 0.98 The flow rate required for GaAs growth is adjusted to a doping concentration of 1×10 18 cm -3 , growing p-Al in a p-upper oxidation confinement structure 0.98 GaAs oxide confinement layer;

[0050] Step 23: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the initial flow rates of TMGa and TMAl are switched to Al 0.9 GaAs growth required flow rate, then linearly gradient to Al z2 The flow rate required for GaAs growth is to grow a 20nm AlGaAs transition layer;

[0051] Step 24: Keep the growth temperature at 640°C, the V / III ratio at 40, the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to a doping concentration of 1×10 18 cm -3 , growing p-Al in a p-upper oxidation confinement structure z2 GaAs high refractive index layer;

[0052] Step 25: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the TMGa and TMAl flows were linearly ramped to Al 0.9 The required flow rate for GaAs growth forms a 20nm AlGaAs transition layer;

[0053] Step 26: Keep the growth temperature at 640°C, the V / III ratio at 40, the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , p-Al in p-DBR 0.9 GaAs low refractive index layer;

[0054] Step 27: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the TMGa and TMAl flows were linearly ramped to Al z4 The required flow rate for GaAs growth forms a 20nm AlGaAs transition layer;

[0055] Step 28: Keep the growth temperature at 640°C, the V / III ratio at 40, the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , p-Al in p-DBR z4 GaAs high refractive index layer;

[0056] Step 29: Repeat steps 25 to 28 to form three pairs of doping concentrations of 1×10 18 cm -3 p-DBR;

[0057] Step 30: Adjust the CBr4 flow rate to make the doping concentration 3×10 18 cm -3 Repeat steps 25 to 28 to form 20 pairs of doping concentrations of 3×10 18 cm -3 p-DBR, completing the growth of p-DBR 09;

[0058] Step 31: The growth temperature is linearly decreased from 640°C to 580°C, the flow rate of TMAl is linearly changed to 0, the V / III ratio is linearly changed to 30, and the flow rate of CBr4 is linearly changed to the flow rate required for doping the p+GaAs contact layer to form an AlGaAs transition layer from p-DBR to the p+GaAs contact layer. The Al component is linearly changed from z to 0, and the doping concentration is linearly changed from 3×10 18 cm -3 Linear Gradient to 2×10 19 cm -3 ;

[0059] Step 32: maintaining the growth temperature at 580°C, the V / III ratio at 30, cutting off the flow rates of TMAl, TMGa and CBr4, and growing a p+GaAs contact layer;

[0060] Step 33: Cut off TMGa and CBr4, cool naturally to room temperature, and then cut off AsH3 to complete epitaxial wafer growth;

[0061] The chip process steps include:

[0062] Step 34: Cleaning the epitaxial wafer using a standard epitaxial wafer cleaning process;

[0063] Step 35: using a photolithography + development process to form an electrode pattern of the p-side electrode layer, retaining the photoresist outside the electrode region of the p-side electrode layer, and removing the photoresist in the electrode region of the p-side electrode layer;

[0064] Step 36: Depositing a metal layer corresponding to the p-side electrode by electron beam evaporation or magnetron sputtering;

[0065] Step 37: Use adhesive stripping process to remove the metal outside the glass ring electrode, leaving the metal in the ring electrode area to form a p-surface ring electrode;

[0066] Step 38: using a photolithography + development process to form a cylindrical table pattern on the wafer surface, leaving the photoresist in the cylindrical table area and removing the photoresist outside the cylindrical table;

[0067] Step 39: using a dry etching process to etch out a cylindrical mesa, etching until the n-DBR layer is reached, and then removing the photoresist on the cylindrical mesa;

[0068] Step 40: Using a chemical polishing process to process the side wall of the cylindrical mesa to eliminate etching damage on the side wall;

[0069] Step 41: oxidizing the oxidation restriction layers in the n-lower oxidation restriction structure layer and the p-upper oxidation restriction structure layer by a wet oxidation process to form an aluminum oxide layer around the oxidation restriction layer;

[0070] Step 42: Depositing a SiO2 insulating layer by plasma chemical vapor deposition technology, wherein the thickness of the SiO2 insulating layer is greater than the height of the cylindrical platform to protect the side wall of the cylindrical platform;

[0071] Step 43: Overlay the cylindrical platform using a photolithography + development process to remove the photoresist on the upper surface of the cylindrical platform and retain the photoresist outside the cylindrical platform area to protect the SiO2 insulating layer;

[0072] Step 44: using a wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical platform, exposing the p-side annular electrode, and then removing all photoresists;

[0073] Step 45: forming the lead and pad patterns of the p-side electrode layer by using a photolithography + development process;

[0074] Step 46: Depositing p-side metal by electron beam evaporation or magnetron sputtering;

[0075] Step 47: stripping the photoresist on the surface of the wafer and the metal thereon by using a stripping process to form a p-side electrode lead and a pad;

[0076] Step 48: Thinning the n-GaAs substrate to 120 μm using a grinding process;

[0077] Step 49: polishing the back side of the n-GaAs substrate using a polishing process;

[0078] Step 50: Depositing metal on the back side of the n-GaAs substrate by electron beam evaporation or magnetron sputtering to form an n-side electrode;

[0079] Step 51: alloying the n-side electrode and the p-side electrode using a high temperature annealing process to form an ohmic contact with the semiconductor;

[0080] Step 52: Slice and split to form a single tube or array chip, completing the preparation of GaAs-based VCSEL chip.

[0081] Compared with the prior art, the present invention has the following beneficial effects:

[0082] First, the vertical cavity surface emitting laser of the present invention adopts a symmetrical oxidation confinement structure, so that more carriers are confined in the oxidation holes, the carrier injection efficiency is significantly improved, the carrier concentration and current density in the active region are significantly improved, and the increase in carrier concentration increases the radiation recombination efficiency, internal quantum efficiency and slope efficiency, thereby significantly increasing the output power and electro-optical conversion efficiency. Figure 4 and attached Figure 5 As shown;

[0083] Second, in the vertical cavity surface emitting laser of the present invention, under the effect of the symmetrical oxidation confinement structure, the confinement capability of the oxidation hole on the light field is improved, the confinement factor is increased, more high-order modes are confined in the oxidation hole, and photon leakage is reduced, which is conducive to the improvement of light output power;

[0084] Third, in the present invention, the symmetrical oxidation confinement structure can be used as a mode control structure of a vertical cavity surface emitting laser. By changing the number of symmetrical oxidation confinement layers and the size of oxidation holes, the number and distribution of transverse modes can be adjusted, thereby increasing the output power. Figure 6 shown. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 A schematic structural diagram of a 940nm vertical cavity surface emitting laser provided in the first embodiment of the present invention;

[0086] Figure 2 is a schematic structural diagram of a p-side electrode layer in Embodiment 1 of the present invention;

[0087] Figure 3 A schematic structural diagram of a 940nm vertical cavity surface emitting laser provided in the second embodiment of the present invention;

[0088] Figure 4 The PIV curves of the vertical cavity surface emitting laser of the first embodiment and the second embodiment of the present invention are compared with the vertical cavity surface emitting laser of the single oxide confinement layer structure; wherein the single oxide confinement structure refers to only a p-oxide confinement structure, no n-oxide confinement structure, and the p-oxide confinement structure has only one period;

[0089] Figure 5 The electro-optical conversion efficiency of the vertical cavity surface emitting laser of the first embodiment and the second embodiment of the present invention is compared with that of the vertical cavity surface emitting laser of the single oxide confinement layer structure;

[0090] Figure 6This is a comparison diagram of the mode distribution of the vertical cavity surface emitting laser of Example 1 and Example 2 of the present invention and the vertical cavity surface emitting laser of a single oxide confinement layer structure, wherein (a) corresponds to the vertical cavity surface emitting laser of a single oxide confinement structure, (b) corresponds to Example 1, and (c) corresponds to Example 2; LP01 LP11, etc. are all transverse modes. DETAILED DESCRIPTION

[0091] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0092] Embodiment 1

[0093] Embodiment 1 of the present invention provides a 940nm vertical cavity surface emitting laser, the structure of which is as shown in the attached figure. Figure 1 As shown, it includes an n-side electrode layer 17, a substrate layer 1, a buffer layer 2, and an n-DBR layer 3 arranged in sequence from bottom to top, a SiO2 insulating layer 16 located on the periphery is arranged above the n-DBR layer 3, and the center of the SiO2 insulating layer 16 is arranged in sequence from bottom to top to form an n-lower oxidation restriction structure layer, a lower space layer 7, a quantum well active region 8, an upper space layer 9, a p-upper oxidation restriction structure layer, a p-DBR layer 13, a contact layer 14, and a p-side electrode layer 15 to form a cylindrical cone.

[0094] The n-underoxidation restriction structure layer includes a periodic n-underoxidation restriction structure, wherein the n-underoxidation restriction structure is sequentially arranged from bottom to top. z1 GaAs high refractive index layer 4, n-Al 0.98 GaAs oxidation confinement layer 5 and n-Al 0.9 GaAs low refractive index layer 6, the n-Al 0.98 A first aluminum oxide layer is formed on the periphery of the GaAs oxidation restriction layer 5 by a wet oxidation process.

[0095] The p-upper oxidation restriction structure layer includes a periodic p-upper oxidation restriction structure, and the p-upper oxidation restriction structure includes p-Al 0.9 GaAs low refractive index layer 10, p-Al 0.98 GaAs oxidation confinement layer 11 and p-Al z2 GaAs high refractive index layer 12, the p-Al 0.98A second aluminum oxide layer is formed on the periphery of the GaAs oxidation restriction layer 11 by a wet oxidation process. Wherein, z1 and z2 represent the Al components in the corresponding materials respectively.

[0096] In this embodiment, z1=z2=0.05, and a 940nm vertical cavity surface emitting laser can be finally obtained. Then the n-lower oxidation confinement structure layer and the p-upper oxidation confinement structure layer form a symmetrical structure.

[0097] Specifically, in this embodiment, the n-side electrode layer 17 includes gold and nickel layers arranged in sequence from bottom to top; and is located below the thinned and polished n-GaAs substrate;

[0098] The substrate layer 1 is an n-GaAs substrate, which has been thinned and polished to a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si.

[0099] The buffer layer 2 is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si.

[0100] Furthermore, an AlGaAs transition layer is provided on the buffer layer 2, and the Al component is linearly changed from 0 to 0.05, and the doping concentration is 2×10 18 cm -3 , doped with Si.

[0101] The n-DBR layer 3 is composed of 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al 0.9 GaAs low refractive index layers are periodically overlapped; among them, n-Al z3 The thickness of the GaAs high refractive index layer is λ / 4n H1 –20nm, z3 satisfies: 1.424+1.247z3>1240 / (λ-50); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n L1 –20nm; λ is the emission wavelength of VCSEL, n H1 n-Al z3 The refractive index of the GaAs high refractive index layer, n L1 n-Al 0.9 Refractive index of the GaAs low refractive index layer.

[0102] Furthermore, each layer of n-Al z3 On top of the GaAs high refractive index layer, a 20nm n-AlGaAs transition layer is set, and the Al composition in the transition layer changes linearly from z3 to 0.9; similarly, each layer of n-Al0.9 A 20nm n-AlGaAs transition layer is arranged on the GaAs low refractive index layer, and the Al composition changes linearly from 0.9 to z3.

[0103] Specifically, the n-DBR layer 3 is composed of 43 pairs of Al 0.05 GaAs / Al 0.9 GaAs is periodically overlapped, Al 0.05 GaAs thickness is 44.3nm, Al 0.9 The thickness of GaAs is 56.9nm, and each layer of Al 0.05 A 20nm AlGaAs transition layer is set on the GaAs, and the Al composition of the transition layer changes linearly from 0.05 to 0.9; similarly, each Al layer 0.9 A 20nm AlGaAs transition layer is arranged on the GaAs, and the Al composition is linearly changed from 0.9 to 0.05; in the n-DBR layer 3, the doping concentration of the three pairs of n-DBRs near the active area is 1×10 18 cm -3 The doping concentration of the remaining 40 pairs of n-DBRs is 2×10 18 cm -3 , doped with Si.

[0104] The n-Al z1 The thickness of the GaAs high refractive index layer 4 is 19.6 nm, and the doping concentration is 1×10 18 cm -3 , doped with Si.

[0105] Furthermore, the n-Al z1 On the GaAs high refractive index layer 4, a 20 nm transition layer is provided, and the Al composition is linearly changed from 0.05 to 0.9, and the doping concentration is 1×10 18 cm -3 , doped with Si.

[0106] The n-Al 0.98 The thickness of the GaAs oxide confinement layer 5 is 30 nm and the doping concentration is 1×10 18 cm -3 , doped with Si.

[0107] The n-Al 0.9 The thickness of the GaAs low refractive index layer 6 is 76.9 nm, and the doping concentration is 1×10 18 cm -3 , doped with Si.

[0108] The lower space layer 7 is an AlGaAs lower space layer with a thickness of 114.1 nm, an Al component linearly changing from 0.9 to 0.05, and no doping.

[0109] The multi-quantum well active region 8 is composed of 3.5 pairs of In 0.15 GaAs / Al 0.05 GaAs quantum well composition, In 0.15 The thickness of GaAs quantum well layer is 8nm, and Al 0.05 The thickness of the GaAs quantum barrier layer is 8 nm, the number of quantum barrier layers is 4, and the number of quantum well layers is 3.

[0110] The upper space layer 9 is an AlGaAs upper space layer with a thickness of 114.1 nm and an Al component linearly varying from 0.05 to 0.9.

[0111] The p-Al 0.9 The thickness of the GaAs low refractive index layer 10 is 76.9 nm and the doping concentration is 1×10 18 cm -3 , doped with C.

[0112] The p-Al 0.98 The thickness of the GaAs oxide restriction layer 11 is 30 nm and the doping concentration is 1×10 18 cm -3 , doped with C.

[0113] Furthermore, the p-Al 0.98 A 20 nm AlGaAs transition layer is disposed on the GaAs oxidation restriction layer 11 , and the Al composition changes linearly from 0.9 to 0.05.

[0114] The p-Al z2 The thickness of the GaAs high refractive index layer 12 is 19.6 nm, and the doping concentration is 1×10 18 cm -3 , doped with C;

[0115] The p-Al z2 A 20 nm AlGaAs transition layer is disposed on the GaAs high refractive index layer 12, and the Al composition is linearly changed from 0.05 to 0.9, and the doping concentration is 1×10 18 cm -3 , doped with C;

[0116] The p-DBR layer consists of 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z4 GaAs high refractive index layers are periodically overlapped; among them, p-Al z4 The thickness of the GaAs high refractive index layer is λ / 4n H2 –20nm, z4 satisfies: 1.424+1.247z4>1240 / (λ-50); p-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4nL2 –20nm; λ is the emission wavelength of VCSEL, n H2 n-Al z4 The refractive index of the GaAs high refractive index layer, n L2 n-Al 0.9 The refractive index of the GaAs low refractive index layer;

[0117] Each layer of p-Al z4 On top of the GaAs high refractive index layer, a 20nm AlGaAs transition layer is set, and the Al composition is linearly gradient from z4 to 0.9; similarly, each p-Al 0.9 A 20nm p-AlGaAs transition layer is set on the GaAs low refractive index layer, and the Al composition changes linearly from 0.9 to z4; the top p-Al z4 A 30nm p-AlGaAs transition layer is set on the GaAs high refractive index layer. The Al composition changes linearly from z4 to 0, and the doping concentration increases from 3×10 18 cm -3 Linear Gradient to 2×10 19 cm -3 ; z3 and z4 represent the Al components in the corresponding materials respectively.

[0118] Specifically, in this embodiment, z4=z3=0.05. In the p-DBR layer, the p-Al 0.9 The thickness of GaAs low refractive index layer is 56.9nm, and the p-Al z2 The thickness of the GaAs high refractive index layer 12 is 44.3 nm, and the doping concentration of the three pairs of p-DBRs near the active area is 1×10 18 cm -3 , the doping concentration of 20p-DBR is 3×10 18 cm -3 , doped with C.

[0119] The contact layer 14 is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C;

[0120] The p-side electrode layer includes titanium, platinum and gold layers arranged in sequence from bottom to top. In this embodiment, the electrode of the p-side electrode layer is annular, the center of which coincides with the center of the n-lower oxidation restriction structure layer, and the inner diameter is larger than the n-Al 0.98 GaAs oxide confinement layer and p-Al 0.98 The diameter of the GaAs oxide limiting layer. Specifically, Figure 2 As shown, in this embodiment, the inner diameter of the circular electrode of the p-side electrode layer is 8 μm, and the outer diameter is 35 μm. The diameter of the oxidation restriction layer is 4-6 μm.

[0121] In this embodiment, the n-lower oxidation restriction structure layer, the lower space layer 7, the quantum well active region 8, the upper space layer 9, the p-upper oxidation restriction structure layer, the p-DBR layer 13, and the contact layer 14 on the n-DBR layer 3 form a cylindrical table with a diameter of 40 μm. The annular electrode of the p-surface electrode layer is located in the middle of the upper surface of the cylindrical table.

[0122] In this embodiment, the thicknesses of the lower space layer 7, the quantum well active region 8, and the upper space layer 9 satisfy:

[0123]

[0124] Among them, h i is the actual thickness of each layer, n i is the refractive index of each layer, m is a positive integer not greater than 5, and λ is the emission wavelength of the VCSEL.

[0125] In this embodiment, n-Al 0.98 GaAs oxide confinement layer and p-Al 0.98 The outer periphery of the GaAs oxide confinement layer is aluminum oxide, and only the middle oxide hole area is Al 0.98 For GaAs, the center of the oxide hole, the center of the p-side annular electrode, and the central axis of the cylindrical cone coincide.

[0126] Embodiment 2

[0127] like Figure 3 As shown, the second embodiment of the present invention provides a 940nm vertical cavity surface emitting laser, which is the same as the first embodiment in that it includes an n-side electrode layer 17, a substrate layer 1, a buffer layer 2, and an n-DBR layer 3 arranged in sequence from bottom to top, and a SiO2 insulating layer 16 located on the periphery is arranged above the n-DBR layer 3, and the center of the SiO2 insulating layer 16 is arranged in sequence from bottom to top to form an n-lower oxidation restriction structure layer, a lower space layer 7, a quantum well active region 8, an upper space layer 9, a p-upper oxidation restriction structure layer, a p-DBR layer 13, a contact layer 14, and a p-side electrode layer 15 to form a cylindrical cone.

[0128] Different from the first embodiment, in the present embodiment, the n-lower oxidation restriction structure layer includes two periods of n-lower oxidation restriction structures, and the p-upper oxidation restriction structure layer includes two periods of p-upper oxidation restriction structures. There are two oxidation restriction layers above and below the active region 8, respectively, forming two pairs of symmetrical oxidation restriction structures including four oxidation restriction layers, while the first embodiment has only one pair of symmetrical oxidation restriction structures.

[0129] Specifically, n-Al is disposed in the first pair and the second pair of n-DBRs close to the active region. 0.98GaAs oxidation restriction layer; p-Al is set in the first and second pairs of p-DBRs near the active area. 0.98 The GaAs oxidation confinement layer can form two pairs of symmetrical oxidation confinement structures with four oxidation confinement layers.

[0130] Furthermore, in the present invention, the n-down oxidation restriction structure layer may include more than two periods of n-down oxidation restriction structures, and the p-up oxidation restriction structure layer may include more than two periods of p-up oxidation restriction structures.

[0131] Embodiment 3

[0132] Embodiment 3 of the present invention provides a method for preparing a vertical cavity surface emitting laser as described in Embodiment 1 and Embodiment 2, comprising an epitaxial growth step and a chip process step; the epitaxial growth step adopts metal organic chemical vapor deposition (MOCVD) technology for epitaxial growth, comprising the following steps:

[0133] (1) Selecting a (001) surface n-type GaAs substrate 1, and placing it on a graphite tray in a MOCVD reaction chamber;

[0134] (2) In a hydrogen atmosphere, arsine (AsH3) is introduced, and the temperature of the graphite tray is raised to 680°C under the protection of AsH3, and impurities and oxide layers on the surface of the substrate are removed by high-temperature baking;

[0135] (3) lowering the temperature to 640°C, introducing trimethylgallium (TMGa) and silane (SiH4), controlling the growth rate of the GaAs buffer layer by adjusting the TMGa flow rate, controlling the V / III ratio to 60 by adjusting the AsH3 flow rate, and controlling the doping concentration by adjusting the SiH4 flow rate to grow an n-GaAs buffer layer;

[0136] (4) Maintaining the growth temperature at 640°C and the V / III ratio at 60, trimethylaluminum (TMAl) was introduced and its flow rate was gradually changed from 0 to Al 0.05 GaAs growth required flow rate to form an AlGaAs transition layer on top of the n-GaAs buffer layer;

[0137] (5) The growth temperature was maintained at 640°C, the V / III ratio was 60, the TMGa and TMAl flow rates were unchanged, and the SiH4 flow rate was adjusted to make the doping concentration 2×10 18 cm -3 , Al in the growth n-DBR 0.05 GaAs high refractive index layer;

[0138] (6) The growth temperature was maintained at 640 °C, the V / III ratio was 60, and the flow rates of TMGa and TMAl were linearly changed to Al 0.9The flow rate required for GaAs growth to form Al 0.05 AlGaAs transition layer on top of GaAs high refractive index layer;

[0139] (7) The growth temperature was maintained at 640°C, the V / III ratio was 60, the TMGa and TMAl flow rates were unchanged, and the SiH4 flow rate was adjusted to make the doping concentration 2×10 18 cm -3 , Al in the growth n-DBR 0.9 GaAs low refractive index layer;

[0140] (8) The growth temperature was maintained at 640 °C, the V / III ratio was 60, and the flow rates of TMGa and TMAl were linearly changed to Al 0.05 The flow rate required for GaAs growth to form Al 0.9 An AlGaAs transition layer on top of a GaAs low refractive index layer;

[0141] (9) Repeat steps (5) to (8) for 40 cycles to form 40 pairs of doping concentrations of 2×10 18 cm -3 n-DBR;

[0142] (10) Adjust the SiH4 flow rate to make the doping concentration 1×10 18 cm -3 Repeat steps (5) to (8) for 3 cycles to form 3 pairs of doping concentrations of 1×10 18 cm -3 n-DBR;

[0143] (11) Using the growth parameters in step (5), but shortening the growth time, n-Al 0.05 GaAs high refractive index layer 04;

[0144] (12) Repeat step (6) to form n-Al 0.05 AlGaAs transition layer on top of GaAs high refractive index layer;

[0145] (13) The growth temperature was maintained at 640 °C, the V / III ratio was 60, and the flow rates of TMGa and TMAl were switched to Al 0.98 The flow rate required for GaAs growth is adjusted to make the doping concentration 1×10 18 cm -3 , growth of n-Al 0.98 GaAs first oxidized confinement layer 5;

[0146] (14) The growth temperature was maintained at 640 °C, the V / III ratio was 60, and the flow rates of TMGa and TMAl were switched to Al 0.9The flow rate required for GaAs growth is adjusted to make the doping concentration 1×10 18 cm -3 , growth of n-Al 0.9 GaAs low refractive index layer 6;

[0147] (15) The growth temperature was maintained at 640 °C, the V / III ratio was 60, the SiH4 supply was cut off, and the TMGa and TMAl flow rates were linearly changed to Al 0.05 GaAs growth required flow rate, grow AlGaAs lower space layer 7;

[0148] (16) Keeping the growth temperature at 640°C, the V / III ratio at 60, and the TMGa and TMAl flow rates unchanged, 8 nm Al was grown. 0.05 GaAs quantum barrier layer, after the growth is completed, cut off the TMGa and TMAl sources and pause the growth for 5s;

[0149] (17) The growth temperature was maintained at 640 °C, the V / III ratio was 60, TMGa and TMIn sources were introduced, and the In 0.15 The growth rate of GaAs quantum well layer is 0.2nm / s, and the growth rate of In 0.15 GaAs quantum well layer, after the growth is completed, cut off the TMGa, TMAl and TMIn sources and pause the growth for 5s;

[0150] (18) Repeat steps (16) and (17) for three cycles to form a 3-cycle In 0.15 GaAs / Al 0.05 GaAs multi-quantum well active region 8;

[0151] (19) Repeat step (16) to complete the last layer of Al in the quantum well active region. 0.05 GaAs quantum barrier layer;

[0152] (20) The growth temperature was maintained at 640 °C, the V / III ratio was 60, and TMGa and TMAl sources were introduced. The initial flow rate was set to Al 0.05 GaAs growth required flow rate, then linearly gradient to Al 0.9 The flow rate required for GaAs growth forms the upper space layer 9 of AlGaAs;

[0153] (21) The growth temperature was kept at 640 °C, the V / III ratio was lowered to 40, the flow rates of TMGa and TMAl were kept constant, and carbon tetrabromide (CBr4) was introduced as a C doping source. The CBr4 flow rate was adjusted to a doping concentration of 1 × 10 18 cm -3 , growth of p-Al 0.9 GaAs low refractive index layer 10;

[0154] (22) The growth temperature was maintained at 640 °C, the V / III ratio was 40, and the flow rates of TMGa and TMAl were switched to Al 0.98 The flow rate required for GaAs growth is adjusted by adjusting the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , grow 30nm p-Al 0.98 GaAs second oxidized confinement layer 11;

[0155] (23) The growth temperature was maintained at 640 °C, the V / III ratio was 40, and the initial flow rates of TMGa and TMAl were switched to Al 0.9 GaAs growth required flow rate, then linearly gradient to Al 0.05 The flow rate required for GaAs growth is to grow a 20nm AlGaAs transition layer;

[0156] (24) The growth temperature was kept at 640°C, the V / III ratio was kept at 40, the TMGa and TMAl flow rates were kept constant, and the CBr4 flow rate was adjusted to make the doping concentration 1×10 18 cm -3 , growing a p-Al z2GaAs high refractive index layer 12 with z2=0.05;

[0157] (25) The growth temperature was maintained at 640 °C, the V / III ratio was 40, and the flow rates of TMGa and TMAl were linearly changed to Al 0.9 The required flow rate for GaAs growth forms a 20nm AlGaAs transition layer, with the Al composition linearly changing from 0.05 to 0.9;

[0158] (26) The growth temperature was kept at 640°C, the V / III ratio was 40, the TMGa and TMAl flow rates were kept constant, and the CBr4 flow rate was adjusted to make the doping concentration 1×10 18 cm -3 , p-Al in p-DBR 0.9 GaAs low refractive index layer;

[0159] (27) The growth temperature was maintained at 640 °C, the V / III ratio was 40, and the flow rates of TMGa and TMAl were linearly changed to Al 0.05 The required flow rate for GaAs growth forms a 20nm AlGaAs transition layer, with the Al composition linearly changing from 0.9 to 0.05;

[0160] (28) The growth temperature was kept at 640°C, the V / III ratio was 40, the TMGa and TMAl flow rates were kept constant, and the CBr4 flow rate was adjusted to make the doping concentration 1×10 18 cm -3 , p-Al in p-DBR0.05 GaAs high refractive index layer;

[0161] (29) Repeat steps (25) to (28) for 3 cycles to form 3 pairs of doping concentrations of 1×10 18 cm -3 p-DBR;

[0162] (30) Adjust the CBr4 flow rate to make the doping concentration 3×10 18 cm -3 Repeat steps (25) to (28) for 20 cycles to form 20 pairs of doping concentrations of 3×10 18 cm -3 p-DBR, completing the growth of p-DBR 13;

[0163] (31) The growth temperature was linearly decreased from 640 °C to 580 °C, the flow rate of TMAl was linearly changed to 0, the V / III ratio was linearly changed to 30, and the flow rate of CBr4 was linearly changed to the flow rate required for doping the p+GaAs contact layer to form an AlGaAs transition layer from p-DBR to p+GaAs contact layer. The Al composition was linearly changed from 0.05 to 0, and the doping concentration was changed from 3×10 18 cm -3 Linear Gradient to 2×10 19 cm -3 ;

[0164] (32) maintaining the growth temperature at 580°C, the V / III ratio at 30, cutting off the TMAl, TMGa and CBr4 flow rates, and growing the p+GaAs contact layer 14;

[0165] (33) Cut off TMGa and CBr4, cool naturally to room temperature, and then cut off AsH3 to complete the epitaxial wafer growth.

[0166] Next is the chip process part:

[0167] (34) Cleaning the epitaxial wafer using a standard epitaxial wafer cleaning process;

[0168] (35) using a photolithography + development process to form a pattern of a p-side annular electrode, retaining the photoresist outside the p-side annular electrode region, and removing the photoresist in the p-side annular electrode region;

[0169] (36) Depositing p-side metal using electron beam evaporation or magnetron sputtering;

[0170] (37) using a tape stripping process to remove the metal outside the glass ring electrode, leaving the metal in the ring electrode area to form a p-surface ring electrode 15;

[0171] (38) forming a VCSEL cylindrical mesa pattern on the wafer surface by using a photolithography + development process, leaving the photoresist in the cylindrical mesa area and removing the photoresist outside the cylindrical mesa;

[0172] (39) A cylindrical terrace is etched using a dry etching process until the n-DBR is reached, leaking out the p-Al 0.98 Sides of the GaAs first oxidation confinement layer and the second oxidation confinement layer, and then removing the photoresist on the cylindrical mesa;

[0173] (40) The sidewalls of the cylindrical mesa are treated by chemical polishing to eliminate etching damage on the sidewalls;

[0174] (41) The two oxide restriction layers are oxidized by a wet oxidation process to form symmetrical oxidation holes with a diameter of 6 μm, that is, the diameter of the two oxide restriction layers is 6 μm; specifically, by using nitrogen to carry water vapor into the reaction chamber, the oxygen atoms in the water react with the Al atoms in the two oxide restriction layers AlGaAs to form aluminum oxide.

[0175] (42) a SiO2 insulating layer is deposited by plasma chemical vapor deposition (PECVD) technology, wherein the thickness of the insulating layer is slightly greater than the height of the cylindrical mesa to protect the side wall of the cylindrical mesa;

[0176] (43) overlaying the cylindrical mesa using a photolithography + development process, removing the photoresist on the upper surface of the cylindrical mesa, and retaining the photoresist outside the cylindrical mesa area to protect the SiO2 insulating layer;

[0177] (44) using a wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical mesa to expose the p-side annular electrode, and then removing all the photoresist;

[0178] (45) Using photolithography + development process to form the lead and pad pattern of the p-side electrode;

[0179] (46) Depositing p-side metal using electron beam evaporation or magnetron sputtering;

[0180] (47) using a stripping process to strip the photoresist on the wafer surface and the metal thereon to form a p-side electrode lead and a pad;

[0181] (48) The n-GaAs substrate was thinned to 120 μm using a grinding process;

[0182] (49) polishing the back side of the n-GaAs substrate using a polishing process;

[0183] (50) depositing metal on the back side of the n-GaAs substrate by electron beam evaporation or magnetron sputtering to form an n-side electrode layer 17;

[0184] (51) alloying the n-side electrode and the p-side electrode by a high temperature annealing process so as to form an ohmic contact with the semiconductor;

[0185] (52) Slicing + splitting to form a single tube or array chip, completing the preparation of GaAs-based VCSEL chips.

[0186] Furthermore, when it is necessary to prepare the vertical cavity surface emitting laser including two pairs of symmetrical oxidation confinement structures in Example 2, only the following process adjustments need to be made:

[0187] In the epitaxial growth step, one more period of n-lower oxidation confinement structure and one more period of p-upper oxidation confinement structure are grown, even if the oxidation confinement layers are grown in two pairs of n-type DBRs and p-type DBRs near the active region;

[0188] In the chip process steps, due to the addition of a pair of symmetrical oxide restriction layers, during the process of dry etching to form the VCSEL cylindrical mesa, the etching depth needs to be increased by the depth of the two pairs of n-type DBRs to ensure that the sides of the two pairs of symmetrical oxide restriction layers are exposed.

[0189] like Figure 4 As shown in the figure, the PIV curve comparison of the vertical cavity surface emitting laser of the first embodiment and the second embodiment of the present invention and the vertical cavity surface emitting laser of the single oxide confinement layer structure is shown; wherein the single oxide confinement structure refers to only the p-oxide confinement structure, no n-oxide confinement structure, and the p-oxide confinement structure has only one period; it can be seen from the figure that the optical power of the vertical cavity surface emitting laser of the present invention is significantly increased. Figure 5 As shown, the electro-optical conversion efficiency of the vertical cavity surface emitting laser of the first embodiment and the second embodiment of the present invention is compared with that of the vertical cavity surface emitting laser of the single oxide confinement layer structure. It can be seen from the figure that the electro-optical conversion efficiency of the vertical cavity surface emitting laser of the present invention is also significantly increased; Figure 6 This is a comparison diagram of the mode distribution of the vertical cavity surface emitting laser of Example 1 and Example 2 of the present invention and the vertical cavity surface emitting laser of a single oxide confinement layer structure. It can be seen from the figure that by changing the number of oxide confinement layers, the number and distribution of transverse modes can be changed. Therefore, the present invention can also achieve mode control of the vertical cavity surface emitting laser.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vertical cavity surface emitting laser, characterized in that: It comprises an n-side electrode layer, a substrate layer, a buffer layer, and an n-DBR layer which are sequentially arranged from bottom to top, a SiO2 insulating layer which is located on the periphery is arranged above the n-DBR layer, and an n-lower oxidation restriction structure layer, a lower space layer, a quantum well active region, an upper space layer, a p-upper oxidation restriction structure layer, a p-DBR layer, a contact layer, and a p-side electrode layer which form a cylindrical platform are sequentially arranged from bottom to top in the center of the SiO2 insulating layer; The n-underoxidation restriction structure layer includes at least one periodic n-underoxidation restriction structure, wherein the n-underoxidation restriction structure is sequentially arranged from bottom to top. z1 GaAs high refractive index layer, n-Al 0.98 GaAs oxide confinement layer and n-Al 0.9 GaAs low refractive index layer, the n-Al 0.98 A first aluminum oxide layer is formed on the periphery of the GaAs oxide confinement layer by a wet oxidation process; The p-upper oxidation restriction structure layer includes at least one period of p-upper oxidation restriction structure, and the p-upper oxidation restriction structure includes p-Al 0.9 GaAs low refractive index layer, p-Al 0.98 GaAs oxide confinement layer and p-Al z2 GaAs high refractive index layer, the p-Al 0.98 A second aluminum oxide layer is formed on the periphery of the GaAs oxide restriction layer by a wet oxidation process, and z1 and z2 represent the Al components in the corresponding materials, respectively.

2. A vertical cavity surface emitting laser according to claim 1, characterized in that: The n-Al 0.98 The thickness of the GaAs oxide restriction layer is 30 nm. 0.98 The thickness of the GaAs oxide confinement layer is 30 nm.

3. A vertical cavity surface emitting laser according to claim 1, characterized in that: The n-Al 0.98 The doping concentration of the GaAs oxide confinement layer is 1×10 18 cm -3 , doped with Si; the p-Al 0.98 The doping concentration of the GaAs oxide confinement layer is 1×10 18 cm -3 , doped with C.

4. The vertical cavity surface emitting laser according to claim 1, characterized in that: The n-Al z1 GaAs high refractive index layer and n-Al 0.98 An n-AlGaAs transition layer is also provided between the GaAs oxidation restriction layers, and its Al composition changes linearly from z1 to 0.9; The p-Al 0.98 GaAs oxide confinement layer and p-Al z A p-AlGaAs transition layer is also arranged between the GaAs high refractive index layers, and its Al composition changes linearly from 0.9 to z2.

5. The vertical cavity surface emitting laser according to claim 1, characterized in that: The n-side electrode layer includes gold and nickel layers arranged in sequence from bottom to top; The substrate layer is an n-GaAs substrate with a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si; The buffer layer is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si; The lower space layer is an AlGaAs lower space layer with a thickness of 114.1 nm and no doping; The upper space layer is an AlGaAs upper space layer 09, with a thickness of 114.1 nm; The contact layer is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C; The p-side electrode layer includes titanium, platinum and gold layers arranged in sequence from bottom to top.

6. The vertical cavity surface emitting laser according to claim 1, characterized in that: The z1=z2.

7. The vertical cavity surface emitting laser according to claim 1, characterized in that: The p-side electrode layer is annular, its center coincides with the center of the n-lower oxidation restriction structure layer, and its inner diameter is larger than that of the n-Al 0.98 GaAs oxide confinement layer and p-Al 0.98 Radius of the GaAs oxide confinement layer.

8. The vertical cavity surface emitting laser according to claim 1, characterized in that: The n-DBR layer is composed of 43 pairs of n-Al z3 GaAs high refractive index layer and n-Al 0.9 GaAs low refractive index layers are periodically overlapped; among them, n-Al z3 The thickness of the GaAs high refractive index layer is λ / 4n H1 –20nm, z3 satisfies: 1.424+1.247z3>1240 / (λ-50); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n L1 –20nm; λ is the emission wavelength of VCSEL, n H1 n-Al z3 The refractive index of the GaAs high refractive index layer, n L1 n-Al 0.9 The refractive index of the GaAs low refractive index layer; Each layer of n-Al z3 On top of the GaAs high refractive index layer, a 20nm n-AlGaAs transition layer is set, and the Al composition in the transition layer changes linearly from z3 to 0.9; similarly, each layer of n-Al 0.9 On top of the GaAs low refractive index layer, a 20nm n-AlGaAs transition layer is set, and the Al composition changes linearly from 0.9 to z3; The p-DBR layer consists of 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z4 GaAs high refractive index layers are periodically overlapped; among them, p-Al z4 The thickness of the GaAs high refractive index layer is λ / 4n H2 –20nm, z4 satisfies: 1.424+1.247z4>1240 / (λ-50); p-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n L2 –20nm; λ is the emission wavelength of VCSEL, n H2 n-Al z4 The refractive index of the GaAs high refractive index layer, n L2 n-Al 0.9 The refractive index of the GaAs low refractive index layer; Each layer of p-Al z On top of the GaAs high refractive index layer, a 20nm AlGaAs transition layer is set, and the Al composition changes linearly from z to 0.9; similarly, each p-Al 0.9 A 20nm p-AlGaAs transition layer is set on the GaAs low refractive index layer, and the Al composition changes linearly from 0.9 to z; each p-Al z A 20nm p-AlGaAs transition layer is set on the GaAs high refractive index layer, and the Al composition changes linearly from z4 to 0.9; the top p-Al z A 30nm p-AlGaAs transition layer is set on the GaAs high refractive index layer. The Al composition changes linearly from z4 to 0, and the doping concentration increases from 3×10 18 cm -3 Linear Gradient to 2×10 19 cm -3 ; z3 and z4 represent the Al components in the corresponding materials respectively.

9. The vertical cavity surface emitting laser according to claim 8, characterized in that: z3=z4.

10. The method for preparing a vertical cavity surface emitting laser according to any one of claims 1 to 9, characterized in that: The method comprises an epitaxial growth step and a chip process step; the epitaxial growth step adopts metal organic chemical vapor deposition technology to perform epitaxial growth, and comprises the following steps: Step 1: Select a (001) surface n-type GaAs substrate and place it on a graphite tray in a MOCVD reaction chamber; Step 2: In a hydrogen atmosphere, introduce arsine (AsH3), raise the temperature of the graphite tray to 680°C under the protection of AsH3, and bake at high temperature to remove impurities and oxide layers on the surface of the substrate; Step 3: lower the temperature to 640°C, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of the GaAs buffer layer by adjusting the TMGa flow rate, control the V / III ratio to 60 by adjusting the AsH3 flow rate, control the doping concentration by adjusting the SiH4 flow rate, and grow an n-GaAs buffer layer; Step 4: Maintaining the growth temperature at 640°C and the V / III ratio at 60, trimethylaluminum (TMAl) was introduced and its flow rate was gradually changed from 0 to Al z GaAs growth required flow rate to form an AlGaAs transition layer on top of the n-GaAs buffer layer; Step 5: Keep the growth temperature at 640℃, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, and adjust the SiH4 flow rate to make the doping concentration 2×10 18 cm -3 , Al in the growth n-DBR z3 GaAs high refractive index layer; Step 6: Maintaining the growth temperature at 640°C and the V / III ratio at 60, the TMGa and TMAl flows were linearly ramped to Al 0.9 The flow rate required for GaAs growth to form Al z3 AlGaAs transition layer on top of GaAs high refractive index layer; Step 7: Keep the growth temperature at 640℃, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, and adjust the SiH4 flow rate to make the doping concentration 2×10 18 cm -3 , Al in the growth n-DBR 0.9 GaAs low refractive index layer; Step 8: Keep the growth temperature at 640℃, V / III ratio at 60, and linearly change the flow rate of TMGa and TMAl to Al z3 The flow rate required for GaAs growth to form Al 0.9 An AlGaAs transition layer on top of a GaAs low refractive index layer; Step 9: Repeat steps 5 to 8 to form 40 pairs of doping concentrations of 2×10 18 cm -3 n-DBR; Step 10: Adjust the SiH4 flow rate to make the doping concentration 1×10 18 cm -3 , repeat steps 5 to 8 again to form three pairs of doping concentrations of 1×10 18 cm -3 n-DBR; Step 11: Use the growth parameters in step 5, but shorten the growth time to grow n-Al in the n-lower oxide confinement structure. z1 GaAs high refractive index layer; Step 12: Repeat step 6 to form n-Al z1 AlGaAs transition layer on top of GaAs high refractive index layer; Step 13: Maintaining the growth temperature at 640°C and the V / III ratio at 60, the TMGa and TMAl flows were switched to Al 0.98 The flow rate required for GaAs growth is adjusted to make the doping concentration 1×10 18 cm -3 , grow n-Al in n-lower oxide confinement structure 04 0.98 GaAs lower oxide restriction layer 05; Step 14: Maintain the growth temperature at 640°C, V / III ratio at 60, and switch the TMGa and TMAl flows to Al 0.9 The flow rate required for GaAs growth is adjusted to make the doping concentration 1×10 18 cm -3 , grow n-Al in n-oxidation confinement structure 0.9 GaAs low refractive index layer; Step 15: maintaining the growth temperature at 640°C and the V / III ratio at 60, cutting off the SiH4 supply, linearly changing the flow rates of TMGa and TMAl to the flow rates required for the growth of the AlGaAs quantum barrier layer, and growing the AlGaAs lower space layer; Step 16: Keep the growth temperature at 640°C, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, grow the AlGaAs quantum barrier layer, cut off the TMGa and TMAl sources after the growth is completed, and pause the growth for 5 seconds; Step 17: maintaining the growth temperature at 640°C and the V / III ratio at 60, introducing TMGa, TMAl and TMIn sources, and adjusting the flow rates of TMGa, TMAl and TMIn sources to make the growth rate of the InGaAlAs quantum well layer 0.2nm / s, growing the quantum well layer, and after the growth is completed, cutting off the TMGa, TMAl and TMIn sources, and pausing the growth for 5s; Step 18: Repeat steps 16 to 17 for multiple cycles to form a quantum well active region; Step 19: Repeat step 16 to complete the last AlGaAs quantum barrier layer of the quantum well active region; Step 20: Keep the growth temperature at 640°C and the V / III ratio at 60, introduce TMGa and TMAl sources, set the initial flow rate to the flow rate required for the growth of the AlGaAs quantum barrier layer, and then linearly change to Al 0.9 The flow rate required for GaAs growth forms the upper space layer of AlGaAs; Step 21: Keep the growth temperature at 640°C, lower the V / III ratio to 40, keep the TMGa and TMAl flow rates unchanged, introduce carbon tetrabromide as the C doping source, and adjust the carbon tetrabromide flow rate to make the doping concentration 1×10 18 cm -3 , growing p-Al in a p-upper oxidation confinement structure 0.9 GaAs low refractive index layer; Step 22: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the TMGa and TMAl flows were switched to Al 0.98 The flow rate required for GaAs growth is adjusted to a doping concentration of 1×10 18 cm -3 , growing p-Al in a p-upper oxidation confinement structure 0.98 GaAs oxide confinement layer; Step 23: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the initial flow rates of TMGa and TMAl are switched to Al 0.9 GaAs growth required flow rate, then linearly gradient to Al z2 The flow rate required for GaAs growth is to grow a 20nm AlGaAs transition layer; Step 24: Keep the growth temperature at 640°C, the V / III ratio at 40, the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to a doping concentration of 1×10 18 cm -3 , growing p-Al in a p-upper oxidation confinement structure z2 GaAs high refractive index layer; Step 25: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the TMGa and TMAl flows were linearly ramped to Al 0.9 The required flow rate for GaAs growth forms a 20nm AlGaAs transition layer; Step 26: Keep the growth temperature at 640°C, the V / III ratio at 40, the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , p-Al in p-DBR 0.9 GaAs low refractive index layer; Step 27: Maintaining the growth temperature at 640°C and the V / III ratio at 40, the TMGa and TMAl flows were linearly ramped to Al z4 The required flow rate for GaAs growth forms a 20nm AlGaAs transition layer; Step 28: Keep the growth temperature at 640°C, the V / III ratio at 40, the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , p-Al in p-DBR z4 GaAs high refractive index layer; Step 29: Repeat steps 25 to 28 to form three pairs of doping concentrations of 1×10 18 cm -3 p-DBR; Step 30: Adjust the CBr4 flow rate to make the doping concentration 3×10 18 cm -3 Repeat steps 25 to 28 to form 20 pairs of doping concentrations of 3×10 18 cm -3 p-DBR, completing the growth of p-DBR 09; Step 31: The growth temperature is linearly decreased from 640°C to 580°C, the flow rate of TMAl is linearly changed to 0, the V / III ratio is linearly changed to 30, and the flow rate of CBr4 is linearly changed to the flow rate required for doping the p+GaAs contact layer to form an AlGaAs transition layer from p-DBR to the p+GaAs contact layer. The Al component is linearly changed from z to 0, and the doping concentration is linearly changed from 3×10 18 cm -3 Linear Gradient to 2×10 19 cm -3 ; Step 32: maintaining the growth temperature at 580°C, the V / III ratio at 30, cutting off the flow rates of TMAl, TMGa and CBr4, and growing a p+GaAs contact layer; Step 33: Cut off TMGa and CBr4, cool naturally to room temperature, and then cut off AsH3 to complete epitaxial wafer growth; The chip process steps include: Step 34: Cleaning the epitaxial wafer using a standard epitaxial wafer cleaning process; Step 35: using a photolithography + development process to form an electrode pattern of the p-side electrode layer, retaining the photoresist outside the electrode region of the p-side electrode layer, and removing the photoresist in the electrode region of the p-side electrode layer; Step 36: Depositing a metal layer corresponding to the p-side electrode by electron beam evaporation or magnetron sputtering; Step 37: Use adhesive stripping process to remove the metal outside the glass ring electrode, leaving the metal in the ring electrode area to form a p-surface ring electrode; Step 38: using a photolithography + development process to form a cylindrical table pattern on the wafer surface, leaving the photoresist in the cylindrical table area and removing the photoresist outside the cylindrical table; Step 39: using a dry etching process to etch out a cylindrical mesa, etching until the n-DBR layer is reached, and then removing the photoresist on the cylindrical mesa; Step 40: Using a chemical polishing process to process the side wall of the cylindrical mesa to eliminate etching damage on the side wall; Step 41: oxidizing the oxidation restriction layers in the n-lower oxidation restriction structure layer and the p-upper oxidation restriction structure layer by a wet oxidation process to form an aluminum oxide layer around the oxidation restriction layer; Step 42: Depositing a SiO2 insulating layer by plasma chemical vapor deposition technology, wherein the thickness of the SiO2 insulating layer is greater than the height of the cylindrical platform to protect the side wall of the cylindrical platform; Step 43: Overlay the cylindrical platform using a photolithography + development process to remove the photoresist on the upper surface of the cylindrical platform and retain the photoresist outside the cylindrical platform area to protect the SiO2 insulating layer; Step 44: using a wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical platform, exposing the p-side annular electrode, and then removing all photoresists; Step 45: forming the lead and pad patterns of the p-side electrode layer by using a photolithography + development process; Step 46: Depositing p-side metal by electron beam evaporation or magnetron sputtering; Step 47: stripping the photoresist on the surface of the wafer and the metal thereon by using a stripping process to form a p-side electrode lead and a pad; Step 48: Thinning the n-GaAs substrate to 120 μm using a grinding process; Step 49: polishing the back side of the n-GaAs substrate using a polishing process; Step 50: Depositing metal on the back side of the n-GaAs substrate by electron beam evaporation or magnetron sputtering to form an n-side electrode; Step 51: alloying the n-side electrode and the p-side electrode using a high temperature annealing process to form an ohmic contact with the semiconductor; Step 52: Slice and split to form a single tube or array chip, completing the preparation of GaAs-based VCSEL chip.

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