GaAs-based vertical cavity surface emitting laser with small-size mesa structure and preparation method of GaAs-based vertical cavity surface emitting laser

Abstract

The invention relates to the technical field of semiconductors, and discloses a GaAs-based vertical-cavity surface-emitting laser with a small-size mesa structure and a preparation method thereof.The laser comprises an n-surface electrode layer, a substrate layer, a buffer layer and an n-DBR layer which are sequentially arranged from bottom to top, and an insulating layer located on the periphery is arranged above the n-DBR layer; a lower space layer, a quantum well active region, an upper space layer, a p-oxidation limiting structure layer, a p-DBR layer, a contact layer and a p-surface electrode layer which form a cylindrical mesa are sequentially arranged at the center of the insulating layer from bottom to top; the p-oxidation limiting structure layer comprises a low-refractive-index layer, an oxidation limiting layer and a high-refractive-index layer which are sequentially arranged from bottom to top, an aluminum oxide layer is formed on the periphery of the oxidation limiting layer through an oxidation process, an oxidation hole is formed in an unoxidized area in the center of the oxidation limiting layer, and the difference between the diameter of the cylindrical table board and the diameter of the oxidation hole is smaller than or equal to 15 microns. According to the invention, the threshold current can be reduced and the luminous power can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a GaAs-based vertical cavity surface emitting laser with a small-sized mesa structure and a preparation method thereof. Background Art

[0002] A vertical cavity surface emitting laser (VCSEL) is a semiconductor laser whose light-emitting direction is perpendicular to the device surface. It has advantages such as low threshold, single longitudinal mode, high beam quality, easy arraying, on-chip testability, and low cost, and has been widely used in the fields of intelligent sensing, optical interconnection, optical communication, optical storage, quantum precision measurement, etc.

[0003] The concept of VCSEL was initially proposed by Japanese scientist Iga in 1977. After more than thirty years of development, VCSEL manufacturing technology has long been developed and commercialized on a large scale. Among existing VCSEL products, the most successful one is the GaAs-based VCSEL. Because in GaAs-based materials, the ternary material AlGaAs has a natural lattice match with GaAs and a large refractive index difference, which is easy to prepare a high-quality distributed Bragg reflector (DBR); in addition, the AlGaAs material with a high Al component is easy to oxidize, and an oxidation confinement structure can be prepared through a wet oxidation process, making the oxidation hole diameter much smaller than the VCSEL mesa diameter, significantly reducing the loss of VCSEL and promoting the commercialization process of VCSEL.

[0004] The GaAs-based VCSEL mesa is generally prepared by dry etching technology, and there are a large number of etching damages on the mesa sidewall. During the transmission of photons and carriers, if close to the mesa sidewall, a large amount of absorption loss will occur. In order to reduce this absorption loss, the mesa size of the GaAs-based VCSEL is often much larger than the oxidation hole diameter. For this kind of VCSEL with a large mesa size, the mesa size has no influence on the light field distribution, and the light field is only limited by the oxidation aperture diameter. Since the oxidation confinement layer is very thin, its lateral confinement ability for the light field is weak, and a large number of photons diffuse outside the oxidation hole, reducing the light extraction efficiency and increasing the threshold current.

[0005] Based on the above technical problems, it is necessary to improve the structure of the GaAs-based vertical cavity surface emitting laser to increase the light extraction power of the vertical cavity surface emitting laser and reduce the threshold current. Summary of the Invention

[0006] The technical problems to be solved by the present invention are as follows: 1) The oxidation confinement structure of the GaAs-based vertical cavity surface emitting laser has a weak ability to confine the optical field, and a large number of photons propagate outside the oxidation holes, unable to form an effective optical output; 2) Due to the dissipation of photons, the gain of the VCSEL is reduced, which limits the increase of the output power and the decrease of the threshold current of the vertical cavity surface emitting laser device.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is: A GaAs-based vertical cavity surface emitting laser with a small-size mesa structure, comprising: an n-side electrode layer, a substrate layer, a buffer layer, and an n-DBR layer arranged in sequence from bottom to top. An SiO2 insulating layer is arranged on the periphery above the n-DBR layer. A lower space layer, a quantum well active region, an upper space layer, a p-oxidation confinement structure layer, a p-DBR layer, a contact layer, and a p-side electrode layer are sequentially arranged from bottom to top at the center of the SiO2 insulating layer to form a cylindrical mesa;

[0008] The p-oxidation confinement structure layer includes a p-Al 0.9 GaAs low refractive index layer, a p-Al 0.98 GaAs oxidation confinement layer, and a p-Al z1 GaAs high refractive index layer. An alumina layer is formed on the periphery of the p-Al 0.98 GaAs oxidation confinement layer through an oxidation process. An oxidation hole is formed in the non-oxidized region at the center of the p-Al 0.98 GaAs oxidation confinement layer. z1 represents the Al component in the corresponding material. The diameter difference between the cylindrical mesa and the oxidation hole is less than or equal to 15 μm.

[0009] The range of the diameter difference between the cylindrical mesa and the oxidation hole is 8 - 15 μm.

[0010] The GaAs-based vertical cavity surface emitting laser with a small-size mesa structure has an emission wavelength of any wavelength within the range of 780 nm - 1064 nm;

[0011] The quantum well active region is a multi-period quantum well or a single-period quantum well. The quantum well / barrier material is InGaAlAs / AlGaAs, and the material components are determined according to the emission wavelength of the VCSEL;

[0012] The thicknesses of the lower space layer, the quantum well active region, and the upper space layer satisfy h i is the actual thickness of each layer, n i is the refractive index of each layer, m is a positive integer not greater than 5, and λ represents the emission wavelength of the laser.

[0013] The n-DBR layer is composed of 44 pairs of n-Al z2The GaAs high refractive index layer and n-Al 0.9 are periodically overlapped by the GaAs low refractive index layer; among them, n-Al z2 The thickness of the GaAs high refractive index layer is λ / 4n H –20 nm, and z2 is determined by the formula (1.424 + 1.247z2>1240 / (λ - 50)); n-Al 0.9 The thickness of the GaAs low refractive index layer is λ / 4n L –20 nm; λ is the emission wavelength of the VCSEL, and n H is the refractive index of the high refractive index layer, and n L is the refractive index of the low refractive index layer; on each layer of n-Al z2 above the GaAs high refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al component gradually changes linearly from z2 to 0.9; similarly, on each layer of n-Al 0.9 above the GaAs low refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al component gradually changes linearly from 0.9 to z2.

[0014] In the n-DBR layer, the doping concentration distribution is divided into two parts. The doping concentration of the n-type Al z2 GaAs high refractive index layer and the n-type Al 0.9 GaAs low refractive index layer in the four periods close to the active region is 1×10 18 cm -3 , and the doping concentration of the n-type Al z2 GaAs high refractive index layer and the n-type Al 0.9 GaAs low refractive index layer in the remaining periods is 2×10 18 cm -3 .

[0015] The p-DBR layer is periodically overlapped by 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z3 GaAs high refractive index layer; among them, the thickness of the p-Al z3 GaAs high refractive index layer is λ / 4n H –20 nm, and the thickness of the n-Al 0.9 GaAs low refractive index layer is λ / 4n L –20 nm; on each layer of p-Al z3 above the GaAs high refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al component gradually changes linearly from z3 to 0.9; similarly, on each layer of p-Al 0.9 above the GaAs low refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al component gradually changes linearly from 0.9 to z3; the topmost p-Alz3 Above the GaAs high refractive index layer, a 30-nm AlGaAs transition layer is provided, with the Al component linearly varying from z3 to 0 and the doping concentration linearly varying from 3×10 18 cm -3 to 2×10 19 cm -3 .

[0016] The doping concentration distribution of the p-DBR layer is divided into two parts. The doping concentrations of the p-Al 0.9 GaAs low refractive index layer and the p-Al z3 GaAs high refractive index layer in the 3 periods close to the active region are 1×10 18 cm -3 , and the doping concentrations of the p-Al 0.9 GaAs low refractive index layer and the p-Al z3 GaAs high refractive index layer in the remaining 20 periods are 3×10 18 cm -3 .

[0017] z2 = z3.

[0018] The substrate layer is an n-GaAs substrate with a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si;

[0019] The buffer layer is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si;

[0020] The lower spacer layer is an AlGaAs lower spacer layer, undoped;

[0021] The upper spacer layer is an AlGaAs upper spacer layer, undoped;

[0022] The contact layer is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C;

[0023] The p-side electrode layer is a ring electrode, and the inner diameter of the ring is larger than the diameter of the oxidation hole.

[0024] In addition, the present invention also provides a preparation method of the GaAs-based vertical cavity surface emitting laser with the small-size mesa structure described above, including an epitaxial growth method and a chip preparation method; the epitaxial growth method uses metalorganic chemical vapor deposition technology for epitaxial growth, and includes the following steps:

[0025] Step 1: Select an n-type GaAs substrate with a (001) plane and place it on the graphite tray in the MOCVD reaction chamber;

[0026] Step 2: Under a hydrogen atmosphere, introduce arsine (AsH3), and raise the temperature of the graphite tray to 680 °C under the protection of AsH3 to bake the substrate at high temperature to remove impurities and oxide layers on the substrate surface;

[0027] Step 3: Lower the temperature to 640 °C, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of the GaAs buffer layer by regulating the flow rate of TMGa, control the V / III ratio to 60 by regulating the flow rate of AsH3, and control the doping concentration by regulating the flow rate of SiH4 to grow an n-GaAs buffer layer;

[0028] Step 4: Keep the growth temperature at 640 °C and the V / III ratio at 60, introduce trimethylaluminum (TMAl), and gradually change its flow rate from 0 to the flow rate required for Al z2 GaAs growth to form an AlGaAs transition layer on top of the n-GaAs buffer layer;

[0029] Step 5: Keep the growth temperature at 640 °C and the V / III ratio at 60, keep the flow rates of TMGa and TMAl unchanged, and regulate the flow rate of SiH4 to make the doping concentration 2×10 18 cm -3 to grow the Al z2 GaAs high refractive index layer in the n-DBR;

[0030] Step 6: Keep the growth temperature at 640 °C and the V / III ratio at 60, linearly gradually change the flow rates of TMGa and TMAl to the flow rate required for Al 0.9 GaAs growth to form an AlGaAs transition layer on top of the Al z2 GaAs high refractive index layer;

[0031] Step 7: Keep the growth temperature at 640 °C and the V / III ratio at 60, keep the flow rates of TMGa and TMAl unchanged, and regulate the flow rate of SiH4 to make the doping concentration 2×10 18 cm -3 to grow the Al 0.9 GaAs low refractive index layer in the n-DBR;

[0032] Step 8: Keep the growth temperature at 640 °C and the V / III ratio at 60, linearly gradually change the flow rates of TMGa and TMAl to the flow rate required for Al z2 GaAs growth to form an AlGaAs transition layer on top of the Al 0.9 GaAs low refractive index layer;

[0033] Step 9: Repeat Steps 5 - 8 cyclically to form 40 pairs of n-DBRs with a doping concentration of 2×10 18 cm -3 ;

[0034] Step 10: Regulate the flow rate of SiH4 to a doping concentration of 1×10 18 cm -3 , repeat Steps (5) - (8) for multiple cycles, and finally complete the growth of the n-DBR layer;

[0035] Step 11: Keep the growth temperature at 640 °C and the V / III ratio at 60. Cut off the supply of SiH4, and linearly vary the flow rates of TMGa and TMAl to the flow rates required for the growth of the AlGaAs quantum barrier layer to grow the AlGaAs lower spacer layer;

[0036] Step 12: Keep the growth temperature at 640 °C and the V / III ratio at 60. Keep the flow rates of TMGa and TMAl unchanged, grow the AlGaAs quantum barrier layer, cut off the TMGa and TMAl sources after growth is completed, and pause growth for 5 s;

[0037] Step 13: Keep the growth temperature at 640 °C and the V / III ratio at 60. Introduce the TMGa, TMAl, and TMIn sources, and regulate the flow rates of the TMGa, TMAl, and TMIn sources to make the growth rate of the InGaAlAs quantum well layer 0.2 nm / s to grow the quantum well layer. Cut off the TMGa, TMAl, and TMIn sources after growth is completed, and pause growth for 5 s;

[0038] Step 14: Repeat the growth of the quantum barrier layer and the quantum well layer multiple times to finally generate a quantum well active region with a quantum well period number of n;

[0039] Step 15: Repeat Step 12 to complete the last AlGaAs quantum barrier layer of the quantum well active region;

[0040] Step 16: Keep the growth temperature at 640 °C and the V / III ratio at 60. Introduce the TMGa and TMAl sources, set the initial flow rate to the flow rate required for the growth of the AlGaAs quantum barrier layer, and then linearly vary it to the flow rate required for the growth of Al 0.9 GaAs to form the AlGaAs upper spacer layer 06;

[0041] Step 17: Keep the growth temperature at 640 °C, lower the V / III ratio to 40, keep the flow rates of TMGa and TMAl unchanged, introduce carbon tetrabromide (CBr4) as a C doping source, and regulate the flow rate of CBr4 to a doping concentration of 1×10 18 cm -3 , grow the p-Al 0.9 GaAs low refractive index layer;

[0042] Step 18: Keep the growth temperature at 640 °C, the V / III ratio at 40, switch the TMGa and TMAl flow rates to the Al 0.98 GaAs growth required flow rate, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al 0.98 GaAs oxidation confinement layer;

[0043] Step 19: Keep the growth temperature at 640 °C, the V / III ratio at 40, switch the initial TMGa and TMAl flow rates to the Al 0.9 GaAs growth required flow rate, and then linearly ramp to the Al z1 GaAs growth required flow rate, and grow a 20-nm AlGaAs transition layer;

[0044] Step 20: Keep the growth temperature at 640 °C, the V / III ratio at 40, keep the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al z1 GaAs high refractive index layer 09;

[0045] Step 21: Keep the growth temperature at 640 °C, the V / III ratio at 40, linearly ramp the TMGa and TMAl flow rates to the Al 0.9 GaAs growth required flow rate, form a 20-nm AlGaAs transition layer, and linearly ramp the Al composition from z1 to 0.9;

[0046] Step 22: Keep the growth temperature at 640 °C, the V / III ratio at 40, keep the TMGa and TMAl flow rates unchanged, adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al 0.9 GaAs low refractive index layer in the p-DBR;

[0047] Step 23: Keep the growth temperature at 640 °C, the V / III ratio at 40, linearly ramp the TMGa and TMAl flow rates to the Al z GaAs growth required flow rate, form a 20-nm AlGaAs transition layer, and linearly ramp the Al composition from 0.9 to z3;

[0048] Step 24: Keep the growth temperature at 640 °C, the V / III ratio at 40, keep the TMGa and TMAl flow rates unchanged, adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al z3 GaAs high refractive index layer in the p-DBR;

[0049] Step 25: Repeat Steps 21 - 24 to form 3 pairs of p-DBRs with a doping concentration of 1×10 18 cm -3 ;

[0050] Step 26: Regulate the CBr4 flow rate to a doping concentration of 3×10 18 cm -3 , repeat Steps 21 - 24 to form 20 pairs of p-DBRs with a doping concentration of 3×10 18 cm -3 , completing the growth of the p-DBR;

[0051] Step 27: Gradually decrease the growth temperature linearly from 640 °C to 580 °C, gradually change the TMAl flow rate linearly to 0, gradually change the V / III ratio linearly to 30, and gradually change the CBr4 flow rate linearly to the flow rate required for doping the p+GaAs contact layer, forming an AlGaAs transition layer from the p-DBR to the p+GaAs contact layer, with the Al composition gradually changing linearly from z3 to 0 and the doping concentration gradually changing linearly from 3×10 18 cm -3 linearly to 2×10 19 cm -3 ;

[0052] Step 28: Maintain the growth temperature at 580 °C and the V / III ratio at 30, cut off the TMAl, keep the TMGa and CBr4 flow rates unchanged, and grow the p+GaAs contact layer;

[0053] Step 29: Cut off the TMGa and CBr4, naturally cool down to room temperature, and then cut off the AsH3 to complete the growth of the epitaxial wafer;

[0054] The chip preparation method includes:

[0055] Step 30: Clean the epitaxial wafer using the standard cleaning process for epitaxial wafers;

[0056] Step 31: Use the photolithography + development process to form a circular pattern for the p-side electrode, retain the photoresist outside the circular area of the p-side electrode, and remove the photoresist in the circular area of the p-side electrode;

[0057] Step 32: Deposit the metal layer corresponding to the p-side electrode using the electron beam evaporation or magnetron sputtering process;

[0058] Step 33: Use the lift-off process with glue to strip the metal outside the circular electrode, leaving the metal in the circular electrode area to form the p-side circular electrode;

[0059] Step 34: Use the photolithography + development process to form a pattern of the VCSEL cylindrical mesa on the wafer surface, retain the photoresist in the cylindrical mesa area, and remove the photoresist outside the cylindrical mesa;

[0060] Step 35: Use a dry etching process to etch downward to form a cylindrical mesa, etch until reaching the n-DBR layer, and then remove the photoresist on the cylindrical mesa;

[0061] Step 36: Use a chemical polishing process to treat the sidewall of the cylindrical mesa to eliminate the etching damage on the sidewall;

[0062] Step 37: Use a wet oxidation process to oxidize the p-Al 0.98 GaAs oxidation confinement layer to form oxidation holes;

[0063] Step 38: Use plasma enhanced chemical vapor deposition technology to deposit a SiO2 insulating layer, and the thickness of the SiO2 insulating layer is slightly greater than the height of the cylindrical mesa to protect the sidewall of the cylindrical mesa;

[0064] Step 39: Use a lithography + development process to perform overlay lithography on the cylindrical mesa, remove the photoresist on the upper surface of the cylindrical mesa, and retain the photoresist outside the cylindrical mesa area to protect the SiO2 insulating layer;

[0065] Step 40: Use a wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical mesa to expose the p-plane ring electrode, and then remove all the photoresist;

[0066] Step 41: Use a lithography + development process to form the lead and Pad patterns of the p-plane electrode;

[0067] Step 42: Use electron beam evaporation or magnetron sputtering process to deposit p-plane metal;

[0068] Step 43: Use a lift-off process to strip the photoresist and the metal on it from the wafer surface to form the p-plane electrode lead and Pad;

[0069] Step 44: Use a grinding process to thin the n-GaAs substrate to 120 μm;

[0070] Step 45: Use a polishing process to polish the back surface of the n-GaAs substrate;

[0071] Step 46: Use electron beam evaporation or magnetron sputtering process to deposit metal on the back surface of the n-GaAs substrate to form an n-plane electrode;

[0072] Step 47: Use a high-temperature annealing process to alloy the n-plane electrode and the p-plane electrode to form an ohmic contact with the semiconductor;

[0073] Step 48: Dicing + singulation to form single devices or array chips; complete the preparation of GaAs-based VCSEL chips.

[0074] The present invention has the following beneficial effects compared with the prior art:

[0075] The present invention provides a GaAs-based vertical cavity surface emitting laser with a small-sized mesa structure and a preparation method thereof. A smaller mesa structure is adopted to enhance the optical field confinement ability. Meanwhile, chemical polishing is used to eliminate the etching damage on the mesa sidewalls, so that the optical field is better confined in the oxidation aperture, reducing the threshold current of the GaAs-based VCSEL and increasing the light output power. Description of the Drawings

[0076] Figure 1 It is a schematic structural diagram of a 795nm VCSEL with a small-sized mesa structure provided in Embodiment 1 of the present invention;

[0077] Figure 2 It is a top view of a cylindrical mesa and a ring electrode pattern in Embodiment 1 of the present invention;

[0078] Figure 3 It is a schematic structural diagram of an 850nm VCSEL with a small-sized mesa structure provided in Embodiment 2 of the present invention;

[0079] Figure 4 It is a top view of a cylindrical mesa and a ring electrode pattern in Embodiment 2 of the present invention; Detailed Embodiments

[0080] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0081] Embodiment 1

[0082] Embodiment 1 of the present invention is a 795nm VCSEL with a small-sized mesa structure, and its structure is as shown in the attached Figure 1 figure, including an n-side electrode layer 00, a substrate layer 01, a buffer layer 02, and an n-DBR layer 03 arranged in sequence from bottom to top. An SiO2 insulating layer 13 is arranged on the periphery above the n-DBR layer 03. A lower spatial layer 04, a quantum well active region 05, an upper spatial layer 06, a p-oxidation confinement structure layer, a p-DBR layer 10, a contact layer 11, and a p-side electrode layer 12 that form a cylindrical mesa are arranged in sequence from bottom to top in the center of the SiO2 insulating layer 13. The p-oxidation confinement structure layer includes a p-Al 0.9 GaAs low refractive index layer 07, a p-Al 0.98 GaAs oxidation confinement layer 08, and a p-Al z1GaAs high refractive index layer 09, the p-Al 0.98 An alumina layer is formed around the GaAs oxidation confinement layer 08 through an oxidation process. The p-Al 0.98 An oxidation hole is formed in the unoxidized area at the center of the GaAs oxidation confinement layer 08. Let z1 represent the Al component in the corresponding material. The difference between the diameter of the cylindrical mesa and the diameter of the oxidation hole is less than or equal to 15 μm.

[0083] Specifically, in this embodiment, z1 = 0.22. That is, the p-Al z1 The GaAs high refractive index layer 09 is specifically the p-Al 0.22 GaAs high refractive index layer.

[0084] As Figure 2 shown, in this embodiment, the diameter of the cylindrical mesa is 15 μm, and the diameter of the oxidation hole is 4 μm. Compared with the prior art, where the diameter of the cylindrical mesa is more than 30 μm larger than the oxidation hole, the size of the cylindrical mesa in the present invention is relatively small, so it is a small mesa.

[0085] Specifically, the n-side electrode layer 00 includes a gold layer and a nickel layer arranged from bottom to top, and is located below the thinned and polished substrate layer 01.

[0086] The substrate layer 01 is an n-GaAs substrate, which has undergone a thinning and polishing process, with a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si.

[0087] The buffer layer 02 is an n-GaAs buffer layer, with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si.

[0088] Above the buffer layer 02, a 30-nm AlGaAs transition layer is provided, and the Al component gradually changes linearly from 0 to 0.22.

[0089] The n-DBR layer 03 is formed by periodically overlapping 44 pairs of n-Al z2 GaAs high refractive index layer and n-Al 0.9 GaAs low refractive index layer; among them, the thickness of the n-Al z2 GaAs high refractive index layer is λ / 4n H –20 nm, and z2 is determined by the formula (1.424 + 1.247z2 > 1240 / (λ - 50)); the thickness of the n-Al 0.9 GaAs low refractive index layer is λ / 4n L –20 nm; λ is the emission wavelength of the VCSEL, and n H is the refractive index of the high refractive index layer, nL is the refractive index of the low refractive index layer; each layer of n-Al z2 Above the GaAs high refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition linearly changes from z2 to 0.9; similarly, each layer of n-Al 0.9 Above the GaAs low refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition linearly changes from 0.9 to z2.

[0090] Specifically, in this embodiment, z2 = 0.22.

[0091] Furthermore, in the n-DBR layer 03, the doping concentration distribution is divided into two parts. The doping concentration of the four periods of n-type Al z2 GaAs high refractive index layer and n-type Al 0.9 GaAs low refractive index layer close to the active region is 1×10 18 cm -3 , and the doping concentration of the n-type Al z2 GaAs high refractive index layer and n-type Al 0.9 GaAs low refractive index layer in the remaining periods is 2×10 18 cm -3 ; doped with Si.

[0092] The lower space layer 04 is an AlGaAs lower space layer with a thickness of 93 nm, and the Al composition linearly changes from 0.9 to 0.3, without doping;

[0093] The quantum well active region 05 is a multi-period quantum well or a single-period quantum well, and the quantum well / barrier material is InGaAlAs / AlGaAs, and the material composition is determined according to the emission wavelength of the VCSEL; specifically, in this embodiment, the quantum well active region 05 is composed of 3.5 pairs of In 0.125 Ga 0.735 Al 0.14 As / Al 0.3 GaAs quantum wells. The In 0.125 Ga 0.735 Al 0.14 As quantum well layer has a thickness of 6.8 nm, the Al 0.3 GaAs quantum barrier layer has a thickness of 8 nm, the number of quantum barrier layers is 4, and the number of quantum well layers is 3.

[0094] The upper space layer 06 is an AlGaAs upper space layer with a thickness of 93 nm, and the Al composition linearly changes from 0.3 to 0.9.

[0095] The p-Al 0.9 GaAs low refractive index layer 07 has a thickness of 64.4 nm and a doping concentration of 1×10 18 cm-3 , doped with C.

[0096] The p-Al 0.98 GaAs oxidation confinement layer 08 has a thickness of 30 nm and a doping concentration of 1×10 18 cm -3 , doped with C.

[0097] The p-Al 0.98 GaAs oxidation confinement layer 08 is provided with a 20-nm AlGaAs transition layer on top, and the Al composition linearly varies from 0.9 to 0.22.

[0098] The p-Al 0.22 GaAs high refractive index layer 09 has a thickness of 11.95 nm and a doping concentration of 1×10 18 cm -3 , doped with C;

[0099] The p-Al 0.22 GaAs high refractive index layer 09 is provided with a 20-nm AlGaAs transition layer on top, and the Al composition linearly varies from 0.22 to 0.9, with a doping concentration of 1×10 18 cm -3 , doped with C.

[0100] The p-DBR layer 10 is periodically formed by overlapping 23 pairs of p-Al 0.9 GaAs low refractive index layer and p-Al z3 GaAs high refractive index layer; among them, the p-Al z3 GaAs high refractive index layer has a thickness of λ / 4n H –20 nm, and the n-Al 0.9 GaAs low refractive index layer has a thickness of λ / 4n L –20 nm; on top of each p-Al z3 GaAs high refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition linearly varies from z3 to 0.9; similarly, on top of each p-Al 0.9 GaAs low refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition linearly varies from 0.9 to z3; on top of the topmost p-Al z3 GaAs high refractive index layer, a 30-nm AlGaAs transition layer is provided, and the Al composition linearly varies from z3 to 0, and the doping concentration linearly varies from 3×10 18 cm -3 to 2×10 19 cm -3 . Specifically, among them, z3 = 0.22.

[0101] The doping concentration distribution of the p-DBR layer is divided into two parts. For the 3 periods of p-Al 0.9 GaAs low refractive index layer and p-Al z3 GaAs high refractive index layer close to the active region, the doping concentration is 1×10 18 cm -3 . For the remaining 20 periods of p-Al 0.9 GaAs low refractive index layer and p-Al z3 GaAs high refractive index layer, the doping concentration is 3×10 18 cm -3 .

[0102] Furthermore, in the p-DBR layer, the thickness of the Al 0.9 GaAs low refractive index layer is 44.4 nm, and the thickness of the Al 0.22 GaAs high refractive index layer is 36.1 nm. The doping concentration of the 3 pairs of p-DBR close to the active region is 1×10 18 cm -3 . The doping concentration of the 20 pairs of p-DBR above it is 3×10 18 cm -3 , doped with C.

[0103] The contact layer 11 is a p+ GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C;

[0104] Specifically, the p-side electrode layer 12 is an annular electrode. The inner diameter of the ring is equal to the diameter of the oxidation hole. The outer diameter of the ring is smaller than the diameter of the mesa. Specifically, in this embodiment, the inner diameter of the annular electrode of the p-side electrode layer 12 is 5 μm, and the outer diameter is 14 μm, which is composed of titanium, platinum, and gold.

[0105] In this embodiment, the 795 nm VCSEL with a small-size mesa structure has, above the n-DBR layer 03, a cylindrical mesa with a diameter of 15 μm, and the p-side electrode is located in the center of the upper surface of the cylindrical mesa.

[0106] For the 795 nm VCSEL with a small-size mesa structure, the periphery of the oxidation confinement layer is alumina, and only the middle oxidation hole region is Al 0.98 GaAs material. The center of the oxidation hole, the center of the p-side annular electrode, and the central axis of the cylindrical mesa coincide.

[0107] Embodiment 2

[0108] Embodiment 2 of the present invention is an 850 nm VCSEL with a small-size mesa structure, and its structure is as shown in Figure 3As shown, it includes an n-side electrode layer 00, a substrate layer 01, a buffer layer 02, and an n-DBR layer 03 arranged successively from bottom to top. Above the n-DBR layer 03, there is a SiO2 insulating layer 13 located on the outer periphery. From bottom to top in the center of the SiO2 insulating layer 13, there are arranged a lower spatial layer 04 forming a cylindrical mesa, a quantum well active region 05, an upper spatial layer 06, a p-oxidation confinement structure layer, a p-DBR layer 10, a contact layer 11, and a p-side electrode layer 12; the p-oxidation confinement structure layer includes a p-Al 0.9 GaAs low refractive index layer 07, a p-Al 0.98 GaAs oxidation confinement layer 08, and a p-Al z1 GaAs high refractive index layer 09 arranged successively from bottom to top. An alumina layer is formed on the outer periphery of the p-Al 0.98 GaAs oxidation confinement layer 08 through an oxidation process. An oxidation hole is formed in the unoxidized region at the center of the p-Al 0.98 GaAs oxidation confinement layer 08. z1 represents the Al component in the corresponding material. The diameter difference between the cylindrical mesa and the oxidation hole is less than or equal to 15 μm.

[0109] Specifically, as Figure 4 shown, in this embodiment, the diameter of the oxidation hole is 8 μm, and the diameter of the cylindrical mesa is 20 μm.

[0110] Specifically, in this embodiment, z1 = 0.2. That is, the p-Al z1 GaAs high refractive index layer 09 is specifically a p-Al 0.2 GaAs high refractive index layer.

[0111] Specifically, the n-side electrode layer 00 includes a gold layer and a nickel layer arranged from bottom to top, located below the thinned and polished n-GaAs substrate.

[0112] The substrate layer 01 is an n-GaAs substrate, which has undergone a thinning and polishing process, with a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si.

[0113] The buffer layer 02 is an n-GaAs buffer layer, with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si.

[0114] Above the buffer layer 02, there is arranged a 30-nm AlGaAs transition layer, and the Al component gradually changes linearly from 0 to 0.2;

[0115] The n-DBR layer 03 is composed of 44 pairs of Al z2 GaAs high refractive index layers and Al 0.9It is formed by periodically overlapping GaAs low-refractive-index layers. Specifically, in this embodiment, z2 = 0.2.

[0116] Specifically, in this embodiment, Al z2 The thickness of the AlGaAs high-refractive-index layer is 38.3 nm, and Al 0.9 The thickness of the AlGaAs low-refractive-index layer is 48.5 nm. For each layer of Al z2 A 20-nm AlGaAs transition layer is provided on each layer of AlGaAs high-refractive-index layer, and the Al composition of the transition layer gradually changes linearly from 0.2 to 0.9; similarly, for each layer of Al 0.9 A 20-nm AlGaAs transition layer is provided on AlGaAs, and the Al composition gradually changes linearly from 0.9 to 0.2.

[0117] Further, in the n-DBR layer 03, the doping concentration distribution is divided into two parts. The doping concentrations of the n-type Al z2 GaAs high-refractive-index layer and the n-type Al 0.9 GaAs low-refractive-index layer in the four periods close to the active region are 1×10 18 cm -3 , and the doping concentrations of the n-type Al z2 GaAs high-refractive-index layer and the n-type Al 0.9 GaAs low-refractive-index layer in the remaining periods are 2×10 18 cm -3 ; Doped with Si.

[0118] The lower spacer layer 04 is an AlGaAs lower spacer layer with a thickness of 106 nm, and the Al composition gradually changes linearly from 0.9 to 0.2, without doping.

[0119] The quantum well active region 05 is composed of 3.5 pairs of In 0.05 GaAs / Al 0.2 GaAs quantum wells. The thickness of the In 0.05 GaAs quantum well layer is 5 nm, and the thickness of the Al 0.2 GaAs quantum barrier layer is 6 nm. The number of quantum barrier layers is 4, and the number of quantum well layers is 3.

[0120] The upper spacer layer 06 is an AlGaAs upper spacer layer with a thickness of 106 nm, and the Al composition gradually changes linearly from 0.2 to 0.9;

[0121] The p-Al 0.9 GaAs low-refractive-index layer 07 has a thickness of 68.5 nm and a doping concentration of 1×10 18 cm -3 , doped with C;

[0122] The p-Al 0.98The GaAs oxidation confinement layer 08 has a thickness of 30 nm and a doping concentration of 1×10 18 cm -3 , doped with C;

[0123] On the p-Al 0.98 GaAs oxidation confinement layer 08, there is a 20-nm AlGaAs transition layer, and the Al composition linearly changes from 0.9 to 0.2;

[0124] On the p-Al 0.2 GaAs high refractive index layer 09, with a thickness of 13.2 nm and a doping concentration of 1×10 18 cm -3 , doped with C;

[0125] On the p-Al 0.2 GaAs high refractive index layer 09, there is a 20-nm AlGaAs transition layer, and the Al composition linearly changes from 0.2 to 0.9, with a doping concentration of 1×10 18 cm -3 , doped with C.

[0126] The p-DBR layer 10 is composed of 23 pairs of p-Al 0.9 GaAs low refractive index layers and p-Al z3 GaAs high refractive index layers overlapping periodically.

[0127] Specifically, z3 = 0.2. Among them, the p-Al 0.9 GaAs low refractive index layer has a thickness of 48.5 nm, and the p-Al z3 GaAs high refractive index layer has a thickness of 38.3 nm. The doping concentration of the 3 pairs of p-DBRs near the active region is 1×10 18 cm -3 , and the doping concentration of the 20 pairs of p-DBRs above it is 3×10 18 cm -3 , doped with C.

[0128] Specifically, in the p-DBR layer 10, on each layer of Al 0.9 GaAs low refractive index layer, there is a 20-nm AlGaAs transition layer, and the Al composition linearly changes from 0.9 to 0.2; Similarly, on each layer of Al 0.2 GaAs high refractive index layer, there is an AlGaAs transition layer, and the Al composition linearly changes from 0.2 to 0.9; In particular, the AlGaAs transition layer on the topmost layer of Al 0.2 GaAs high refractive index layer, the Al composition linearly changes from 0.2 to 0, with a thickness of 30 nm and a doping concentration from 3×10 18 cm -3Linear gradient to 2×10 19 cm -3 ;

[0129] The contact layer 11 is a p+ GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C;

[0130] The p-side electrode layer 12 is an annular electrode with an inner diameter of 10 μm and an outer diameter of 18 μm, which consists of a titanium layer, a platinum layer, and a gold layer arranged in sequence from bottom to top.

[0131] The 850 nm VCSEL with a small-size mesa structure in this embodiment has a cylindrical mesa with a diameter of 20 μm above the n-DBR layer, and the p-side electrode is located at the center of the upper surface of the cylindrical mesa.

[0132] For the 850 nm VCSEL with a small-size mesa structure, the periphery of the oxidation confinement layer is alumina, and only the middle oxidation hole region is made of Al 0.98 GaAs material, and the centers of the oxidation hole, the p-side annular electrode, and the central axis of the cylindrical mesa coincide.

[0133] Example 3

[0134] Embodiment 3 of the present invention provides a preparation method for a vertical cavity surface emitting laser as described in Embodiment 1 and Embodiment 2, which includes two major parts: an epitaxial growth method and a chip preparation method.

[0135] Among them, the epitaxial growth method uses metalorganic chemical vapor deposition (MOCVD) technology for epitaxial growth, which specifically includes the following steps:

[0136] (1) Select an n-type GaAs substrate 01 with a (001) plane and place it on the graphite tray in the MOCVD reaction chamber;

[0137] (2) Under a hydrogen atmosphere, introduce arsine (AsH3), and raise the temperature of the graphite tray to 680 °C under the protection of AsH3 to bake the impurities and oxide layer on the substrate surface at high temperature;

[0138] (3) Lower the temperature to 640 °C, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of the GaAs buffer layer by regulating the flow rate of TMGa, control the V / III ratio to 60 by regulating the flow rate of AsH3, and control the doping concentration by regulating the flow rate of SiH4 to grow an n-GaAs buffer layer;

[0139] (4) Keep the growth temperature at 640 °C and the V / III ratio at 60, introduce trimethylaluminum (TMAl), and gradually change its flow rate from 0 to Al 0.22Flow rates required for GaAs growth to form an AlGaAs transition layer on top of the n-GaAs buffer layer;

[0140] (5) Keep the growth temperature at 640 °C, the V / III ratio at 60, the flow rates of TMGa and TMAl unchanged, and regulate the flow rate of SiH4 to make the doping concentration 2×10 18 cm -3 , and grow the Al z2 GaAs high refractive index layer in the n-DBR;

[0141] (6) Keep the growth temperature at 640 °C, the V / III ratio at 60, and linearly vary the flow rates of TMGa and TMAl to the flow rates required for Al 0.9 GaAs growth to form an AlGaAs transition layer on top of the Al z2 GaAs high refractive index layer;

[0142] (7) Keep the growth temperature at 640 °C, the V / III ratio at 60, the flow rates of TMGa and TMAl unchanged, and regulate the flow rate of SiH4 to make the doping concentration 2×10 18 cm -3 , and grow the Al 0.9 GaAs low refractive index layer in the n-DBR;

[0143] (8) Keep the growth temperature at 640 °C, the V / III ratio at 60, and linearly vary the flow rates of TMGa and TMAl to the flow rates required for Al z2 GaAs growth to form an AlGaAs transition layer on top of the Al 0.9 GaAs low refractive index layer;

[0144] (9) Repeat steps (5) - (8) 40 times to form 40 pairs of n-DBRs with a doping concentration of 2×10 18 cm -3 ;

[0145] (10) Regulate the flow rate of SiH4 to make the doping concentration 1×10 18 cm -3 , and repeat steps (5) - (8) 4 times to form 4 pairs of n-DBRs with a doping concentration of 1×10 18 cm -3 ;

[0146] (15) Keep the growth temperature at 640 °C, the V / III ratio at 60, and linearly vary the flow rates of TMGa and TMAl to the flow rates required for Al 0.3 GaAs growth, cut off the supply of SiH4, and grow the AlGaAs lower space layer 04;

[0147] (16) Maintain the growth temperature at 640 °C, the V / III ratio at 60, keep the TMGa and TMAl flow rates unchanged, and grow an 8-nm Al 0.3 GaAs quantum barrier layer. After growth is completed, cut off the TMGa and TMAl sources and pause growth for 5 s;

[0148] (17) Maintain the growth temperature at 640 °C, the V / III ratio at 60, introduce the TMGa, TMAl, and TMIn sources, and adjust the flow rates of the TMGa, TMAl, and TMIn sources to make the growth rate of the In 0.125 Ga 0.735 Al 0.14 As quantum well layer 0.2 nm / s, and grow a 6.8-nm In 0.125 Ga 0.735 Al 0.14 As quantum well layer. After growth is completed, cut off the TMGa, TMAl, and TMIn sources and pause growth for 5 s;

[0149] (18) Repeat steps (16) and (17) three cycles to form a 3-period In 0.125 Ga 0.735 Al 0.14 As / Al 0.3 GaAs multi-quantum well active region 05;

[0150] (19) Repeat step (16) to complete the last layer of the Al 0.3 GaAs quantum barrier layer;

[0151] (20) Maintain the growth temperature at 640 °C, the V / III ratio at 60, introduce the TMGa and TMAl sources, set the initial flow rate to the flow rate required for Al 0.3 GaAs growth, and then linearly taper to the flow rate required for Al 0.9 GaAs growth to form the AlGaAs upper spacer layer 06;

[0152] (21) Maintain the growth temperature at 640 °C, lower the V / III ratio to 40, keep the TMGa and TMAl flow rates unchanged, introduce carbon tetrabromide (CBr4) as a C doping source, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al 0.9 GaAs low refractive index layer 07;

[0153] (22) Maintain the growth temperature at 640 °C, the V / III ratio at 40, switch the TMGa and TMAl flow rates to the flow rate required for Al 0.98 GaAs growth, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3, grow a 30-nm p-Al 0.98 GaAs oxidation confinement layer 08;

[0154] (23) Maintain the growth temperature at 640 °C, the V / III ratio at 40, and switch the initial flow rates of TMGa and TMAl to the flow rates required for Al 0.9 GaAs growth, and then linearly ramp to the flow rates required for Al z1 GaAs growth, and grow a 20-nm AlGaAs transition layer;

[0155] (24) Maintain the growth temperature at 640 °C, the V / III ratio at 40, keep the flow rates of TMGa and TMAl unchanged, and adjust the flow rate of CBr4 to make the doping concentration 1×10 18 cm -3 , and grow a p-Al z1 GaAs high refractive index layer 09;

[0156] (25) Maintain the growth temperature at 640 °C, the V / III ratio at 40, and linearly ramp the flow rates of TMGa and TMAl to the flow rates required for Al 0.9 GaAs growth, form a 20-nm AlGaAs transition layer, and linearly ramp the Al composition from z1 to 0.9;

[0157] (26) Maintain the growth temperature at 640 °C, the V / III ratio at 40, keep the flow rates of TMGa and TMAl unchanged, and adjust the flow rate of CBr4 to make the doping concentration 1×10 18 cm -3 , and grow a p-Al 0.9 GaAs low refractive index layer in the p-DBR;

[0158] (27) Maintain the growth temperature at 640 °C, the V / III ratio at 40, and linearly ramp the flow rates of TMGa and TMAl to the flow rates required for Al z3 GaAs growth, form a 20-nm AlGaAs transition layer, and linearly ramp the Al composition from 0.9 to z3;

[0159] (28) Maintain the growth temperature at 640 °C, the V / III ratio at 40, keep the flow rates of TMGa and TMAl unchanged, and adjust the flow rate of CBr4 to make the doping concentration 1×10 18 cm -3 , and grow a p-Al z3 GaAs high refractive index layer in the p-DBR;

[0160] (29) Repeat steps (25) to (28) three cycles to form three pairs of p-DBR with a doping concentration of 1×10 18 cm -3 ;

[0161] (30) Adjust the CBr4 flow rate to make the doping concentration 3×10 18 cm -3 , repeat steps (25) to (28) for 20 cycles to form 20 pairs of p-DBR with a doping concentration of 3×10 18 cm -3 , and complete the growth of p-DBR 10;

[0162] (31) Gradually decrease the growth temperature linearly from 640 °C to 580 °C, gradually change the TMAl flow rate linearly to 0, gradually change the V / III ratio linearly to 30, and gradually change the CBr4 flow rate linearly to the flow rate required for doping the p+GaAs contact layer to form an AlGaAs transition layer from p-DBR to p+GaAs contact layer. The Al component gradually changes linearly from z3 to 0, and the doping concentration gradually changes linearly from 3×10 18 cm -3 to 2×10 19 cm -3 ;

[0163] (32) Keep the growth temperature at 580 °C, the V / III ratio at 30, cut off TMAl, and keep the TMGa and CBr4 flow rates unchanged to grow the p+GaAs contact layer 11;

[0164] (33) Cut off TMGa and CBr4, cool down to room temperature naturally, and then cut off AsH3 to complete the growth of the epitaxial wafer.

[0165] The chip preparation method specifically includes the following steps:

[0166] (34) Clean the epitaxial wafer using the standard cleaning process for epitaxial wafers;

[0167] (35) Use the photolithography + development process to form the pattern of the p-side ring electrode, retain the photoresist outside the p-side ring electrode area, and remove the photoresist in the p-side ring electrode area;

[0168] (36) Deposit the p-side metal using the electron beam evaporation or magnetron sputtering process;

[0169] (37) Use the lift-off process to remove the metal outside the glass ring electrode, leaving the metal in the ring electrode area to form the p-side ring electrode 12;

[0170] (38) Use the photolithography + development process to form the pattern of the VCSEL cylindrical mesa on the wafer surface, retain the photoresist in the cylindrical mesa area, and remove the photoresist outside the cylindrical mesa;

[0171] (39) Use the dry etching process to etch out the cylindrical mesa, etch until reaching the n-DBR, expose the side of the p-Al 0.98 GaAs oxidation confinement layer, and then remove the photoresist on the cylindrical mesa;

[0172] (40) Treat the sidewall of the cylindrical mesa by chemical polishing process to eliminate the etching damage on the sidewall.

[0173] (41) Oxidize the two layers of oxidation confinement layers by wet oxidation process to form symmetric oxidation holes with a diameter of 4 μm.

[0174] (42) Deposit a SiO2 insulating layer by plasma enhanced chemical vapor deposition (PECVD) technology. The thickness of the insulating layer is slightly greater than the height of the cylindrical mesa to protect the sidewall of the cylindrical mesa.

[0175] (43) Perform overlay etching on the cylindrical mesa by photolithography + development process, remove the photoresist on the upper surface of the cylindrical mesa, and retain the photoresist outside the cylindrical mesa area to protect the SiO2 insulating layer.

[0176] (44) Remove the SiO2 insulating layer on the upper surface of the cylindrical mesa by wet etching process to expose the p - surface ring electrode, and then remove all the photoresist.

[0177] (45) Form the lead and Pad patterns of the p - surface electrode by photolithography + development process.

[0178] (46) Deposit p - surface metal by electron beam evaporation or magnetron sputtering process.

[0179] (47) Strip the photoresist and the metal on it on the wafer surface by lift - off process to form the p - surface electrode lead and Pad.

[0180] (48) Thinning the n - GaAs substrate to 120 μm by grinding process.

[0181] (49) Polish the back surface of the n - GaAs substrate by polishing process.

[0182] (50) Deposit metal on the back surface of the n - GaAs substrate by electron beam evaporation or magnetron sputtering process to form the n - surface electrode 00.

[0183] (51) Alloy the n - surface electrode and the p - surface electrode by high - temperature annealing process to form ohmic contact with the semiconductor.

[0184] (52) Saw + Break the wafer to form single - tube or array chips.

[0185] (53) Complete the preparation of GaAs - based VCSEL chips.

[0186] The present invention provides a GaAs-based vertical cavity surface emitting laser with a small-size mesa structure and a preparation method thereof. A small-size mesa structure is adopted to enhance the optical field confinement, and chemical polishing is used to eliminate the etching damage on the mesa sidewalls, so that the optical field is better confined in the oxidation aperture, reducing the threshold current and increasing the light output power.

[0187] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GaAs-based vertical cavity surface emitting laser with a small-size mesa structure, characterized in that, Including: An n-side electrode layer, a substrate layer, a buffer layer, and an n-DBR layer are sequentially arranged from bottom to top. An SiO2 insulating layer is disposed above the n-DBR layer at the periphery. From bottom to top in the center of the SiO2 insulating layer, a lower spatial layer forming a cylindrical mesa, a quantum well active region, an upper spatial layer, a p-oxidation confinement structure layer, a p-DBR layer, a contact layer, and a p-side electrode layer are sequentially arranged; The p-oxidation confinement structure layer includes a p-Al 0.9 GaAs low refractive index layer, a p-Al 0.98 GaAs oxidation confinement layer, and a p-Al z1 GaAs high refractive index layer. An alumina layer is formed by an oxidation process on the outer periphery of the p-Al 0.98 GaAs oxidation confinement layer. An oxidation hole is formed in the unoxidized area at the center of the p-Al 0.98 GaAs oxidation confinement layer. Let z1 represent the Al component in the corresponding material. The difference between the diameter of the cylindrical mesa and the diameter of the oxidation hole is less than or equal to 15 μm.

2. The GaAs-based vertical cavity surface emitting laser with a small-sized mesa structure according to claim 1, wherein The range of the difference between the diameter of the cylindrical mesa and the diameter of the oxidation hole is 8 - 15 μm.

3. The GaAs-based vertical cavity surface emitting laser with a small-size mesa structure according to claim 1, characterized in that, Its emission wavelength is any wavelength within the range of 780 nm to 1064 nm; The quantum well active region is a multi-period quantum well or a single-period quantum well. The quantum well / barrier material is InGaAlAs / AlGaAs, and the material composition is determined according to the emission wavelength of the VCSEL; The thicknesses of the lower spatial layer, the quantum well active region, and the upper spatial layer satisfy h i is the actual thickness of each layer, and n i is the refractive index of each layer, m is a positive integer not greater than 5, and λ represents the emission wavelength of the laser.

4. A GaAs-based vertical cavity surface emitting laser with a small-size mesa structure according to claim 1, characterized in that The n-DBR layer consists of 44 pairs of n-Al z2 GaAs high refractive index layers and n-Al 0.9 GaAs low refractive index layers that overlap periodically; among them, the thickness of the n-Al z2 GaAs high refractive index layer is λ / 4n H –20 nm, and z2 is determined by the formula (1.424 + 1.247z2 > 1240 / (λ - 50)); the thickness of the n-Al 0.9 GaAs low refractive index layer is λ / 4n L –20 nm; λ is the emission wavelength of the VCSEL, n H is the refractive index of the high refractive index layer, and n L is the refractive index of the low refractive index layer; on top of each n-Al z2 GaAs high refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition gradually changes linearly from z2 to 0.9; similarly, on top of each n-Al 0.9 GaAs low refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition gradually changes linearly from 0.9 to z2.

5. The GaAs-based vertical cavity surface emitting laser with a small-size mesa structure according to claim 4, characterized in that, In the n-DBR layer, the doping concentration distribution is divided into two parts. The doping concentrations of the four periods of n-type Al z2 GaAs high refractive index layers and n-type Al 0.9 GaAs low refractive index layers close to the active region are 1×10 18 cm -3 . The doping concentrations of the n-type Al z2 GaAs high refractive index layers and n-type Al 0.9 GaAs low refractive index layers in the remaining periods are 2×10 18 cm -3 .

6. The GaAs-based vertical cavity surface emitting laser with a small-size mesa structure according to claim 4, characterized in that, The p-DBR layer is formed by periodically overlapping 23 pairs of p-Al 0.9 GaAs low refractive index layers and p-Al z3 GaAs high refractive index layers; among them, the thickness of the p-Al z3 GaAs high refractive index layer is λ / 4n H –20 nm, and the thickness of the n-Al 0.9 GaAs low refractive index layer is λ / 4n L –20 nm; on top of each p-Al z3 GaAs high refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition gradually changes linearly from z3 to 0.9; similarly, on top of each p-Al 0.9 GaAs low refractive index layer, a 20-nm AlGaAs transition layer is provided, and the Al composition gradually changes linearly from 0.9 to z3; on top of the uppermost p-Al z3 GaAs high refractive index layer, a 30-nm AlGaAs transition layer is provided, and the Al composition gradually changes linearly from z3 to 0, and the doping concentration gradually changes linearly from 3×10 18 cm -3 to 2×10 19 cm -3 .

7. The GaAs-based vertical cavity surface emitting laser with a small-sized mesa structure according to claim 6, characterized in that The doping concentration distribution of the p-DBR layer is divided into two parts. The doping concentrations of the p-Al 0.9 GaAs low refractive index layers and the p-Al z3 GaAs high refractive index layers in the 3 periods close to the active region are 1×10 18 cm -3 . The doping concentrations of the p-Al 0.9 GaAs low refractive index layers and the p-Al z3 GaAs high refractive index layers in the remaining 20 periods are 3×10 18 cm -3 .

8. A GaAs-based vertical cavity surface emitting laser with a small-size mesa structure according to claim 6, characterized in that, z2 = z3.

9. The GaAs-based vertical cavity surface emitting laser with a small-sized mesa structure according to claim 1, characterized in that The substrate layer is an n-GaAs substrate with a thickness of 120 μm and a doping concentration of 2×10 18 cm -3 , doped with Si; The buffer layer is an n-GaAs buffer layer with a thickness of 150 nm and a doping concentration of 2×10 18 cm -3 , doped with Si; The lower spatial layer is an undoped AlGaAs lower spatial layer; The upper spatial layer is an undoped AlGaAs upper spatial layer; The contact layer is a p-GaAs contact layer with a thickness of 100 nm and a doping concentration of 2×10 19 cm -3 , doped with C; The p-side electrode layer is an annular electrode, and the inner diameter of the annulus is greater than the diameter of the oxidation hole.

10. The preparation method of a GaAs-based vertical cavity surface emitting laser with a small-size mesa structure according to any one of claims 1 to 9, characterized in that, Including an epitaxial growth method and a chip preparation method; the epitaxial growth method uses metalorganic chemical vapor deposition technology for epitaxial growth, including the following steps: Step 1: Select an n-type GaAs substrate with a (001) plane and place it on a graphite tray in the MOCVD reaction chamber; Step 2: In a hydrogen atmosphere, introduce arsine (AsH3), and raise the temperature of the graphite tray to 680 °C under the protection of AsH3 to bake the substrate surface at a high temperature to remove impurities and oxide layers; Step 3: Lower the temperature to 640 °C, introduce trimethylgallium (TMGa) and silane (SiH4), control the growth rate of the GaAs buffer layer by regulating the flow rate of TMGa, control the V / III ratio to 60 by regulating the flow rate of AsH3, and control the doping concentration by regulating the flow rate of SiH4 to grow an n-GaAs buffer layer; Step 4: Maintain the growth temperature at 640 °C, the V / III ratio at 60, introduce trimethylaluminum (TMAl), and gradually vary its flow rate from 0 to the flow rate required for Al z2 GaAs growth to form an AlGaAs transition layer on top of the n-GaAs buffer layer; Step 5: Keep the growth temperature at 640 °C, the V / III ratio at 60, the TMGa and TMAl flow rates unchanged, and regulate the SiH4 flow rate to make the doping concentration 2×10 18 cm -3 , and grow the Al z2 GaAs high refractive index layer in the n-DBR; Step 6: Maintain the growth temperature at 640 °C, the V / III ratio at 60, and linearly ramp the TMGa and TMAl flow rates to the Al 0.9 GaAs growth required flow rate to form Al z2 AlGaAs transition layer on top of the GaAs high refractive index layer; Step 7: Keep the growth temperature at 640 °C, the V / III ratio at 60, the flow rates of TMGa and TMAl unchanged, and regulate the flow rate of SiH4 to make the doping concentration 2×10 18 cm -3 , and grow the Al 0.9 GaAs low refractive index layer in the n-DBR; Step 8: Maintain the growth temperature at 640 °C, the V / III ratio at 60, and linearly ramp the TMGa and TMAl flow rates to the Al z2 GaAs growth required flow rate to form Al 0.9 AlGaAs transition layer on top of the GaAs low refractive index layer; Step 9: Repeat steps 5 to 8 in a loop to form 40 pairs of n-DBRs with a doping concentration of 2×10 18 cm -3 ; Step 10: Adjust the flow rate of SiH4 to make the doping concentration 1×10 18 cm -3 , repeat steps (5)-(8) for multiple cycles, and finally complete the growth of the n-DBR layer; Step 11: Keep the growth temperature at 640 °C and the V / III ratio at 60, cut off the supply of SiH4, and linearly change the flow rates of TMGa and TMAl to the flow rates required for growing the AlGaAs quantum barrier layer to grow the AlGaAs lower spatial layer; Step 12: Keep the growth temperature at 640 °C and the V / III ratio at 60, keep the flow rates of TMGa and TMAl unchanged, grow the AlGaAs quantum barrier layer, cut off the TMGa and TMAl sources after growth is completed, and pause growth for 5 s; Step 13: Keep the growth temperature at 640 °C and the V / III ratio at 60, introduce TMGa, TMAl, and TMIn sources, and make the growth rate of the InGaAlAs quantum well layer 0.2 nm / s by regulating the flow rates of the TMGa, TMAl, and TMIn sources to grow the quantum well layer. Cut off the TMGa, TMAl, and TMIn sources after growth is completed, and pause growth for 5 s; Step 14: Repeat the growth of the quantum barrier layer and the quantum well layer multiple times to finally generate a quantum well active region with n quantum well periods; Step 15: Repeat Step 12 to complete the last AlGaAs quantum barrier layer of the quantum well active region; Step 16: Maintain the growth temperature at 640 °C and the V / III ratio at 60. Introduce TMGa and TMAl sources, with the initial flow rate set to the flow rate required for the growth of the AlGaAs quantum barrier layer, and then linearly ramp it up to the flow rate required for the growth of 0.9 0.9 AlGaAs to form the upper spacer layer 06 of AlGaAs; Step 17: Maintain the growth temperature at 640 °C, lower the V / III ratio to 40, keep the TMGa and TMAl flow rates unchanged, introduce carbon tetrabromide (CBr4) as the C doping source, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al 0.9 GaAs low refractive index layer; Step 18: Maintain the growth temperature at 640 °C, the V / III ratio at 40, and switch the TMGa and TMAl flow rates to the Al 0.98 GaAs growth required flow rate, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al 0.98 GaAs oxidation confinement layer; Step 19: Maintain the growth temperature at 640 °C, the V / III ratio at 40, and switch the initial flow rates of TMGa and TMAl to the flow rates required for Al 0.9 GaAs growth, and then gradually change linearly to the flow rates required for Al z1 GaAs growth to grow a 20-nm-thick AlGaAs transition layer; Step 20: Maintain the growth temperature at 640 °C, the V / III ratio at 40, keep the TMGa and TMAl flow rates unchanged, and adjust the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al z1 GaAs high refractive index layer 09; Step 21: Maintain the growth temperature at 640 °C, the V / III ratio at 40, and linearly ramp the TMGa and TMAl flow rates to the flow rates required for GaAs growth to form a 20-nm AlGaAs transition layer with the Al composition linearly ramping from z1 to 0.9; 0.9 ​ Step 22: Maintain the growth temperature at 640 °C, the V / III ratio at 40, keep the TMGa and TMAl flow rates unchanged, and regulate the CBr4 flow rate to make the doping concentration 1×10 18 cm -3 , and grow the p-Al 0.9 GaAs low refractive index layer in the p-DBR; Step 23: Maintain the growth temperature at 640 °C, the V / III ratio at 40, and linearly vary the TMGa and TMAl fluxes to the Al z flux required for GaAs growth to form a 20-nm AlGaAs transition layer, with the Al composition linearly varying from 0.9 to z3; Step 24: Keep the growth temperature at 640 °C, the V / III ratio at 40, the flow rates of TMGa and TMAl unchanged, and regulate the flow rate of CBr4 to make the doping concentration 1×10 18 cm -3 , and grow the p-Al z3 GaAs high refractive index layer in the p-DBR; Step 25: Repeat steps 21 to 24 to form three pairs of p-DBRs with a doping concentration of 1×10 18 cm -3 ; Step 26: Regulate the flow rate of CBr4 to make the doping concentration 3×10 18 cm -3 , repeat Steps 21 to 24 to form 20 pairs of p-DBRs with a doping concentration of 3×10 18 cm -3 , and complete the growth of the p-DBR; Step 27: The growth temperature linearly decreases from 640 °C to 580 °C, the flow rate of TMAl linearly changes to 0, the V / III ratio linearly changes to 30, the CBr4 flow rate linearly changes to the flow rate required for doping the p+GaAs contact layer, forming an AlGaAs transition layer from p-DBR to the p+GaAs contact layer, the Al composition linearly changes from z3 to 0, and the doping concentration linearly changes from 3×10 18 cm -3 to 2×10 linearly 19 cm -3 ; Step 28: Keep the growth temperature at 580 °C and the V / III ratio at 30. Cut off TMA1, keep the flow rates of TMGa and CBr4 unchanged, and grow the p+ GaAs contact layer; Step 29: Cut off TMGa and CBr4, naturally cool down to room temperature, and then cut off AsH3 to complete the growth of the epitaxial wafer; The chip preparation method includes: Step 30: Clean the epitaxial wafer using the standard cleaning process for epitaxial wafers; Step 31: Use the photolithography + development process to form an annular pattern for the p-side electrode, keep the photoresist outside the annular area of the p-side electrode, and remove the photoresist in the annular area of the p-side electrode; Step 32: Deposit the metal layer corresponding to the p-side electrode using the electron beam evaporation or magnetron sputtering process; Step 33: Use the lift-off process with photoresist to strip the metal outside the annular electrode, leaving the metal in the annular electrode area to form the p-side annular electrode; Step 34: Use the photolithography + development process to form a pattern of the VCSEL cylindrical mesa on the wafer surface, keep the photoresist in the cylindrical mesa area, and remove the photoresist outside the cylindrical mesa; Step 35: Use the dry etching process to etch down to form the cylindrical mesa, etch until reaching the n-DBR layer, and then remove the photoresist on the cylindrical mesa; Step 36: Use the chemical polishing process to treat the sidewall of the cylindrical mesa to eliminate the etching damage on the sidewall; Step 37: Oxidize the p-Al 0.98 GaAs oxidation confinement layer by means of a wet oxidation process to form oxidation holes; Step 38: Deposit the SiO2 insulating layer using the plasma enhanced chemical vapor deposition technology. The thickness of the SiO2 insulating layer is slightly greater than the height of the cylindrical mesa to protect the sidewall of the cylindrical mesa; Step 39: Use the photolithography + development process to perform overlay etching on the cylindrical mesa, remove the photoresist on the upper surface of the cylindrical mesa, and keep the photoresist outside the cylindrical mesa area to protect the SiO2 insulating layer; Step 40: Use the wet etching process to remove the SiO2 insulating layer on the upper surface of the cylindrical mesa to expose the p-side annular electrode, and then remove all the photoresist; Step 41: Use the photolithography + development process to form the lead and Pad patterns for the p-side electrode; Step 42: Deposit the p-side metal using the electron beam evaporation or magnetron sputtering process; Step 43: Use the lift-off process with photoresist to strip the photoresist and the metal on it from the wafer surface to form the p-side electrode lead and Pad; Step 44: Use the grinding process to thin the n-GaAs substrate to 120 μm; Step 45: Use the polishing process to polish the back surface of the n-GaAs substrate; Step 46: Deposit metal on the back surface of the n-GaAs substrate using the electron beam evaporation or magnetron sputtering process to form the n-side electrode; Step 47: Use the high-temperature annealing process to alloy the n-side electrode and the p-side electrode to form an ohmic contact with the semiconductor; Step 48: Dicing + singulation to form single chips or array chips; complete the preparation of GaAs-based VCSEL chips.

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