Switching power supply circuit and power supply chip

Abstract

The application discloses a switching power supply circuit and a power supply chip, and relates to the technical field of switching power supply chips.The switching power supply circuit is provided with a continuous conduction mode and a discontinuous conduction mode, and comprises: a switching circuit, an input end of the switching circuit being used for being connected with an external power supply, and an output end of the switching circuit being used for being connected with an external load; a switching control driving circuit, which is electrically connected with a controlled end of the switching circuit, and is used for controlling the switching circuit to work; in the continuous conduction mode, a first feedback loop is started to work, a charging signal is generated according to first voltage signal processing, and the charging signal is output to the switching control driving circuit so as to control the switching circuit to work; in the discontinuous conduction mode, a second feedback loop is started to work, a charging signal is generated according to second voltage signal processing, and the charging signal is output to the switching control driving circuit so as to control the switching circuit to work; thus, the problem that too many detection loops of the adaptive switching power supply chip work in a loop can be reduced, and the power consumption of the chip can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of switching power supply chip technology, and in particular to a switching power supply circuit and power chip. Background Technology

[0002] With the continuous development of the electronics, communications, and medical industries, the requirements for the performance of switching power supplies are also constantly increasing. As a crucial component of power management chips, switching power supplies offer advantages such as high efficiency, high voltage step-down ratio, and low output ripple, and are commonly used in DC-DC buck power supply chips. In consumer electronics products powered by small, low-voltage batteries, such as medical monitoring, smart wearable devices, and high-speed, small-size storage devices, it is necessary to maintain a low-power, high-endurance state for extended periods. Therefore, low-power DC-DC power supply chips have advantages in reducing the energy consumption of electronic devices and extending battery life. For devices requiring low-voltage power supplies, such as low-power Wi-Fi modules, central processing units (CPUs), and digital-to-analog converters, DC-DC buck power supply chips are also needed for voltage reduction and buffering. Designing even lower-power DC-DC buck power supply chips has always been a key challenge in this field. Choosing Constant On-Time Control (COT) and Pulse Width Modulation (PFM) can reduce switching losses and maintain high efficiency under light load conditions. However, under heavy and medium load conditions, the switching power supply operates in Continuous Conduction Mode (CCM). The characteristic of this mode is that the inductor current is continuous within a switching cycle; the inductor current can drop to 0 but will not remain at 0. Because the on-time is constant, the switching power supply frequency is affected by changes in input and output voltages, leading to variations in the duty cycle and preventing a constant switching frequency. Adaptive On-Time Control (AOT) can dynamically adjust the on-time based on the input and output voltages, thereby maintaining a constant switching frequency for the power supply chip under CCM. In the light-load Discontinuous Conduction Mode (DCM), the characteristic is that the inductor current always remains at 0 for a period within a switching cycle. This solution can dynamically reduce the frequency, exhibiting PFM characteristics, thereby reducing switching losses and maintaining high efficiency.

[0003] While adaptive on-time control can improve efficiency under light loads, it typically involves high-power feedback loops and comparators. In light-load mode, keeping the loop running continuously reduces the power supply chip's light-load efficiency. Minimizing the operational portion of the loop in DCM effectively improves the power supply chip's light-load efficiency.

[0004] In traditional power management chips, if the chip uses a second feedback loop and operates near zero inductor current under DCM, the response of the second feedback loop has a certain delay, and the output voltage VOUT will exhibit subharmonic oscillation, resulting in an unstable output voltage and failing to achieve the desired effect. Summary of the Invention

[0005] The main objective of this invention is to propose a switching power supply circuit and power chip, which aims to solve the problem of excessive power consumption caused by too many detection loops in the switching power supply chip under light load mode.

[0006] To achieve the above objectives, the present invention proposes a switching power supply circuit, which has a continuous conduction mode and an intermittent conduction mode, the circuit comprising:

[0007] A switching circuit, wherein the input terminal of the switching circuit is used to connect to an external power source, and the output terminal of the switching circuit is used to connect to an external load;

[0008] A switch control drive circuit is electrically connected to the controlled terminal of the switch circuit, and the switch control drive circuit is used to control the operation of the switch circuit;

[0009] The first feedback loop has its input terminal electrically connected to the output terminal of the switching circuit, and its output terminal electrically connected to the signal feedback terminal of the switch control drive circuit.

[0010] The second feedback loop has its input terminal electrically connected to the output terminal of the switching circuit, and its output terminal electrically connected to the signal feedback terminal of the switch control drive circuit.

[0011] In the continuous conduction mode, the first feedback loop starts working. The first feedback loop processes the first voltage signal output by the switching circuit to generate a charging signal, which is then output to the switch control drive circuit so that the switch control drive circuit controls the switching circuit to work according to the charging signal.

[0012] In the intermittent conduction mode, the second feedback loop starts working. The second feedback loop processes the second voltage signal output by the switching circuit to generate a charging signal, which is then output to the switch control drive circuit so that the switch control drive circuit controls the switching circuit to work according to the charging signal.

[0013] In one embodiment, the first feedback loop further includes

[0014] A first voltage amplifier, wherein the positive input terminal of the first voltage amplifier is connected to the reference power supply electrical connection terminal, and the negative input terminal of the first voltage amplifier is electrically connected to the output terminal of the switching circuit, is used to amplify and output the first voltage signal and the reference voltage signal received from the external load feedback.

[0015] A first voltage comparator, wherein the negative input terminal of the first voltage comparator is electrically connected to the first output terminal of the first voltage amplifier, and the positive input terminal of the first voltage comparator is electrically connected to the second output terminal of the first voltage amplifier, is used to output a first voltage amplification signal when the first voltage signal of the amplified external load is less than the amplified reference voltage signal.

[0016] A current comparator is provided, with its negative input terminal connected to an inductor current sampling terminal and its positive input terminal electrically connected to the output terminal of the first voltage comparator. The comparator is used to calculate based on the sampled current value sent by the inductor current sampling terminal and the received first voltage amplification signal, so that when a preset charging threshold is reached, the charging signal is output to the switch control drive circuit.

[0017] In one embodiment, the second feedback loop includes:

[0018] The second voltage amplifier has its positive input terminal connected to the reference power supply connection terminal, and the negative input terminal of the first voltage amplifier is connected to the output terminal of the switching circuit. It is used to receive the second voltage signal from the external load and the reference voltage signal, amplify them, and then output them.

[0019] The second voltage comparator has its negative input terminal electrically connected to the first output terminal of the second voltage amplifier, and its positive input terminal electrically connected to the second output terminal of the second voltage amplifier. It is used to output a charging operation comparison signal when the second voltage signal of the amplified external load is greater than the reference voltage signal.

[0020] The third voltage comparator has its negative input terminal electrically connected to the output terminal of the second voltage comparator, and its positive input terminal connected to the ramp compensation circuit connection terminal. It is used to compare the received charging operation comparison signal with the ramp compensation voltage signal sent by the ramp compensation circuit, so that when the ramp compensation voltage signal is reached, the charging signal is output to the switch control drive circuit.

[0021] In one embodiment, the switching power supply circuit further includes:

[0022] A slope compensation circuit, which is electrically connected to the positive input terminal of the third voltage comparator, is used to provide a slope compensation voltage signal to prevent secondary harmonic oscillations.

[0023] In one embodiment, the ramp compensation circuit includes:

[0024] The system comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first current mirror, a second current mirror, a first capacitor, and a working power supply connection terminal, wherein;

[0025] The input terminals of the first current mirror and the second current mirror are electrically connected to the working power supply connection terminal, respectively. The output terminal of the first current mirror is electrically connected to the source of the first PMOS transistor, the first terminal of the first capacitor, the source of the second PMOS transistor, the drain of the third PMOS transistor, and the positive input terminal of the third voltage comparator, respectively. The output terminal of the second current mirror is electrically connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is electrically connected to the output terminal of the first voltage inverter. The second terminal of the first capacitor, the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the drain of the second PMOS transistor are grounded, respectively. The gate of the second PMOS transistor is electrically connected to the output terminal of the second voltage inverter.

[0026] In one embodiment, the switch control drive circuit includes:

[0027] A multiplexer, wherein the first input terminal of the multiplexer is connected to the output terminal of the first feedback loop, and the second input terminal of the multiplexer is connected to the output terminal of the second feedback loop, for outputting the charging signal received from the first feedback loop or the second feedback loop;

[0028] The RS controller has its first input terminal connected to the output terminal of the multiplexer, and is used to process and generate a charging control signal when the charging signal is received, and then output it.

[0029] The logic control and driver are electrically connected to the output of the RS controller and to the controlled terminal of the switching circuit. The logic control and driver are used to process the received charging control signal to generate a charging drive signal to drive the switching circuit to operate in a charging state.

[0030] In one embodiment, the switching power supply circuit further includes:

[0031] A discharge state transition circuit is provided, wherein the input terminal of the discharge state transition circuit is electrically connected to the output terminal of the switching circuit, and the output terminal of the discharge state transition circuit is electrically connected to the second input terminal of the RS controller. The discharge state transition circuit is used to send a discharge signal to the RS controller, and the RS controller generates a discharge control signal and outputs it to control the logic controller and driver to process the discharge control signal to generate a discharge drive signal, thereby driving the switching circuit to work in the discharge state.

[0032] In one embodiment, the switching power supply circuit further includes:

[0033] A sleep state transition circuit is provided, wherein the negative input terminal of the sleep state transition circuit is connected to the inductor current sampling terminal, the positive input terminal of the sleep state transition circuit is connected to the switching circuit, and the output terminal of the sleep state transition circuit is electrically connected to the input terminal of the logic control and driver. When the inductor current is detected to be zero, a sleep control signal is generated to control the logic control and driver to process the sleep control signal to generate a sleep drive signal, thereby driving the switching circuit to operate in a sleep state.

[0034] In one embodiment, the switching circuit includes:

[0035] The first switching transistor has its source connected to an external power supply, its gate electrically connected to the output terminal of the logic control and driver, and its drain electrically connected to the external load.

[0036] The second switch has its source electrically connected to the drain of the first switch and the external load, its gate electrically connected to the output of the logic control and driver, and its drain electrically connected to the positive input of the sleep state transition circuit.

[0037] When the logic control and driver outputs a charging drive signal, it controls the first switch to turn on and the second switch to turn off; or when the logic control and driver outputs a discharging drive signal, it controls the first switch to turn off and the second switch to turn on; or when the logic control and driver outputs a sleep drive signal, it controls the first switch and the second switch to turn off.

[0038] The present invention also proposes a power supply chip, which includes the switching power supply circuit as described above.

[0039] The technical solution of this invention employs a switching power supply circuit, which has a continuous conduction mode and an intermittent conduction mode. The circuit includes: a switching circuit, the input terminal of which is used to connect to an external power source, and the output terminal of which is used to connect to an external load; a switching control drive circuit, electrically connected to the controlled terminal of the switching circuit, used to control the operation of the switching circuit; a first feedback loop, the input terminal of which is electrically connected to the output terminal of the switching circuit, and the output terminal of which is electrically connected to the signal feedback terminal of the switching control drive circuit; and a second feedback loop, the input terminal of which is electrically connected to the output terminal of the switching circuit. The first feedback loop is electrically connected to the signal feedback terminal of the switch control drive circuit. In the continuous conduction mode, the first feedback loop is activated, processing the first voltage signal output by the switch circuit to generate a charging signal, which is then output to the switch control drive circuit, enabling the switch control drive circuit to control the switch circuit based on the charging signal. In the intermittent conduction mode, the second feedback loop is activated, processing the second voltage signal output by the switch circuit to generate a charging signal, which is also output to the switch control drive circuit, enabling the switch control drive circuit to control the switch circuit based on the charging signal. Thus, the switching power supply circuit can select to activate the first feedback loop in the continuous conduction mode or the second feedback loop in the intermittent conduction mode, thereby reducing the problem of excessive detection loop operation in the adaptive switching power supply chip under light load mode and effectively reducing chip power consumption. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0041] Figure 1 This is a system block diagram of an embodiment of the switching power supply circuit provided by the present invention;

[0042] Figure 2 A detailed structural diagram of an embodiment of the switching power supply circuit provided by the present invention;

[0043] Figure 3 A schematic diagram of the internal ramp compensation circuit in another embodiment of the switching power supply circuit provided by the present invention;

[0044] Figure 4This is a schematic diagram showing the changes in circuit-related signals during operation of the switching power supply circuit provided by the present invention in intermittent conduction mode and continuous conduction mode.

[0045] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0047] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0048] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0049] In DC-DC buck power supply chips with adaptive on-time modulation under AOT control mode, the power consumption of this type of power switch chip is greatly increased in order to keep the detection loop running continuously so that the chip can switch operating modes in a timely manner.

[0050] It is worth mentioning that in AOT control mode, the step-down power supply chip often has inductors and capacitors on the line between it and the external load to filter the voltage output to the external load. The switching power supply chip in this solution can operate in continuous conduction mode under heavy and medium load conditions. This mode is characterized by the inductor repeatedly switching between charging and discharging states within a switching cycle. In continuous conduction mode, the inductor current in the switching power supply chip is continuous and can drop to 0, but it will not remain at 0 continuously. Under light load conditions, the switching power supply chip can switch to discontinuous conduction mode. This mode is characterized by the inductor repeatedly switching between charging, discharging, and sleep states within a switching cycle. In discontinuous conduction mode, the inductor current in the switching power supply chip always remains at 0 for a period of time. Furthermore, by utilizing the state where the inductor current is maintained at 0, the operation of certain components can be stopped (i.e., sleep state), thereby reducing switching losses and maintaining high efficiency.

[0051] Please refer to Figures 1 to 3 This invention proposes a switching power supply circuit, which has a continuous conduction mode and an intermittent conduction mode. The circuit includes:

[0052] A switching circuit 1, wherein the input terminal of the switching circuit 1 is used to connect to an external power source, and the output terminal of the switching circuit 1 is used to connect to an external load;

[0053] A switch control drive circuit 2 is electrically connected to the controlled terminal of the switch circuit 1, and the switch control drive circuit 2 is used to control the operation of the switch circuit 1.

[0054] The first feedback loop 3 has its input terminal electrically connected to the output terminal of the switch circuit 1, and its output terminal electrically connected to the signal feedback terminal of the switch control drive circuit 2.

[0055] The second feedback loop 4 has its input terminal electrically connected to the output terminal of the switching circuit 1, and its output terminal electrically connected to the signal feedback terminal of the switch control drive circuit 2.

[0056] In the continuous conduction mode, the first feedback loop 3 starts working. The first feedback loop 3 processes the first voltage signal output by the switching circuit 1 to generate a charging signal, and outputs it to the switch control drive circuit 2 so that the switch control drive circuit 2 controls the switching circuit 1 to work according to the charging signal.

[0057] In the intermittent conduction mode, the second feedback loop 4 starts working. The second feedback loop 4 processes the second voltage signal output by the switching circuit 1 to generate a charging signal, and outputs it to the switch control drive circuit 2 so that the switch control drive circuit 2 controls the switching circuit 1 to work according to the charging signal.

[0058] In this embodiment, the switching circuit 1 can be implemented by one or more transistors, and the switching control drive circuit 2 can be implemented by PLC (Programmable Logic Controller), MCU (Microcontroller Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), SOC (System On Chip), etc. The first feedback loop 3 and the second feedback loop 4 can be implemented by using an amplifier and a comparator together. The first voltage signal and the second voltage signal are both voltage values ​​within a certain range (for example, the voltage value V1 of the first voltage signal is set to be less than a preset threshold of 600mV, and the voltage value V2 of the second voltage signal is set to be greater than or equal to the preset threshold of 600mV). The R&D personnel can set the voltage range values ​​of the first voltage signal and the second voltage signal according to the product requirements. The first voltage signal only needs to be set to be less than the second voltage signal to ensure that the two are mutually exclusive, so no fixed value limit is made here.

[0059] Specifically, when the switching power supply circuit is running in continuous conduction mode, the output voltage of the external load is the first voltage signal. The first feedback loop 3 processes the first voltage signal output by the switching circuit 1 to generate a charging signal, which is then output to the switching control drive circuit 2 so that the switching control drive circuit 2 controls the switching circuit 1 to work according to the charging signal.

[0060] When the switching power supply circuit is running in the intermittent conduction mode, the output voltage of the external load is the second voltage signal. The second feedback loop 4 processes the second voltage signal output by the switching circuit 1 to generate a charging signal and outputs it to the switching control drive circuit 2, so that the switching control drive circuit 2 controls the switching circuit 1 to work according to the charging signal, thereby enabling the switching power supply circuit to enter the charging state in both the continuous conduction mode and the intermittent conduction mode.

[0061] It is worth mentioning that, since the step-down power supply switching chip in AOT control mode often has a filter circuit composed of inductors and capacitors, when the external load connected to the switching circuit 1 is lightly loaded, the current in the line between the external load and the switching circuit 1 decreases, and the capacitor in the filter circuit continuously charges, causing the voltage output by the switching circuit 1 to the external load to rise. This causes the voltage fed back to the first feedback loop 3 and the second feedback loop 4 to rise accordingly. When the feedback voltage rises from the first voltage signal to the second voltage signal, the second feedback loop 4 is switched to start working; otherwise, the first feedback loop 3 is switched to start working. Furthermore, by setting appropriate logic circuits, the comparator in the first feedback loop 3 can be stopped from working when the voltage rises from the first voltage signal to the second voltage signal, thereby reducing power consumption.

[0062] Furthermore, the first feedback loop 3 also includes:

[0063] A first voltage amplifier, the positive input terminal of which is connected to the reference power supply electrical connection terminal, and the negative input terminal of which is connected to the output terminal of the switching circuit 1, is used to amplify and output the first voltage signal and the reference voltage signal received from the external load feedback.

[0064] A first voltage comparator COMP1, with its negative input terminal electrically connected to the first output terminal of the first voltage amplifier and its positive input terminal electrically connected to the second output terminal of the first voltage amplifier, is used to output a first voltage amplification signal when the received amplified first voltage signal from an external load is less than the amplified reference voltage signal.

[0065] The current comparator ICMP has its negative input terminal connected to the inductor current sampling terminal and its positive input terminal electrically connected to the output terminal of the first voltage comparator COMP1. It is used to calculate based on the sampled current value sent by the inductor current sampling terminal and the received first voltage amplification signal, so that when a preset charging threshold is reached, the charging signal is output to the switch control drive circuit 2.

[0066] In this embodiment, the first voltage amplifier can be implemented by an error amplifier, the first voltage comparator COMP1 can be implemented by an error comparator, the reference power supply can be implemented by a reference circuit or an external power supply, and the inductor current in the circuit can be monitored in real time by a current sensor or RI module, and the current value of the monitored inductor current is output to the inductor current sampling terminal. In the continuous conduction mode, the current comparator not only performs feedback adjustment based on the monitored inductor current change, but also performs feedback adjustment based on the monitored first voltage signal change, so as to control the output state of the current comparator ICMP.

[0067] Specifically, when the first voltage amplifier receives and amplifies the first voltage signal and reference voltage signal from the external load, it outputs the amplified first voltage signal to the negative terminal of the first voltage comparator COMP1 and the amplified reference voltage signal to the positive terminal of the first voltage comparator COMP1. When the amplified first voltage signal from the external load is less than the amplified reference voltage signal, the first voltage amplification signal is output to the positive input terminal of the current comparator COMP1. This first voltage amplification signal serves as the comparison reference parameter for the current comparator ICMP. It is used to perform weighted calculations with the sampled current value and the operating voltage value received from the power supply terminal of the current comparator (not shown in the figure), and then added to generate a comparison value (e.g., first voltage amplification signal + current weight * sampled current). The sample current value + working voltage weight * working voltage value equals the comparison value OUTM, i.e., PIBI1*12k+0.6*SW+0.4*INTVCC=OUTM), is compared with a preset charging threshold. This preset charging threshold (e.g., working voltage weight * working voltage value + constant threshold equals the preset charging threshold OUTP, i.e., 0.4*INTVCC+PIBI0*12k=OUTP) can be generated by the constant threshold obtained by the current comparator through the external resistor voltage divider and the working voltage value weighted. When the current drops to the preset charging threshold, a charging signal is output to the switch control drive circuit 2, so that the switch control drive circuit 2 controls the switch circuit 1 to work according to the charging signal, and controls the switch circuit 1 to realize the transition from the discharge state of the continuous conduction mode to the charging state.

[0068] It is worth mentioning that in the continuous conduction mode discharge state, the inductor current and load voltage will continue to decrease. The first voltage amplification signal is amplified by the load voltage when the first voltage signal is generated, and the comparison value generated therefrom also continues to decrease.

[0069] In one embodiment, the second feedback loop 4 includes:

[0070] The second voltage amplifier has its positive input terminal connected to the reference power supply connection terminal, and the negative input terminal of the first voltage amplifier is connected to the output terminal of the switching circuit 1. It is used to receive the second voltage signal from the external load and the reference voltage signal, amplify them, and then output them.

[0071] The second voltage comparator COMP2 has its negative input terminal electrically connected to the first output terminal of the second voltage amplifier, and its positive input terminal electrically connected to the second output terminal of the second voltage amplifier. It is used to output a charging operation comparison signal when the second voltage signal of the amplified external load is greater than the reference voltage signal.

[0072] The third voltage comparator COMP4 has its negative input terminal electrically connected to the output terminal of the second voltage comparator COMP2, and its positive input terminal connected to the ramp compensation circuit 7. It is used to compare the received charging operation comparison signal with the ramp compensation voltage signal sent by the ramp compensation circuit 7, so that when the ramp compensation voltage signal is reached, the charging signal is output to the switch control drive circuit 2.

[0073] In this embodiment, the second voltage amplifier can be implemented by an error amplifier, and both the second voltage comparator COMP2 and the third voltage comparator COMP4 can be implemented by error comparators. The reference power supply can be implemented by a reference circuit or an external power supply. When the second voltage amplifier receives the second voltage signal fed back from the external load and the reference voltage signal, it amplifies them and outputs the amplified second voltage signal to the negative terminal of the second voltage comparator COMP2, and outputs the amplified reference voltage signal to the positive terminal of the second voltage comparator COMP2. The amplified first voltage from the external load is received through the first voltage comparator COMP1. After comparing the signal with the amplified reference voltage signal, a charging operation comparison signal is output to the negative input terminal of the third voltage comparator COMP4. The slope compensation voltage signal received at the positive input terminal of the third voltage comparator COMP4 is used as the non-constant voltage threshold of the third voltage comparator COMP4. When the charging operation comparison signal rises to the voltage threshold, the charging signal is output to the switch control drive circuit 2, so that the switch control drive circuit 2 controls the switch circuit 1 to work according to the charging signal, and controls the switch circuit 1 to switch from the sleep state to the charging state in the intermittent conduction mode.

[0074] Specifically, the charging operation comparison signal is an error amplification voltage value, and the slope compensation voltage signal is also a voltage value. The first voltage amplifier and the second voltage amplifier can be configured as the same component (e.g., Figure 2 The voltage amplifier AMP1 (with dual-phase input and dual-phase output) or two independently configured voltage amplifiers are used for implementation. Since the charging operation comparison signal has a certain time delay in the second feedback loop 4, there will be a certain phase delay. If there is no phase difference, the voltage output to the external load in the sleep stage of the intermittent conduction mode drops rapidly, and the corresponding charging operation comparison signal should rise rapidly. At this time, the third voltage comparator COMP4 only needs to compare the charging operation comparison signal with the slope compensation voltage signal. When the charging operation comparison signal rises to the slope compensation voltage signal, the output of the third voltage comparator COMP4 flips, and then the charging stage begins.

[0075] In one embodiment, the switching power supply circuit further includes:

[0076] The slope compensation circuit 7 is electrically connected to the positive input terminal of the third voltage comparator COMP4 and is used to provide a slope compensation voltage signal to prevent secondary harmonic oscillations.

[0077] In this embodiment, due to the phase difference between the voltage signal output to the load and the output signal of the second voltage comparator COMP2, the charging comparison signal may have a trough during the sleep phase in the intermittent conduction mode; that is, the charging comparison signal may first decrease and then increase during this phase. Since the sleep time of this switching power supply circuit is short, if a constant comparison threshold provided by a reference circuit is used, the comparison threshold will be reached when the charging comparison signal decreases, rather than when it increases. This would cause the third voltage comparator COMP4 to flip prematurely into the charging phase of the next cycle, resulting in subharmonic oscillation. Therefore, a slope compensation circuit 7 is introduced instead of using a reference circuit to provide a constant comparison threshold.

[0078] Furthermore, the slope compensation circuit 7 includes:

[0079] The components include a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first current mirror I1, a second current mirror I2, a first capacitor C1, and a power supply connection terminal.

[0080] The input terminals of the first current mirror I1 and the second current mirror I2 are electrically connected to the working power supply connection terminal, respectively. The output terminal of the first current mirror I1 is electrically connected to the source of the first PMOS transistor MP1, the first terminal of the first capacitor C1, the source of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3, and the positive input terminal of the third voltage comparator, respectively. The output terminal of the second current mirror I2 is electrically connected to the source of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is electrically connected to the output terminal of the first voltage inverter. The second terminal of the first capacitor C1, the gate of the first PMOS transistor MP1, the drain of the first PMOS transistor MP1, and the drain of the second PMOS transistor MP2 are grounded, respectively. The gate of the second PMOS transistor MP2 is electrically connected to the output terminal of the second voltage inverter.

[0081] In this embodiment, the working power supply connection terminal can be implemented by a reference circuit providing a reference power supply. The input terminal of the first voltage inverter is connected to the inductor in the switching power supply circuit to invert the voltage signal of the inductor, and outputs it to the gate of the third PMOS transistor MP3 through the output terminal of the first voltage inverter (not shown in the figure). This serves as a switch to periodically control the charging and discharging of the first capacitor C1, thereby generating a triangular wave signal to provide a ramp compensation voltage. The input terminal of the second voltage inverter (not shown in the figure) is connected to a certain switching transistor in the switching circuit 1 (specifically...). Figure 2 The second switch MN can be obtained by inverting the gate signal in the second switch MN, performing a logical AND operation with the gate signal in the first switch MP, and then inverting the result. Figure 3 The SW2 signal in the circuit is used to make it low level when it is off, so that the first capacitor C1 discharges faster and the slope of the ramp compensation voltage is larger in this stage. The first current mirror I1 and the second current mirror I2 are both used as bias current sources. The first current mirror I1 is used to charge the first capacitor C1, so that the first PMOS transistor MP1 with its gate and drain connected is in the critical conduction state.

[0082] Specifically, when the switching power supply circuit is in the charging state, the signal output by the first voltage inverter is low, the third PMOS transistor MP3 is turned on, the signal output by the second voltage inverter is high, and the second PMOS transistor MP2 is turned off. At this time, the current flowing through the second current mirror I2 is in the order of the third PMOS transistor MP3, the first capacitor C1, and the first PMOS transistor MP1. Since the first capacitor C1 is currently in a stable charging state and will rise at a fixed slope, when the switching power supply circuit is in the discharging state, the signal output by the first voltage inverter (i.e., SW1) is high, the third PMOS transistor MP3 is turned off, the signal output by the second voltage inverter is high (i.e., SW2), and the second PMOS transistor MP2 is turned off. At this time, the circuit for charging the first capacitor C1 by the second current mirror I2 is broken. Capacitor C1 will operate in a stable discharge state. When the switching power supply circuit is in sleep mode, the signal output by the first voltage inverter is high, the third PMOS transistor MP3 is off, the signal output by the second voltage inverter is low, and the second PMOS transistor MP2 is on. At this time, the circuit for charging the first capacitor C1 by the second current mirror I2 is broken. Although the first capacitor C1 is still in the discharge state, the discharge current flows through the first PMOS transistor MP1 and the second PMOS transistor MP2. The conduction of the second PMOS transistor increases the discharge current of the first capacitor C1. Therefore, the output voltage threshold signal will drop at a greater slope, so that the third voltage comparator can more accurately determine the output charging signal, so that the switching power supply circuit can complete the transition from sleep mode to charging mode in intermittent conduction mode.

[0083] In one embodiment, the switch control drive circuit 2 includes:

[0084] Multiplexer 21, the first input terminal of multiplexer 21 is connected to the output terminal of the first feedback loop 3, and the second input terminal of multiplexer 21 is connected to the output terminal of the second feedback loop 4, for outputting the charging signal received from the first feedback loop 3 or the second feedback loop 4;

[0085] RS controller 22, the first input terminal of which is connected to the output terminal of multiplexer 21, is used to process and generate a charging control signal when the charging signal is received and then output it.

[0086] The logic controller and driver 23 has its input terminal electrically connected to the output terminal of the RS controller 22 and its output terminal electrically connected to the controlled terminal of the switching circuit 1. It is used to process the received charging control signal to generate a charging drive signal to drive the switching circuit 1 to work in a charging state.

[0087] In this embodiment, the switch control drive circuit 2 receives charging signals from the first feedback loop 3 and the second feedback loop 4 via the multiplexer 21, and after receiving the charging signals via the RS controller 22, processes and generates charging control signals, which are then output to the logic controller and driver 23. The logic controller and driver 23 then processes and generates corresponding charging drive signals to drive the switch circuit 1 to switch to the charging state and operate, thereby enabling the switching power supply circuit to enter the charging state.

[0088] Furthermore, the switching power supply circuit also includes:

[0089] The discharge state transition circuit 5 has its input terminal electrically connected to the output terminal of the switching circuit 1 and its output terminal electrically connected to the second input terminal of the RS controller 22. It is used to send a discharge signal to the RS controller 22, and after the RS controller 22 generates a discharge control signal, it outputs the signal to control the logic controller and driver 23 to process the discharge control signal and generate a discharge drive signal to drive the switching circuit 1 to work in the discharge state.

[0090] In this embodiment, the discharge state transition circuit 5 includes a TON on-time generation circuit, a phase-locked loop (PLL), and an RT circuit. The first end of the RT resistor is electrically connected to the output terminal of the switching circuit 1, and the second end of the RT resistor is electrically connected to the input terminal of the PLL. The output terminal of the PLL is electrically connected to the CLK input terminal of the TON on-time generation circuit. The VIN input terminal of the TON on-time generation circuit is connected to an external power supply, and the VOUT terminal of the TON on-time generation circuit is connected to the output terminal of the switching circuit 1. The output terminal of the TON on-time generation circuit is electrically connected to the second input terminal of the RS controller 22.

[0091] When the switching power supply circuit enters the charging state, the TON conduction time generation circuit can be activated by logic control and driver 23 or an external controller. It receives an external clock signal CLK obtained from the phase-locked loop (the frequency of which can be programmed by setting the resistance value of the RT resistor), and simultaneously receives the voltage of the external power supply VIN and the voltage VOUT output from the switching power supply circuit to the external load. At this time, a capacitor with an initial voltage of zero inside the TON conduction time generation circuit module begins charging. The charging current is directly proportional to the external power supply VIN voltage and inversely proportional to the RT resistance. When the capacitor is in the charging stage, the capacitor voltage rises steadily. At this time, the chip is in the charging stage, and the inductor current rises steadily. When the internal capacitor voltage rises to the set threshold, a discharge signal is output to the RS controller 22. The RS controller 22 generates a discharge control signal and outputs it to control the logic controller and driver 23 to process the discharge control signal and generate a discharge drive signal to drive the switching circuit 1 to work in the discharge state, thereby controlling the switching circuit 1 to enter the discharge working state from the charging working state. This setting enables the switching power supply circuit to work in AOT control mode. Since the TON conduction time generation circuit does not start working when the switching power supply circuit enters the sleep state in the intermittent conduction mode, the power consumption of the switching power supply circuit in the intermittent conduction mode can be effectively reduced.

[0092] Furthermore, the switching power supply circuit also includes:

[0093] The sleep state transition circuit 6 has its negative input terminal connected to the inductor current sampling terminal and its positive input terminal connected to the switching circuit 1. The output terminal of the sleep state transition circuit 6 is electrically connected to the input terminal of the logic control and driver 23. When the inductor current is detected to be zero, the circuit generates a sleep control signal to control the logic control and driver 23 to process the sleep control signal and generate a sleep drive signal to drive the switching circuit 1 to operate in a sleep state.

[0094] In this embodiment, the sleep state transition circuit 6 can be implemented by a zero-crossing comparator. Since the inductor current is always maintained at 0 for a period of time during one switching cycle in the intermittent conduction mode, the zero-crossing comparator generates a sleep control signal when it detects that the inductor current is 0. This signal controls the logic controller and driver 23 to process the sleep control signal and generate a sleep drive signal, which drives the switching circuit 1 to work in a sleep state. This controls the switching circuit 1 to enter the sleep state from the discharge working state in the intermittent conduction mode.

[0095] Furthermore, the switching circuit 1 includes:

[0096] The first switching transistor MN has its source connected to an external power supply, its gate electrically connected to the output terminal of the logic control and driver, and its drain electrically connected to the external load.

[0097] The source of the second switch MP is electrically connected to the drain of the first switch MN and the external load, the gate of the second switch MP is electrically connected to the output terminal of the logic control and driver, and the drain of the second switch MP is electrically connected to the positive input terminal of the sleep state transition circuit 6.

[0098] When the logic control and driver outputs a charging drive signal, it controls the first switch MN to turn on and the second switch MP to turn off; or when the logic control and driver outputs a discharging drive signal, it controls the first switch MN to turn off and the second switch MP to turn on; or when the logic control and driver outputs a sleep drive signal, it controls the first switch MN and the second switch MP to turn off.

[0099] In this embodiment, the first switch MN and the second switch MP can be implemented by transistors. In the continuous conduction mode, the logic control and driver only need to output charging drive signals and discharging drive signals to complete the state transition between charging and discharging in one switching cycle within the switching power supply circuit. In the continuous conduction mode, the logic control and driver need to output charging drive signals, discharging drive signals, and sleep drive signals to complete the state transition between charging, discharging, and sleep in one switching cycle within the switching power supply circuit. Specifically, the first switch MN is a fourth PMOS transistor, and the second switch MP is a first NMOS transistor.

[0100] To facilitate the explanation of the technical principles of this solution, the following working process is provided for reference:

[0101] The working process of the DC-DC buck power supply switching power supply circuit of this invention in CCM (Continuous On-Mode) state is combined with Figure 2 and Figure 4 The following is a display:

[0102] When the first NMOS transistor MP is turned on and the fourth PMOS transistor MN is turned off, the switching power supply circuit enters the charging phase, at which point the inductor current begins to rise. At this time, the TON on-time generation circuit module 7 begins to operate. This module receives the external clock signal CLK obtained from the phase-locked loop debugging (the frequency of this signal can be programmed by setting the resistance value of the RT resistor), and simultaneously receives the external operating voltage VIN and the external load voltage VOUT.

[0103] At this point, an internal capacitor with an initial voltage of zero begins charging within the TON conduction time generation circuit module. The charging current is directly proportional to the operating voltage VIN and inversely proportional to the resistance RT. While this capacitor is charging, its voltage steadily increases, and the inductor current steadily increases as the switching power supply circuit enters its charging phase. When the internal capacitor voltage rises to the load feedback voltage threshold VOUT, Figure 2 The RS controller in the circuit generates a high pulse (i.e., a charging signal) at the signal sigoff receiving terminal (second input terminal). The change of this signal is received by the logic control and drive module, which generates a high potential drive signal PG and a high potential drive signal NG, causing the first NMOS transistor MP to turn off and the fourth PMOS transistor MN to turn on. The charging stage of the switching power supply circuit ends and it enters the discharging stage.

[0104] After entering the discharge phase, the inductor current begins to decrease. The output voltage VOUT to the load begins to decrease, causing the feedback voltage V fed back to the amplifier to decrease. FB The decrease is propagated in the second feedback loop. Amplifier AMP1 will reduce V... FB The reference voltage signal V provided by the reference circuit REF The amplification is performed, and the result is input into the first voltage comparator COMP1 for error comparison (because the operating thresholds of comparators COMP2 and COMP1 are different: the second voltage comparator COMP2 operates at a different threshold at the feedback voltage V). FB The voltage rises to 605mV for operation; the feedback voltage V when comparator COMP1 is operating. FB Less than 605mV. COMP1 and COMP2 operate in a mutually exclusive manner; COMP2 is not working in this state. COMP1 output error amplification result V ERR1 (i.e., the first voltage amplification signal). The current comparator ICMP compares the sampled current I from the inductor. SW and V ERr1 At this time, I SW The change in V is propagated within the first feedback loop. ErR1 AC V is filtered by comparator COMP1 FB The output obtained after amplification is relatively stable, mainly due to I. SW This affects the output of the current comparator ICMP. When I SW When the current drops to the threshold, the output of the current comparator ICMP flips, and the sigon signal terminal (first input terminal) of the RS controller 22 generates a high pulse. The change of this signal is received by the logic control and drive module 23, which generates a drive signal PG at a low potential and a drive signal NG at a low potential, so that the first NMOS transistor MP is turned on and the fourth PMOS transistor MN is turned off. The discharge stage of the switching power supply circuit ends and enters the charging stage.

[0105] The working process of the DC-DC step-down power supply switching power supply circuit of this invention in DCM mode is combined with Figure 2 and Figure 4 The following is a display:

[0106] Due to the decrease in load current, the capacitor C used with the inductor... OUT As the battery continues to charge, the output voltage VOUT rises further. This, in turn, feeds back to the amplifier's feedback voltage V. FB Rise, when V FB When the load current rises to a certain threshold, it enters the operating range of comparator COMP2. At this time, the logic control and drive module generates a logic control signal to turn off the first voltage comparator COMP1 and the current comparator ICMP in the second feedback loop under CCM state. As the load current gradually decreases and approaches 0, the switching power supply circuit begins to switch from CCM to DCM. When the first NMOS transistor MP is turned off and the fourth PMOS transistor MN is turned on, the switching power supply circuit operates in the discharge phase, and the inductor current is sampled as I. SW As the current continues to decrease until it reaches 0, the zero-crossing comparator COMP3 in the sleep state transition circuit 6 flips, generating a zero current detection signal that is transmitted to the logic control and drive module. This module generates a drive signal to turn off both MOSFETs MP and MN, and the switching power supply circuit enters the sleep stage (both MOSFETs MP and MN are turned off).

[0107] During the sleep phase, the first voltage comparator COMP1, the current comparator ICMP, and the fourth voltage comparator (zero-crossing detection comparator) COMP3 are all turned off. At this time, changes in the feedback signal flow through the second feedback loop path, including amplifier AMP1, comparator COMP2, and comparator COMP4. This strategy avoids the energy loss caused by the operation of these turned-off comparators, and completes the function of the second feedback loop involving the second voltage comparator COMP2 solely through voltage comparison, thus reducing the overall power consumption of the switching power supply circuit.

[0108] Regarding the second feedback loop involving comparator COMP2, due to a certain delay in the response of the second feedback loop, the output voltage VOUT exhibits subharmonic oscillation. To further reduce the subharmonic oscillation generated in this stage, a slope compensation voltage signal V is introduced into this loop. sIope This voltage has a steeper slope during the sleep phase, allowing the third voltage comparator COMP4 to more accurately determine the transition from the sleep phase to the charging phase. Comparator COMP4 compares V... slope and COMP2 output V ERR2 When V ERR2When the voltage rises to the threshold, the comparator COMP4 output flips, generating a charging signal sigon. The logic control and drive module generates a corresponding drive signal to turn on the first NMOS transistor MP and turn off the fourth PMOS transistor MN, thus switching the power supply circuit into the charging state.

[0109] When the signal is transmitted in the second feedback loop, due to a certain time delay, the voltage VOUT output to the load differs from the output V of COMP2. ERR2 (V ERR2 The relationship between VOUT and VOUT is inverse, indicating a certain phase difference (see reference). Figure 4 China V ERR2 (The curve). If there is no phase difference, then during the sleep phase, when the output voltage VOUT drops rapidly, the corresponding V... ERR2 It should rise rapidly; at this point, comparator COMP4 only needs to set V... ERR2 Compared with the preset comparator toggling threshold, when V ERR2 When the voltage rises to the flip threshold, the output of comparator COMP4 flips, and the charging phase begins. Due to the phase difference, during the sleep phase, V... ERR2 There may be a trough value during this stage, namely V. ERR2 It may first decrease and then increase during this phase. Because the sleep time of the switching power supply circuit is short, if a constant comparison threshold is used, then at V... ERR2 The comparison threshold is reached when the voltage drops, not after it rises. This would cause comparator COMP4 to flip prematurely and enter the charging phase of the next cycle, resulting in subharmonic oscillations. Therefore, a slope compensation circuit 7 is introduced instead of using a constant comparison threshold, thereby preventing V from reaching the comparison threshold. ERR2 When the threshold V is decreased, compare it. slope The charging operation comparison signal also drops, preventing comparator COMP4 from flipping prematurely at this time.

[0110] Generate slope compensation voltage V slope The structure of the slope compensation circuit is as follows: Figure 3 As shown, for ease of explanation, the first PMOS transistor MP1 is referred to as MP1, the second PMOS transistor MP2 as MP2, and the third PMOS transistor MP3 as MP3. MP1 and MP2 are PMOS transistors with the same parameters. The first current mirror I1 provides the bias current source I. BIAS1 The second current mirror I2 provides the bias current source I. BIAS2 .

[0111] Signal SW1 controls the on / off state of MP3. It is low during the charging phase and high during the discharging phase of the switching power supply circuit, meaning MP3 is on during charging and off during discharging. Signal SW2 controls the on / off state of MP2. It is low only during the sleep phase of the switching power supply circuit and high at other times, meaning MP2 is on during the sleep phase and off at other times. Signal SW1 is generated by an external first inverter connected to the inductor SW node. It is obtained by inverting the gate signal in the second switching transistor MN, performing a logical AND operation with the gate signal in the first switching transistor MP, and then inverting the result. Figure 3 The SW2 signal in the circuit. Bias current source I. BIAS1 Charging the first capacitor C1 brings the PMOS transistor MP1, whose gate and drain are connected, into a critical conduction state. At this moment, the source voltage of PMOS transistor MP1 is V. slope The initial value of the bias current source I BIAS1 The current is relatively small. Bias current source I BIAS2 Responsible for charging the first capacitor C1 so that V slope It exhibits a significant rate of change over time. During the charging phase of the switching power supply circuit, signal SW1 is low, MP3 is on; signal SW2 is high, MP2 is off. At this time, the bias current source I... BIAS2 The current flows through MP3, the first capacitor C1, and MP3. Since the first capacitor C1 is in a stable charging state, the internal voltage of the first capacitor C1 will rise at a fixed slope. This is to ensure that comparator COMP4 compares V during the sleep phase of the switching power supply circuit. slope and V ERR2 This allows for more accurate determination of the output flip-off moment, therefore, during the discharge phase of the switching power supply circuit, V... slope The descent at a lower slope acts as a buffer, allowing V to descend during the dormant phase. slope It can decrease at a greater slope. During the discharge phase of the switching power supply circuit, when signal SW1 is high, MP3 is off; when signal SW2 is high, MP2 is off. At this time, the bias current source I... BIAS2 The circuit for charging the first capacitor C1 is disconnected, and the first capacitor C1 will be in a stable discharge state. The discharge current flows through MP1, where the internal voltage of the first capacitor C1 is C. slope .

[0112] Let D1 be the proportion of the discharge phase within one switching cycle T in the switching power supply circuit, and D2 be the proportion of the sleep phase within cycle T. Then, the proportion of the charging phase within cycle T is D = 1 - D1 - D2. The slope sloping down during the discharge phase is:

[0113] Slope1 = D*I BIAS2 / C slope ;

[0114] During the sleep phase of the switching power supply circuit, signal SW1 is high, MP3 is off; signal SW2 is low, MP2 is on. At this time, the bias current source I... BIAS2 The circuit charging the first capacitor C1 is disconnected, and the first capacitor C1 will remain in a discharging state, with the discharge current flowing through MOSFETs MP1 and MP2. Because MP2 is turned on, the discharge current of the first capacitor C1 increases, therefore V... slope It descends with a steeper slope. The descent slope Slope2 during the dormant phase is:

[0115] Slope2 = 2D * I BIAS2 / (1+D2)C slope ;

[0116] It is evident that since D2 < 1, then 2 / (1+D2) > 1, Slope1 <Slope2。

[0117] The purpose of disclosing the embodiments is to help to further understand the present invention, which should be understood by those skilled in the art.

[0118] The present invention also proposes a power chip, which includes the switching power supply circuit described above. The specific structure of the switching power supply circuit is as described in the above embodiments. Since the power chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0119] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A switching power supply circuit, characterized in that, The switching power supply circuit has a continuous conduction mode and an intermittent conduction mode. The circuit includes: A switching circuit, wherein the input terminal of the switching circuit is used to connect to an external power source, and the output terminal of the switching circuit is used to connect to an external load; A switch control drive circuit is electrically connected to the controlled terminal of the switch circuit, and the switch control drive circuit is used to control the operation of the switch circuit; The first feedback loop has its input terminal electrically connected to the output terminal of the switching circuit and the inductor current sampling terminal, respectively, and its output terminal electrically connected to the signal feedback terminal of the switching control drive circuit. The second feedback loop has its input terminal electrically connected to the output terminal of the switching circuit and the connection terminal of the ramp compensation circuit, respectively, and its output terminal electrically connected to the signal feedback terminal of the switching control drive circuit. In the continuous conduction mode, the first feedback loop is activated. The first feedback loop is used to calculate based on the first voltage signal output by the switching circuit and the sampled current value sent by the inductor current sampling terminal to generate a charging signal, and output it to the switch control drive circuit so that the switch control drive circuit controls the switching circuit to work according to the charging signal. In the intermittent conduction mode, the second feedback loop is activated. The second feedback loop is used to calculate based on the second voltage signal output by the switching circuit and the slope compensation voltage signal sent by the connection terminal of the slope compensation circuit to generate a charging signal, and output it to the switch control drive circuit so that the switch control drive circuit controls the switching circuit to work according to the charging signal.

2. The switching power supply circuit as described in claim 1, characterized in that, The first feedback loop also includes A first voltage amplifier, wherein the positive input terminal of the first voltage amplifier is connected to the reference power supply electrical connection terminal, and the negative input terminal of the first voltage amplifier is electrically connected to the output terminal of the switching circuit, is used to amplify and output the first voltage signal and the reference voltage signal received from the external load feedback. A first voltage comparator, wherein the negative input terminal of the first voltage comparator is electrically connected to the first output terminal of the first voltage amplifier, and the positive input terminal of the first voltage comparator is electrically connected to the second output terminal of the first voltage amplifier, is used to output a first voltage amplification signal when the first voltage signal of the amplified external load is less than the amplified reference voltage signal. A current comparator is provided, with its negative input terminal connected to an inductor current sampling terminal and its positive input terminal electrically connected to the output terminal of the first voltage comparator. The comparator is used to calculate based on the sampled current value sent by the inductor current sampling terminal and the received first voltage amplification signal, so that when a preset charging threshold is reached, the charging signal is output to the switch control drive circuit.

3. The switching power supply circuit as described in claim 2, characterized in that, The second feedback loop includes: The second voltage amplifier has its positive input terminal connected to the reference power supply connection terminal, and the negative input terminal of the first voltage amplifier is connected to the output terminal of the switching circuit. It is used to receive the second voltage signal from the external load and the reference voltage signal, amplify them, and then output them. The second voltage comparator has its negative input terminal electrically connected to the first output terminal of the second voltage amplifier, and its positive input terminal electrically connected to the second output terminal of the second voltage amplifier. It is used to output a charging operation comparison signal when the second voltage signal of the amplified external load is greater than the reference voltage signal. The third voltage comparator has its negative input terminal electrically connected to the output terminal of the second voltage comparator, and its positive input terminal connected to the ramp compensation circuit connection terminal. It is used to compare the received charging operation comparison signal with the ramp compensation voltage signal sent by the ramp compensation circuit, so that when the ramp compensation voltage signal is reached, the charging signal is output to the switch control drive circuit.

4. The switching power supply circuit as described in claim 3, characterized in that, The switching power supply circuit also includes: A slope compensation circuit, which is electrically connected to the positive input terminal of the third voltage comparator, is used to provide a slope compensation voltage signal to prevent secondary harmonic oscillations.

5. The switching power supply circuit as described in claim 4, characterized in that, The slope compensation circuit includes: The system comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first current mirror, a second current mirror, a first capacitor, and a working power supply connection terminal, wherein; The input terminals of the first current mirror and the second current mirror are electrically connected to the working power supply connection terminal, respectively. The output terminal of the first current mirror is electrically connected to the source of the first PMOS transistor, the first terminal of the first capacitor, the source of the second PMOS transistor, the drain of the third PMOS transistor, and the positive input terminal of the third voltage comparator, respectively. The output terminal of the second current mirror is electrically connected to the source of the third PMOS transistor. The gate of the third PMOS transistor is electrically connected to the output terminal of the first voltage inverter. The second terminal of the first capacitor, the gate of the first PMOS transistor, the drain of the first PMOS transistor, and the drain of the second PMOS transistor are grounded, respectively. The gate of the second PMOS transistor is electrically connected to the output terminal of the second voltage inverter.

6. The switching power supply circuit as described in claim 1, characterized in that, The switch control drive circuit includes: A multiplexer, wherein the first input terminal of the multiplexer is connected to the output terminal of the first feedback loop, and the second input terminal of the multiplexer is connected to the output terminal of the second feedback loop, for outputting the charging signal received from the first feedback loop or the second feedback loop; The RS controller has its first input terminal connected to the output terminal of the multiplexer, and is used to process and generate a charging control signal when the charging signal is received, and then output it. The logic control and driver are electrically connected to the output of the RS controller and to the controlled terminal of the switching circuit. The logic control and driver are used to process the received charging control signal to generate a charging drive signal to drive the switching circuit to operate in a charging state.

7. The switching power supply circuit as described in claim 6, characterized in that, The switching power supply circuit also includes: A discharge state transition circuit is provided, wherein the input terminal of the discharge state transition circuit is electrically connected to the output terminal of the switching circuit, and the output terminal of the discharge state transition circuit is electrically connected to the second input terminal of the RS controller. The discharge state transition circuit is used to send a discharge signal to the RS controller, and the RS controller generates a discharge control signal and outputs it to control the logic controller and driver to process the discharge control signal to generate a discharge drive signal, thereby driving the switching circuit to work in the discharge state.

8. The switching power supply circuit as described in claim 7, characterized in that, The switching power supply circuit also includes: A sleep state transition circuit is provided, wherein the negative input terminal of the sleep state transition circuit is connected to the inductor current sampling terminal, the positive input terminal of the sleep state transition circuit is connected to the switching circuit, and the output terminal of the sleep state transition circuit is electrically connected to the input terminal of the logic control and driver. When the inductor current is detected to be zero, a sleep control signal is generated to control the logic control and driver to process the sleep control signal to generate a sleep drive signal, thereby driving the switching circuit to operate in a sleep state.

9. The switching power supply circuit as described in claim 8, characterized in that, The switching circuit includes: The first switching transistor has its source connected to an external power supply, its gate electrically connected to the output terminal of the logic control and driver, and its drain electrically connected to the external load. The second switch has its source electrically connected to the drain of the first switch and the external load, its gate electrically connected to the output of the logic control and driver, and its drain electrically connected to the positive input of the sleep state transition circuit. When the logic control and driver outputs a charging drive signal, it controls the first switch to turn on and the second switch to turn off; or when the logic control and driver outputs a discharging drive signal, it controls the first switch to turn off and the second switch to turn on; or when the logic control and driver outputs a sleep drive signal, it controls the first switch and the second switch to turn off.

10. A power supply chip, characterized in that, Includes the switching power supply circuit as described in any one of claims 1-9.

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