Buck converter and power manager

Abstract

The application provides a voltage reduction converter and power manager, wherein the voltage reduction converter comprises: a phase-locked loop circuit for generating a frequency modulation current signal and a synchronous clock signal according to a received external clock signal and a frequency adjustment value output by the frequency modulation element; and at least one channel circuit for outputting a voltage input by an external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency modulation current signal. The application comprises the phase-locked loop circuit and the channel circuit, and the channel circuit outputs the voltage input by the external power supply at the corresponding output frequency according to the frequency modulation current signal and the synchronous clock signal generated by the phase-locked loop circuit, so that the working frequency of the voltage reduction converter is not limited to one frequency, but can be adjusted in a wide range. At a certain working frequency, the working frequency is not affected by working conditions such as input voltage and output voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power management, in particular to a step-down converter and a power manager. BACKGROUND

[0002] Constant on-time control mode is widely used in DC-DC step-down converter because of its simple structure and fast transient response. The traditional control method keeps the on-time unchanged, and when the input voltage or output voltage changes, the duty cycle will also change, resulting in a large change in switching frequency, which cannot be applied to circuits with fixed frequency requirements. To achieve the purpose of fixed switching frequency, adaptive on-time control mode is applied to step-down converter. The circuit can automatically adjust the on-time according to the input voltage and output voltage, so as to keep the duty cycle unchanged, and then keep the switching frequency basically unchanged.

[0003] In the existing adaptive on-time circuit, the switching frequency is related to the specific values of internal resistors, capacitors and other electronic components. Once integrated into the circuit, the switching frequency can only be kept at a fixed value, and the switching frequency cannot be adjusted to adapt to multiple scenarios. Therefore, a step-down converter capable of adjusting the switching frequency is needed. SUMMARY

[0004] The main purpose of the present application is to provide a step-down converter and a power manager, which aims to solve the problem that the traditional step-down converter cannot adjust the switching frequency.

[0005] In view of the above problems, the present application provides a step-down converter, comprising:

[0006] A phase-locked loop circuit, an external clock input end of the phase-locked loop circuit is used to input an external clock signal, and a frequency adjustment input end of the phase-locked loop circuit is used to input a frequency adjustment element; the phase-locked loop circuit is used to generate a frequency adjustment current signal and a synchronous clock signal according to the received external clock signal and the frequency adjustment value output by the frequency adjustment element;

[0007] At least one channel circuit, a clock signal input end of the channel circuit is connected with a synchronous clock output end of the phase-locked loop circuit, a voltage input end of the channel circuit is used to input an external power supply, and a voltage output end is used to input a load; the channel circuit is used to receive and output the voltage input by the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency adjustment current signal.

[0008] Optionally, the number of channel circuits is two.

[0009] The phase-locked loop circuit is specifically used for outputting a first synchronous clock signal and a second synchronous clock signal; the first synchronous clock signal and the second synchronous clock signal are received by two channel circuits respectively; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 180°.

[0010] Optionally, the plurality of buck converters operate in parallel,

[0011] The synchronous clock output end of the phase-locked loop circuit in the previous buck converter is electrically connected with the external clock input end of the next buck converter.

[0012] Alternatively, the external clock input end of the phase-locked loop circuit in each buck converter is used to access the same external clock signal.

[0013] Optionally, the phase-locked loop circuit comprises:

[0014] A selection switch, one end of which is electrically connected with the external clock access end or the frequency modulation element, and the other end of which is electrically connected with the oscillator and the frequency modulation current generating circuit; the selection switch is used to select whether the phase-locked loop circuit accesses the external clock signal or the frequency adjustment value output by the frequency modulation element;

[0015] An oscillator, which is used to receive the frequency adjustment value output by the frequency modulation element, output a synchronous clock signal or output a synchronous clock signal according to the external clock signal;

[0016] A frequency modulation current generating circuit, which is used to receive the frequency adjustment value output by the frequency modulation element and output a frequency modulation current signal or output a frequency modulation current signal according to the external clock signal.

[0017] Optionally, the phase-locked loop circuit further comprises:

[0018] A frequency discriminator, which is electrically connected with the external clock access end and is used to receive the external clock signal, compare the frequency error between the external clock signal and the synchronous clock signal, and output to the low-pass filter;

[0019] A low-pass filter, an input end of which is electrically connected with the frequency discriminator, and an output end of which is connected with the selection switch; the low-pass filter is used to convert the received frequency error into a voltage;

[0020] A frequency divider, which is electrically connected with the frequency discriminator and the oscillator; the frequency divider is used to divide the synchronous clock signal output by the oscillator into a plurality of synchronous clock signals.

[0021] Optionally, the channel circuit comprises:

[0022] A switch circuit, an input end of which is used to access an external power supply; the switch circuit is used to turn on / off the connection between the external power supply and the voltage output end;

[0023] a feedback loop, an input end of the feedback loop being electrically connected with the voltage output end; the feedback loop being configured to output a feedback signal;

[0024] a conduction time generation circuit, an input end of the conduction time generation circuit being connected with a synchronous clock signal, a frequency-modulated current signal, a voltage of an external power supply and an output voltage of the voltage output end; the conduction time generation circuit being configured to receive and output a conduction time signal according to the synchronous clock signal, the frequency-modulated current signal, the voltage of the external power supply and the output voltage of the voltage output end;

[0025] a logic circuit and a driving circuit, the logic circuit and the driving circuit being electrically connected with the switching circuit, the feedback loop and the conduction time generation circuit; the logic circuit and the driving circuit being configured to receive and output a control signal according to the conduction time signal and the feedback signal, so as to control the switching circuit to connect / disconnect the external power supply and the voltage output end.

[0026] Optionally, the conduction time generation circuit comprises:

[0027] an input voltage to current circuit, an input end of the input voltage to current circuit being electrically connected with the voltage of the external power supply; the input voltage to current circuit being configured to convert the input voltage into a first current signal;

[0028] an error current generation circuit, input ends of the error current generation circuit being connected with the synchronous clock signal and the conduction time signal; the error current generation circuit being configured to compare the conduction time signal and the synchronous clock signal, and output an error current;

[0029] a current multiplier, the current multiplier being electrically connected with the error current generation circuit, the voltage to current circuit and the conduction signal inverting circuit; the current multiplier being configured to receive and output a second current signal according to the frequency-modulated current signal, the error current and the first current signal;

[0030] a conduction signal inverting circuit, input ends of the conduction signal inverting circuit being electrically connected with the current multiplier and the output voltage of the voltage output end; the conduction signal inverting circuit being configured to receive and output the conduction time signal according to the second current signal and the output voltage.

[0031] Optionally, the switching circuit comprises a first switch tube and a second switch tube, a source of the first switch tube being connected with the external power supply, a drain of the first switch tube and a drain of the second switch tube being connected with one end of an inductor as a SW node, the other end of the inductor being electrically connected with an output end of the channel circuit, gates of the first switch tube and the second switch tube being electrically connected with the logic circuit and the driving circuit, and a source of the second switch tube being grounded.

[0032] Optionally, the feedback loop comprises an error comparator and a current comparator, the error comparator has an input electrically connected to the reference voltage and the feedback voltage, and an output electrically connected to the current comparator, and the current comparator has an input electrically connected to the SW node and an output electrically connected to the logic circuit and the driving circuit.

[0033] The error comparator is configured to compare the reference voltage and the feedback voltage, and output an error between the reference voltage and the feedback voltage to the current comparator.

[0034] The current comparator is configured to output the feedback signal according to the inductive current signal of the SW node and the error between the reference voltage and the feedback voltage at the end of the inductive discharge.

[0035] The application further provides a power manager comprising the step-down converter.

[0036] The application comprises a phase-locked loop circuit and a channel circuit, the channel circuit outputs the voltage input by the external power supply at a corresponding output frequency according to the frequency modulation current signal and the synchronous clock signal generated by the phase-locked loop circuit, so that the working frequency of the step-down converter is not limited to one frequency, but can be adjusted in a wide range. At a certain working frequency, the working frequency is not affected by the working conditions such as the input voltage and the output voltage. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained according to the structures shown in the drawings without creative labor.

[0038] Figure 1 FIG. 1 is a circuit diagram of a step-down converter according to the present application;

[0039] Figure 2 FIG. 2 is a phase-locked loop circuit diagram of the step-down converter according to the present application;

[0040] Figure 3 FIG. 3 is a channel circuit diagram of the step-down converter according to the present application;

[0041] Figure 4 FIG. 4 is a conduction time control circuit diagram of the step-down converter according to the present application.

[0042] The first double-channel step-down converter 200, the first PLL circuit 101, the frequency discriminator 11, the low-pass filter 12, the selection switch 13, the oscillator 14, the frequency divider 15, the frequency-modulated current generating circuit 16, the channel one 201, the channel two 202, the switch module 21, the logic circuit and driving circuit 22, the feedback loop 23, the on-time generating circuit 24, the second double-channel step-down converter 300, the second PLL circuit 102, the channel three 301, the channel four 302, the input voltage to current module 501, the on signal flipping module 502, the error current generating module 503, and the current multiplier 54.

[0043] The purposes, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0045] It should be noted that all the directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings). If the specific posture changes, the directionality indications also change accordingly.

[0046] In the present application, unless otherwise explicitly specified and limited, the terms “connection”, “fixation” and the like should be understood in a broad sense. For example, “fixation” can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through an intermediate medium; can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0047] In addition, the descriptions such as "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implying the number of the indicated technical features. Therefore, the features defined as "first", "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of the ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0048] Constant on-time control mode is widely used in DC-DC step-down converter because of its simple structure and fast transient response. The traditional control method is to keep the on-time unchanged, when the input voltage or output voltage changes, the duty cycle will also change, resulting in a large change in switching frequency, which cannot be applied to circuits with fixed frequency requirements. In order to achieve the purpose of fixed switching frequency, adaptive on-time control mode is applied to step-down converter, the circuit can automatically adjust the on-time according to the input voltage and output voltage, so as to keep the duty cycle unchanged, and then keep the switching frequency basically unchanged. In the existing adaptive on-time circuit, the switching frequency is related to the specific values of internal resistors, capacitors and other electronic components. Once integrated on the circuit, the switching frequency can only be kept at a fixed value, and the switching frequency cannot be adjusted to adapt to various scenes. Moreover, due to the influence of process, voltage and temperature, the actual switching frequency has a certain deviation.

[0049] Multi-phase step-down converter is a group of parallel step-down power devices. Single-channel step-down converter has only a single output and can only power a single load. Compared with single-phase step-down converter, multi-phase step-down converter has the advantages of reducing input capacitance, output capacitance, improving thermal performance under high load, etc., and becomes the default choice for high-power and high-performance applications. Multi-channel step-down converter has multiple outputs and can have independent input and output voltages, powering each module independently without affecting each other. Different channels can also be connected to each other, with higher performance working modes. For example, when a dual-channel step-down converter is coupled to the same output, ensuring that the switching frequency of the two channels is 180° out of phase can increase the load capacity and reduce the output voltage ripple. In higher phase working modes, more channels are needed. Considering the circuit area, the number of channels of a single step-down converter cannot be too many, so it is necessary to have multiple step-down converters in parallel output to further improve the load capacity and reduce the output voltage ripple.

[0050] To this end, the present application provides a step-down converter, comprising:

[0051] The phase-locked loop circuit has an external clock input end for inputting an external clock signal and a frequency adjustment input end for inputting a frequency adjustment element; the phase-locked loop circuit is used to generate a frequency adjustment current signal and a synchronous clock signal according to the received external clock signal and the frequency adjustment value output by the frequency adjustment element;

[0052] The at least one channel circuit has a clock signal input end connected with the synchronous clock output end of the phase-locked loop circuit, a voltage input end for inputting an external power supply and a voltage output end for inputting a load; the channel circuit is used to receive and output the voltage input by the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency adjustment current signal.

[0053] More specifically, in order to enable the step-down converter to adjust the working frequency at a wide frequency range while reducing the influence of process, voltage, temperature and other factors on the adjustment capability, the application provides a DC-DC step-down converter, which comprises a phase-locked loop circuit (PLL) and at least one channel (n channels, n is an integer greater than or equal to 1).

[0054] The first PLL circuit 101 generates a frequency adjustment current signal IPLL and synchronous clock signals CLK1, CLK2...CLKn required by each channel, and the synchronous clock signals CLK1, CLK2...CLKn of different channels maintain a certain phase difference; each channel receives the synchronous clock signal, the frequency adjustment current signal IPLL and the input voltage VIN of the external power supply, and outputs a voltage signal VOUT at the voltage output end.

[0055] The first PLL circuit 101 has an external clock input end (port MODE) for inputting an external clock signal or being directly grounded, a frequency adjustment input end (port RT) for inputting a frequency adjustment element, thereby generating a clock signal CLK and a frequency adjustment current signal IPLL. The port MODE can be connected with an external clock or be grounded, when being connected with an external clock, the output clock signal is synchronized with the external clock, and when being grounded, the output clock is controlled by the frequency adjustment element connected with the port RT.

[0056] The port MODE is grounded, and the switching frequency is controlled by an external frequency adjustment element. The oscillator 14 in the first PLL circuit 101 generates a synchronous clock signal CLK according to the port RT, and a frequency adjustment current generation module in the first PLL circuit 101 receives the RT signal to generate a frequency adjustment current signal IPLL, which is inversely proportional to the frequency adjustment element RT (the frequency adjustment element is preferably a resistor), and the frequency adjustment current signal IPLL is proportional to the frequency of the output synchronous clock signal CLK.

[0057] PLL is a feedback control system, used to lock the phase of the input signal and generate an output signal with the same frequency and phase as the input signal. It is mainly composed of phase detector, filter and oscillator three parts. When the phase difference between the input signal and the VCO output signal is not zero, the phase detector will produce an error signal. The error signal is filtered by the loop filter to get a smooth DC control voltage.

[0058] This control voltage acts on the VCO, so that the frequency and phase of the output signal change to reduce the phase difference with the input signal. When the phase difference is reduced to zero, the system reaches the lock state, at this time the frequency and phase of the VCO output signal is completely synchronized with the input signal.

[0059] In this application, the first PLL circuit 101 is added with a selection switch 13, a frequency divider 15 and a frequency modulation current generating circuit 16. The establishment of the selection switch 13 enables the first PLL circuit 101 to select the switch frequency controlled by the external frequency modulation element or the external clock signal. When precise control of the switch frequency of the PLL circuit is needed, the external frequency modulation element control mode can be selected, and when synchronization with the external clock signal is needed, the external clock signal control mode can be selected.

[0060] The frequency divider 15 can divide the synchronous clock signal output by the oscillator to several synchronous clock signals, and the step-down converter can form a multi-channel step-down converter (one synchronous clock signal for one channel) or parallel multiple step-down converters (the synchronous clock signal of the previous step-down converter for the clock signal input of the next step-down converter) based on frequency division.

[0061] The frequency modulation current generating circuit 16 generates a frequency modulation current signal IPLL based on the frequency adjustment value output by the selection switch 13. When the selection switch 13 selects the phase-locked loop circuit to access the external clock signal, the frequency adjustment value is a fixed voltage after LPF; when the selection switch 13 selects the external frequency modulation element, the frequency modulation current generating circuit 16 receives the RT signal to generate, which is inversely proportional to the frequency modulation element RT, and the frequency modulation current signal IPLL is proportional to the frequency of the output synchronous clock signal CLK. The frequency modulation current signal IPLL is used for the switch frequency of the channel circuit, so that the working frequency of the step-down converter is not limited to one frequency.

[0062] The channel circuit receives and outputs the voltage inputted by the external power supply at corresponding output frequency according to the synchronous clock signal and the frequency-modulated current signal, which comprises a logic circuit, a switch circuit for turning on / off the connection between the external power supply and the output voltage, and a signal processing circuit for receiving the synchronous clock signal and the frequency-modulated current signal, the signal processing circuit feeds back the synchronous clock signal and the frequency-modulated current signal to the logic circuit, and the logic circuit sends a signal to the switch circuit to turn on / off the connection between the external power supply and the output voltage according to the received signal, so as to control the switching frequency of the step-down converter.

[0063] The application comprises a phase-locked loop circuit and a channel circuit, the channel circuit outputs the voltage inputted by the external power supply at corresponding output frequency according to the frequency-modulated current signal and the synchronous clock signal generated by the phase-locked loop circuit, so that the working frequency of the step-down converter is not limited to one frequency, but can be adjusted in a wide range. At a certain working frequency, the working frequency is not affected by the working conditions such as input voltage and output voltage.

[0064] In an embodiment, as shown in Figure 1 , Figure 1 The number of channel circuits of the first dual-channel step-down converter 200 in

[0065] The phase-locked loop circuit is specifically used for outputting a first synchronous clock signal and a second synchronous clock signal; the first synchronous clock signal and the second synchronous clock signal are respectively received by two channel circuits; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 180°.

[0066] The first dual-channel step-down converter 200 comprises a first PLL circuit 101, a channel one 201 and a channel two 202; the port MODE of the first PLL circuit 101 receives an external synchronous clock, and the port RT is externally connected with an external resistance element; the channel one 201 and the channel two 202 respectively have input ports for receiving a first input voltage VIN1 and a second input voltage VIN2, and output ports VOUT1 and VOUT2 for respectively outputting a first output voltage and a second output voltage, and connecting a load.

[0067] The ports VFB1 and VFB2 detect the first output voltage and the second output voltage respectively, and the ports SW1 and SW2 are connected to the inductors L1 and L2 respectively. The channel one 201 has an input end receiving the first input voltage VIN1, the first clock signal CLK1, the current frequency modulation signal IPLL, and an output end having the port VOUT1, the port SW1 and the port VFB1. The first clock signal CLK1 is the synchronous clock signal of the channel one 201, and the current frequency modulation signal IPLL controls the on-time and thus controls the switching frequency of the channel one 201. Similarly, the channel two 202 has an input end receiving the second input voltage VIN2, the second clock signal CLK2, the current frequency modulation signal IPLL, and an output end having the port VOUT2, the port SW2 and the port VFB2. The second clock signal CLK2 is the synchronous clock of the channel two 202, and the current frequency modulation signal IPLL controls the on-time and thus controls the switching frequency of the channel two 202.

[0068] Those skilled in the art can understand that the example dual-channel buck converter is only an example, and the multi-channel buck converter can have n channels, where n is an integer greater than or equal to 1.

[0069] In the first dual-channel buck converter 200, each channel can independently receive an input voltage and an output voltage. The values and sources of the different input voltages VIN1 and VIN2 can be independent and different, which is very important in the case of energy sharing between two power sources. The values of the output voltages VOUT1 and VOUT2 and the size of the load current can be different, and multiple circuit modules can be independently powered to meet different needs.

[0070] In one embodiment, the first dual-channel buck converter 200 outputs are coupled together and work in two phases to power a load. For example, Figure 1As shown, the circuit is composed of a first dual-channel buck converter 200 and an output load. The values and sources of different input voltages VIN1, VIN2 can be independent and different, the input port MODE is grounded, the port RT is externally connected with a resistance element, and the frequency is controlled by the external resistance element in inverse proportion to the resistance. The frequency of the frequency-modulated current signal IPLL is proportional to the frequency. The output voltages VOUT1, VOUT2 are commonly coupled at the same node, and there is only one output for multiple channels. When operating in two phases, the first PLL circuit 101 outputs clock signals CLK1 and CLK2 with the same frequency and a phase difference of 180°, the working frequency of channel one 201 is synchronized with the first clock signal CLK1, and the working frequency of channel two 202 is synchronized with the second clock signal CLK2, so the working frequency of channel one 201 is the same as that of channel two 202, and the phase difference is 180°. Due to the 180° phase difference in working frequency, when channel one 201 charges the load, channel two 202 discharges, and vice versa when channel one 201 discharges the load, channel two 202 charges, so the voltage ripple is greatly reduced, and the load capacity is doubled, improving the performance.

[0071] Therefore, even if a single circuit is powered, each channel can be coupled to operate in multiple phases, greatly improving performance. In addition, energy can be shared between the two channels, and the electrical energy of the input voltage VIN1 can be output to the load through channel one 201 and also coupled to channel two 202 through the output.

[0072] In an embodiment, the buck converters operate in parallel,

[0073] The synchronous clock output end of the phase-locked loop circuit in the first dual-channel buck converter 200 is electrically connected to the external clock input end of the second dual-channel buck converter 300. The clock signal CLKOUT output by the first PLL circuit 101 in the first dual-channel buck converter 200 is transmitted to the second PLL circuit 102 in the parallel second dual-channel buck converter 300, and the clock signal CLKOUT maintains the same working frequency while having a certain phase difference, so that the working frequency and the control phase between different buck converters can be synchronized to realize parallel multi-phase operation.

[0074] Alternatively, the external clock input end of the phase-locked loop circuit in each buck converter is used to access the same external clock signal.

[0075] The output port of the first PLL circuit 101 outputs a clock signal CLKOUT, and the clock signal CLKOUT has the same clock frequency as the MODE and a constant phase difference. Similarly, as Figure 1As shown, the first dual-channel buck converter 200 and the second dual-channel buck converter 300 have the same structure, and the second dual-channel buck converter 300 includes a second PLL circuit 102, a third channel 301, and a fourth channel 302. In an embodiment, the two first dual-channel buck converters 200 and the second dual-channel buck converter 300 operate in four-phase mode in parallel to supply power to the same load, and the phase difference between CLKOUT and MODE is 90°. The circuit is composed of the first dual-channel buck converter 200 and the output load. The input signal MODE of the first dual-channel buck converter 200 is coupled with an external synchronization clock signal, and the frequency is controlled by the external synchronization clock, while the output clock signal CLKOUT is coupled to the input port MODE of the second dual-channel buck converter 300. CLKOUT and CLK have the same clock frequency, and the phase difference is 90°. Since the clock signals CLK1 and CLK2 inside the second dual-channel buck converter 300 have a phase difference of 180°, and the clock signals CLK3 and CLK4 inside the second dual-channel buck converter 300 have a phase difference of 180°, CLK1, CLK3, CLK2, and CLK4 have the same frequency and a phase difference of 90° from each other.

[0076] Each channel has an input port to receive an input voltage VIN1, VIN2, VIN3, and VIN4, respectively. The output ports VOUT1 to VOUT4, the ports VFB1 to VFB4, and the inductors L1 to L4 of each channel are coupled together to supply power to the same load. Energy is shared among the four channels. In four-phase operation mode, since the four channels are connected in parallel, the outputs are coupled together, the switching clock frequencies are the same, and the phase difference between each other is 90°, and the charging and discharging times of different channels are staggered, the output voltage ripple is reduced to one fourth of the original, the load capacity is four times of the original, and the performance is greatly improved.

[0077] In an embodiment, the phase-locked loop circuit includes:

[0078] The selection switch 13 has one end electrically connected to an external clock input terminal or a frequency adjustment element, and the other end electrically connected to the oscillator 14 and the frequency modulation current generating circuit 16. The selection switch 13 is used to select whether the phase-locked loop circuit is connected to an external clock signal or a frequency adjustment value output by the frequency adjustment element.

[0079] The oscillator 14 is used to receive the frequency adjustment value output by the frequency adjustment element, and output a synchronization clock signal or a synchronization clock signal according to an external clock signal.

[0080] The frequency modulation current generating circuit 16 is used to receive the frequency adjustment value output by the frequency adjustment element, and output a frequency modulation current signal or a frequency modulation current signal according to an external clock signal.

[0081] The frequency and phase detector 11 is electrically connected to the external clock input terminal. It is used to receive the external clock signal, compare the frequency error between the external clock signal and the synchronous clock signal, and output to the low-pass filter 12.

[0082] Low-pass filter 12, the input of low-pass filter 12 is electrically connected to frequency and phase detector 11, and the output is connected to selection switch 13; low-pass filter 12 is used to convert the received frequency error into voltage.

[0083] Frequency divider 15 is electrically connected to frequency and phase detector 11 and oscillator 14; frequency divider 15 is used to divide the synchronous clock signal output by oscillator 14 into multiple synchronous clock signals.

[0084] Figure 2 for Figure 1 The detailed circuit diagram of the first PLL circuit 101 is shown below. Figure 2 As shown, the first PLL circuit 101 includes a frequency phase detector (PFD) 11, a low-pass filter (LC) 12, a selection switch 13, an oscillator 14, a frequency divider 15, and a frequency modulation current generation circuit 16.

[0085] The first PLL circuit 101 has two paths, namely the MODE path and the RT path. The MODE path includes a frequency and phase detector 11 (PFD), a low-pass filter 12 (LC) 12, a selection switch 13, an oscillator 14, a frequency divider 15, and a frequency modulation current generation circuit 16.

[0086] The RT path includes a resistor, a selector switch 13, an oscillator 14, a frequency divider 15, and a frequency modulation current generation circuit 16. The path is controlled by the selector switch 13, with the MODE port input signal serving as the control signal. When an external clock is connected to the MODE port, the selector switch 13 is connected to the MODE path; when the MODE port is grounded, the selector switch 13 is connected to the RT path.

[0087] In one embodiment, the outputs of the first dual-channel buck converter 200 are coupled together and operate in two phases. The MODE port is grounded, and the switching frequency is controlled by an external resistor. With the MODE port grounded, the selector switch 13 is connected to the RT path. The oscillator 14 generates a clock signal f based on the RT port, which is input to the frequency divider 15 to generate the signal CLK and output signals CLK1, CLK2, and CLKOUT. The frequency-modulated current generation module 16 receives the RT signal and generates a frequency-modulated current signal IPLL, which is inversely proportional to the resistor RT. IPLL is directly proportional to the frequency of the output signals CLK1, CLK2, and CLKOUT.

[0088] In one embodiment, the first dual-channel buck converter 200 and the second dual-channel buck converter 300 are coupled together and operate in parallel as four-phase operation. The port MODE is connected to an external synchronization clock, and the operating frequency of each buck converter is synchronized with the external clock. When the port MODE is connected to an external synchronization clock, the selection switch 13 is connected to the MODE path. The frequency error between the external signal and the clock signal CLK output by the frequency divider 15 is compared by the phase-frequency detector 11, and the voltage output to the selection switch 13 is converted by the low-pass filter 12. The oscillator 14 receives the voltage to generate the clock signal f, which is input to the frequency divider 15 to generate the signals CLK and CLK1, CLK2, CLKOUT. The frequency modulation current generation module 16 receives the output voltage of the low-pass filter 12 to generate the frequency modulation current signal IPLL, which is proportional to the frequency.

[0089] In one embodiment, as shown in FIG. 1, the channel circuit includes: Figure 3

[0090] The switch circuit is connected to the external power supply at the input end, and is used to turn on / off the connection between the external power supply and the voltage output end.

[0091] The feedback loop 23 is connected to the voltage output end at the input end, and is used to output a feedback signal.

[0092] The on-time generation circuit 24 is connected to the synchronization clock signal, the frequency modulation current signal, the voltage of the external power supply, and the output voltage of the voltage output end at the input end, and is used to receive and output an on-time signal according to the synchronization clock signal, the frequency modulation current signal, the voltage of the external power supply, and the output voltage of the voltage output end.

[0093] The logic circuit and driving circuit 22 are connected to the switch circuit, the feedback loop 23, and the on-time generation circuit 24, and are used to receive and output a control signal according to the on-time signal and the feedback signal, so as to control the switch circuit to turn on / off the connection between the external power supply and the voltage output end.

[0094] Figure 3 A schematic diagram of the channel 201 of the buck converter is shown in FIG. 2. Each channel includes a switch module 21, a logic circuit and driving circuit 22, a feedback loop 23, and an on-time generation circuit 24. The logic circuit and driving circuit 22 receive the feedback signal Toff of the feedback loop 23 and the on-time signal Ton output by the on-time generation circuit 24, and drive the switch module 21 to convert the input voltage VIN into a constant output voltage VOUT by controlling the on / off of the control tube.

[0095] ​Switching module 21 converts the input voltage VIN into a constant output voltage VOUT by controlling the switching of the control transistors. Logic circuit and drive circuit 22 receive the feedback signal Toff from feedback loop 23 and the output signal Ton from conduction time generation circuit 24, driving the first switching transistor 41 and the second switching transistor 42 of switching module 21 to turn on and off. Conduction time generation circuit 24 has an input port that receives the input voltage VIN, output voltage VOUT, frequency-modulated current signal IPLL, and synchronous clock CLK1. Synchronous clock CLK1 is generated by the first PLL circuit 101, and the conduction time signal Ton is a square wave signal output by conduction time generation circuit 24. The output conduction time signal Ton determines the charging time.

[0096] In one embodiment, the on-time generation circuit 24 includes:

[0097] The input voltage to current conversion circuit is electrically connected to the voltage of an external power source at its input terminal; the input voltage to current conversion circuit is used to convert the input voltage into a first current signal;

[0098] An error current generation circuit is used to compare the conduction time signal and the synchronous clock signal at its input terminal and output an error current.

[0099] The current multiplier 54 is electrically connected to the error current generation circuit, the voltage-to-current circuit, and the conduction signal switching circuit; the current multiplier 54 is used to receive and output a second current signal based on the frequency modulation current signal, the error current, and the first current signal.

[0100] The on-signal switching circuit has its input terminal electrically connected to the current multiplier 54 and the output voltage of the voltage output terminal. The on-signal switching circuit is used to receive and output the on-time signal according to the second current signal and the output voltage.

[0101] The on-time generation circuit 24 has an input port to receive the input voltage VIN, the output voltage VOUT, the frequency-modulated current signal IPLL, and the synchronization clock CLK1. The synchronization clock CLK1 is generated by the first PLL circuit 101, and the on-time signal Ton is a square wave signal output by the on-time generation circuit 24. The output on-time signal Ton determines the length of the charging time.

[0102] Figure 4 The circuit schematic for circuit 24, which generates the conduction time. Figure 4 As shown, the conduction time generation circuit 24 includes an input voltage to current conversion module 501, a conduction signal inversion module 502, an error current generation module 503, and a current multiplier 54.

[0103] The input voltage to current conversion module 501 includes voltage divider resistors R1 and R2, and a voltage feedback structure. The voltage feedback structure includes an operational amplifier, a MOSFET M1, a resistor R3, and a current mirror. The positive terminal of the operational amplifier receives the voltage obtained by voltage division from VIN, the negative terminal is coupled to the first terminal of resistor R3 and the source of MOSFET M1, the output terminal is coupled to the gate of MOSFET, and the second terminal of resistor R3 is grounded. MOSFET M1, resistor R3, and the current mirror form the output branch. The voltage divider resistors R1 and R2 are connected in series to divide the input voltage VIN to obtain the voltage. The voltage is then input to the operational amplifier, and the voltage feedback structure ensures that the voltage drop across resistor R3 equals the voltage input to the operational amplifier. Specifically, the input voltage to current module 501 outputs a current signal proportional to the input voltage VIN. .

[0104] The conduction signal toggling module 502 includes a charging capacitor CTON, a switch, and a voltage comparator. The positive input of the voltage comparator is connected to the output voltage VOUT, and the negative input is connected to the first terminal of the charging capacitor CTON, outputting a signal Ton. The switch is controlled by the output signal Ton. During charging, the switch is open, and current I charges the charging capacitor CTON, causing the voltage at the first terminal of CTON to rise. When the voltage exceeds VOUT, the voltage comparator output signal Ton toggles, the switch closes, and the voltage at the first terminal of CTON drops to zero. The toggled Ton signal is input to the logic circuit and the drive circuit 22, controlling the switch module 21 to switch from charging to discharging. The conduction time signal Ton controls the charging time, specifically the duration... Where I is the charging current, VOUT is the output voltage, and CTON is the charging capacitor.

[0105] The error current generation module 503 includes a frequency and phase detector 11, a charge pump module (PFD / CP), and a voltage feedback structure. The voltage feedback structure includes an operational amplifier, a MOSFET M2, and a resistor R4. The positive input of the operational amplifier is connected to the output of the frequency and phase detector 11 and the charge pump module, the negative input is coupled to the first terminal of resistor R4 and the source of MOSFET M2, and the output is coupled to the gate of the MOSFET. The second terminal of resistor R3 is grounded. MOSFET M2 and resistor R4 form the output branch. The frequency and phase detector 11 and the charge pump module compare the on-time signal Ton with the synchronization clock signal CLK1 and output an error voltage VCO. The voltage feedback structure ensures that the voltage drop across resistor R4 equals the error signal VCO, and the error current generation module 503 outputs an error current proportional to the error signal VCO. .

[0106] The frequency-modulated current signal IPLL comes from the first PLL circuit 101 and is synchronized with the frequency of an external clock. Proportional, that is * where k1 is a constant, is the frequency of the external synchronization clock. The current multiplier 54 multiplies the input current (IPLL+ICO) and Ivin and outputs.

[0107] The conventional conduction circuit module only contains the input voltage to current module 501 and the conduction signal flip-flop module 502. The charging current I=Ivin, and the conduction time where k2 is a constant related to the internal resistance-capacitance element, is the duty cycle. Therefore, the switching frequency The switching frequency is determined by the internal elements, and for the integrated conduction circuit module, the switching frequency cannot be regulated by external elements or signals. Due to the influence of process, power voltage, and temperature, the actual working frequency also deviates. Some circuits only use charge pumps to modulate the charging current ICO to regulate the working frequency, but this structure has a limited frequency range and cannot guarantee high-precision synchronization of the frequency channel.

[0108] In the conduction time generation circuit 24 of the present application, in addition to the input voltage to current module 501 and the conduction signal flip-flop module 502, the error current generation module 503 and the current multiplier 54 are also included. The frequency modulation current signal IPLL and the error current output by the error current generation module 503 are added together and input into the current multiplier 54. The current multiplier 54 multiplies the two input currents and outputs the current I=Ivin*(IPLL+ICO). as the charging current of the conduction signal flip-flop module 502.

[0109] The conduction time is directly proportional to the duty cycle D and inversely proportional to the frequency of the external synchronization clock The switching frequency .

[0110] In general, k1*k2≈1, numerically greater than , the working frequency of the step-down converter The error voltage VCO output by the frequency discriminator and phase detector 11 and the charge pump module detects the error between the switching frequency and the synchronization clock frequency, further fine-tunes the switching frequency within a small range, so that the switching frequency of the channel is the same as the synchronization clock frequency, and at the same time ensures phase locking. The same switching frequency and synchronization clock frequency and phase locking enable the step-down converter to work in multiple phases. In one embodiment, two channels of a single step-down converter are coupled to work in two phases. In one embodiment, two step-down converters are connected in parallel to output and work in four phases with a synchronous external clock signal.

[0111] In an embodiment, the switch circuit comprises a first switch tube and a second switch tube, the source of the first switch tube is connected to the external power supply, the drain of the first switch tube is connected to the drain of the second switch tube and one end of the inductor as the SW node, the other end of the inductor is connected to the output of the pass circuit, the gates of the first switch tube and the second switch tube are connected to the logic circuit and the driving circuit 22, and the source of the second switch tube is connected to the ground.

[0112] The switch module 21 converts the input voltage VIN into a constant output voltage VOUT by controlling the conduction and the closing of the tubes. The switch module 21 comprises a first switch tube 41 and a second switch tube 42. The source of the first switch tube 41 is connected to the input voltage VIN, the drain of the first switch tube 41 is connected to the drain of the second switch tube 42 and the first end of the inductor L as the SW node, the second end of the inductor L is connected to the first end of the resistor Rfb2 to generate the output voltage VOUT, the second end of the resistor Rfb2 is connected to the first end of the resistor Rfb1 to generate the feedback voltage VFB, the second end of the resistor Rfb1 is connected to the ground, and the gates of the first switch tube 41 and the second switch tube 42 are connected to the logic circuit and the driving circuit 22.

[0113] Specifically, when the switch module 21 receives the conduction charging signal of the logic circuit and the driving circuit 22, the first switch tube 41 is opened, the second switch tube 42 is closed, the voltage at the SW node is VIN, the inductor current and the output voltage rise. When the switch module 21 receives the closing discharging signal of the logic circuit and the driving circuit 22, the first switch tube 41 is closed, the second switch tube 42 is opened, the voltage at the SW node is 0, the inductor current and the output voltage fall.

[0114] The logic circuit and the driving circuit 22 receive the feedback signal Toff of the feedback loop 23 and the output conduction time signal Ton of the conduction time generation circuit 24 to drive the conduction and the closing of the first switch tube 41 and the second switch tube 42 of the switch module 21.

[0115] In an embodiment, the feedback loop 23 comprises an error comparator and a current comparator, the input end of the error comparator is connected to the reference voltage and the feedback voltage, the output end of the error comparator is connected to the current comparator, the input end of the current comparator is connected to the SW node, and the output end of the current comparator is connected to the logic circuit and the driving circuit 22.

[0116] The error comparator is used to compare the reference voltage and the feedback voltage, and output the error of the reference voltage and the feedback voltage to the current comparator;

[0117] The current comparator is used to output the feedback signal according to the inductor current signal of the SW node and the error of the reference voltage and the feedback voltage at the end of the inductor discharging.

[0118] The feedback loop 23 comprises an error comparator (EA) 31 and a current comparator (ICMP) 32. The positive input terminal of the error comparator 31 is connected to a reference voltage VREF, the negative input terminal is connected to a feedback voltage VFB, and the output terminal outputs the error between the reference voltage and the feedback voltage. The reference voltage can be from a band-gap reference or an external signal, and the feedback voltage detects the output voltage. The positive input terminal of the current comparator 32 is connected to the output terminal of the error comparator 31, and the negative input terminal is connected to the inductor current signal of the SW node. When the inductor L is discharged, the current comparator 32 outputs a high level Toff. The feedback loop 23 is enabled when the switch module 21 is in the discharging state, and outputs a high level Toff when the threshold is reached. The switch module 21 is switched from the discharging state to the charging state.

[0119] The present application also provides a power manager comprising the buck converter as described above. The buck converter reduces the input voltage to a desired output voltage for supplying a load. The working frequency of the buck converter comprised in the power manager of the present application is not limited to one frequency, but can be adjusted in a wide range. At a certain working frequency, the working frequency is not affected by the working conditions such as the input voltage, the output voltage, etc.

[0120] The above description is only optional embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation, direct / indirect application in other related technical fields, or the like, which is made under the inventive concept of the present application, using the content of the present application specification and drawings, is included in the patent protection scope of the present application.

Claims

1. A step-down converter, characterized by, The application relates to a voltage regulator, comprising: a phase-locked loop circuit, an external clock input end of the phase-locked loop circuit being used for inputting an external clock signal, and a frequency adjustment input end of the phase-locked loop circuit being used for inputting a frequency adjustment element; the phase-locked loop circuit is used for generating a frequency adjustment current signal and at least one synchronous clock signal according to the received external clock signal and the frequency adjustment value output by the frequency adjustment element; wherein when the external clock signal is inputted at the external clock input end, the phase-locked loop circuit generates the frequency adjustment current signal and the at least one synchronous clock signal based on the external clock signal; at least one channel circuit, a clock signal input end of the channel circuit being connected with a synchronous clock output end of the phase-locked loop circuit, a voltage input end of the channel circuit being used for inputting an external power supply, and a voltage output end being used for inputting a load; the channel circuit is used for receiving and outputting the voltage inputted by the external power supply at a corresponding output frequency according to the synchronous clock signal and the frequency adjustment current signal; the number of the channel circuits is two; the phase-locked loop circuit is used for outputting a first synchronous clock signal, a second synchronous clock signal and a frequency adjustment current signal; the first synchronous clock signal and the second synchronous clock signal are respectively received by the two channel circuits, and the frequency adjustment current signal is simultaneously inputted into the input ends of the two channel circuits; wherein the phase difference between the first synchronous clock signal and the second synchronous clock signal is 180 degrees; the voltage regulators are operated in parallel, the synchronous clock output end of the phase-locked loop circuit in a previous voltage regulator is electrically connected with the external clock input end of a next voltage regulator; or the external clock input end of the phase-locked loop circuit in each voltage regulator is used for inputting the same external clock signal; the phase-locked loop circuit comprises: a selection switch, one end of the selection switch being electrically connected with the external clock input end or the frequency adjustment element, and the other end being electrically connected with an oscillator and a frequency adjustment current generating circuit; the selection switch is used for selecting the phase-locked loop circuit to input the external clock signal or the frequency adjustment value output by the frequency adjustment element; the oscillator is used for receiving the frequency adjustment value output by the frequency adjustment element, and outputting a synchronous clock signal or outputting the synchronous clock signal according to the external clock signal; the frequency adjustment current generating circuit is used for receiving the frequency adjustment value output by the frequency adjustment element, and outputting a frequency adjustment current signal or outputting the frequency adjustment current signal according to the external clock signal.

2. The step-down converter of claim 1, wherein, The phase-locked loop circuit further comprises: a frequency discriminator, which is electrically connected with the external clock input end, is used for receiving the external clock signal and comparing the frequency error of the external clock signal and the synchronous clock signal, and outputs to a low-pass filter; the low-pass filter, an input end of the low-pass filter being electrically connected with the frequency discriminator, and an output end being connected with the selection switch; the low-pass filter is used for converting the received frequency error into a voltage; a frequency divider, which is electrically connected with the frequency discriminator and the oscillator; the frequency divider is used for dividing the synchronous clock signal output by the oscillator into multiple synchronous clock signals.

3. The step-down converter of claim 1, wherein, The channel circuit comprises: a switch circuit, an input end of the switch circuit being used for inputting an external power supply; the switch circuit is used for turning on / off the connection between the external power supply and the voltage output end. A feedback loop, an input end of the feedback loop being electrically connected to the voltage output end; the feedback loop being configured to output a feedback signal; A conduction time generation circuit, input ends of the conduction time generation circuit being connected to a synchronous clock signal, a frequency-modulated current signal, a voltage of an external power supply, and an output voltage of the voltage output end; the conduction time generation circuit being configured to receive and output a conduction time signal according to the synchronous clock signal, the frequency-modulated current signal, the voltage of the external power supply, and the output voltage of the voltage output end; A logic circuit and a driving circuit, the logic circuit and the driving circuit being electrically connected to the switching circuit, the feedback loop, and the conduction time generation circuit; the logic circuit and the driving circuit being configured to receive and output a control signal according to the conduction time signal and the feedback signal, so as to control the switching circuit to connect / disconnect the external power supply and the voltage output end.

4. The step-down converter of claim 3, wherein, The conduction time generation circuit comprises: An input voltage-to-current circuit, an input end of the input voltage-to-current circuit being electrically connected to the voltage of the external power supply; the input voltage-to-current circuit being configured to convert the input voltage into a first current signal; An error current generation circuit, input ends of the error current generation circuit being connected to the synchronous clock signal and the conduction time signal; the error current generation circuit being configured to compare the conduction time signal and the synchronous clock signal, and output an error current; A current multiplier, the current multiplier being electrically connected to the error current generation circuit, the voltage-to-current circuit, and a conduction signal inverting circuit; the current multiplier being configured to receive and output a second current signal according to the frequency-modulated current signal, the error current, and the first current signal; The conduction signal inverting circuit, input ends of the conduction signal inverting circuit being electrically connected to the current multiplier and the output voltage of the voltage output end; the conduction signal inverting circuit being configured to receive and output the conduction time signal according to the second current signal and the output voltage.

5. The step-down converter of claim 3, wherein, The switching circuit comprises a first switch tube and a second switch tube, a source of the first switch tube being connected to the external power supply, a drain of the first switch tube and a drain of the second switch tube being connected to one end of an inductor as an SW node, the other end of the inductor being electrically connected to an output end of the pass-through circuit, gates of the first switch tube and the second switch tube being electrically connected to the logic circuit and the driving circuit, and a source of the second switch tube being grounded.

6. The step-down converter of claim 3, wherein, The feedback loop comprises an error comparator and a current comparator, input ends of the error comparator being electrically connected to a reference voltage and a feedback voltage, an output end of the error comparator being electrically connected to the current comparator, and input ends of the current comparator being electrically connected to the SW node, and an output end of the current comparator being electrically connected to the logic circuit and the driving circuit; The error comparator is configured to compare the reference voltage and the feedback voltage, and output an error of the reference voltage and the feedback voltage to the current comparator; The current comparator is configured to output the feedback signal at the end of inductor discharge according to an inductor current signal of the SW node and the error of the reference voltage and the feedback voltage.

7. A power manager, comprising: The buck converter comprises the buck converter according to any one of claims 1-6.

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