Smooth switching loop selector

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a smooth switching loop selector which comprises a bias circuit, four loop comparators connected in parallel and a voltage feedback circuit. The voltage feedback circuit is used for generating a reference voltage according to signals output by the four loop comparators connected in parallel, the four loop comparators connected in parallel are used for being combined with the voltage feedback circuit to generate a composite feedback voltage, and the generated reference voltage and the composite feedback voltage are sent into the error amplifier to control a loop. The loop selection circuit provided by the invention adopts a compensation network multiplexing strategy, stability of four loops is realized through a single Type-II compensation network, and 75% of the layout area of the compensation network is reduced; in addition, by introducing a multi-loop composite feedback design, the smoothness of loop switching is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a smoothly switched loop selector. Background Art

[0002] The constant current and constant voltage charging method is widely used in various power management systems. The main feature of this method is to provide a large charging current in the early stage of charging to accelerate the charging speed. When the battery is close to being fully charged, it switches to floating voltage charging to improve the overall charging efficiency. Because the power management system has multiple feedback loops with different characteristics, each loop must be designed with specific compensation parameters to ensure stability. However, if different compensation resistors and capacitors are used for each control loop, these passive devices will occupy more chip layout area, resulting in increased costs. Summary of the invention

[0003] In view of the complex constant current and constant voltage compensation problem of the traditional power management system, the present invention proposes a smoothly switching loop selector, including a bias circuit, four loop comparators in parallel, and a voltage feedback circuit, wherein the current bias circuit is used to provide a bias voltage for the subsequent circuit, the voltage feedback circuit is used to generate a reference voltage according to the signal output by the four loop comparators in parallel, and the four loop comparators in parallel are used to generate a composite feedback voltage in combination with the voltage feedback circuit, and the generated reference voltage and composite feedback voltage are used to be sent to the error amplifier to control the loop. Further, the bias circuit includes a first MOS tube, a second MOS tube, a first resistor, and a current mirror, wherein:

[0004] One end of the current mirror is grounded, and the other end is connected to one end of the first resistor and the gate of the second MOS tube, and provides a second gate bias voltage for four loop comparators in parallel; the other end of the first resistor is connected to the drain of the second MOS tube and the gate of the first MOS tube, and provides a first gate bias voltage for four loop comparators in parallel; the drain of the first MOS tube is connected to the source of the second MOS tube, and the drain of the first MOS tube is connected to the power supply terminal. Further, the four loop comparators have the same structure, and a bias circuit includes a loop comparator including a third MOS tube, a fourth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a twenty-first MOS tube, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, and a first transistor; wherein:

[0005] The bias circuit provides a bias voltage for the gate of the third MOS tube, the source of the third MOS tube is connected to the power supply terminal, and the drain of the third MOS tube is connected to the source of the fourth MOS tube;

[0006] The bias circuit provides a bias voltage for the gate of the fourth MOS tube, and the drain of the fourth MOS tube is connected with one end of the third resistor and one end of the fourth resistor;

[0007] The other end of the second resistor is connected to the source of the thirteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the first input control terminal, and the drain of the thirteenth MOS transistor is connected to one end of the fourth resistor;

[0008] The other end of the third resistor is connected to the source of the fourteenth MOS transistor, the gate of the fourteenth MOS transistor is connected to the second input control terminal, the drain of the fourteenth MOS transistor is connected to one end of the fifth resistor, one end of the first capacitor and the base of the first transistor, and the other end of the first capacitor is grounded;

[0009] The other end of the fourth resistor and the other end of the fifth resistor are connected together and serve as the output end of the loop comparator;

[0010] The emitter of the first transistor outputs a composite feedback voltage, the collector of the first transistor is connected with the gate and drain of the twenty-first MOS tube, and the source of the twenty-first MOS tube is connected with the power supply terminal.

[0011] Preferably, the composite feedback voltage output by the present invention is compared with a reference voltage, and the obtained output voltage can adjust the peak current of the inductor in the error amplifier circuit.

[0012] Furthermore, a nineteenth resistor is arranged between the composite feedback voltage and the ground terminal.

[0013] Furthermore, each loop comparator represents one of the constant voltage state, the constant current state, the voltage limiting state, and the current limiting state. When the corresponding loop comparator outputs a high level, it represents the current battery state, where:

[0014] The first input control terminal of the loop comparator for indicating the input voltage limiting state is connected to the reference voltage of the voltage limiting state, and the second input control terminal is connected to the sampling voltage of the input voltage;

[0015] A first input control terminal of a loop comparator for indicating an input current limiting state is connected to an input current sampling signal, and a second input control terminal is connected to a reference voltage of an input current limiting state;

[0016] The first input control terminal of the loop comparator for indicating the constant current charging state is connected to the inductor current sampling signal, and the second input control terminal is connected to the reference voltage of the constant current state;

[0017] The first input control terminal of the loop comparator for indicating the constant voltage charging state is connected to the sampling signal of the battery voltage, and the second input control terminal is connected to the reference voltage of the constant voltage state.

[0018] Further, the voltage feedback circuit includes an eleventh MOS transistor, a twelfth MOS transistor, a twentieth MOS transistor, a twenty-fifth MOS transistor, an eighteenth resistor, a twentieth resistor, a fifth transistor, a sixth transistor and a fifth capacitor; wherein:

[0019] The bias circuit provides a bias voltage for the gate of the eleventh MOS tube, the source of the eleventh MOS tube is connected to the power supply terminal, and the drain is connected to the source of the twelfth MOS tube;

[0020] The bias circuit provides a bias voltage for the gate of the twelfth MOS tube, and the drain of the twelfth MOS tube is connected with one end of the eighteenth resistor, one end of the fifth capacitor, and the base of the sixth transistor;

[0021] The other end of the eighteenth resistor is connected to the base and collector of the fifth transistor, and is connected to the output ends of the four loop comparators connected in parallel;

[0022] The emitter of the fifth transistor, the other end of the fifth capacitor and one end of the twentieth resistor are grounded;

[0023] The source of the twenty-fifth MOS transistor is connected to the power supply terminal, and the gate and drain are connected together with the collector of the sixth transistor;

[0024] The emitter of the sixth transistor is connected to the other end of the twentieth resistor and is also connected to the reference voltage terminal.

[0025] Preferably, the present invention generates a base voltage of the sixth transistor Q6 by adding the voltage drop generated on the eighteenth resistor R18 through the bias current of the branch where the eighteenth resistor R18 is located and the VBE of the fifth transistor Q5. This voltage generates current at the emitter of the sixth transistor Q6, and finally generates a voltage drop on the twentieth resistor R20 to form a reference voltage.

[0026] Furthermore, the transistor is an NPN transistor.

[0027] Furthermore, the MOS tube is a P-type MOS tube.

[0028] Furthermore, the voltage of the power supply terminal is 5V.

[0029] The loop selection circuit proposed in the present invention adopts a compensation network multiplexing strategy, and realizes the stability of four loops through a single Type-Ⅱ compensation network, reducing the compensation network layout area by 75%; in addition, by introducing a multi-loop composite feedback design, the smoothness of the loop switching is achieved. A smoothly switching loop selector of the present invention can smoothly switch between constant current charging, constant voltage charging, input current limiting and input voltage limiting loops, and effectively reduce the compensation network layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of a loop selector for smooth switching of the present invention;

[0031] Figure 2 A waveform diagram of switching from CC ring to CV ring of a loop selector for smooth switching of the present invention;

[0032] Among them: M1~M25, the first MOS tube to the twenty-fifth MOS tube; R1~R20, the first resistor to the twentieth resistor; C1~C5, the first capacitor to the fifth capacitor; Q1~Q6, the first transistor to the sixth transistor; IBIAS, a current mirror; LDO_5V, a power supply terminal; GND, a ground terminal; EA_REF, a reference voltage; EA_FB, a composite feedback voltage; REF_VLIM, a reference voltage in a voltage-limited state; FB_VIN, a sampling voltage of an input voltage; FB_IIN, an input current sampling signal; REF_ILIM, a reference voltage in an input current-limited state; FB_ICC, an inductor current sampling signal; REF_ICC, a reference voltage in a constant current state; FB_CV, a sampling signal of a battery voltage; REF_CV, a reference voltage in a constant voltage state. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The present invention proposes a smooth switching loop selector, comprising a bias circuit, four loop comparators connected in parallel and a voltage feedback circuit, wherein the current bias circuit is used to provide a bias voltage for a subsequent circuit, the voltage feedback circuit is used to generate a reference voltage according to the output signals of the four loop comparators connected in parallel, the four loop comparators connected in parallel are used to generate a composite feedback voltage in combination with the voltage feedback circuit, and the generated reference voltage and the composite feedback voltage are used to be sent to a control loop in an error amplifier.

[0035] In this embodiment, each loop comparator represents one of the constant voltage state, the constant current state, the voltage limiting state, and the current limiting state. When the corresponding loop comparator outputs a high level, it represents the current battery state, where:

[0036] The first input control terminal of the loop comparator for indicating the input voltage limiting state is connected to the reference voltage of the voltage limiting state, and the second input control terminal is connected to the sampling voltage of the input voltage;

[0037] A first input control terminal of a loop comparator for indicating an input current limiting state is connected to an input current sampling signal, and a second input control terminal is connected to a reference voltage of an input current limiting state;

[0038] The first input control terminal of the loop comparator for indicating the constant current charging state is connected to the inductor current sampling signal, and the second input control terminal is connected to the reference voltage of the constant current state;

[0039] The first input control terminal of the loop comparator for indicating the constant voltage charging state is connected to the sampling signal of the battery voltage, and the second input control terminal is connected to the reference voltage of the constant voltage state.

[0040] like Figure 1 A smoothly switched loop selector of the present invention comprises a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, a fourth PMOS tube M4, a fifth PMOS tube M5, a sixth PMOS tube M6, a seventh PMOS tube M7, an eighth PMOS tube M8, a ninth PMOS tube M9, a tenth PMOS tube M10, an eleventh PMOS tube M11, a twelfth PMOS tube M12, a thirteenth PMOS tube M13, a fourteenth PMOS tube M14, a fifteenth PMOS tube M15, a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, an eighteenth PMOS tube M18, a nineteenth PMOS tube M19, a twentieth PMOS tube M20, a twenty-first PMOS tube M21, a twenty-second PMOS tube M22, a twenty-third PMOS tube M23, a twenty-fourth PMOS tube M24, a fifteenth PMOS tube M15, a sixteenth PMOS tube M16, a seventeenth PMOS tube M17, an eighteenth PMOS tube M18, a nineteenth PMOS tube M19, a twentieth PMOS tube M20, a twenty-first PMOS tube M21, a twenty-second PMOS tube M22, a twenty-third PMOS tube M23, a twenty-fourth PMOS tube M24 OS transistor M24, twenty-fifth PMOS transistor M25, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, tenth resistor R10, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, eighteenth resistor R18, nineteenth resistor R19, twentieth resistor R20, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, first NPN transistor Q1, second NPN transistor Q2, third NPN transistor Q3, fourth NPN transistor Q4, fifth NPN transistor Q5, sixth NPN transistor Q6; wherein:

[0041] The source of the first PMOS tube is connected to the power supply terminal LDO_5V (a 5V power supply is used in this embodiment), the drain is connected to the source of the second PMOS tube, and the gate is connected to the gate of the third PMOS tube, the gate of the fifth PMOS tube, the gate of the seventh PMOS tube, the gate of the ninth PMOS tube, the gate of the eleventh PMOS tube, the drain of the second PMOS tube, and the upper end of the first resistor;

[0042] The gate of the second PMOS tube is connected to the gate of the fourth PMOS tube, the gate of the sixth PMOS tube, the gate of the eighth PMOS tube, the gate of the tenth PMOS tube, the gate of the twelfth PMOS tube, and the lower end of the first resistor;

[0043] The source of the third PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the fourth PMOS tube;

[0044] The drain of the fourth PMOS tube is connected to the right end of the second resistor and the left end of the third resistor;

[0045] The source of the fifth PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the sixth PMOS tube;

[0046] The drain of the sixth PMOS tube is connected to the right end of the sixth resistor and the left end of the seventh resistor;

[0047] The source of the seventh PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the eighth PMOS tube;

[0048] The drain of the eighth PMOS tube is connected to the right end of the tenth resistor and the left end of the eleventh resistor;

[0049] The source of the ninth PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the tenth PMOS tube;

[0050] The drain of the tenth PMOS tube is connected to the right end of the fourteenth resistor and the left end of the fifteenth resistor;

[0051] The source of the eleventh PMOS tube is connected to the power supply voltage, and the drain is connected to the source of the twelfth PMOS tube;

[0052] The drain of the twelfth PMOS tube is connected to the upper end of the eighteenth resistor, the upper end of the fifth capacitor, and the base of the sixth NPN tube;

[0053] The source of the thirteenth PMOS tube is connected to the left end of the second resistor, the drain is connected to the upper end of the fourth resistor, and the gate is connected to the reference voltage REF_VLIM in the input voltage limiting state;

[0054] The source of the fourteenth PMOS tube is connected to the right end of the third resistor, the drain is connected to the upper end of the fifth resistor, the upper end of the first capacitor, and the base of the first NPN transistor, and the gate is connected to the sampling voltage FB_VIN of the input voltage;

[0055] The source of the fifteenth PMOS tube is connected to the left end of the sixth resistor, the drain is connected to the upper end of the eighth resistor, and the gate is connected to the input signal FB_IIN;

[0056] The source of the sixteenth PMOS tube is connected to the right end of the seventh resistor, the drain is connected to the upper end of the ninth resistor, the upper end of the second capacitor, and the base of the second NPN transistor, and the gate is connected to the input current sampling signal REF_ILIM;

[0057] The source of the seventeenth PMOS tube is connected to the left end of the tenth resistor, the drain is connected to the upper end of the twelfth resistor, and the gate is connected to the inductor current sampling signal FB_ICC;

[0058] The source of the eighteenth PMOS tube is connected to the right end of the eleventh resistor, the drain is connected to the upper end of the thirteenth resistor, the upper end of the third capacitor, and the base of the third NPN transistor, and the gate is connected to the reference voltage REF_ICC in the constant current state;

[0059] The source of the nineteenth PMOS tube is connected to the left end of the fourteenth resistor, the drain is connected to the upper end of the sixteenth resistor, and the gate is connected to the sampling signal FB_CV of the battery voltage;

[0060] The source of the 20th PMOS tube is connected to the right end of the 15th resistor, the drain is connected to the upper end of the 17th resistor, the upper end of the fourth capacitor, and the base of the fourth NPN transistor, and the gate is connected to the reference voltage REF_CV in the constant voltage state;

[0061] The source of the twenty-first PMOS tube is connected to the power supply voltage, and the gate is connected to the drain and the collector of the first NPN transistor;

[0062] The source of the twenty-second PMOS tube is connected to the power supply voltage, and the gate is connected to the drain and the collector of the second NPN transistor;

[0063] The source of the twenty-third PMOS tube is connected to the power supply voltage, and the gate is connected to the drain and the collector of the third NPN transistor;

[0064] The source of the twenty-fourth PMOS tube is connected to the power supply voltage, and the gate is connected to the drain and the collector of the fourth NPN transistor;

[0065] The source of the twenty-fifth PMOS transistor is connected to the power supply voltage, and the gate is connected to the drain and the collector of the sixth NPN transistor;

[0066] The lower end of the fourth resistor is connected to the lower end of the fifth resistor, the lower end of the eighth resistor, the lower end of the ninth resistor, the lower end of the twelfth resistor, the lower end of the thirteenth resistor, the lower end of the sixteenth resistor, the lower end of the seventeenth resistor, the base of the fifth NPN transistor, the collector of the fifth NPN transistor, and the lower end of the eighteenth resistor; the upper end of the nineteenth resistor is connected to the emitter of the fourth NPN transistor, and the lower end is connected to the ground terminal GND;

[0067] The upper end of the twentieth resistor is connected to the emitter of the sixth NPN transistor and the output signal EA_REF, and the lower end is grounded; the lower end of the first capacitor is grounded;

[0068] The lower end of the second capacitor is grounded; the lower end of the third capacitor is grounded;

[0069] The lower end of the fourth capacitor is grounded; the lower end of the fifth capacitor is grounded;

[0070] The emitter of the first NPN transistor is connected to the output composite feedback voltage EA_FB; the emitter of the second NPN transistor is connected to the output composite feedback voltage EA_FB; the emitter of the third NPN transistor is connected to the output composite feedback voltage EA_FB; the emitter of the fourth NPN transistor is connected to the output composite feedback voltage EA_FB; and the emitter of the fifth NPN transistor is connected to the ground terminal.

[0071] This embodiment takes the switching from CC loop to CV loop as an example. Figure 2 When the battery voltage gradually rises, the battery voltage FB_CV obtained by feedback gradually rises and approaches the reference voltage REF_CV. At this time, the base voltage of the fourth NPN transistor gradually increases. In this stage, the fourth NPN transistor and the third NPN transistor are both turned on, resulting in the composite feedback voltage EA_FB being higher than the reference voltage EA_REF. These two voltages will be respectively transmitted to the negative and positive terminals of the loop error amplifier. Subsequently, the output voltage of the error amplifier decreases, and the inductor current also decreases, causing the CC loop to gradually exit. The loop switching process is not the selection of logic signals, but a transition state in which there are two control loops at the same time.

[0072] As time goes by, the battery voltage is gradually filled. When the battery feedback voltage FB_CV is close to the constant voltage loop reference voltage REF_CV, the base voltage of the fourth NPN transistor of the constant voltage loop rises, which introduces an additional current path and injects it into the nineteenth resistor, making EA_FB greater than EA_REF, thereby causing the EA_OUT of the subsequent stage to decrease. According to the peak current control mode, the peak value of the inductor current will gradually decrease, thereby reducing the charging current of the battery. At this time, FB_ICC also gradually decreases, causing the base voltage of the third NPN transistor to drop, and the constant current loop gradually exits. After the constant current loop completely exits, the loop is dominated by the constant voltage loop.

[0073] A diode-connected PMOS tube is designed on the NPN transistors of the four loop comparators connected in parallel in the present invention, and its function is to indicate the current dominant loop. For example, when the CV loop is dominant, the fourth NPN transistor is turned on, the first NPN transistor is turned on, the second NPN transistor is turned on, and the third NPN transistor is turned on and off. The twenty-fourth PMOS tube mirrors the current of the fourth NPN transistor and compares it with the reference current to generate a logic control signal to indicate that the power management system operates in the CV state.

[0074] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A loop selector for smooth switching, characterized in that: It includes a bias circuit, four loop comparators in parallel and a voltage feedback circuit, wherein the current bias circuit is used to provide a bias voltage for the subsequent circuit, the voltage feedback circuit is used to generate a reference voltage according to the output signals of the four loop comparators in parallel, the four loop comparators in parallel are used to generate a composite feedback voltage in combination with the voltage feedback circuit, and the generated reference voltage and composite feedback voltage are used to be sent to the error amplifier control loop.

2. A loop selector for smooth switching according to claim 1, characterized in that: The bias circuit includes a first MOS transistor, a second MOS transistor, a first resistor and a current mirror, wherein: One end of the current mirror is grounded, and the other end is connected with one end of the first resistor and the gate of the second MOS tube, and provides a second gate bias voltage for four loop comparators connected in parallel; the other end of the first resistor is connected with the drain of the second MOS tube and the gate of the first MOS tube, and provides a first gate bias voltage for the four loop comparators connected in parallel; the drain of the first MOS tube is connected with the source of the second MOS tube, and the drain of the first MOS tube is connected to the power supply end.

3. A loop selector for smooth switching according to claim 1, characterized in that: The four loop comparators have the same structure. A bias circuit includes a loop comparator including a third MOS tube, a fourth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a twenty-first MOS tube, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, and a first transistor; wherein: The bias circuit provides a bias voltage for the gate of the third MOS tube, the source of the third MOS tube is connected to the power supply terminal, and the drain of the third MOS tube is connected to the source of the fourth MOS tube; The bias circuit provides a bias voltage for the gate of the fourth MOS tube, and the drain of the fourth MOS tube is connected with one end of the third resistor and one end of the fourth resistor; The other end of the second resistor is connected to the source of the thirteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the first input control terminal, and the drain of the thirteenth MOS transistor is connected to one end of the fourth resistor; The other end of the third resistor is connected to the source of the fourteenth MOS transistor, the gate of the fourteenth MOS transistor is connected to the second input control terminal, the drain of the fourteenth MOS transistor is connected to one end of the fifth resistor, one end of the first capacitor and the base of the first transistor, and the other end of the first capacitor is grounded; The other end of the fourth resistor and the other end of the fifth resistor are connected together and serve as the output end of the loop comparator; The emitter of the first transistor outputs a composite feedback voltage, the collector of the first transistor is connected with the gate and drain of the twenty-first MOS tube, and the source of the twenty-first MOS tube is connected with the power supply terminal.

4. A loop selector for smooth switching according to claim 3, characterized in that: A nineteenth resistor is arranged between the composite feedback voltage and the ground terminal.

5. A loop selector for smooth switching according to claim 3, characterized in that: Each loop comparator represents one of the constant voltage state, constant current state, voltage limit state, and current limit state. When the corresponding loop comparator outputs a high level, it indicates the current battery state, where: The first input control terminal of the loop comparator for indicating the input voltage limiting state is connected to the reference voltage of the voltage limiting state, and the second input control terminal is connected to the sampling voltage of the input voltage; A first input control terminal of a loop comparator for indicating an input current limiting state is connected to an input current sampling signal, and a second input control terminal is connected to a reference voltage of an input current limiting state; The first input control terminal of the loop comparator for indicating the constant current charging state is connected to the inductor current sampling signal, and the second input control terminal is connected to the reference voltage of the constant current state; The first input control terminal of the loop comparator for indicating the constant voltage charging state is connected to the sampling signal of the battery voltage, and the second input control terminal is connected to the reference voltage of the constant voltage state.

6. A loop selector for smooth switching according to claim 1, characterized in that: The voltage feedback circuit includes an eleventh MOS transistor, a twelfth MOS transistor, a twentieth MOS transistor, a twenty-fifth MOS transistor, an eighteenth resistor, a twentieth resistor, a fifth transistor, a sixth transistor and a fifth capacitor; wherein: The bias circuit provides a bias voltage for the gate of the eleventh MOS tube, the source of the eleventh MOS tube is connected to the power supply terminal, and the drain is connected to the source of the twelfth MOS tube; The bias circuit provides a bias voltage for the gate of the twelfth MOS tube, and the drain of the twelfth MOS tube is connected with one end of the eighteenth resistor, one end of the fifth capacitor, and the base of the sixth transistor; The other end of the eighteenth resistor is connected to the base and collector of the fifth transistor, and is connected to the output ends of the four loop comparators connected in parallel; The emitter of the fifth transistor, the other end of the fifth capacitor and one end of the twentieth resistor are grounded; The source of the twenty-fifth MOS transistor is connected to the power supply terminal, and the gate and drain are connected together with the collector of the sixth transistor; The emitter of the sixth transistor is connected to the other end of the twentieth resistor and is also connected to the reference voltage terminal.

7. A loop selector for smooth switching according to claim 3 or 6, characterized in that: The transistor is an NPN transistor.

8. A loop selector for smooth switching according to claim 2, 3 or 6, characterized in that: The MOS tube is a P-type MOS tube.

9. A loop selector for smooth switching according to claim 2, 3 or 6, characterized in that: The voltage at the power supply terminal is 5V.

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