High-speed PWM comparator circuit

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a high-speed PWM comparator circuit, a PWM comparator comprises a comparator main body and a latch unit, the comparator main body adopts a three-stage amplification structure, the first two stages adopt a common source differential pair of a resistor load, and the third stage adopts an amplifier with a current mirror as a load. And the latch unit is directly connected with the output end of the third-stage amplifier of the comparator main body. According to the high-speed PWM comparator circuit designed by the invention, the small signal response speed of the comparator is improved by the first two-stage pre-amplifiers, and the third stage adopts the active load amplifier, so that the gain is improved, and the speed and the precision of a loop are considered; the circuit designed by the invention is simple in structure and low in complexity; the process compatibility is good, and circuit integration is facilitated.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a high-speed PWM comparator circuit. Background Art

[0002] A DC / DC converter is a converter circuit that converts DC to DC. The current mode control structure is widely used due to its fast response speed and system stability, and the periodic overcurrent shutdown better protects the switch tube. The PWM comparator is one of the key modules in the PWM control circuit. Its function is to compare the output voltage and current sampling signal of the error amplifier and output the PWM modulation signal. Summary of the invention

[0003] In order to solve the problems existing in the above prior art, the present invention proposes a high-speed PWM comparator circuit, the PWM comparator includes a comparator body and a latch unit, the comparator body adopts a three-stage amplification structure, the first two stages use a common-source differential pair of a resistive load, and the third stage uses a current mirror as an amplifier of the load, and the latch unit is directly connected to the output end of the third-stage amplifier of the comparator body.

[0004] The first two stages of pre-amplifiers of the high-speed PWM comparator circuit designed by the present invention improve the small signal response speed of the comparator, and the third stage adopts an active load amplifier to improve the gain, taking into account both the speed and accuracy of the loop; the circuit structure designed by the present invention is simple and the complexity is low; the process compatibility of the present invention is good, which is conducive to circuit integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 This is a common flyback power internal architecture diagram;

[0006] Figure 2 A high-speed PWM comparator circuit structure diagram of the present invention;

[0007] in, Figure 1 In: M, N-type MOS tube; T, transformer; C, capacitor; D, diode;

[0008] Figure 2 Middle: MS, the first step-down tube; MSI, the second step-down tube; Md, the third step-down tube;

[0009] M1~M14, the first MOS tube to the fourteenth MOS tube; I1~I4, the first current source to the fourth current source; R1~R9, the first resistor to the ninth resistor; INV1~INV3, the first inverter to the third inverter DETAILED DESCRIPTION

[0010] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0011] The present invention provides a high-speed PWM comparator circuit. The PWM comparator includes a comparator body and a latch unit. The comparator body adopts a three-stage amplification structure. The first two stages use a common-source differential pair of a resistor load and the third stage uses a current mirror as an amplifier load. The latch unit is directly connected to the output end of the third-stage amplifier of the comparator body.

[0012] A common flyback power internal architecture diagram is as follows: Figure 1 As shown, it mainly includes N-type MOS tube M, transformer T, capacitor C, diode D, PWM controller, compensation network and sampling circuit. When N-type MOS tube M is turned on, Vin charges the transformer, the voltage of the transformer secondary side opposite-name end is greater than the same-name end, and diode D is cut off. At this time, capacitor C wants to output energy; when N-type MOS tube M is turned off, the voltage of the transformer secondary side opposite-name end is greater than the same-name end, diode D is turned on, and the transformer provides stored energy to the output. When the output voltage or current changes, the PWM controller chip immediately responds after the sampling circuit and adjusts the opening time of the power tube M to maintain the output voltage at a stable value.

[0013] A specific implementation of a high-speed PWM comparator circuit, such as Figure 2 As shown, the circuit structure includes: a loop information reference level conversion implementation circuit and a PWM comparator circuit; the output end of the loop information reference level conversion implementation circuit is connected to the positive electrode of the PWM comparator, and the negative electrode of the PWM comparator is connected to the SW signal. The high-speed PWM comparator includes a comparator body and a latch unit. The comparator body adopts a three-stage amplification structure, the first two stages use a common source differential pair with a resistor load, and the third stage uses a current mirror as a load amplifier to increase the gain. The positive feedback latch unit is directly connected to the output end of the comparator to form a high-speed PWM comparator.

[0014] A specific implementation of a loop information reference level, the circuit includes a first buck tube MS, a second buck tube MSI, a third buck tube Md, a third inverter INV3, two N-type MOS tubes, namely a ninth MOS tube M9 and a tenth MOS tube M10, two P-type MOS tubes, namely an eleventh MOS tube M11 and a twelfth MOS tube M12, a first triode Q1, a second triode Q2, a third triode Q3, a fourth current source I4, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; wherein:

[0015] The drain of the first step-down tube MS is connected to the external power supply voltage terminal V IN (As an optional implementation, in this embodiment, the external power supply voltage terminal V IN The voltage value is 12V), the gate of the first buck tube MS and the gate of the second buck tube MSI are connected to the power tube feedback voltage terminal V HSDRV Connect to the power tube feedback voltage terminal V HSDRV It is used to control Figure 1 The logic signal of whether the MOS tube M is turned on, V HSDRV When the voltage is high, the upper tube of the PWM circuit, namely the MOS tube M, is turned on, and V HSDRV When the voltage is low, the MOS tube M is turned off; the source of the first step-down tube MS is connected to one end of the seventh resistor R7, the drain of the third step-down tube Md, and the drain of the second step-down tube MSI;

[0016] The source of the second step-down buck tube MSI is connected to the collector of the first transistor Q1; the source of the third step-down tube Md is connected to the SW potential, which provides an internal power supply for the circuit, generally 3.4V, and the other end of the first power supply terminal to the third power supply terminal is connected to the BST level terminal, which provides a voltage higher than the SW potential for the circuit;

[0017] The emitter of the first transistor Q1 is connected to the drain of the ninth MOS transistor M9, and the base of the first transistor Q1 is connected to the source of the eleventh MOS transistor M11, the source of the twelfth MOS transistor M12, and the fourth current source I4;

[0018] The gate of the ninth MOS transistor M9 is connected to the first enabling voltage terminal V C , the first enabling voltage terminal V C Provide an enable signal for the ninth MOS tube M9 and enable it at a low level. In the art, when the voltage value is greater than the set threshold, it is at a high level, otherwise it is at a low level. Generally, the corresponding power supply or power supply end is regarded as a high level, and the ground end is regarded as a low level. The source of the ninth MOS tube M9 is connected to the drain of the tenth MOS tube M10.

[0019] The gate of the tenth MOS tube M10 is connected to the third inverter INV3, and the source of the tenth MOS tube M10 is connected to one end of the eighth resistor R8 and the drain of the eleventh MOS tube M11; the input end of the third inverter is connected to the second enable voltage end, and when the enable port is at a high level, the circuit module subsequently connected thereto works normally, and when the enable port is at a low level, the circuit module subsequently connected thereto enters a sleep mode;

[0020] The gate of the eleventh MOS transistor M11 is connected to the gate of the twelfth MOS transistor M12 and the incident voltage of the second transistor Q2; the emitter of the third transistor Q2 is connected to one end of the ninth resistor R9, and the base of the second transistor Q2 is connected to the emitter of the third transistor Q3; the incident voltage of the third transistor Q3 is connected to the ground GND, and the base of the third transistor Q3 is connected to the periodic ramp voltage terminal V SAW , periodic ramp voltage terminal V SAW Provides a ramp current to the sampling port.

[0021] This embodiment provides a specific implementation of a PWM comparator, such as Figure 2 , which includes a first current source I1, a second current source I2, a third current source I3, six P-type MOS tubes, namely a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, and a sixth MOS tube M6, two N-type MOS tubes, namely a seventh MOS tube M7 and an eighth MOS tube M8, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; wherein:

[0022] The gate of the first MOS transistor M1 is connected to one end of the seventh resistor R7, the source is connected to the first current source I1 and the source of the second MOS transistor M2, and the drain is connected to one end of the first resistor R1 and the gate of the third MOS transistor M3;

[0023] The source of the second MOS tube M2 is connected to the first current source I1, the drain is connected to the second resistor R2 and the gate of the fourth MOS tube M4, and the gate is connected to the SW potential;

[0024] The gate of the third MOS transistor M3 is connected to one end of the first resistor R1, the source is connected to the second current source I2, and the drain is connected to the gates of the third resistor R3 and M5;

[0025] The source of the fourth MOS tube M4 is connected to the second current source I2, the gate is connected to one end of the second resistor R2, and the drain is connected to the fourth resistor R4 and the gate of the sixth MOS tube M6;

[0026] The gate of the fifth MOS tube M5 is connected to one end of the third resistor R3, the source is connected to the third current source I3, the drain is connected to the drain of the eighth MOS tube M8, and the drain of the eighth MOS tube M8 is used as the output of the PWM circuit;

[0027] The gate of the sixth MOS transistor M6 is connected to the fourth resistor R4, the source is connected to the third current source I3, and the drain is connected to the drain of the eighth MOS transistor M8 and the input end of the first inverter INV1;

[0028] The drain of the seventh MOS tube M7 is connected to the gate of the eighth MOS tube M8 and the gate of the seventh MOS tube M7, and the source is connected to the SW potential;

[0029] The drain of the eighth MOS tube M8 is connected to the input end of the first inverter INV1 , and the drain is connected to the SW potential.

[0030] This embodiment also provides a specific implementation of a positive feedback and latch unit. The circuit includes a P-type MOS tube, namely, a thirteenth MOS tube M13, an N-type MOS tube, namely, a fourteenth MOS tube M14, a first inverter INV1, and a second inverter INV2, wherein:

[0031] The source of the thirteenth MOS tube M13 is connected to the BST signal, the first current source I1, the second current source I2, and the third current source I3, and the gate is connected to the output end of the first inverter and the input end of the second inverter, and the output end of the second inverter serves as the output of a high-speed PWM comparator circuit of the present invention;

[0032] The drain of the fourteenth MOS tube M14 is connected to the drain of the fourteenth MOS tube and the input end of the first inverter, the source is connected to the SW level, and the gate is connected to the upper tube conduction signal EN_COMP. The signal is a latch enable port, which is controlled by the latch time defined by the system. The high level of the port clears the output of the PWM of the present invention, and the low level maintains the output of the PWM.

[0033] High-speed PWM comparator structure, the circuit includes two parts: comparator body and latch unit. The PWM comparator adopts a three-stage differential input structure. The first two stages use a common source differential pair with a resistor load as differential input and differential output. This structure has high bandwidth characteristics and meets the large prevention requirements for input signals. The third stage uses a current mirror as a load for the differential input to single-ended output structure to increase the gain. Using a current mirror instead of a resistor as a load can isolate the output from affecting the front-end circuit. The transfer function Gain of the comparator can be written as:

[0034]

[0035] Where s is the variable of the transfer function; R1, R4, and R6 are the resistance values ​​of the first resistor, the fourth resistor, and the sixth resistor, respectively; g m2 , g m4 , g m6 They represent the transconductance of the second MOS tube M2, the fourth MOS tube M4, and the sixth MOS tube M6, respectively. o8 、r o6 They represent the equivalent resistance of the channel modulation effect of the eighth MOS tube M8 and the sixth MOS tube M6, r o8 / / r o6 Represents resistance r o8 With resistor r o6 Resistance after parallel connection; ω p1 ,ω p2 and ωp3 Represents the main pole of each amplifier, 2ω p4 and ω p4 It is used to represent the mirror zero-pole pair of the last differential pair. Since the output node resistance of the first two stages of the comparator is a passive resistance, ω p4 and 2ω p4 The corresponding node resistance is 1 / gm12, so the frequencies corresponding to these zeros and poles are relatively high. At this time, the transfer function Gain and transient response of the comparator can be approximated as:

[0036]

[0037] It can be seen from the above formula that the first two stages of pre-amplification comparators improve the small signal response speed of the comparator. From the perspective of transient state, the speed bottleneck of the comparator lies in the charging speed of the drain node of the eighth MOS tube M8. The first two stages of the pre-amplification structure increase the input of the third stage differential pair and increase the charging current of the node.

[0038] The positive feedback latch unit is directly connected to the output end of the comparator. The latch unit is composed of the thirteenth MOS tube M13, the fourteenth MOS tube M14 and two inverters. When the comparator flips, the first inverter INV1 pulls down the gate potential of the thirteenth MOS tube M13, and the thirteenth MOS tube M13 further pulls up the input voltage of IN1 to form positive feedback. This structure can accelerate the charging and discharging of the drain node of the thirteenth MOS tube M13 in the output flipping stage of the PWM comparator, pull the node up to the BST potential, speed up the response speed of the circuit, and improve the output swing. After the positive feedback structure establishes a steady state, a latch unit is formed. The latch unit latches the output result after each PWM comparator completes the comparison. At this time, the output is no longer affected by the PWM comparator shutdown bias and power stage noise. Only when the holding time thold ends, EN_COMP becomes a high potential. Since the driving capability of the fourteenth MOS tube M14 is significantly greater than that of the thirteenth MOS tube M13, the COMP output will be reset to zero at this time.

[0039] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed PWM comparator circuit, characterized in that: The PWM comparator includes a comparator body and a latch unit. The comparator body adopts a three-stage amplification structure. The first two stages use a common-source differential pair with a resistive load, and the third stage uses a current mirror as an amplifier load. The latch unit is directly connected to the output end of the third-stage amplifier of the comparator body.

2. A high-speed PWM comparator circuit according to claim 1, characterized in that: The comparator body includes the first to eighth MOS tubes, the first to sixth resistors, and the first to third current sources. The first to sixth MOS tubes are P-type MOS tubes, and the seventh to eighth MOS tubes are N-type MOS tubes, wherein: The gate of the first MOS tube is connected to the output end of the loop information reference level conversion circuit output, the source is connected to one end of the first current source and the source of the second MOS tube, and the drain is connected to one end of the first resistor and the gate of the third MOS tube; The drain of the second MOS tube is connected to one end of the second resistor and the gate of the fourth MOS tube, and the gate is connected to the SW signal; The source of the third MOS tube is connected with the source of the fourth MOS tube and one end of the second current source, and the drain is connected with one end of the third resistor and the gate of the fifth MOS tube; The drain of the fourth MOS tube is connected to one end of the fourth resistor and the gate of the sixth MOS tube; The source of the fifth MOS tube is connected to one end of the third current source and the source of the sixth MOS tube, and the drain is connected to the drain and gate of the seventh MOS tube and the gate of the eighth MOS tube; The drain of the sixth MOS tube is connected to the drain of the eighth MOS tube and serves as the output of the comparator body; The other end of the first resistor, the other end of the fourth resistor, and one end of the sixth resistor are connected; the other end of the second resistor, the other end of the third resistor, and one end of the fifth resistor are connected together; The other end of the fifth resistor, the other end of the sixth resistor, the source of the seventh MOS tube, and the source of the eighth MOS tube are connected to the SW signal; The other ends of the first to third current sources are connected to the BST level end.

3. A high-speed PWM comparator circuit according to claim 2, characterized in that: The latch unit includes a thirteenth MOS tube and a fourteenth MOS tube, a first inverter and a second inverter, the thirteenth MOS tube is a P-type MOS tube, and the fourteenth MOS tube is an N-type MOS tube, wherein: The output of the comparator body is connected to the input terminal of the first inverter, the drain of the thirteenth MOS tube, and the drain of the fourteenth MOS tube; The output end of the first inverter is connected to the input end of the second inverter and the gate of the thirteenth MOS tube, and the output end of the second inverter serves as an output end of a high-speed PWM comparator circuit; The source of the thirteenth MOS tube is connected to the BST level terminal; The gate of the fourteenth MOS tube is connected to the first enable signal, and the source of the fourteenth MOS tube is connected to the SW signal.

4. A high-speed PWM comparator circuit according to claim 3, characterized in that: When the comparator flips, the first inverter pulls down the gate potential of the thirteenth MOS tube, and the thirteenth MOS tube pulls up the input voltage of the first inverter to form positive feedback, and a latch unit is formed when the positive feedback forms a steady state.

5. A high-speed PWM comparator circuit according to claim 4, characterized in that: After the PWM comparator completes the comparison, the latch unit is used to latch the comparison result. When the holding time ends and the first enable signal becomes high, the driving force of the fourteenth MOS tube is greater than that of the thirteenth MOS tube, and the latch result is cleared.

6. A high-speed PWM comparator circuit according to claim 2, characterized in that: The loop information reference level conversion realization circuit includes first to third buck tubes, ninth to twelfth MOS tubes, first to third triodes, fourth current source, seventh to ninth resistors and third inverter, wherein: One end of the seventh resistor is used as the output end of the loop information reference level conversion implementation circuit, and the other end is connected to the source of the first buck tube, the drain of the second buck tube and the drain of the third buck tube; The gates of the first buck tube and the second buck tube are connected together and connected to the voltage terminal of the power tube feedback voltage terminal, and the drain of the first buck tube is connected to the external power supply voltage terminal; The source of the third buck tube is connected to the SW signal, the source of the second buck tube is connected to the collector of the first triode, the base of the first triode is connected to the sources of the eleventh MOS tube, the twelfth MOS tube and the fourth current source, and the emitter of the first triode is connected to the drain of the ninth MOS tube; The gate of the ninth MOS tube is connected to the first enable voltage terminal, and the source of the ninth MOS tube is connected to the drain of the tenth MOS tube; The gate of the tenth MOS tube is connected to the output end of the third inverter, the input end of the third inverter is connected to the second enable voltage end, and the source of the tenth MOS tube is connected to one end of the eighth resistor and the drain of the eleventh MOS tube; The gate of the eleventh MOS tube, the gate and drain of the twelfth MOS tube, and the incident electrode of the second triode are connected together, and the emitter of the second triode is connected to one end of the ninth resistor; The other end of the eighth resistor, the other end of the ninth resistor and the incident voltage of the third triode are connected to the ground terminal; The base of the second triode, the emitter of the third triode and the fourth current source are connected, and the base of the third triode is connected to the periodic ramp voltage terminal.

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