Frequency-adaptive duty ratio modulation circuit

Abstract

The invention provides a frequency self-adaptive duty ratio modulation circuit, which receives a variable frequency clock and a reference voltage source, realizes pulse waveform output with a fixed duty ratio, solves the technical problem that the duty ratio of a pulse width modulation circuit cannot be directly controlled, and has the advantages that the duty ratio of the pulse width modulation circuit can be directly controlled besides necessary input clock signals; no extra digital control signal needs to be received to carry out human intervention on the pulse width, and the device has the advantages of few output waveform burrs, small device scale, low power consumption and the like; the duty ratio of the output pulse is irrelevant to the input clock frequency and can be quickly locked along with the change of the clock frequency, the modulation process is simple, and the stability is high.

Description

Technical Field

[0001] The invention belongs to the technical field of duty cycle modulation circuits, and in particular relates to a frequency adaptive duty cycle modulation circuit. Background Art

[0002] As the most mature technology in the design of switching power supply circuits, the duty cycle of the pulse width modulation circuit determines the energy efficiency of the power conversion process in the switching power supply circuit. If the duty cycle is too large, the energy efficiency will be reduced, and if the duty cycle is too small, the driving ability of the output power will be limited. The traditional pulse width modulation circuit is easy to realize the modulation of the pulse width, but in order to ensure that the duty cycle does not change with the frequency, it is necessary to add a digital logic circuit to quantize the pulse width. The device scale, power consumption level and response speed of the pulse width modulation circuit cannot be guaranteed. Summary of the invention

[0003] In order to overcome the deficiencies in the prior art, the inventors have conducted intensive research and provided a frequency-adaptive duty cycle modulation circuit to solve the technical problem that the duty cycle of a pulse width modulation circuit cannot be directly controlled.

[0004] The technical solution provided by the present invention is as follows:

[0005] A frequency adaptive duty cycle modulation circuit, comprising a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first NMOS switch tube NS1, a second NMOS switch tube NS2, a third NMOS switch tube NS3, a first constant current source I1, a second constant current source I2, a third constant current source I3, a fourth constant current source I4, an operational amplifier A1, a D trigger D1, an inverter INV1, a resistor R and a capacitor C;

[0006] The input ends of the first constant current source I1 and the second constant current source I2 are connected to the power supply VDD, the output end of the first constant current source I1 is connected to the drain and gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, the output end of the second constant current source I2 is connected to the drain of the first NMOS switch tube NS1, the input end of the third constant current source I3 is connected to the source of the second NMOS switch tube NS2, the input end of the fourth constant current source I4 is connected to the source of the third NMOS switch tube NS3, and the output ends of the third constant current source I3 and the fourth constant current source I4 are connected to the ground potential;

[0007] The source of the first NMOS tube N1 is connected to the drain of the third NMOS tube N3 and the source of the fourth NMOS tube N4, the drain of the second NMOS tube N2 is connected to the power supply VDD, the source of the second NMOS tube N2 is connected to the drain of the fourth NMOS tube N4, the upper plate of the capacitor C, the drain of the third NMOS switch tube NS3, and the reverse input terminal of the operational amplifier A1, the source of the third NMOS tube N3 is connected to the ground potential, the gate of the third NMOS tube N3 is connected to one end of the resistor R, the lower plate of the capacitor C, and the drain of the second NMOS switch tube NS2, and the gate of the fourth NMOS tube N4 is connected to the other end of the resistor R and the source of the first switch NMOS tube NS1;

[0008] The positive input of operational amplifier A1 receives the reference voltage source V REF The output of operational amplifier A1 is connected to the reset input CLR of D flip-flop D1, the data input of D flip-flop D1 is connected to the power supply VDD, and the clock input CLK of D flip-flop D1 receives the variable frequency clock signal V CLK , the inverting output terminal of the D flip-flop D1 The input end of the inverter INV1 is connected to the gate of the second NMOS switch tube NS2, the output end of the inverter INV1 is connected to the gate of the first NMOS switch tube NS1, the gate of the third NMOS switch tube NS3, and the output end of the duty cycle modulation circuit, and the output end of the duty cycle modulation circuit outputs the duty cycle modulation output signal V PWM .

[0009] In a second aspect, a method for generating a frequency-adaptive duty-cycle modulation output signal adopts the frequency-adaptive duty-cycle modulation circuit described in the first aspect, comprising:

[0010] S1 stable charging: Set the active area of ​​the first and third NMOS switch tubes NS1 and NS3 to be the same and much larger than the active area of ​​the second NMOS switch tube NS2; when the upper plate voltage of capacitor C is lower than the input reference voltage source V REF When the operational amplifier A1 outputs a high potential, the D flip-flop D1 is reset, and the inverting output terminal Output high potential, duty cycle modulated output signal V PWM is low potential; the second NMOS switch tube NS2 is turned on, and the first and third NMOS switch tubes NS1 and NS3 are turned off; the gate voltage of the fourth NMOS tube N4 is equal to the potential of the lower plate of the capacitor and is in the off state; the leakage current of the third NMOS tube N3 is maintained at the current I1; the lower plate of the capacitor begins to discharge with the current I3, and the upper plate is charged with the current I3 through the second NMOS tube N2, the voltage of the upper plate rises linearly, and the lower plate is subjected to the negative feedback of the current and keeps the potential unchanged; the current I1 represents the steady-state current output by the first constant current source I1, and I3 represents the steady-state current output by the third constant current source I3;

[0011] The negative feedback mechanism of charging is as follows: when the charging current of the upper plate of the capacitor C is greater than the discharging current I3 of the lower plate, the potential of the lower plate increases due to the induced positive charge, the current of the third NMOS tube N3 increases exponentially, the fourth NMOS tube N4 is turned on, and the charging speed of the upper plate slows down; when the charging current of the upper plate of the capacitor C is less than the discharging current I3 of the lower plate, the potential of the lower plate decreases due to the accumulation of negative charge, the current of the third NMOS tube N3 decreases exponentially, the gate-source-drain voltage of the first NMOS tube N1 is simultaneously increased, the current of the second NMOS tube N2 increases, and the charging speed of the upper plate is accelerated;

[0012] S2 discharges quickly: receives variable frequency clock signal V CLK After the rising edge, the inverting output terminal of D flip-flop D1 Turns to low potential, duty cycle modulated output signal V PWM is a high potential; the second NMOS switch tube NS2 is turned off, the first and third NMOS switch tubes NS1 and NS3 are turned on, the gate voltage of the fourth NMOS tube N4 is higher than the potential of the lower plate of the capacitor by I2*R, the fourth NMOS tube N4 is briefly turned on, and the upper and lower plates induce positive charges due to the switching of the gate signals of the three NMOS switch tubes, causing the potential to be raised, the lower plate is charged at a speed of current I2, and the upper plate is discharged at a speed greater than the current I2; due to the existence of the discharge negative feedback mechanism, the potential of the lower plate gradually decreases until the current of the third NMOS tube N3 is equal to I1, the potential of the lower plate tends to be stable, and the fourth NMOS tube N4 is turned off, and the rapid discharge ends; I2 represents the steady-state current output by the second constant current source I2, and R is the resistance value of the resistor R;

[0013] The negative feedback mechanism of discharge is as follows: when the discharge current of the upper plate of the capacitor is greater than the charging current I2 of the lower plate, the potential of the lower plate decreases due to the induced negative charge, the current of the third NMOS tube N3 decreases exponentially, the current of the fourth NMOS tube N4 decreases, the gate-source-drain voltage of the first NMOS tube N1 is simultaneously pulled up, and the discharge speed of the upper plate slows down; when the discharge current of the upper plate is less than the charging current I2 of the lower plate, the potential of the lower plate increases due to the accumulation of positive charge, the leakage current of the third NMOS tube N3 increases exponentially, the leakage current of the fourth NMOS tube N4 increases, and the discharge speed of the upper plate accelerates;

[0014] S3 discharges stably: When the fourth NMOS tube N4 is turned off, the duty cycle modulates the output signal V PWM The potential remains high, the upper plate of capacitor C discharges steadily at the current rate of current I2, the potential drops linearly, and the lower plate charges steadily at the current rate of current I2. Due to the negative feedback mechanism, the potential remains unchanged until the potential of the upper plate is lower than the reference voltage source V connected to the positive input terminal of the comparator. REFAfter that, the upper plate starts to charge stably again, repeating the S1 to S3 stages, and continuously outputting the duty cycle modulated output signal V PWM .

[0015] In a third aspect, a switching power supply circuit is provided, wherein the switching power supply circuit comprises the frequency adaptive duty cycle modulation circuit described in the first aspect.

[0016] A frequency adaptive duty cycle modulation circuit provided by the present invention has the following beneficial effects:

[0017] (1) The present invention provides a frequency-adaptive duty cycle modulation circuit, which utilizes the capacitor bootstrap effect and negative feedback mechanism to promote the rapid stabilization of the lower plate potential, and the upper plate voltage upper limit quickly reaches a convergence state. The charge and discharge charge of the lower plate are equal in a single clock cycle, and the output duty cycle is only controlled by the charge and discharge current of the lower plate: D = I2 / (I2+I3), and the output pulse voltage V PWM The duty cycle is stable and does not change with the frequency of the input clock signal.

[0018] (2) The frequency-adaptive duty cycle modulation circuit provided by the present invention does not need to receive additional digital control signals to modulate the pulse width except for the necessary input clock, has few output glitches, small device size and low power consumption;

[0019] (3) The present invention provides a frequency-adaptive duty cycle modulation circuit, in which the duty cycle of the output pulse can be quickly locked following the change of the clock frequency, and the modulation process is simple and has high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a structural diagram of a frequency adaptive duty cycle modulation circuit of the present invention;

[0021] Figure 2 The structure diagram of the duty cycle modulation circuit when the upper plate of the capacitor is in a stable charging state;

[0022] Figure 3 The structure diagram of the duty cycle modulation circuit when the upper plate of the capacitor is in a fast discharge state;

[0023] Figure 4 The structure diagram of the duty cycle modulation circuit when the upper plate of the capacitor is in a stable discharge state;

[0024] Figure 5 The figure is a waveform diagram of an output signal of the frequency adaptive duty cycle modulation circuit of the present invention. DETAILED DESCRIPTION

[0025] The following detailed description of the present invention will make the features and advantages of the present invention more clear and explicit.

[0026] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0027] like Figure 1 As shown, the present invention provides a frequency-adaptive duty cycle modulation circuit, which receives a variable frequency clock signal VCLK and a reference voltage source VREF to generate a duty cycle modulation output signal VPWM. The duty cycle modulation circuit includes a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first NMOS switch tube NS1, a second NMOS switch tube NS2, a third NMOS switch tube NS3, a first constant current source I1, a second constant current source I2, a third constant current source I3, a fourth constant current source I4, an operational amplifier A1, a D trigger D1, an inverter INV1, a resistor R, and a capacitor C.

[0028] The input ends of the first constant current source I1 and the second constant current source I2 are connected to the power supply VDD, the output end of the first constant current source I1 is connected to the drain and gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, the output end of the second constant current source I2 is connected to the drain of the first NMOS switch tube NS1, the input end of the third constant current source I3 is connected to the source of the second NMOS switch tube NS2, the input end of the fourth constant current source I4 is connected to the source of the third NMOS switch tube NS3, and the output ends of the third constant current source I3 and the fourth constant current source I4 are connected to the ground potential;

[0029] The source of the first NMOS tube N1 is connected to the drain of the third NMOS tube N3 and the source of the fourth NMOS tube N4, the drain of the second NMOS tube N2 is connected to the power supply VDD, the source of the second NMOS tube N2 is connected to the drain of the fourth NMOS tube N4, the upper plate of the capacitor C, the drain of the third NMOS switch tube NS3, and the reverse input terminal of the operational amplifier A1, the source of the third NMOS tube N3 is connected to the ground potential, the gate of the third NMOS tube N3 is connected to one end of the resistor R, the lower plate of the capacitor C, and the drain of the second NMOS switch tube NS2, and the gate of the fourth NMOS tube N4 is connected to the other end of the resistor R and the source of the first switch NMOS tube NS1;

[0030] The positive input of operational amplifier A1 receives the reference voltage source V REF The output of operational amplifier A1 is connected to the reset input CLR of D flip-flop D1, the data input of D flip-flop D1 is connected to the power supply VDD, and the clock input CLK of D flip-flop D1 receives the variable frequency clock signal V CLK , the inverting output terminal of the D flip-flop D1 The input end of the inverter INV1 is connected to the gate of the second NMOS switch tube NS2, the output end of the inverter INV1 is connected to the gate of the first NMOS switch tube NS1, the gate of the third NMOS switch tube NS3, and the output end of the duty cycle modulation circuit, and the output end of the duty cycle modulation circuit outputs the duty cycle modulation output signal V PWM .

[0031] The duty cycle modulation circuit modulates the duty cycle of the output signal waveform depending on the three stages of charging and discharging of the upper plate of capacitor C:

[0032] (I) Stable charging: In order to stabilize the upper and lower plate potentials of capacitor C during this process, the active area of ​​the first and third NMOS switch tubes NS1 and NS3 must be set to be the same and much larger than the active area of ​​the second NMOS switch tube NS2. REF When the operational amplifier A1 outputs a high potential, the D flip-flop D1 is reset, and the inverting output terminal Output high potential, duty cycle modulated output signal V PWM is a low potential. Figure 2 As shown, the second NMOS switch tube NS2 is turned on, and the first and third NMOS switch tubes NS1 and NS3 are turned off. The gate voltage of the fourth NMOS tube N4 is equal to the potential of the lower plate of the capacitor, and is in the off state. The leakage current of the third NMOS tube N3 is maintained at I1. The lower plate of the capacitor begins to discharge with the current I3, and the upper plate is charged with the current I3 through the second NMOS tube N2. The voltage of the upper plate rises linearly, and the lower plate is subjected to the negative feedback of the current and keeps the potential unchanged;

[0033] Charging negative feedback mechanism: When the charging current of the upper plate of capacitor C is greater than the discharging current I3 of the lower plate, the potential of the lower plate increases due to the induced positive charge, the current of the third NMOS tube N3 increases exponentially, the fourth NMOS tube N4 is turned on, and the charging speed of the upper plate slows down; when the charging current of the upper plate of capacitor C is less than the discharging current I3 of the lower plate, the potential of the lower plate decreases due to the accumulation of negative charge, the current of the third NMOS tube N3 decreases exponentially, the gate-source-drain voltage of the first NMOS tube N1 is simultaneously pulled up, the current of the second NMOS tube N2 increases, and the charging speed of the upper plate is accelerated;

[0034] (ii) Fast discharge: receiving a variable frequency clock signal V CLK After the rising edge, the inverting output terminal of D flip-flop D1 Turns to low potential, duty cycle modulated output signal V PWM is a high potential. Figure 3As shown, the second NMOS switch tube NS2 is turned off, the first and third NMOS switch tubes NS1 and NS3 are turned on, the gate voltage of the fourth NMOS tube N4 is I2*R higher than the potential of the lower plate of the capacitor, and the fourth NMOS tube N4 is briefly turned on. The upper and lower plates induce positive charges due to the switching of the gate signals of the three NMOS switch tubes, causing the potential to rise. The lower plate is charged at a speed of current I2, and the upper plate is discharged rapidly at a speed greater than the current I2. Due to the existence of the negative feedback mechanism of discharge, the potential of the lower plate gradually decreases until the current of the third NMOS tube N3 is equal to I1, the potential of the lower plate tends to stabilize, and the fourth NMOS tube N4 is turned off, and the rapid discharge ends;

[0035] Discharge negative feedback mechanism: When the discharge current of the upper plate of the capacitor is greater than the charging current I2 of the lower plate, the potential of the lower plate decreases due to the induced negative charge, the current of the third NMOS tube N3 decreases exponentially, the current of the fourth NMOS tube N4 decreases, the gate-source-drain voltage of the first NMOS tube N1 is simultaneously pulled up, and the discharge speed of the upper plate slows down; when the discharge current of the upper plate is less than the charging current I2 of the lower plate, the potential of the lower plate increases due to the accumulation of positive charge, the leakage current of the third NMOS tube N3 increases exponentially, the leakage current of the fourth NMOS tube N4 increases, and the discharge speed of the upper plate increases. The higher the potential of the upper plate in the charging stage, the longer the rapid discharge time;

[0036] (III) Stable discharge: Figure 4 As shown, when the fourth NMOS tube N4 is turned off, the duty cycle modulated output signal V PWM The potential remains high, the upper plate of capacitor C discharges steadily at the current rate of current I2, the potential drops linearly, and the lower plate charges steadily at the current rate of current I2. Due to the negative feedback mechanism, the potential remains unchanged until the potential of the upper plate is lower than the reference voltage source V connected to the positive input terminal of the comparator. REF After that, the upper plate starts to charge stably again, repeating the first to third stages, and continuously outputting the duty cycle modulated output signal V PWM .

[0037] like Figure 5 The figure shows the output signal waveform of the frequency adaptive duty cycle modulation circuit of the present invention. The duty cycle modulation circuit is input with the clock V CLK After the frequency changes, the duty cycle modulates the output signal V because the charge and discharge of the lower plate is controlled to remain unchanged within the unit cycle. PWM The duty cycle does not change with frequency, the duty cycle modulated output signal V PWM The duty cycle is D=I2 / (I2+I3).

[0038] In the duty cycle modulation circuit, the capacitive reactance of capacitor C is much larger than the capacitive reactance of all parasitic capacitors of NMOS transistors connected thereto including the NMOS switch tube. Preferably, the capacitive reactance of capacitor C is at least 10 times the capacitive reactance of the parasitic capacitors of the NMOS tubes and NMOS switch tubes connected thereto.

[0039] The present invention provides a duty cycle modulation circuit that can adaptively adjust the pulse width according to the frequency change of the input clock. The proposed duty cycle modulation circuit overcomes the shortcomings of the prior art, and utilizes the capacitor bootstrap effect and negative feedback mechanism to cause the lower plate potential to stabilize quickly, and the upper plate voltage upper limit quickly reaches a convergence state. The charging charge and the discharging charge of the lower plate are equal in a single clock cycle, and the output duty cycle is only controlled by the charging and discharging current of the lower plate: D=I2 / (I2+I3). In addition to the necessary input clock signal, the present invention does not need to receive additional digital control signals to manually intervene in the pulse width, has few output glitches, a small device size, and low power consumption; the duty cycle of the output pulse of the present invention is independent of the input clock frequency, can be quickly locked following the change of the clock frequency, and has a simple modulation process and high stability.

[0040] The present invention has been described in detail above in conjunction with specific implementations and exemplary examples, but these descriptions cannot be understood as limiting the present invention. Those skilled in the art understand that, without departing from the spirit and scope of the present invention, a variety of equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its implementation methods, all of which fall within the scope of the present invention. The scope of protection of the present invention shall be subject to the attached claims.

[0041] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A frequency adaptive duty cycle modulation circuit, characterized in that: It includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first NMOS switch transistor NS1, a second NMOS switch transistor NS2, a third NMOS switch transistor NS3, a first constant current source I1, a second constant current source I2, a third constant current source I3, a fourth constant current source I4, an operational amplifier A1, a D trigger D1, an inverter INV1, a resistor R and a capacitor C; The input ends of the first constant current source I1 and the second constant current source I2 are connected to the power supply VDD, the output end of the first constant current source I1 is connected to the drain and gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, the output end of the second constant current source I2 is connected to the drain of the first NMOS switch tube NS1, the input end of the third constant current source I3 is connected to the source of the second NMOS switch tube NS2, the input end of the fourth constant current source I4 is connected to the source of the third NMOS switch tube NS3, and the output ends of the third constant current source I3 and the fourth constant current source I4 are connected to the ground potential; The source of the first NMOS tube N1 is connected to the drain of the third NMOS tube N3 and the source of the fourth NMOS tube N4, the drain of the second NMOS tube N2 is connected to the power supply VDD, the source of the second NMOS tube N2 is connected to the drain of the fourth NMOS tube N4, the upper plate of the capacitor C, the drain of the third NMOS switch tube NS3, and the reverse input terminal of the operational amplifier A1, the source of the third NMOS tube N3 is connected to the ground potential, the gate of the third NMOS tube N3 is connected to one end of the resistor R, the lower plate of the capacitor C, and the drain of the second NMOS switch tube NS2, and the gate of the fourth NMOS tube N4 is connected to the other end of the resistor R and the source of the first switch NMOS tube NS1; The positive input of operational amplifier A1 receives the reference voltage source V REF The output of operational amplifier A1 is connected to the reset input CLR of D flip-flop D1, the data input of D flip-flop D1 is connected to the power supply VDD, and the clock input CLK of D flip-flop D1 receives the variable frequency clock signal V CLK , the inverting output terminal of D flip-flop D1 The input end of the inverter INV1 is connected to the gate of the second NMOS switch tube NS2, the output end of the inverter INV1 is connected to the gate of the first NMOS switch tube NS1, the gate of the third NMOS switch tube NS3, and the output end of the duty cycle modulation circuit, and the output end of the duty cycle modulation circuit outputs the duty cycle modulation output signal V PWM .

2. The frequency adaptive duty cycle modulation circuit according to claim 1, characterized in that: The duty cycle modulated output signal V PWM The duty cycle D is D=I2 / (I2+I3), I2 represents the steady-state current output by the second constant current source I2, and I3 represents the steady-state current output by the third constant current source I3.

3. The frequency adaptive duty cycle modulation circuit according to claim 1, characterized in that: The capacitive reactance of the capacitor C is at least 10 times the capacitive reactance of the parasitic capacitors of the NMOS tube and the NMOS switch tube connected thereto.

4. A frequency adaptive duty cycle modulation output signal generation method, characterized in that: The frequency adaptive duty cycle modulation circuit according to any one of claims 1 to 3 comprises: S1 stable charging: Set the active area of ​​the first and third NMOS switch tubes NS1 and NS3 to be the same and much larger than the active area of ​​the second NMOS switch tube NS2; when the upper plate voltage of capacitor C is lower than the input reference voltage source V REF When the operational amplifier A1 outputs a high potential, the D flip-flop D1 is reset, and the inverting output terminal Output high potential, duty cycle modulated output signal V PWM is low potential; the second NMOS switch tube NS2 is turned on, and the first and third NMOS switch tubes NS1 and NS3 are turned off; the gate voltage of the fourth NMOS tube N4 is equal to the potential of the lower plate of the capacitor and is in the off state; the leakage current of the third NMOS tube N3 is maintained at the current I1; the lower plate of the capacitor begins to discharge with the current I3, and the upper plate is charged with the current I3 through the second NMOS tube N2, the voltage of the upper plate rises linearly, and the lower plate is subjected to the negative feedback of the current and keeps the potential unchanged; the current I1 represents the steady-state current output by the first constant current source I1, and I3 represents the steady-state current output by the third constant current source I3; The negative feedback mechanism of charging is as follows: when the charging current of the upper plate of the capacitor C is greater than the discharging current I3 of the lower plate, the potential of the lower plate increases due to the induced positive charge, the current of the third NMOS tube N3 increases exponentially, the fourth NMOS tube N4 is turned on, and the charging speed of the upper plate slows down; when the charging current of the upper plate of the capacitor C is less than the discharging current I3 of the lower plate, the potential of the lower plate decreases due to the accumulation of negative charge, the current of the third NMOS tube N3 decreases exponentially, the gate-source-drain voltage of the first NMOS tube N1 is simultaneously increased, the current of the second NMOS tube N2 increases, and the charging speed of the upper plate is accelerated; S2 discharges quickly: receives variable frequency clock signal V CLK After the rising edge, the inverting output terminal of D flip-flop D1 Turns to low potential, duty cycle modulated output signal V PWM is a high potential; the second NMOS switch tube NS2 is turned off, the first and third NMOS switch tubes NS1 and NS3 are turned on, the gate voltage of the fourth NMOS tube N4 is higher than the potential of the lower plate of the capacitor by I2*R, the fourth NMOS tube N4 is briefly turned on, and the upper and lower plates induce positive charges due to the switching of the gate signals of the three NMOS switch tubes, causing the potential to be raised, the lower plate is charged at a speed of current I2, and the upper plate is discharged at a speed greater than the current I2; due to the existence of the discharge negative feedback mechanism, the potential of the lower plate gradually decreases until the current of the third NMOS tube N3 is equal to I1, the potential of the lower plate tends to be stable, and the fourth NMOS tube N4 is turned off, and the rapid discharge ends; I2 represents the steady-state current output by the second constant current source I2, and R is the resistance value of the resistor R; The negative feedback mechanism of discharge is as follows: when the discharge current of the upper plate of the capacitor is greater than the charging current I2 of the lower plate, the potential of the lower plate decreases due to the induced negative charge, the current of the third NMOS tube N3 decreases exponentially, the current of the fourth NMOS tube N4 decreases, the gate-source-drain voltage of the first NMOS tube N1 is simultaneously pulled up, and the discharge speed of the upper plate slows down; when the discharge current of the upper plate is less than the charging current I2 of the lower plate, the potential of the lower plate increases due to the accumulation of positive charge, the leakage current of the third NMOS tube N3 increases exponentially, the leakage current of the fourth NMOS tube N4 increases, and the discharge speed of the upper plate accelerates; S3 discharges stably: When the fourth NMOS tube N4 is turned off, the duty cycle modulates the output signal V PWM The potential remains high, the upper plate of capacitor C discharges steadily at the current rate of current I2, the potential drops linearly, and the lower plate charges steadily at the current rate of current I2. Due to the negative feedback mechanism, the potential remains unchanged until the potential of the upper plate is lower than the reference voltage source V connected to the positive input terminal of the comparator. REF After that, the upper plate starts to charge stably again, repeating the S1 to S3 stages, and continuously outputting the duty cycle modulated output signal V PWM .

5. A switching power supply circuit, characterized in that: The switching power supply circuit comprises the frequency adaptive duty cycle modulation circuit as claimed in any one of claims 1 to 3.

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