Wide input voltage range current-limiting protection circuit suitable for load switch

Abstract

The invention discloses a wide input voltage range current-limiting protection circuit suitable for a load switch. The wide input voltage range current-limiting protection circuit comprises a power tube MN1, a sampling tube MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload and a capacitor Cload. The whole loop can achieve the current-limiting protection function within the power supply voltage range of 0.5-5.5 V, and the current-limiting protection function can also be achieved when the output is as low as 0V. Different from a current-limiting protection circuit in a traditional load switch, the current-limiting protection circuit has the advantages that a sampling loop is formed by sampling the potential of the drain end, and the problem that the loop cannot work normally when the output voltage is too low due to sampling of the potential of the source end is solved; and secondly, a mode of combining a power supply switching module and a rail-to-rail operational amplifier is designed, so that a current-limiting protection function can be realized in a wider input voltage range.

Description

Technical Field

[0001] The invention relates to a current limiting protection circuit, in particular to a current limiting protection circuit with a wide input voltage range suitable for a load switch, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] Load switches are widely used in various systems that consume high power in standby conditions or need to control power sequencing due to their advantages such as space saving, high integration, and high efficiency. Load switches are in great demand in consumer electronics such as mobile phones and tablets, as well as in automotive systems. For load switches, limiting the maximum current of the subsequent circuit can effectively avoid damage to the device due to excessive line current caused by improper operation or lack of consideration, and can ensure that the load switch maintains a stable and reliable output when processing the subsequent circuit, preventing system overload. A current limiting protection load switch circuit with a wide input voltage range can limit the current of the chip and the subsequent circuit in various common input voltage scenarios, thereby improving the reliability and life of the system.

[0003] A current limiting protection circuit proposed by Chinese patent publication number CN110739835B is as follows Figure 4 As shown, the N-type field effect tube MN1 is a power tube, and MN2 is a sampling tube. Due to the large size difference between the two, the sampling ratio is greatly affected by the over-driving voltage. The voltage drop generated by the resistor R1 and the current source IB1 reduces the threshold difference between the two and improves the accuracy of the sampling ratio. The virtual short characteristic of the operational amplifier 101 makes the source terminal potentials of the MN1 and MN2 tubes equal. The current flowing through the sampling tube MN2 is 1 / N of the current flowing through the power tube MN1. When the output current is too large, the negative input voltage of the error amplifier 102 is the product of the current flowing through the sampling tube and the external resistor RSET. This value is greater than the voltage generated by the preset current source IB2 and the resistor R2. Therefore, the output level of the error amplifier 102 pulls down NGATE, so that the gate-source voltage of the power tube MN1 is reduced, thereby reducing the output current. The loop makes the output current reach stability after exceeding a certain value, and will not increase with the reduction of the load, playing the role of current limiting protection.

[0004] The current limiting protection circuit proposed by Chinese patent publication numbers CN114679040A and CN113009956A is similar to patent CN110739835B. The power tube is a P-type field effect tube. The sampling tube is also used to sample the current on the power tube, convert the sampled current into a voltage, and output it directly or indirectly to the gate end of the power tube through the error amplifier, thereby realizing the current limiting protection function.

[0005] It can be seen that traditional current limiting protection circuits use the internal electrical quantity of the sampling circuit and the conversion and amplification of the electrical quantity to clamp the maximum current output by the power tube to achieve the current limiting protection function. When the power supply voltage is lower than 1V, traditional circuits face the problem that the input voltage common mode range exceeds the power supply range, resulting in incompatibility with a wider input voltage range. At the same time, when the output VOUT is lower than a certain potential, the operational amplifier 101 module clamps the potential at both ends due to the virtual short characteristic, making the MP1 tube unable to work normally, the loop fails, and the current limiting protection function loses its function. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a current limiting protection circuit with a wide input voltage range suitable for a load switch, which can realize the current limiting protection function within the power supply voltage range of 0.5V~5.5V, and can also realize the current limiting protection function when the output is as low as 0V.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: A wide input voltage range current limiting protection circuit suitable for a load switch comprises a power tube MN1, a sampling tube MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload and a capacitor Cload, wherein a first input end of the sampling module, one end of the sampling resistor Rsense and a drain of the power tube MN1 are connected to a power source VIN, a second input end of the sampling module is connected to a voltage signal VH, a third input end of the sampling module is connected to the other end of the sampling resistor Rsense and the drain of the sampling tube MN3, an output end of the sampling module is connected to a positive input end of the error amplifier EA, an inverting input end of the error amplifier EA is connected to a reference voltage VREF, an output end of the error amplifier EA is connected to a gate of the sampling tube MN3 and a gate of the power tube MN1, a source of the sampling tube MN3 is connected to a source of the power tube MN1, one end of the resistor Rload and one end of the capacitor Cload to generate an output voltage VOUT, the other end of the capacitor Rload and the other end of the capacitor Cload are grounded, a first input end of the power switching module is connected to a power source VIN, a second input end of the power switching module is connected to a power source VDD, and an output end of the power switching module generates a voltage signal VH.

[0008] Further, the power switching module includes NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, PMOS tube MP5, PMOS tube MP6, PMOS tube MP7, PMOS tube MP8, PMOS tube MP9, PMOS tube MP10, PMOS tube MP11, PMOS tube MP12, PMOS tube MP13, current source IB3, Schmitt inverter SMIT, inverter INV1, inverter INV2 and inverter INV3, one end of the current source IB3 is connected to the NMOS tube The drain of the OS transistor MN4, the gate of the NMOS transistor MN4, the gate of the NMOS transistor MN5, the gate of the NMOS transistor MN6, the gate of the NMOS transistor MN7, the gate of the NMOS transistor MN8 and the gate of the NMOS transistor MN9 are connected, the drain of the NMOS transistor MN5 is connected to the drain of the PMOS transistor MP2, the gate of the PMOS transistor MP2 and the gate of the PMOS transistor MP3, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP4 and is connected to the power supply VIN as the first input end of the power switching module, the drain of the NMOS transistor MN6 is connected to the drain of the PMOS transistor MP3, the gate of the PMOS transistor MP4 and the drain of the NMOS transistor MN7, the source of the PMOS transistor MP3 is connected as the power switching module. The second input end of the source switching module is connected to the power supply VDD, the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN10, the gate of the NMOS tube MN10 is connected to the voltage signal VINH, the drain of the NMOS tube MN8 is connected to the drain of the PMOS tube MP4 and the input end of the Schmidt inverter SMIT, the drain of the NMOS tube MN9 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP5, the gate of the PMOS tube MP6, the gate of the PMOS tube MP7, the gate of the PMOS tube MP8 and the gate of the PMOS tube MP9, the source of the NMOS tube MN4, the source of the NMOS tube MN5, the source of the NMOS tube MN6 and the source of the NMOS tube MN10 are ... , the source of the NMOS tube MN8 and the source of the NMOS tube MN9 are grounded, the source of the PMOS tube MP5 is connected to the source of the PMOS tube MP6, the source of the PMOS tube MP7, the source of the PMOS tube MP8 and the source of the PMOS tube MP9 and serves as the output end of the power switching module to generate a voltage signal VH, the drain of the PMOS tube MP6 is connected to the control end of the Schmidt inverter SMIT, the drain of the PMOS tube MP7 is connected to the control end of the inverter INV2, the drain of the PMOS tube MP8 is connected to the control end of the inverter INV3, the drain of the PMOS tube MP9 is connected to the control end of the inverter INV1, the output end of the Schmidt inverter SMIT is connected to the input end of the inverter INV2,The output end of the inverter INV2 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the input end of the inverter INV1 and the gate of the PMOS tube MP11 and generates a voltage signal VDDH, the output end of the inverter INV1 is connected to the gate of the PMOS tube MP10 and generates a voltage signal VINH, the source of the PMOS tube MP10 is connected to the source of the PMOS tube MP12 and connected to the power supply VDD, the gate of the PMOS tube MP12 is connected to the voltage signal VINH, the drain of the PMOS tube MP10 is connected to the drain of the PMOS tube MP11, the source of the PMOS tube MP11 is connected to the source of the PMOS tube MP13 and connected to the power supply VIN, the gate of the PMOS tube MP13 is connected to the voltage signal VDDH, the drain of the PMOS tube MP12 is connected to the drain of the PMOS tube MP13 and connected to the voltage signal VH.

[0009] Furthermore, the NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8 and NMOS tube MN9 constitute an N-type current mirror, and the width-to-length ratio of the NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8 and NMOS tube MN9 is 1:1:1:n:1:m.

[0010] Furthermore, the NMOS transistor MN7 and the NMOS transistor MN10 constitute a hysteresis module, the setting of the hysteresis voltage is achieved by changing the value of n, and the limitation of the transient large current during voltage switching is achieved by changing the value of m.

[0011] Furthermore, the PMOS tube MP2 and the PMOS tube MP3 form a first P-type current mirror, and the ratio of the width to length of the PMOS tube MP2 and the PMOS tube MP3 is 1:1.

[0012] Furthermore, the PMOS transistor MP5 , the PMOS transistor MP6 , the PMOS transistor MP7 , the PMOS transistor MP8 , and the PMOS transistor MP9 form a second P-type current mirror.

[0013] Furthermore, the sampling module includes a resistor R3, a resistor R4, a rail-to-rail operational amplifier OP1, an NMOS tube MN11 and a programmable resistor Rset, one end of the resistor R3 serves as a first input end of the sampling module and is connected to a power supply VIN, the other end of the resistor R3 is connected to a non-inverting input end of the rail-to-rail operational amplifier OP1 and a drain of the NMOS tube MN11, the control end of the rail-to-rail operational amplifier OP1 serves as a third input end of the sampling module and is connected to a voltage signal VH, the inverting input end of the rail-to-rail operational amplifier OP1 is connected to one end of the resistor R4, the other end of the resistor R4 serves as a third input end of the sampling module, the output end of the rail-to-rail operational amplifier OP1 is connected to a gate of the NMOS tube MN11, the source of the NMOS tube MN11 is connected to one end of the programmable resistor Rset and serves as an output end of the sampling module, and the other end of the programmable resistor Rset is grounded.

[0014] Furthermore, the rail-to-rail operational amplifier OP1 adopts an auto-zero rail-to-rail input operational amplifier or a rail-to-rail input chopper operational amplifier, and the rail-to-rail operational amplifier OP1 adopts a single-stage operational amplifier or a multi-stage operational amplifier.

[0015] Compared with the prior art, the present invention has the following advantages and effects: the present invention discloses a current limiting protection circuit with a wide input voltage range suitable for a load switch, which realizes a wide input voltage range through a power switching module, thereby solving the problem that the operational amplifier cannot work normally under an ultra-low input voltage; by sampling and converting the drain voltage, the problem that the current limiting loop cannot work normally when the output is short-circuited is solved; compared with traditional current limiting protection circuits, the current limiting protection function realized by the present invention has a wider application range and higher circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention is a schematic diagram of a current limiting protection circuit with a wide input voltage range suitable for a load switch.

[0017] Figure 2 is a circuit diagram of the power switching module of the present invention.

[0018] Figure 3 is a circuit diagram of the sampling module of the present invention.

[0019] Figure 4 The present invention is a schematic diagram of a current limiting protection circuit applicable to a load switch in the prior art. DETAILED DESCRIPTION

[0020] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0021] like Figure 1 As shown, a wide input voltage range current limiting protection circuit suitable for a load switch of the present invention comprises a power tube MN1, a sampling tube MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload and a capacitor Cload, wherein a first input end of the sampling module, one end of the sampling resistor Rsense and a drain of the power tube MN1 are connected to a power source VIN, a second input end of the sampling module is connected to a voltage signal VH, a third input end of the sampling module is connected to the other end of the sampling resistor Rsense and the drain of the sampling tube MN3, an output end of the sampling module is connected to a positive input end of the error amplifier EA, an inverting input end of the error amplifier EA is connected to a reference voltage VREF, an output end of the error amplifier EA is connected to a gate of the sampling tube MN3 and a gate of the power tube MN1, a source of the sampling tube MN3 is connected to a source of the power tube MN1, one end of the resistor Rload and one end of the capacitor Cload and generates an output voltage VOUT, the other end of the capacitor Rload and the other end of the capacitor Cload are grounded, a first input end of the power switching module is connected to a power source VIN, a second input end of the power switching module is connected to a power source VDD, and an output end of the power switching module generates a voltage signal VH.

[0022] The structure and amplification stages of the error amplifier EA are not limited. A folded common-source common-gate operational amplifier, a sleeve common-source common-gate operational amplifier, etc. can be used. The operational amplifier can be a single-stage operational amplifier or a multi-stage operational amplifier. Due to the wide input range of the power supply voltage VIN, in order to ensure the normal operation of the NMOS tube MN11, the voltage of the reference voltage VREF should be low, so the error amplifier EA input pair tube needs to use a P-type field effect tube.

[0023] The error amplifier EA and the rail-to-rail operational amplifier OP1 in the sampling module are reasonably designed so that their open-loop gain does not change with the power supply voltage, so that the current limiting accuracy does not change with the power supply voltage, and the current limiting loop has higher reliability.

[0024] like Figure 2As shown, the power switching module includes NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, PMOS tube MP5, PMOS tube MP6, PMOS tube MP7, PMOS tube MP8, PMOS tube MP9, PMOS tube MP10, PMOS tube MP11, PMOS tube MP12, PMOS tube MP13, current source IB3, Schmitt inverter SMIT, inverter INV1, inverter INV2 and inverter INV3, one end of the current source IB3 is connected to the NMOS tube The drain of the NMOS tube MN4, the gate of the NMOS tube MN4, the gate of the NMOS tube MN5, the gate of the NMOS tube MN6, the gate of the NMOS tube MN7, the gate of the NMOS tube MN8 and the gate of the NMOS tube MN9 are connected, the drain of the NMOS tube MN5 is connected to the drain of the PMOS tube MP2, the gate of the PMOS tube MP2 and the gate of the PMOS tube MP3, the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP4 and is connected to the power source VIN as the first input end of the power switching module, the drain of the NMOS tube MN6 is connected to the drain of the PMOS tube MP3, the gate of the PMOS tube MP4 and the drain of the NMOS tube MN7, the source of the PMOS tube MP3 is connected as the power switching module. The second input end of the switching module is connected to the power supply VDD, the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN10, the gate of the NMOS tube MN10 is connected to the voltage signal VINH, the drain of the NMOS tube MN8 is connected to the drain of the PMOS tube MP4 and the input end of the Schmidt inverter SMIT, the drain of the NMOS tube MN9 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP5, the gate of the PMOS tube MP6, the gate of the PMOS tube MP7, the gate of the PMOS tube MP8 and the gate of the PMOS tube MP9, the source of the NMOS tube MN4, the source of the NMOS tube MN5, the source of the NMOS tube MN6, the source of the NMOS tube MN10, The source of the NMOS tube MN8 and the source of the NMOS tube MN9 are grounded, the source of the PMOS tube MP5 is connected to the source of the PMOS tube MP6, the source of the PMOS tube MP7, the source of the PMOS tube MP8 and the source of the PMOS tube MP9 and serves as the output end of the power switching module to generate a voltage signal VH, the drain of the PMOS tube MP6 is connected to the control end of the Schmidt inverter SMIT, the drain of the PMOS tube MP7 is connected to the control end of the inverter INV2, the drain of the PMOS tube MP8 is connected to the control end of the inverter INV3, the drain of the PMOS tube MP9 is connected to the control end of the inverter INV1, the output end of the Schmidt inverter SMIT is connected to the input end of the inverter INV2,The output end of the inverter INV2 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the input end of the inverter INV1 and the gate of the PMOS tube MP11 and generates a voltage signal VDDH, the output end of the inverter INV1 is connected to the gate of the PMOS tube MP10 and generates a voltage signal VINH, the source of the PMOS tube MP10 is connected to the source of the PMOS tube MP12 and connected to the power supply VDD, the gate of the PMOS tube MP12 is connected to the voltage signal VINH, the drain of the PMOS tube MP10 is connected to the drain of the PMOS tube MP11, the source of the PMOS tube MP11 is connected to the source of the PMOS tube MP13 and connected to the power supply VIN, the gate of the PMOS tube MP13 is connected to the voltage signal VDDH, the drain of the PMOS tube MP12 is connected to the drain of the PMOS tube MP13 and connected to the voltage signal VH.

[0025] NMOS tubes MN4, MN5, MN6, MN7, MN8 and MN9 constitute an N-type current mirror, and the width-to-length ratios of NMOS tubes MN4, MN5, MN6, MN7, MN8 and MN9 are 1:1:1:n:1:m.

[0026] The NMOS transistor MN7 and the NMOS transistor MN10 constitute a hysteresis module. The setting of the hysteresis voltage is achieved by changing the value of n, and the limitation of the transient large current during voltage switching is achieved by changing the value of m.

[0027] The PMOS transistor MP2 and the PMOS transistor MP3 form a first P-type current mirror, and the ratio of the width to length of the PMOS transistor MP2 and the PMOS transistor MP3 is 1:1.

[0028] The PMOS transistor MP5 , the PMOS transistor MP6 , the PMOS transistor MP7 , the PMOS transistor MP8 , and the PMOS transistor MP9 form a second P-type current mirror.

[0029] like Figure 3As shown, the sampling module includes a resistor R3, a resistor R4, a rail-to-rail operational amplifier OP1, an NMOS tube MN11 and a programmable resistor Rset. One end of the resistor R3 serves as the first input end of the sampling module and is connected to the power supply VIN. The other end of the resistor R3 is connected to the non-inverting input end of the rail-to-rail operational amplifier OP1 and the drain of the NMOS tube MN11. The control end of the rail-to-rail operational amplifier OP1 serves as the third input end of the sampling module and is connected to the voltage signal VH. The inverting input end of the rail-to-rail operational amplifier OP1 is connected to one end of the resistor R4. The other end of the resistor R4 serves as the third input end of the sampling module. The output end of the rail-to-rail operational amplifier OP1 is connected to the gate of the NMOS tube MN11. The source of the NMOS tube MN11 is connected to one end of the programmable resistor Rset and serves as the output end of the sampling module. The other end of the programmable resistor Rset is grounded.

[0030] The rail-to-rail operational amplifier OP1 adopts an auto-zero rail-to-rail input operational amplifier or a rail-to-rail input chopper operational amplifier, and the rail-to-rail operational amplifier OP1 adopts a single-stage operational amplifier or a multi-stage operational amplifier.

[0031] The current limiting value of the current limiting protection circuit can be adjusted by modifying the resistance of the off-chip programmable resistor Rset and adjusting the ratio of the current limiting value to the off-chip programmable resistor Rset. The current limiting ratio can be modified by adjusting the resistance of the resistor R3. Different applications require different sampling ratios. In this case, the current limiting value can be kept unchanged by modifying the resistance of the resistor R3.

[0032] The sampling tube MN3 is connected to the gate-source of the power tube MN1, and the gate-source voltage is kept consistent. When the output voltage VOUT is 0V, the current sampling is not affected. When the sampling tube MN3 and the power tube MN1 are in the saturation region, the ratio of their drain-source current is 1:N. The current flowing through the sampling resistor Rsense is 1 / N times the current of the power tube, that is, IOUT / N. Utilizing the "virtual break" characteristic of the input end of the rail-to-rail op amp OP1, the sampling module converts the voltage drop generated on the sampling resistor Rsense into the voltage drop generated on the resistor R3, thereby making the current flowing through the programmable resistor Rset equal to the current flowing through the resistor R3. Utilizing the "virtual short" characteristic of the input end of the error amplifier EA, the voltage drop on the programmable resistor Rset is clamped at VREF, and the following relationship can be obtained: IOUT / N*Rsense=VREF / Rset*R3; When the output current IOUT reaches the current limit value, IOUT=ICL=VREF*R3*N / (RSET*Rsense); The normal operation of the loop needs to ensure that each part of the circuit is in the expected working state. For the wide range input power supply VIN of 0.5V~5.5V, if the rail-to-rail operational amplifier OP1 uses the power supply VIN, when VIN=0.5V, whether the input pair is a P-type field effect tube or an N-type field effect tube, it cannot work properly because the power supply voltage is not enough to support the normal operation of all devices. This is also the main reason that limits the traditional current limiting loop from working in a wide voltage range. For this situation, the power switching module designed by the present invention compares the input power supply VIN with the system power supply VDD and selects the higher signal of the two as the power supply. When VIN is less than VDD, since the gate terminals of PMOS tube MP2 and PMOS tube MP3 are connected, the gate-source voltage of PMOS tube MP3 is greater than the gate-source voltage of PMOS tube MP2. Since the pull-down current mirror NMOS tube MN5 and NMOS tube MN6 have the same size, the drain potential of PMOS tube MP3 is close to VDD, ensuring that the currents of the branches on both sides are equal. At this time, PMOS tube MP4 is turned off, and the input signal of Schmitt inverter is low level. After passing through the logic gate, VDDH is high level, VINH is low level, PMOS tube MP10 and PMOS tube MP12 are turned on, PMOS tube MP11 and PMOS tube MP13 are turned off, and VH output is equal to VDD; similarly, when VIN is greater than VDD, VH output is equal to VIN. The function of the hysteresis module is to ensure that the transient characteristics of output VH are better during the switching process of VIN. The function of the second P-type current mirror is to control the instantaneous current from being too large during the switching process of VIN. The input range of system voltage VDD is 2.5V~5.5V, and VH takes the larger value of VIN1 and VDD. Therefore, the output voltage range of VH is 2.5V~5.5V, which can be used as the power supply of rail-to-rail op amp OP1. The input common-mode voltage range of rail-to-rail op amp OP1 is always smaller than the power supply voltage VH range, so it can ensure that the loop can work normally under a wide input voltage range. Rail-to-rail op amp OP1 needs to adopt rail-to-rail design to meet the input common-mode voltage requirement of 0.5V~5.5V.

[0033] By adjusting the temperature coefficient of the external input reference voltage VREF so that the product of the temperature coefficient of the reference voltage VREF and the temperature coefficient of the resistor R3 is equal to the product of the temperature coefficients of the sampling resistor Rsense and the programmable resistor RSET, the current limit value can be kept constant with temperature.

[0034] The present invention discloses a current limiting protection circuit with a wide input voltage range suitable for a load switch. The wide input voltage range is achieved through a power switching module, thereby solving the problem that an operational amplifier cannot work normally under an ultra-low input voltage. The problem that a current limiting loop cannot work normally under an output short circuit is solved through sampling and conversion of a drain voltage. Compared with a traditional current limiting protection circuit, the current limiting protection function achieved by the present invention has a wider application range and higher circuit reliability.

[0035] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A current limiting protection circuit with a wide input voltage range suitable for a load switch, characterized in that: The invention comprises a power tube MN1, a sampling tube MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload and a capacitor Cload. The first input end of the sampling module, one end of the sampling resistor Rsense and the drain of the power tube MN1 are connected to a power source VIN, the second input end of the sampling module is connected to a voltage signal VH, the third input end of the sampling module is connected to the other end of the sampling resistor Rsense and the drain of the sampling tube MN3, the output end of the sampling module is connected to a positive input end of the error amplifier EA, the negative input end of the error amplifier EA is connected to a reference voltage VREF, the output end of the error amplifier EA is connected to a gate of the sampling tube MN3 and a gate of the power tube MN1, the source of the sampling tube MN3 is connected to a source of the power tube MN1, one end of the resistor Rload and one end of the capacitor Cload to generate an output voltage VOUT, the other end of the capacitor Rload and the other end of the capacitor Cload are grounded, the first input end of the power switching module is connected to a power source VIN, the second input end of the power switching module is connected to a power source VDD, and the output end of the power switching module generates a voltage signal VH.

2. A current limiting protection circuit with a wide input voltage range suitable for a load switch according to claim 1, characterized in that: The power switching module comprises NMOS tube MN4, NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, PMOS tube MP5, PMOS tube MP6, PMOS tube MP7, PMOS tube MP8, PMOS tube MP9, PMOS tube MP10, PMOS tube MP11, PMOS tube MP12, PMOS tube MP13, current source IB3, Schmitt inverter SMIT, inverter INV1, inverter INV2 and inverter INV3. One end of current source IB3 is connected to NMOS tube M The drain of N4, the gate of NMOS tube MN4, the gate of NMOS tube MN5, the gate of NMOS tube MN6, the gate of NMOS tube MN7, the gate of NMOS tube MN8 and the gate of NMOS tube MN9 are connected; the drain of NMOS tube MN5 is connected to the drain of PMOS tube MP2, the gate of PMOS tube MP2 and the gate of PMOS tube MP3; the source of PMOS tube MP2 is connected to the source of PMOS tube MP4 and is connected to the power source VIN as the first input end of the power switching module; the drain of NMOS tube MN6 is connected to the drain of PMOS tube MP3, the gate of PMOS tube MP4 and the drain of NMOS tube MN7; the source of PMOS tube MP3 is used as the power switching module. The second input end of the switching module is connected to the power supply VDD, the source of the NMOS tube MN7 is connected to the drain of the NMOS tube MN10, the gate of the NMOS tube MN10 is connected to the voltage signal VINH, the drain of the NMOS tube MN8 is connected to the drain of the PMOS tube MP4 and the input end of the Schmidt inverter SMIT, the drain of the NMOS tube MN9 is connected to the drain of the PMOS tube MP5, the gate of the PMOS tube MP5, the gate of the PMOS tube MP6, the gate of the PMOS tube MP7, the gate of the PMOS tube MP8 and the gate of the PMOS tube MP9, the source of the NMOS tube MN4, the source of the NMOS tube MN5, the source of the NMOS tube MN6, the source of the NMOS tube MN10, The source of the NMOS tube MN8 and the source of the NMOS tube MN9 are grounded, the source of the PMOS tube MP5 is connected to the source of the PMOS tube MP6, the source of the PMOS tube MP7, the source of the PMOS tube MP8 and the source of the PMOS tube MP9 and serves as the output end of the power switching module to generate a voltage signal VH, the drain of the PMOS tube MP6 is connected to the control end of the Schmidt inverter SMIT, the drain of the PMOS tube MP7 is connected to the control end of the inverter INV2, the drain of the PMOS tube MP8 is connected to the control end of the inverter INV3, the drain of the PMOS tube MP9 is connected to the control end of the inverter INV1, the output end of the Schmidt inverter SMIT is connected to the input end of the inverter INV2,The output end of the inverter INV2 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the input end of the inverter INV1 and the gate of the PMOS tube MP11 and generates a voltage signal VDDH, the output end of the inverter INV1 is connected to the gate of the PMOS tube MP10 and generates a voltage signal VINH, the source of the PMOS tube MP10 is connected to the source of the PMOS tube MP12 and connected to the power supply VDD, the gate of the PMOS tube MP12 is connected to the voltage signal VINH, the drain of the PMOS tube MP10 is connected to the drain of the PMOS tube MP11, the source of the PMOS tube MP11 is connected to the source of the PMOS tube MP13 and connected to the power supply VIN, the gate of the PMOS tube MP13 is connected to the voltage signal VDDH, the drain of the PMOS tube MP12 is connected to the drain of the PMOS tube MP13 and connected to the voltage signal VH.

3. A current limiting protection circuit with a wide input voltage range suitable for a load switch according to claim 2, characterized in that: The NMOS tubes MN4, MN5, MN6, MN7, MN8 and MN9 constitute an N-type current mirror, and the width-to-length ratios of the NMOS tubes MN4, MN5, MN6, MN7, MN8 and MN9 are 1:1:1:n:1:m.

4. A current limiting protection circuit with a wide input voltage range suitable for a load switch according to claim 3, characterized in that: The NMOS transistor MN7 and the NMOS transistor MN10 constitute a hysteresis module, the setting of the hysteresis voltage is achieved by changing the value of n, and the limitation of the transient large current during voltage switching is achieved by changing the value of m.

5. The wide input voltage range current limiting protection circuit suitable for a load switch according to claim 2, characterized in that: The PMOS tube MP2 and the PMOS tube MP3 form a first P-type current mirror, and the ratio of the width to length of the PMOS tube MP2 and the PMOS tube MP3 is 1:

1.

6. A current limiting protection circuit with a wide input voltage range suitable for a load switch according to claim 2, characterized in that: The PMOS transistor MP5 , the PMOS transistor MP6 , the PMOS transistor MP7 , the PMOS transistor MP8 , and the PMOS transistor MP9 form a second P-type current mirror.

7. A current limiting protection circuit with a wide input voltage range suitable for a load switch according to claim 1, characterized in that: The sampling module includes a resistor R3, a resistor R4, a rail-to-rail operational amplifier OP1, an NMOS tube MN11 and a programmable resistor Rset. One end of the resistor R3 serves as a first input end of the sampling module and is connected to a power supply VIN. The other end of the resistor R3 is connected to a positive input end of the rail-to-rail operational amplifier OP1 and a drain of the NMOS tube MN11. The control end of the rail-to-rail operational amplifier OP1 serves as a third input end of the sampling module and is connected to a voltage signal VH. The inverting input end of the rail-to-rail operational amplifier OP1 is connected to one end of the resistor R4. The other end of the resistor R4 serves as a third input end of the sampling module. The output end of the rail-to-rail operational amplifier OP1 is connected to a gate of the NMOS tube MN11. The source of the NMOS tube MN11 is connected to one end of the programmable resistor Rset and serves as an output end of the sampling module. The other end of the programmable resistor Rset is grounded.

8. The current limiting protection circuit with a wide input voltage range suitable for a load switch according to claim 1, characterized in that: The rail-to-rail operational amplifier OP1 adopts an auto-zero rail-to-rail input operational amplifier or a rail-to-rail input chopper operational amplifier, and the rail-to-rail operational amplifier OP1 adopts a single-stage operational amplifier or a multi-stage operational amplifier.

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