A wide input voltage range current limiting protection circuit for load switches

Abstract

This invention discloses a wide input voltage range current limiting protection circuit suitable for load switches, comprising a power transistor MN1, a sampling transistor MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload, and a capacitor Cload. The overall loop of this invention can achieve current limiting protection within a power supply voltage range of 0.5V to 5.5V, and it can also achieve current limiting protection when the output voltage is as low as 0V. This circuit differs from traditional current limiting protection circuits in load switches in two ways: firstly, it samples the drain potential to form a sampling loop, avoiding the problem of the loop failing to function properly when the output voltage is too low due to sampling the source potential; secondly, it designs a combination of a power switching module and a rail-to-rail operational amplifier, achieving current limiting protection within a wider input voltage range.

Description

Technical Field

[0001] This invention relates to a current limiting protection circuit, and more particularly to a wide input voltage range current limiting protection circuit suitable for load switches, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Load switches are widely used in systems with high power consumption in standby mode or requiring power sequencing control due to their space-saving, high integration, and high efficiency. They are in significant demand in consumer electronics such as mobile phones and tablets, as well as automotive systems. For load switches, limiting the maximum current of downstream circuits effectively prevents damage to components due to excessive line current caused by improper operation or insufficient consideration. This ensures that the load switch maintains a stable and reliable output when handling downstream circuits, preventing system overload. A wide input voltage range current-limiting protection load switch circuit can limit the current of chips and downstream circuits under various common input voltage scenarios, improving system reliability and lifespan.

[0003] A current limiting protection circuit is proposed in Chinese Patent Publication No. CN110739835B, such as... Figure 4 As shown, N-type field-effect transistor MN1 is the power transistor, and MN2 is the sampling transistor. Due to the significant size difference between them, the sampling ratio is greatly affected by the overdrive voltage. The voltage drop generated by resistor R1 and current source IB1 reduces the threshold difference between the two transistors, improving the accuracy of the sampling ratio. The virtual short characteristic of op-amp 101 makes the source potentials of transistors MN1 and MN2 equal. The current flowing through sampling transistor MN2 is 1 / N of the current flowing through power transistor MN1. When the output current is too large, the input voltage at the negative terminal of error amplifier 102 is the product of the current flowing through the sampling transistor and the external resistor RSET. This value is greater than the preset voltage generated by current source IB2 and resistor R2. Therefore, the output level of error amplifier 102 pulls down NGATE, reducing the gate-source voltage of power transistor MN1, thereby reducing the output current. The loop ensures that the output current stabilizes after exceeding a certain value and will not increase with the decrease of load, thus playing a current limiting protection role.

[0004] The current limiting protection circuit proposed in Chinese patent publications CN114679040A and CN113009956A is similar to that in patent CN110739835B. The power transistor is a P-type field-effect transistor. It also uses a sampling transistor to sample the current on the power transistor, converts the sampled current into a voltage, and outputs it directly or indirectly to the gate terminal of the power transistor through an error amplifier, thereby realizing the current limiting protection function.

[0005] Therefore, it can be seen that traditional current limiting protection circuits use the internal electrical quantities of the sampling circuit, and through the conversion and amplification of the electrical quantities, clamp the maximum current output of the power transistor to achieve the current limiting protection function. When the power supply voltage is lower than 1V, traditional circuits face the problem that the input voltage common-mode range exceeds the power supply range, resulting in incompatibility with a wide input voltage range. At the same time, when the output VOUT is lower than a certain potential, the op-amp 101 module clamps the potential at both ends due to the virtual short characteristic, which prevents the MP1 transistor from being in normal working state, causing the loop to fail and the current limiting protection function to lose its effect. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a wide input voltage range current limiting protection circuit suitable for load switches, which can realize the current limiting protection function in the power supply voltage range of 0.5V to 5.5V, and can also realize the current limiting protection function when the output is as low as 0V.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A wide input voltage range current limiting protection circuit suitable for load switches includes a power transistor MN1, a sampling transistor MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload, and a capacitor Cload. The first input terminal of the sampling module, one end of the sampling resistor Rsense, and the drain of the power transistor MN1 are connected to the power supply VIN. The second input terminal of the sampling module is connected to the voltage signal VH. The third input terminal of the sampling module is connected to the other end of the sampling resistor Rsense and the drain of the sampling transistor MN3. The output terminal of the sampling module is connected to the non-inverting input terminal of the error amplifier EA. The inverting input terminal of the error amplifier EA is connected to the reference voltage VREF. The output terminal of the error amplifier EA is connected to the gate of the sampling transistor MN3 and the gate of the power transistor MN1. The source of the sampling transistor MN3 is connected to the source of the power transistor MN1, one end of the resistor Rload, and one end of the capacitor Cload to generate an output voltage VOUT. The other ends of the capacitor Rload and the other ends of the capacitor Cload are grounded. The first input terminal of the power switching module is connected to the power supply VIN. The second input terminal of the power switching module is connected to the power supply VDD. The output terminal of the power switching module generates the voltage signal VH.

[0009] Further, the power switching module includes NMOS transistors MN4, MN5, MN6, MN7, MN8, MN9, MN10, PMOS transistors MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, current source IB3, Schmitt trigger inverter SMIT, inverter INV1, inverter INV2, and inverter INV3. One end of current source IB3 is connected to NMOS transistor MN4, MN5, MN6, MN7, MN8, MN9, MN10, PMOS transistors MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, current source IB3, Schmitt trigger inverter SMIT, inverter INV1, inverter INV2, and inverter INV3. The drain of transistor MN4, the gate of NMOS transistor MN4, the gate of NMOS transistor MN5, the gate of NMOS transistor MN6, the gate of NMOS transistor MN7, the gate of NMOS transistor MN8, and the gate of NMOS transistor MN9 are connected. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP2, and the gate of PMOS transistor MP3. The source of PMOS transistor MP2 is connected to the source of PMOS transistor MP4 and serves as the first input terminal of the power switching module, connected to the power supply VIN. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP3, the gate of PMOS transistor MP4, and the drain of NMOS transistor MN7. The source of PMOS transistor MP3 serves as the power supply VIN. The second input terminal of the source switching module is connected to the power supply VDD. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN10. The gate of NMOS transistor MN10 is connected to the voltage signal VINH. The drain of NMOS transistor MN8 is connected to the drain of PMOS transistor MP4 and the input terminal of Schmitt trigger inverter SMIT. The drain of NMOS transistor MN9 is connected to the drain, gate, MP5, MP6, MP7, MP8, and MP9 of PMOS transistors. The sources of NMOS transistors MN4, MN5, MN6, and MN10 are also connected. The sources of NMOS transistors MN8 and MN9 are grounded. The sources of PMOS transistors MP5, MP6, MP7, MP8, and MP9 are connected and serve as the output of the power switching module to generate the voltage signal VH. The drain of PMOS transistor MP6 is connected to the control terminal of Schmitt trigger inverter SMIT, the drain of PMOS transistor MP7 is connected to the control terminal of inverter INV2, the drain of PMOS transistor MP8 is connected to the control terminal of inverter INV3, and the drain of PMOS transistor MP9 is connected to the control terminal of inverter INV1. The output of Schmitt trigger inverter SMIT is connected to the input of inverter INV2.The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV1 and the gate of PMOS transistor MP11, generating a voltage signal VDDH. The output of inverter INV1 is connected to the gate of PMOS transistor MP10, generating a voltage signal VINH. The source of PMOS transistor MP10 is connected to the source of PMOS transistor MP12 and connected to the power supply VDD. The gate of PMOS transistor MP12 is connected to the voltage signal VINH. The drain of PMOS transistor MP10 is connected to the drain of PMOS transistor MP11. The source of PMOS transistor MP11 is connected to the source of PMOS transistor MP13 and connected to the power supply VIN. The gate of PMOS transistor MP13 is connected to the voltage signal VDDH. The drain of PMOS transistor MP12 is connected to the drain of PMOS transistor MP13 and connected to the voltage signal VH.

[0010] Furthermore, the NMOS transistors MN4, MN5, MN6, MN7, MN8, and MN9 constitute an N-type current mirror, and the width-to-length ratio of the NMOS transistors MN4, MN5, MN6, MN7, MN8, and MN9 is 1:1:1:n:1:m.

[0011] Furthermore, the NMOS transistors MN7 and MN10 constitute a hysteresis module. The hysteresis voltage is set by changing the value of n, and the transient large current during voltage switching is limited by changing the value of m.

[0012] Furthermore, the PMOS transistors MP2 and MP3 constitute a first P-type current mirror, and the width-to-length ratio of the PMOS transistors MP2 and MP3 is 1:1.

[0013] Furthermore, the PMOS transistors MP5, MP6, MP7, MP8, and MP9 constitute a second P-type current mirror.

[0014] Furthermore, the sampling module includes resistors R3 and R4, a rail-to-rail operational amplifier OP1, an NMOS transistor MN11, and a programmable resistor Rset. One end of resistor R3 serves as the first input terminal of the sampling module and is connected to the power supply VIN. The other end of resistor R3 is connected to the non-inverting input terminal of the rail-to-rail operational amplifier OP1 and the drain of the NMOS transistor MN11. The control terminal of the rail-to-rail operational amplifier OP1 serves as the third input terminal of the sampling module and is connected to the voltage signal VH. The inverting input terminal of the rail-to-rail operational amplifier OP1 is connected to one end of resistor R4. The other end of resistor R4 serves as the third input terminal of the sampling module. The output terminal of the rail-to-rail operational amplifier OP1 is connected to the gate of the NMOS transistor MN11. The source of the NMOS transistor MN11 is connected to one end of the programmable resistor Rset and serves as the output terminal of the sampling module. The other end of the programmable resistor Rset is grounded.

[0015] Furthermore, the rail-to-rail operational amplifier OP1 is an auto-zero rail-to-rail input operational amplifier or a rail-to-rail input chopper operational amplifier, and the rail-to-rail operational amplifier OP1 is a single-stage operational amplifier or a multi-stage operational amplifier.

[0016] Compared with the prior art, the present invention has the following advantages and effects: The present invention discloses a wide input voltage range current limiting protection circuit suitable for load switches. It achieves a wide input voltage range through a power switching module, solving the problem that the operational amplifier cannot work properly under ultra-low input voltage. By sampling and converting the drain voltage, it solves the problem that the current limiting loop cannot work properly under output short circuit. Compared with traditional current limiting protection circuits, the current limiting protection function implemented by the present invention has a wider range of applications and higher circuit reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a wide input voltage range current limiting protection circuit for load switches according to the present invention.

[0018] Figure 2 This is a circuit diagram of the power switching module of the present invention.

[0019] Figure 3 This is a circuit diagram of the sampling module of the present invention.

[0020] Figure 4 This is a schematic diagram of a current-limiting protection circuit for a load switch applicable to existing technology. Detailed Implementation

[0021] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0022] like Figure 1 As shown, this invention provides a wide input voltage range current limiting protection circuit suitable for load switches, comprising a power transistor MN1, a sampling transistor MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload, and a capacitor Cload. The first input terminal of the sampling module, one end of the sampling resistor Rsense, and the drain of the power transistor MN1 are connected to the power supply VIN. The second input terminal of the sampling module is connected to the voltage signal VH. The third input terminal of the sampling module is connected to the other end of the sampling resistor Rsense and the drain of the sampling transistor MN3. The output terminal of the sampling module is connected to the non-inverting input terminal of the error amplifier EA. The inverting input terminal of the error amplifier EA is connected to the reference voltage VREF. The output terminal of the error amplifier EA is connected to the gate of the sampling transistor MN3 and the gate of the power transistor MN1. The source of the sampling transistor MN3 is connected to the source of the power transistor MN1, one end of the resistor Rload, and one end of the capacitor Cload to generate an output voltage VOUT. The other ends of the capacitor Rload and the other ends of the capacitor Cload are grounded. The first input terminal of the power switching module is connected to the power supply VIN, the second input terminal of the power switching module is connected to the power supply VDD, and the output terminal of the power switching module generates the voltage signal VH.

[0023] The structure and number of amplification stages of the error amplifier EA are not limited; it can employ folded cascode op-amps, sleeve-type cascode op-amps, etc., and the op-amp can be a single-stage or multi-stage op-amp. Due to the wide input range of the power supply voltage VIN, the reference voltage VREF should be relatively low to ensure the normal operation of the NMOS transistor MN11. Therefore, the input pair of the error amplifier EA must use P-type field-effect transistors.

[0024] By rationally designing the error amplifier EA and the rail-to-rail operational amplifier OP1 in the sampling module, their open-loop gain remains unchanged with the power supply voltage, which in turn ensures that the current limiting accuracy remains unchanged with the power supply voltage and that the reliability of the current limiting loop is higher.

[0025] like Figure 2As shown, the power switching module includes NMOS transistors MN4, MN5, MN6, MN7, MN8, MN9, and MN10; PMOS transistors MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, and MP13; current source IB3; Schmitt trigger inverter SMIT; inverters INV1, INV2, and INV3; and one end of current source IB3 is connected to the NMOS transistors. The drain of MN4, the gate of NMOS transistor MN4, the gate of NMOS transistor MN5, the gate of NMOS transistor MN6, the gate of NMOS transistor MN7, the gate of NMOS transistor MN8, and the gate of NMOS transistor MN9 are connected. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP2, and the gate of PMOS transistor MP3. The source of PMOS transistor MP2 is connected to the source of PMOS transistor MP4 and serves as the first input terminal of the power switching module, connected to the power supply VIN. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP3, the gate of PMOS transistor MP4, and the drain of NMOS transistor MN7. The source of PMOS transistor MP3 serves as the power switching... The second input terminal of the module is connected to the power supply VDD. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN10. The gate of NMOS transistor MN10 is connected to the voltage signal VINH. The drain of NMOS transistor MN8 is connected to the drain of PMOS transistor MP4 and the input of Schmitt trigger inverter SMIT. The drain of NMOS transistor MN9 is connected to the drain, gate, MP5, MP6, MP7, MP8, and MP9 of PMOS transistors. The sources of NMOS transistors MN4, MN5, MN6, and MN10 are also connected. The sources of NMOS transistors MN8 and MN9 are grounded. The sources of PMOS transistors MP5, MP6, MP7, MP8, and MP9 are connected and serve as the output of the power switching module to generate a voltage signal VH. The drain of PMOS transistor MP6 is connected to the control terminal of Schmitt trigger inverter SMIT, the drain of PMOS transistor MP7 is connected to the control terminal of inverter INV2, the drain of PMOS transistor MP8 is connected to the control terminal of inverter INV3, and the drain of PMOS transistor MP9 is connected to the control terminal of inverter INV1. The output of Schmitt trigger inverter SMIT is connected to the input of inverter INV2.The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV1 and the gate of PMOS transistor MP11, generating a voltage signal VDDH. The output of inverter INV1 is connected to the gate of PMOS transistor MP10, generating a voltage signal VINH. The source of PMOS transistor MP10 is connected to the source of PMOS transistor MP12 and connected to the power supply VDD. The gate of PMOS transistor MP12 is connected to the voltage signal VINH. The drain of PMOS transistor MP10 is connected to the drain of PMOS transistor MP11. The source of PMOS transistor MP11 is connected to the source of PMOS transistor MP13 and connected to the power supply VIN. The gate of PMOS transistor MP13 is connected to the voltage signal VDDH. The drain of PMOS transistor MP12 is connected to the drain of PMOS transistor MP13 and connected to the voltage signal VH.

[0026] NMOS transistors MN4, MN5, MN6, MN7, MN8, and MN9 form an N-type current mirror. The width-to-length ratio of NMOS transistors MN4, MN5, MN6, MN7, MN8, and MN9 is 1:1:1:n:1:m.

[0027] NMOS transistors MN7 and MN10 constitute a hysteresis module. The hysteresis voltage is set by changing the value of n, and the transient large current during voltage switching is limited by changing the value of m.

[0028] PMOS transistors MP2 and MP3 form the first P-type current mirror, with a width-to-length ratio of 1:1.

[0029] PMOS transistors MP5, MP6, MP7, MP8, and MP9 constitute the second P-type current mirror.

[0030] like Figure 3As shown, the sampling module includes resistors R3 and R4, a rail-to-rail operational amplifier OP1, an NMOS transistor MN11, and a programmable resistor Rset. One end of resistor R3 serves as the first input terminal of the sampling module and is connected to the power supply VIN. The other end of resistor R3 is connected to the non-inverting input terminal of the rail-to-rail operational amplifier OP1 and the drain of the NMOS transistor MN11. The control terminal of the rail-to-rail operational amplifier OP1 serves as the third input terminal of the sampling module and is connected to the voltage signal VH. The inverting input terminal of the rail-to-rail operational amplifier OP1 is connected to one end of resistor R4. The other end of resistor R4 serves as the third input terminal of the sampling module. The output terminal of the rail-to-rail operational amplifier OP1 is connected to the gate of the NMOS transistor MN11. The source of the NMOS transistor MN11 is connected to one end of the programmable resistor Rset and serves as the output terminal of the sampling module. The other end of the programmable resistor Rset is grounded.

[0031] The rail-to-rail operational amplifier OP1 uses an auto-zero rail-to-rail input operational amplifier or a rail-to-rail input chopper operational amplifier. The rail-to-rail operational amplifier OP1 can be a single-stage operational amplifier or a multi-stage operational amplifier.

[0032] The current limiting value of the current limiting protection circuit can be adjusted by modifying the resistance value of the external programmable resistor Rset, thereby adjusting the ratio between the current limiting value and Rset. The current limiting ratio can be modified by adjusting the resistance value of resistor R3. Different applications require different sampling ratios; in such cases, the current limiting value can be kept constant by modifying the resistance value of resistor R3.

[0033] The sampling transistor MN3 is connected to the gate and source of the power transistor MN1, and their gate and source voltages remain consistent. When the output voltage VOUT is 0V, it does not affect the current sampling. When the sampling transistor MN3 and the power transistor MN1 are in the saturation region, their drain-source current ratio is 1:N. The current flowing through the sampling resistor Rsense is 1 / N times the power transistor current, i.e., IOUT / N. Utilizing the "virtual open" characteristic of the rail-to-rail operational amplifier OP1 input, the sampling module converts the voltage drop generated across the sampling resistor Rsense into a voltage drop across resistor R3, thus making the current flowing through the programmable resistor Rset equal to the current flowing through resistor R3. Utilizing the "virtual short" characteristic of the error amplifier EA input, the voltage drop across the programmable resistor Rset is clamped at VREF, resulting in the following relationship:

[0034] IOUT / N*Rsense=VREF / Rset*R3;

[0035] When the output current IOUT reaches the current limit value

[0036] IOUT=ICL=VREF*R3*N / (RSET*Rsense);

[0037] For a loop to function properly, all components of the circuit must be in their intended operating states. For a wide-range input power supply VIN of 0.5V to 5.5V, if the rail-to-rail operational amplifier OP1 uses VIN, then when VIN = 0.5V, neither P-type nor N-type MOSFETs in the input pair will function correctly because the power supply voltage is insufficient to support the normal operation of all devices. This is the main reason why traditional current-limiting loops cannot operate within a wide voltage range. To address this, this invention designs a power switching module that compares the input power supply VIN with the system power supply VDD, selecting the higher signal as the power supply. When VIN is less than VDD, since PMOS transistors MP2 and MP3 are connected at their gates, the gate-source voltage of PMOS transistor MP3 is greater than that of PMOS transistor MP2. Because the pull-down current mirrors NMOS transistors MN5 and MN6 are the same size, the drain potential of PMOS transistor MP3 is close to VDD, ensuring equal current in both branches. At this time, PMOS transistor MP4 is off, the Schmitt trigger input signal is low, and after passing through the logic gate, VDDH is high and VINH is low. PMOS transistors MP10 and MP12 are on, while PMOS transistors MP11 and MP13 are off, and the VH output is equal to VDD. Similarly, when VIN is greater than VDD, the VH output is equal to VIN. The hysteresis module ensures better transient characteristics of the output VH during VIN switching. The second P-type current mirror controls the instantaneous current from becoming excessive during VIN switching. The system voltage VDD input range is 2.5V~5.5V. VH takes the larger value of VIN1 and VDD, so the output voltage range of VH is 2.5V~5.5V. It can be used as the power supply for rail-to-rail op-amp OP1. The input common-mode voltage range of rail-to-rail op-amp OP1 is always less than the power supply voltage VH range, so the loop can be guaranteed to work normally under a wide input voltage range. Rail-to-rail op-amp OP1 needs to adopt a rail-to-rail design to meet the input common-mode voltage requirement of 0.5V~5.5V.

[0038] By adjusting the temperature coefficient of the externally input reference voltage VREF so that its product with the temperature coefficient of resistor R3 is equal to the product of the temperature coefficients of the sampling resistor Rsense and the programmable resistor RSET, the current limiting value can be made to remain unchanged with temperature.

[0039] This invention discloses a wide input voltage range current limiting protection circuit suitable for load switches. It achieves a wide input voltage range through a power switching module, solving the problem that the operational amplifier cannot work properly under ultra-low input voltage. By sampling and converting the drain voltage, it solves the problem that the current limiting loop cannot work properly under output short circuit. Compared with traditional current limiting protection circuits, the current limiting protection function implemented by this invention has a wider range of applications and higher circuit reliability.

[0040] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A wide input voltage range current limiting protection circuit suitable for load switches, characterized in that: The system includes a power transistor MN1, a sampling transistor MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload, and a capacitor Cload. The first input terminal of the sampling module, one end of the sampling resistor Rsense, and the drain of the power transistor MN1 are connected to the power supply VIN. The second input terminal of the sampling module is connected to the voltage signal VH. The third input terminal of the sampling module is connected to the other end of the sampling resistor Rsense and the drain of the sampling transistor MN3. The output terminal of the sampling module is connected to the non-inverting input terminal of the error amplifier EA. The inverting input terminal of the error amplifier EA is connected to the reference voltage VREF. The output terminal of the error amplifier EA is connected to the gate of the sampling transistor MN3 and the gate of the power transistor MN1. The source of the sampling transistor MN3 is connected to the source of the power transistor MN1, one end of the resistor Rload, and one end of the capacitor Cload to generate an output voltage VOUT. The other ends of the capacitor Rload and the other ends of the capacitor Cload are grounded. The first input terminal of the power switching module is connected to the power supply VIN. The second input terminal of the power switching module is connected to the power supply VDD. The output terminal of the power switching module generates a voltage signal VH. The power switching module includes NMOS transistors MN4, MN5, MN6, MN7, MN8, MN9, and MN10, PMOS transistors MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, and MP13, current source IB3, Schmitt trigger inverter SMIT, inverter INV1, inverter INV2, and inverter INV3. One end of current source IB3 is connected to NMOS transistor M... The drain of N4, the gate of NMOS transistor MN4, the gate of NMOS transistor MN5, the gate of NMOS transistor MN6, the gate of NMOS transistor MN7, the gate of NMOS transistor MN8, and the gate of NMOS transistor MN9 are connected. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP2, and the gate of PMOS transistor MP3. The source of PMOS transistor MP2 is connected to the source of PMOS transistor MP4 and serves as the first input terminal of the power switching module, connected to the power supply VIN. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP3, the gate of PMOS transistor MP4, and the drain of NMOS transistor MN7. The source of PMOS transistor MP3 serves as the power switching... The second input terminal of the module is connected to the power supply VDD. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN10. The gate of NMOS transistor MN10 is connected to the voltage signal VINH. The drain of NMOS transistor MN8 is connected to the drain of PMOS transistor MP4 and the input of Schmitt trigger inverter SMIT. The drain of NMOS transistor MN9 is connected to the drain, gate, MP5, MP6, MP7, MP8, and MP9 of PMOS transistors. The sources of NMOS transistors MN4, MN5, MN6, and MN10 are also connected. The sources of NMOS transistors MN8 and MN9 are grounded. The sources of PMOS transistors MP5, MP6, MP7, MP8, and MP9 are connected and serve as the output of the power switching module to generate a voltage signal VH. The drain of PMOS transistor MP6 is connected to the control terminal of Schmitt trigger inverter SMIT, the drain of PMOS transistor MP7 is connected to the control terminal of inverter INV2, the drain of PMOS transistor MP8 is connected to the control terminal of inverter INV3, and the drain of PMOS transistor MP9 is connected to the control terminal of inverter INV1. The output of Schmitt trigger inverter SMIT is connected to the input of inverter INV2.The output of inverter INV2 is connected to the input of inverter INV3. The output of inverter INV3 is connected to the input of inverter INV1 and the gate of PMOS transistor MP11, generating a voltage signal VDDH. The output of inverter INV1 is connected to the gate of PMOS transistor MP10, generating a voltage signal VINH. The source of PMOS transistor MP10 is connected to the source of PMOS transistor MP12 and connected to the power supply VDD. The gate of PMOS transistor MP12 is connected to the voltage signal VINH. The drain of PMOS transistor MP10 is connected to the drain of PMOS transistor MP11. The source of PMOS transistor MP11 is connected to the source of PMOS transistor MP13 and connected to the power supply VIN. The gate of PMOS transistor MP13 is connected to the voltage signal VDDH. The drain of PMOS transistor MP12 is connected to the drain of PMOS transistor MP13 and connected to the voltage signal VH.

2. The wide input voltage range current limiting protection circuit for load switches according to claim 1, characterized in that: The NMOS transistors MN4, MN5, MN6, MN7, MN8, and MN9 form an N-type current mirror. The width-to-length ratio of the NMOS transistors MN4, MN5, MN6, MN7, MN8, and MN9 is 1:1:1:n:1:m.

3. A wide input voltage range current limiting protection circuit for load switches according to claim 2, characterized in that: The NMOS transistors MN7 and MN10 constitute a hysteresis module. The hysteresis voltage is set by changing the value of n, and the transient large current during voltage switching is limited by changing the value of m.

4. A wide input voltage range current limiting protection circuit for load switches according to claim 1, characterized in that: The PMOS transistors MP2 and MP3 form the first P-type current mirror, and the width-to-length ratio of PMOS transistors MP2 and MP3 is 1:

1.

5. A wide input voltage range current limiting protection circuit for load switches according to claim 1, characterized in that: The PMOS transistors MP5, MP6, MP7, MP8, and MP9 constitute the second P-type current mirror.

6. A wide input voltage range current limiting protection circuit for load switches according to claim 1, characterized in that: The sampling module includes resistors R3 and R4, a rail-to-rail operational amplifier OP1, an NMOS transistor MN11, and a programmable resistor Rset. One end of resistor R3 serves as the first input terminal of the sampling module and is connected to the power supply VIN. The other end of resistor R3 is connected to the non-inverting input terminal of rail-to-rail operational amplifier OP1 and the drain of NMOS transistor MN11. The control terminal of rail-to-rail operational amplifier OP1 serves as the third input terminal of the sampling module and is connected to the voltage signal VH. The inverting input terminal of rail-to-rail operational amplifier OP1 is connected to one end of resistor R4. The other end of resistor R4 serves as the third input terminal of the sampling module. The output terminal of rail-to-rail operational amplifier OP1 is connected to the gate of NMOS transistor MN11. The source of NMOS transistor MN11 is connected to one end of programmable resistor Rset and serves as the output terminal of the sampling module. The other end of programmable resistor Rset is grounded.

7. A wide input voltage range current limiting protection circuit for load switches according to claim 6, characterized in that: The rail-to-rail operational amplifier OP1 is an auto-zero rail-to-rail input operational amplifier or a rail-to-rail input chopper operational amplifier. The rail-to-rail operational amplifier OP1 can be a single-stage operational amplifier or a multi-stage operational amplifier.

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