Startup and shutdown control device and method

Abstract

The invention relates to a startup and shutdown control device and method. Relates to an electronic circuit technology, and solves the problem of functional errors of the electronic equipment caused by reset failure after startup. The on-off control device comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a first voltage stabilizing diode, a first capacitor, a second capacitor and a first field effect transistor. The technical scheme provided by the invention is suitable for reset control of the electronic equipment, and a low-cost and high-reliability reset scheme is realized.

Description

Technical Field

[0001] The present disclosure relates to electronic circuit technology, and more particularly to a power on / off control device and method. Background Art

[0002] Due to power supply voltage drops, incomplete discharge of energy storage devices after shutdown, and the diversity of control chips, it is often necessary to reset the control chip of the electronic device when starting up to avoid signal errors.

[0003] A reset signal can be generated through a resistor-capacitor (RC) reset circuit, and the reset operation of the control chip can be realized by providing the reset signal to the corresponding pin of the control chip.

[0004] However, as the circuits of electronic devices become increasingly complex, a large number of energy storage elements will cause the main power discharge process to take a long time after power failure. If the device is turned on when the main power is not fully discharged, it will cause abnormal power-on timing inside the electronic device, leading to functional errors in the electronic device. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the present disclosure provides a power on / off control device and method. Through a reset circuit that responds to a power on signal, the power on / off, especially the reset operation management in the frequent and rapid power on / off scenario, is realized, the problem of functional errors in electronic equipment caused by incomplete reset at power on is solved, and a low-cost, high-reliability reset solution is realized.

[0006] According to a first aspect of an embodiment of the present disclosure, there is provided a power on / off control device, comprising: a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a first voltage stabilizing diode, a first capacitor, a second capacitor and a first field effect transistor; One end of the first resistor is connected to a switch to obtain a power-on signal, and the other end is connected to the second resistor, the first capacitor, the second capacitor and the cathode of the first voltage-stabilizing diode; The second resistor is connected in series with the first resistor, one end of the second resistor is connected to the first resistor, and the other end is grounded; One end of the first capacitor is connected to the first resistor, and the other end is connected to the cathode of the first diode, the fourth resistor and the gate of the first field effect transistor; One end of the second capacitor is connected to the first resistor, and the other end is grounded; The cathode of the first diode is connected to the first capacitor, and the anode is grounded; The cathode of the first voltage stabilizing diode is connected to the first resistor, and the anode is grounded; One end of the third resistor is connected to the first capacitor, and the other end is grounded, so as to form a discharge loop with the first capacitor; The gate of the first field effect transistor is connected to the first capacitor, the source is grounded, and the drain is connected to the fourth resistor; One end of the fourth resistor is connected to the control power supply, and the other end is connected to the drain of the first field effect transistor and the reset pin of the processing chip, and outputs a high level signal to the reset pin when the first field effect transistor is disconnected.

[0007] Furthermore, when the switch is closed, a power-on signal is divided by the first resistor and the second resistor to obtain a divided voltage signal on both sides of the second resistor. The divided voltage signal is transmitted to the gate of the first field effect transistor through the first capacitor. When the divided voltage signal is greater than a preset gate voltage, the first field effect transistor is turned on.

[0008] Furthermore, the discharge time of the first capacitor from power-on to discharge until the voltage-divided signal is less than a preset gate voltage is greater than or equal to the time taken for the reset operation of the processing chip.

[0009] According to a second aspect of an embodiment of the present disclosure, a power on / off control method is provided, which is applicable to the power on / off control device described above, and the method includes: After detecting the power-on signal, the processing chip is reset; After the reset operation is completed, the processing chip is started to enter a normal working state.

[0010] Furthermore, after detecting the power-on signal, the step of resetting the processing chip includes: A reset signal is generated according to the power-on signal and output to the processing chip to instruct the processing chip to perform a reset operation.

[0011] Furthermore, the duration of outputting the reset signal to the processing chip is greater than or equal to the duration of the reset operation of the processing chip.

[0012] According to a third aspect of an embodiment of the present disclosure, a power on / off control device is provided, which is applicable to the power on / off control device described above, and the device includes: A reset control module, used to reset the processing chip after detecting a power-on signal; The startup module is used to start the processing chip to enter a normal working state after the reset operation is completed.

[0013] Furthermore, the reset control module is used to generate a reset signal according to the power-on signal and output it to the processing chip to instruct the processing chip to perform a reset operation.

[0014] Furthermore, the duration for which the reset control module outputs the reset signal to the processing chip is greater than or equal to the duration for which the processing chip performs a reset operation.

[0015] According to a fourth aspect of an embodiment of the present disclosure, a non-temporary computer-readable storage medium is provided. When instructions in the storage medium are executed by a processor of a mobile terminal, the mobile terminal is enabled to execute a power on / off control method as described above.

[0016] The technical solution provided by the embodiment of the present disclosure may include the following beneficial effects: the power on / off control device responds to the power on operation and initiates the reset operation for the processing chip after detecting the power on signal. The power on signal is captured by utilizing the DC isolation characteristics of the capacitor, thereby realizing the generation of the reset signal in a short time, and ensuring the rapid reset operation after power on. The problem of functional errors in electronic equipment caused by incomplete reset at power on is solved, and a low-cost, high-reliability reset solution is realized.

[0017] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0019] Figure 1 It is a schematic diagram of an RC reset circuit.

[0020] Figure 2 The figure is a circuit structure diagram of a power on / off control device according to an exemplary embodiment.

[0021] Figure 3 It is a schematic diagram of a simulation waveform of a scenario in which the power on and off is repeatedly performed at a frequency of 1 time / s according to an exemplary embodiment.

[0022] Figure 4 It is a schematic diagram of simulation waveforms of a scenario in which the power on and off is repeatedly performed at a frequency of 4 times / s according to an exemplary embodiment.

[0023] Figure 5 It is a schematic diagram of waveforms actually measured during a single power on / off operation according to an exemplary embodiment.

[0024] Figure 6 It is a schematic diagram of waveforms actually measured during rapid multiple power on and off operations according to an exemplary embodiment.

[0025] Figure 7 The figure is a flow chart of a power on / off control method according to an exemplary embodiment.

[0026] Figure 8 is a block diagram of another power on / off control device according to an exemplary embodiment. DETAILED DESCRIPTION

[0027] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0028] A reset signal can be generated through the RC reset circuit, and the reset operation of the control chip can be realized by providing the reset signal to the corresponding pin of the control chip.

[0029] Figure 1 An RC reset circuit is shown. When the power is turned on, the capacitor C is in a short circuit state. At this time, the reset signal (Reset) is pulled to a low level. The microcontroller detects the low level and enters the reset state. After a few milliseconds, the capacitor C is fully charged and becomes an open circuit state. At this time, Reset is pulled to a high level. After the microcontroller detects the high level, it stops resetting and prepares to enter the normal working state.

[0030] However, as the circuits of electronic devices become increasingly complex, a large number of energy storage elements will cause the main power discharge process to take a long time after power failure. If the device is turned on when the main power is not fully discharged, it will cause abnormal power-on timing inside the electronic device, leading to functional errors in the electronic device.

[0031] In order to solve the above problems, the embodiments of the present disclosure provide a power on / off control device and method, which initiates reset according to a power on signal, implements a reliable reset mechanism in frequent switching scenarios, and solves the problem of functional errors in electronic devices caused by incomplete reset when powered on.

[0032] The embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0033] An exemplary embodiment of the present disclosure provides a power on / off control device, whose circuit structure is as follows: Figure 2 As shown, including: A first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first diode D1, a first voltage zener diode Z1, a first capacitor C1, a second capacitor C2 and a first field effect transistor Q1; One end of R1 is connected to the switch to obtain the power-on signal, and the other end is connected to the cathode of R2, C1, C2 and Z1.

[0034] R2 is connected in series with R1, with one end of R2 connected to R1 and the other end grounded.

[0035] One end of C1 is connected to R1, and the other end is connected to the cathode of D1, R4, and the gate of Q1.

[0036] One end of C2 is connected to R1 and the other end is grounded.

[0037] The cathode of D1 is connected to C1 and the anode is grounded.

[0038] The cathode of Z1 is connected to R1 and the anode is grounded.

[0039] One end of R3 is connected to C1, and the other end is grounded, forming a discharge loop with C1.

[0040] Q1's gate is connected to C1, its source is grounded, and its drain is connected to R4.

[0041] One end of R4 is connected to the control power supply VCC, and the other end is connected to the drain of Q1 and the reset pin of the processing chip, and outputs a high level signal to the reset pin when Q1 is disconnected. The high level signal is input to the reset pin of the processing chip as a reset signal (Reset). According to one embodiment, the processing chip may be a microprocessing unit (MCU).

[0042] Furthermore, when the switch is closed, the input power Vin generates a power-on signal (such as a key switch signal generated by a key switch) through the switch. ) The voltage divided by R1 and R2 is used to obtain the voltage divided signal on both sides of R2 , Transmitted to the gate of Q1 via C1 (specifically, the gate signal ,exist When the gate voltage is greater than the preset value, Q1 is turned on.

[0043] Furthermore, C1 is discharged from power on to The discharge time which is less than the preset gate voltage is greater than or equal to the reset operation time of the processing chip.

[0044] C1 is used to block direct current and transmit the power-on signal to Q1. Q1 acts as a switch, and the on and off control of Q1 generates low-level pulses and high-level pulses, and outputs low-level and high-level reset signals.

[0045] C1 and R3 form an RC discharge circuit. According to the reset time required by the MCU, the corresponding parameters can be modified to fully meet the conditions required for MCU reset. Among them, the modified parameters include the parameters of the electronic components in the power on / off control device, Regardless of the input voltage, the power-on signal is introduced to the capacitor input terminal through the resistor voltage divider to generate a voltage pulse and output a reset signal; The circuit is simple, which is beneficial to the reliability and safety of the product.

[0046] Figure 3 It is a schematic diagram of the simulation waveform of the power on / off scenario which is repeated at a frequency of 1 time / s. Figure 4 This is a schematic diagram of the simulation waveform of the power on / off scenario that is repeated at a frequency of 4 times / s. is a switch signal (specifically a key switch signal), is the voltage signal of the second resistor R4 relative to GND, is the gate signal of Q1, and Reset is the output reset signal. It can be seen from the simulation waveform that the reset waveform can be generated normally when the machine is turned on and off at a frequency of 1 time / s and 4 times / s.

[0047] Figure 5 This is a waveform diagram obtained by measuring a single power on / off operation. Figure 6 This is a waveform diagram obtained by measuring the actual situation when the machine is turned on and off multiple times quickly. Figure 5 and Figure 6 middle, is a switch signal (specifically a key switch signal), is the voltage signal of the second resistor R4 relative to GND, is the gate signal of Q1, and Reset is the output reset signal. Through the measured waveform, it can be seen that in the scenario of fast power on and off, each power on operation can normally generate a reset waveform.

[0048] An exemplary embodiment of the present disclosure also provides a power on / off control method suitable for Figure 2 The power on / off control device shown in FIG. 1 uses this method to perform a reset operation when the power is turned on. Figure 7 As shown, including: Step 701: After detecting a power-on signal, reset the processing chip.

[0049] In this step, a reset signal is generated according to the power-on signal and output to the processing chip to instruct the processing chip to perform a reset operation.

[0050] According to one implementation, after a power-on signal is detected, in response to the power-on signal, Q1 is turned on, and a low-level reset signal is output to a processing chip such as an MCU, triggering a reset operation of the processing chip.

[0051] Step 702: After the reset operation is completed, start the processing chip to enter a normal working state.

[0052] In this step, the duration of outputting the reset signal to the processing chip is greater than or equal to the duration of the processing chip performing the reset operation, and the reset signal is a low level signal. Specifically, this can be achieved by setting the parameters of each electronic device in the power on / off control device.

[0053] The reset signal is continuously output during the reset operation. Further, it can be set to continue to delay outputting the reset signal for a period of time after the reset operation is completed. After the system power supply is directly stable, the reset signal is canceled (for example, the reset signal is set to a high level), thereby ensuring the timing of normal operation of the system.

[0054] An exemplary embodiment of the present disclosure also provides another power on / off control device, which is suitable for Figure 2 In this embodiment, the structure of the device is as follows: Figure 8 As shown, including: The reset control module 801 is used to reset the processing chip after detecting the power-on signal; The startup module 802 is used to start the processing chip to enter a normal working state after the reset operation is completed.

[0055] Furthermore, the reset control module 801 is used to generate a reset signal according to the power-on signal and output it to the processing chip to instruct the processing chip to perform a reset operation.

[0056] Furthermore, the duration for which the reset control module 801 outputs the reset signal to the processing chip is greater than or equal to the duration for which the processing chip performs the reset operation.

[0057] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0058] An exemplary embodiment of the present disclosure further provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a processor of a mobile terminal, the mobile terminal is enabled to execute a power on / off control method provided by an embodiment of the present disclosure.

[0059] The embodiments of the present disclosure provide a power on / off control device and method, which responds to the power on operation and starts the reset operation for the processing chip after detecting the power on signal. The power on signal is captured by utilizing the DC isolation characteristics of the capacitor, thereby realizing the generation of the reset signal in a short time, and ensuring the rapid reset operation after power on. The problem of functional errors in electronic equipment caused by incomplete reset at power on is solved, and a low-cost, high-reliability reset solution is realized.

[0060] In the fast power on and off scenario, the working sequence problem caused by the reset not being completed in time is avoided.

[0061] The technical solution provided by the embodiments of the present disclosure has a simple and reliable circuit design, low cost, and universality, which is conducive to the miniaturization of electronic equipment and can be applied to a variety of different electronic equipment, such as control systems of electric vehicles.

[0062] Those skilled in the art may also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application may be implemented by electronic hardware, computer software, or a combination of the two. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the functions described for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present application.

[0063] In addition, the word "exemplary" is used herein to indicate serving as an example, instance, or diagram. Any aspect or design described as "exemplary" in this article is not necessarily understood to be advantageous compared to other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a specific way. As used herein, the term "or" is intended to represent an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X applies A or B" is intended to represent any one of the natural inclusive arrangements. That is, if X applies A; X applies B; or X applies both A and B, "X applies A or B" is satisfied under any of the aforementioned examples. In addition, unless otherwise specified or clearly pointed to a singular form from the context, the articles "one" and "an" as used in this application and the appended claims are generally understood to mean "one or more".

[0064] Likewise, although the present disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art after reading and understanding the specification and drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components (e.g., elements, resources, etc.) described above, unless otherwise indicated, the terms used to describe such components are intended to correspond to any component (functionally equivalent) that performs the specific functions of the described components, even if the structure is not equivalent to the disclosed structure. In addition, although specific features of the present disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations as may be desired and conducive to any given or specific application. In addition, with respect to "including", "having", "having", "having", or variations thereof used in a specific embodiment or claim, such terms are intended to be inclusive in a manner similar to the term "comprising".

[0065] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0066] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A power on / off control device, characterized in that: include: A first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a first voltage-stabilizing diode, a first capacitor, a second capacitor, and a first field effect transistor; t One end of the first resistor is connected to a switch to obtain a power-on signal, and the other end is connected to the second resistor, the first capacitor, the second capacitor and the cathode of the first voltage-stabilizing diode; The second resistor is connected in series with the first resistor, one end of the second resistor is connected to the first resistor, and the other end is grounded; One end of the first capacitor is connected to the first resistor, and the other end is connected to the cathode of the first diode, the fourth resistor and the gate of the first field effect transistor; One end of the second capacitor is connected to the first resistor, and the other end is grounded; The cathode of the first diode is connected to the first capacitor, and the anode is grounded; The cathode of the first voltage stabilizing diode is connected to the first resistor, and the anode is grounded; One end of the third resistor is connected to the first capacitor, and the other end is grounded, so as to form a discharge loop with the first capacitor; The gate of the first field effect transistor is connected to the first capacitor, the source is grounded, and the drain is connected to the fourth resistor; One end of the fourth resistor is connected to the control power supply, and the other end is connected to the drain of the first field effect transistor and the reset pin of the processing chip, and outputs a high level signal to the reset pin when the first field effect transistor is disconnected.

2. The power on / off control device according to claim 1, characterized in that: When the switch is closed, a power-on signal is divided by the first resistor and the second resistor to obtain a divided voltage signal on both sides of the second resistor. The divided voltage signal is transmitted to the gate of the first field effect transistor through the first capacitor. When the divided voltage signal is greater than a preset gate voltage, the first field effect transistor is turned on.

3. The power on / off control device according to claim 1, characterized in that: The discharge time of the first capacitor from power-on to discharge until the voltage-divided signal is less than the preset gate voltage is greater than or equal to the reset operation time of the processing chip.

4. A power on / off control method, applicable to the power on / off control device as claimed in claims 1-3, characterized in that: The method comprises: After detecting the power-on signal, the processing chip is reset; After the reset operation is completed, the processing chip is started to enter a normal working state.

5. The power on / off control method according to claim 4, characterized in that: The step of resetting the processing chip after detecting the power-on signal comprises: A reset signal is generated according to the power-on signal and output to the processing chip to instruct the processing chip to perform a reset operation.

6. The power on / off control method according to claim 5, characterized in that: The duration of outputting the reset signal to the processing chip is greater than or equal to the duration of the processing chip performing the reset operation.

7. A power on / off control device, applicable to the power on / off control device as claimed in claims 1 to 3, characterized in that: The device comprises: A reset control module, used to reset the processing chip after detecting a power-on signal; The startup module is used to start the processing chip to enter a normal working state after the reset operation is completed.

8. The power on / off control device according to claim 7, characterized in that: The reset control module is used to generate a reset signal according to the power-on signal and output it to the processing chip to instruct the processing chip to perform a reset operation.

9. The power on / off control device according to claim 8, characterized in that: The duration for which the reset control module outputs the reset signal to the processing chip is greater than or equal to the duration for which the processing chip performs a reset operation.

10. A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of a mobile terminal, the mobile terminal is enabled to execute a power on / off control method as claimed in any one of claims 4 to 6.

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