Non-reference clock type clock data recovery device and clock data recovery method thereof

Abstract

The invention provides a reference-clock-free clock data recovery device and a clock data recovery method thereof, and relates to the technical field of electronics. The reference-clock-free clock data recovery device comprises a linear phase discriminator used for carrying out phase discrimination processing on received four-level pulse amplitude modulation data and outputting a phase discrimination signal voltage; the frequency discriminator is used for carrying out frequency discrimination processing on the received phase discrimination voltage signal and outputting a frequency discrimination signal voltage; the first voltage-current converter is used for outputting pulse signal current; the loop filter is used for converting the pulse signal current into control voltage; the inductance-capacitance oscillator is used for converting the control voltage into an orthogonal clock signal; the self-biased multiphase clock generator is used for outputting a multiphase clock signal according to the orthogonal clock signal; and the starting circuit is used for discharging the control voltage to zero during power-on starting, so that the orthogonal clock signal is at the initial frequency, and traversal search of the control voltage is realized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronics, and more particularly, to a reference clock-free clock data recovery device and a clock data recovery method thereof. Background Art

[0002] As data centers continue to expand, the data exchange rate within the data center continues to rise. In order to maintain the lowest possible power consumption and hardware cost while transmitting at high speed, higher requirements are placed on the serializer / deserializer (SerDes) chips used for internal communication in the data center.

[0003] Traditional data transmission based on non-return-to-zero data format can only transmit one bit of data per baud, so the data density is low. Data transmission based on four-level pulse amplitude modulation data format can transmit two bits of data per baud, with higher data density. It can transmit data at twice the data rate under the same bandwidth, and is currently widely used in data exchange within data centers. The clock data recovery device is an important component module in the SerDes chip. The clock data recovery device is needed at the receiving end of the SerDes to retime the high-frequency data input outside the chip to recover clean data. However, since there are different communication protocols and transmission data rates within the data center, if different clock data recovery devices are designed for different data rates, the system complexity and design cost will increase. Summary of the invention

[0004] In view of this, the present disclosure provides a reference clock type clock data recovery device and a clock data recovery method thereof.

[0005] On the one hand, the present disclosure provides a reference clock-free clock data recovery device, including: a linear phase detector, used to perform phase detection processing on received four-level pulse amplitude modulation data and output a phase detection signal voltage, wherein the phase detection signal voltage is used to represent the phase difference between the four-level pulse amplitude modulation data and the multi-phase clock signal; a frequency detector, used to perform frequency detection processing on the received phase detection voltage signal and output a frequency detection signal voltage, wherein the frequency detection signal voltage is used to represent the frequency difference between the four-level pulse amplitude modulation data and the multi-phase clock signal; a first voltage-to-current converter, used to convert the phase detection signal voltage into a phase detection signal current, and to convert the frequency detection signal voltage into a frequency detection signal current, and to output a pulse signal current according to the phase detection signal current and the frequency detection signal current; a loop filter, used to convert the pulse signal current into a control voltage; an inductor-capacitor oscillator, used to convert the control voltage into an orthogonal clock signal; a self-biased multi-phase clock generator, used to output a multi-phase clock signal according to the orthogonal clock signal; a startup circuit, used to discharge the control voltage to zero when powered on, so that the orthogonal clock signal is at an initial frequency, so as to realize a traversal search for the control voltage.

[0006] According to an embodiment of the present disclosure, it also includes: a data sampler for sampling the output multi-phase clock signal to generate a thermometer code; a decoder for decoding the thermometer code to generate a first data signal; and an output buffer for buffering the first data signal and outputting a second data signal.

[0007] According to an embodiment of the present disclosure, a linear phase detector determines a phase difference using a Euclidean distance algorithm.

[0008] According to an embodiment of the present disclosure, a linear phase detector includes: a first sampling and holding circuit, used to sample and output input four-level pulse amplitude modulation data as a first data edge, a second data edge and a third data edge, wherein the third data edge is an intermediate data edge between the first data edge and the second data edge; a voltage-current conversion unit, used to convert the first data edge, the second data edge and the third data edge into corresponding first data current, second data current and third data current, respectively; a first resistor, used to convert the first data current, the second data current and the third data current into a first voltage; a second sampling and holding circuit, used to sample the first voltage; a direction decision circuit, used to determine the edge direction of the sampled first voltage, and output a phase-detection voltage signal according to the edge direction.

[0009] According to an embodiment of the present disclosure, the linear phase detector also includes: a first low-pass filter, used to determine whether the sampled first voltage has a DC bias; a second voltage-to-current converter, used to eliminate the DC bias when the sampled first voltage has a DC bias, output the first current, and output the first current through the first resistor to update the first voltage.

[0010] According to an embodiment of the present disclosure, the demodulator includes: a current logic circuit for outputting a first logic voltage and a second logic voltage; a comparator for determining a logic signal voltage based on the first logic voltage and the second logic voltage, outputting a demodulation signal voltage based on the logic signal voltage, and controlling a demodulation signal current using the demodulation signal voltage to reduce the frequency difference between four-level pulse amplitude modulation data and a multi-phase clock signal.

[0011] According to an embodiment of the present disclosure, a current logic circuit includes: a second resistor and a third resistor connected in series, for outputting a first logic voltage from a connection point between the second resistor and the third resistor; a fourth resistor and a fifth resistor connected in series, for outputting a second logic voltage from a connection point between the third resistor and the fourth resistor, wherein the difference between the first logic voltage and the second logic voltage is a logic signal voltage; a first transistor, wherein the source of the first transistor is connected to an end of the third resistor away from the second resistor, and the gate of the first transistor is used to receive an input first phase-locking voltage; a second transistor, wherein the source of the second transistor is connected to an end of the fifth resistor away from the fourth resistor, and the drain of the second transistor is connected to the drain of the first transistor, and the gate of the second transistor is used to receive an input second phase-locking voltage, wherein the difference between the first phase-locking voltage and the second phase-locking voltage is a phase-locking signal voltage.

[0012] According to an embodiment of the present disclosure, a self-biased multi-phase clock generator includes: a phase detector for receiving an orthogonal clock signal and outputting a phase difference between the orthogonal clock signal and the multi-phase clock signal; a charge pump for generating a first multi-phase current from the phase difference output by the phase detector; a second low-pass filter, arranged to be connected to the output end of the charge pump, for converting the first multi-phase current into a first multi-phase voltage; a third transistor, a gate of the third transistor is arranged to be connected to the output end of the second low-pass filter, the gate is arranged to receive the first multi-phase voltage, and outputs a second multi-phase current from the drain; a fourth transistor, a gate of the fourth transistor is arranged to be connected to the gate of the third transistor, and the drain of the fourth transistor is arranged to be connected to the charge pump, for outputting a third multi-phase current, and using the third multi-phase current to regulate the first multi-phase current; a ring oscillator, arranged to be connected to the drain of the third transistor, for regulating the frequency and phase of the received second multi-phase current; and a multi-phase clock circuit, for outputting a multi-phase clock signal from the regulated second multi-phase current.

[0013] According to an embodiment of the present disclosure, the phase differences of adjacent clock signals in the multi-phase clock signal are the same.

[0014] The second aspect of the present disclosure discloses a clock data recovery method based on a clock data recovery device without a reference clock, comprising: when the startup circuit is powered on and started, the startup circuit outputs a high-level signal; according to the high-level signal, the control voltage of the loop filter is controlled to discharge to zero, the loop is disconnected, and the orthogonal clock signal output by the inductor-capacitor oscillator is controlled to be the initial frequency; after the startup circuit is powered on and started, the startup circuit outputs a low-level signal to control the loop to be closed; based on the input four-level pulse amplitude modulation data, the output phase-detection voltage signal and the frequency-detection voltage signal are determined; according to the phase-detection voltage signal and the frequency-detection voltage signal, the first voltage-current converter is controlled to charge and discharge the loop so that the device starts to lock until the phase-detection voltage signal and the frequency-detection voltage signal respectively meet the preset conditions; when the phase-detection voltage signal and the frequency-detection voltage signal respectively meet the preset conditions, the output multi-phase clock signal is sampled and a thermometer code is generated; the thermometer code is decoded and buffered, and a data signal is output.

[0015] According to the embodiments of the present disclosure, four-level pulse amplitude modulation data with a wide range of data rates can be received, which can meet the data rate requirements of different communication protocols. At the same time, no additional crystal oscillator is required to provide a reference clock, and the device has low power consumption, low jitter and high reliability.

[0016] According to the embodiments of the present disclosure, the linear phase detector based on Euclidean distance calculation can utilize the data edges of all types of four-level pulse amplitude modulation data without the need for additional data edge selection operations, thereby improving the utilization rate of data edge phase information and accelerating the locking speed, and can quickly lock the multi-phase clock signal to the target frequency and phase. In addition, the frequency and phase detection paths and the data sampling paths can be decoupled without the need for edge selection operations, thereby improving the stability of the clock data recovery device.

[0017] According to the embodiments of the present disclosure, by setting the frequency detector to receive the phase difference output by the linear phase detector, the frequency difference between the four-level pulse amplitude modulation data and the multi-phase clock signal is directly determined, and then the frequency of the multi-phase clock model is adjusted, thereby reducing the hardware complexity and the chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1 A block diagram schematically shows a clock data recovery device without a reference clock according to an embodiment of the present disclosure;

[0020] Figure 2 A circuit block diagram of a linear phase detector according to an embodiment of the present disclosure is schematically shown;

[0021] Figure 3The circuit block diagram of the frequency discriminator according to the embodiment of the present disclosure is schematically shown;

[0022] Figure 4 A circuit block diagram of a self-biased multi-phase clock generator according to an embodiment of the present disclosure is schematically shown;

[0023] Figure 5 A circuit block diagram of a first voltage-to-current converter according to an embodiment of the present disclosure is schematically shown;

[0024] Figure 6 The circuit block diagram of the LC oscillator according to the embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known systems and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0026] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0027] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0028] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0029] Figure 1 A block diagram of a clock data recovery device without a reference clock according to an embodiment of the present disclosure is schematically shown.

[0030] like Figure 1 As shown, the present disclosure provides a reference clock-free clock data recovery device, comprising:

[0031] The linear phase detector 10 is used to perform phase detection processing on the received four-level pulse amplitude modulation data DATA_IN and output a phase detection signal voltage V p , wherein the phase detection signal voltage is used to indicate the phase difference between the four-level pulse amplitude modulation data DATA_IN and the multi-phase clock signal REC_CLK.

[0032] The frequency detector 11 is used to perform frequency detection processing on the received phase detection voltage signal and output a frequency detection signal voltage V F , wherein the frequency discrimination signal voltage is used to represent the frequency difference between the four-level pulse amplitude modulation data DATA_IN and the multi-phase clock signal REC_CLK.

[0033] The first voltage-to-current converter 12 is used to convert the phase-comparison signal voltage V p Converted into phase-comparison signal current I p , and convert the discrimination signal voltage into the discrimination signal current I F , and output pulse signal current I according to the phase detection signal current and frequency detection signal current c .

[0034] The loop filter 13 is used to convert the pulse signal current I c Converted to control voltage V c .

[0035] The LC oscillator 14 is used to control the voltage V c Convert to quadrature clock signals.

[0036] The self-biased multi-phase clock generator 15 is used to output a multi-phase clock signal according to the orthogonal clock signal.

[0037] The start-up circuit 19 is used to discharge the control voltage to zero when powered on, so that the orthogonal clock signal has an initial frequency, so as to realize ergodic search of the control voltage.

[0038] In the embodiment of the present disclosure, the frequency detector is connected to the output end of the linear phase detector to receive the phase detection voltage signal V output by the linear phase detector. p , and directly according to the phase-comparison signal voltage V p Output frequency discrimination voltage signal V F , used to characterize whether the four-level pulse amplitude modulation data DATA_IN and the multi-phase clock signal REC_CLK have a large frequency difference. Compared with the existing input-based four-level pulse amplitude modulation data output frequency discrimination voltage signal, the connection structure is simpler. P With V F Converted to current, where V P The generated current I P With VP proportional to the current, and the current is small, V F The generated current I F For a larger current pulse, when V F When a pulse appears, output I F The pulse signal current output by the voltage-charge converter 12 is I C =I F +I P The control voltage is output according to the pulse signal current, and the frequency and phase of the generated clock signal are regulated based on the control voltage. Multiple adjustments are made in this loop until the phase and frequency are consistent with the input four-level pulse amplitude modulation data DATA_IN, thus completing data recovery.

[0039] Through the device of this embodiment, a wide range of data rates can be received without the need for an external reference clock, and the data rate can be spontaneously traversed and searched by controlling the voltage Vc, so that the clock data recovery device can operate at different data rates, improving the versatility under different communication protocols, making the device compatible with different communication protocols, and there is no need to redesign it in different usage scenarios, thereby improving efficiency.

[0040] According to an embodiment of the present disclosure, the acceptable range of the four-level pulse amplitude modulation data rate may be 52 Gb / s to 64 Gb / s.

[0041] According to an embodiment of the present disclosure, the device further includes: a data sampler 16, configured to sample the output multi-phase clock signal to generate a thermometer code.

[0042] The decoder 17 is used to decode the thermometer code to generate a first data signal; the output buffer 18 is used to buffer the first data signal and output a second data signal.

[0043] In the embodiments of the present disclosure, by connecting the input end of the data sampler with the output end of the linear phase detector, decoupling of the data sampler from the linear phase detector and the frequency detector is achieved, which will not interfere with the stability of the operation of the linear phase detector and the frequency detector and simplifies the circuit structure.

[0044] According to an embodiment of the present disclosure, a linear phase detector determines a phase difference using a Euclidean distance algorithm.

[0045] In the embodiments of the present disclosure, since the traditional linear phase detector can only accept fixed edge data, it is necessary to set a feedback circuit inside it to connect with the data sampler to determine whether the input four-level pulse amplitude modulation data can be received, which makes the circuit structure of the linear phase detector complex and also affects the stability of the operation of the linear phase detector.

[0046] Based on this, in this embodiment, the linear phase detector based on the Euclidean distance algorithm can reduce the fluctuation of the control voltage Vc of the loop filter after the clock data recovery device is stabilized, and the differential clock jitter recovered by the inductor capacitor oscillator is small, so that the jitter of the final sampling clock REC_CLK is small, and the input data DATA_IN can be accurately sampled, reducing the bit error rate. At the same time, the data edges of all types of four-level pulse amplitude modulation data can be used, without the need for additional data edge selection operations, thereby improving the utilization rate of data edge phase information and accelerating the locking speed, so that the recovered clock REC_CLK can be quickly locked to the target frequency and phase. In addition, the frequency and phase detection path can be decoupled from the data sampling path without edge selection operations, thereby improving the stability of the clock data recovery device.

[0047] Figure 2 A circuit block diagram of a linear phase detector according to an embodiment of the present disclosure is schematically shown.

[0048] like Figure 2 As shown, according to an embodiment of the present disclosure, the linear phase detector includes:

[0049] The first sampling and holding circuit 20 is used to sample and output the input four-level pulse amplitude modulation data as the first data edge V D0 , the second data edge V D1 and the third data edge V E0 , wherein the third data edge is an intermediate data edge between the first data edge and the second data edge.

[0050] The voltage-current conversion unit 21 is used to convert the first data edge, the second data edge and the third data edge into the corresponding first data current, the second data current and the third data current respectively.

[0051] The first resistor R1 is used to convert the first data current, the second data current and the third data current into a first voltage V SUM .

[0052] The second sample and hold circuit 22 is used for sampling the first voltage.

[0053] The direction determination circuit 23 is used to determine the edge direction of the sampled first voltage and output a phase-discrimination voltage signal V according to the edge direction. P .

[0054] In the embodiment of the present disclosure, the first data edge V D0 , the second data edge V D1 and the third data edge V E0 , using the Euclidean distance algorithm to calculate, the calculated value is V D0 +V D1 -2×VE0 Among them, the first data edge V D0 , the second data edge V D1 and the third data edge V E0 The ratio of the voltage-to-current converters is 1:-2:1. The current converted by the three voltage-to-current converters is calculated according to the ratio relationship set, and the first voltage V is calculated according to the first resistor. SUM , for V SUM After passing through the second sampling and holding circuit, the direction determination circuit determines whether the target data edge is a rising edge or a falling edge, and then determines V SUM The positive and negative of V P Input voltage to current converter.

[0055] The linear phase detection circuit of this embodiment can utilize data edges of all types of four-level pulse amplitude modulation data without the need for additional data edge selection operations, thereby improving the utilization rate of data edge phase information.

[0056] According to an embodiment of the present disclosure, the linear phase detector further includes:

[0057] The first low-pass filter 24 is used to determine whether the sampled first voltage has a DC bias.

[0058] The second voltage-to-current converter 25 is used for eliminating the DC bias when the sampled first voltage has a DC bias, outputting the first current, and outputting the first current as an updated first voltage through the first resistor.

[0059] In the embodiment of the present disclosure, since the current converted by the voltage-to-current conversion unit 21 usually brings about a DC offset, which affects the stability of the voltage, in this embodiment, a calibration loop composed of a low-pass filter 24 and a voltage-to-current converter 25 is provided to eliminate the DC offset in the circuit, thereby ensuring the stability of the phase detector under different process deviations, temperatures, and voltages.

[0060] Figure 3 The circuit block diagram of the frequency discriminator according to the embodiment of the present disclosure is schematically shown.

[0061] like Figure 3 As shown, according to an embodiment of the present disclosure, the frequency detector includes: a current logic circuit 30, which is used to output a first logic voltage V OP and the second logic voltage V ON .

[0062] The comparator 31 is used to determine the logic signal voltage V according to the first logic voltage and the second logic voltage. O, outputting a discrimination signal voltage according to the logic signal voltage, and controlling the discrimination signal current by using the discrimination signal voltage to reduce the frequency difference between the four-level pulse amplitude modulation data and the multi-phase clock signal.

[0063] In the embodiment of the present disclosure, the logic signal voltage is the difference between the first logic voltage and the second logic voltage. When the logic signal voltage is greater than zero, it is determined that the frequency difference between the four-level pulse amplitude modulation data and the multi-phase clock signal is too large, and the first voltage-to-current converter is controlled to open by outputting the discrimination signal voltage through the comparator 31, releasing a large current to the loop filter, and reducing the frequency difference between DATA_IN and REC_CLK. The self-closing function of the discriminator circuit can be realized by this device.

[0064] According to an embodiment of the present disclosure, the current logic circuit includes: a second resistor R2 and a third resistor R3 connected in series, for outputting a first logic voltage V from a connection point between the second resistor and the third resistor. OP .

[0065] The fourth resistor R4 and the fifth resistor R5 connected in series are used to output a second logic voltage V from the connection point between the third resistor and the fourth resistor. ON , wherein the difference between the first logic voltage and the second logic voltage is the logic signal voltage.

[0066] The first transistor M1, the source of the first transistor is connected to the end of the third resistor away from the second resistor, and the gate of the first transistor is used to receive the input first phase-discrimination voltage V PP .

[0067] The second transistor M2, the source of the second transistor is connected to the end of the fifth resistor away from the fourth resistor, the drain of the second transistor is connected to the drain of the first transistor and connected to the current source and then grounded, and the gate of the second transistor is used to receive the input second phase-discrimination voltage V PN , where the difference between the first phase-comparison voltage and the second phase-comparison voltage is the phase-comparison signal voltage V P .

[0068] In the embodiment of the present disclosure, the current mode logic circuit 30 can linearly amplify the output V of the linear phase detector. P And isolate the feedthrough of the subsequent comparator 31 from V P In addition, the resistor matrix R2, R3, R4, and R5 in the current mode logic circuit 30 can be used to output V O Bringing DC offset, only the phase detection signal voltage V P Greater than the threshold V TH When V O will be greater than 0, in which case it is judged that the deviation between the DATA_IN data rate and the REC_CLK clock frequency is too large. Ois greater than 0, the comparator will output the frequency discrimination signal V F , V F The voltage-to-current converter will be controlled to open, releasing a large current to the loop filter and reducing the frequency difference between DATA_IN and REC_CLK.

[0069] Figure 4 A circuit block diagram of a self-biased multi-phase clock generator according to an embodiment of the present disclosure is schematically shown.

[0070] like Figure 4 As shown, according to an embodiment of the present disclosure, the self-biased multi-phase clock generator includes: a phase detector 40, which is used to receive an orthogonal clock signal and output a phase difference between the orthogonal clock signal and the multi-phase clock signal.

[0071] The charge pump 41 is used to generate a first multi-phase current using the phase difference output by the phase detector.

[0072] The second low-pass filter 42 is connected to the output end of the charge pump and is used for converting the first multi-phase current into a first multi-phase voltage.

[0073] The third transistor M3 has a gate connected to the output end of the second low-pass filter, the gate is used to receive the first multi-phase voltage, and outputs the second multi-phase current from the drain.

[0074] The fourth transistor M4 has a gate connected to the gate of the third transistor and a drain connected to the charge pump, and is used to output a third multi-phase current and use the third multi-phase current to regulate the first multi-phase current.

[0075] The ring oscillator 43 is connected to the drain of the third transistor and is used to adjust the frequency and phase of the received second multi-phase current.

[0076] The multi-phase clock circuit 44 is used to output the regulated second multi-phase current as a multi-phase clock signal.

[0077] According to an embodiment of the present disclosure, the phase differences of adjacent clock signals in the multi-phase clock signal are the same, and the number of the multi-phase clock signal includes 8 phases.

[0078] In the embodiment of the present disclosure, after the quadrature clock generated by the inductive capacitor oscillator is input into the self-biased multi-phase clock generator, the phase difference between the multi-phase clock signal and the quadrature clock is first extracted by the phase detector and output to the charge pump to generate the first multi-phase current I CP . Through the first multi-phase current I CP After passing through the second low-pass filter, the first multi-phase voltage V is generated CP , controlling the current magnitude of transistors M3 and M4, wherein M1 generates a third multi-phase current I RCCOIt will be input into the ring oscillator to control the frequency and phase of the ring oscillator output signal. M4 generates current I B Will be fed back to the charge pump to regulate I CP The size of the circuit can keep the loop bandwidth consistent under different process deviations, temperatures, and voltages, improve the stability of the device, and fully suppress the phase noise introduced by the internal ring oscillator. Therefore, a ring oscillator with a smaller area and the ability to generate multi-phase clocks can still achieve lower jitter, reduce the complexity of chip design, and accurately sample DATA_IN at the same time.

[0079] According to an embodiment of the present disclosure, a frequency divider 45 is further included to make the phases and frequencies of the orthogonal clock signal output by the LC oscillator and the multi-phase clock signal output by the self-biased multi-phase clock generator the same at 0° and 180°.

[0080] Figure 5 A circuit block diagram of a first voltage-to-current converter according to an embodiment of the present disclosure is schematically shown.

[0081] like Figure 5 As shown, according to an embodiment of the present disclosure, the first voltage-to-current converter includes: a linear voltage-to-current converter 50 and a pulse voltage-to-current converter 51 .

[0082] The linear voltage-to-current converter comprises: a fifth transistor M5, whose gate is used to receive the first phase-discrimination voltage V PP。

[0083] The sixth transistor M6 has a gate and a drain connected to the source of the fifth transistor, and a source of the sixth transistor connected to a voltage source.

[0084] The seventh transistor M7 has a gate for receiving the second phase-discrimination voltage V PN The drain of the seventh transistor is connected to the drain of the fifth transistor, and is connected to the current source and then grounded.

[0085] The eighth transistor M8 has a gate and a drain connected to the source of the seventh transistor, and a source of the eighth transistor connected to a voltage source.

[0086] The ninth transistor M9 has a gate connected to the gate of the sixth transistor, and a source connected to the voltage source.

[0087] The tenth transistor M 10 , a gate of which is connected to the gate of the eighth transistor, and a source of the tenth transistor is connected to the voltage source.

[0088] The eleventh transistor M 11 , its gate and source are connected to the drain of the ninth transistor, and the drain of the eleventh transistor is grounded.

[0089] The twelfth transistor M 12 , whose gate is connected to the gate of the eleventh transistor, the source of the twelfth transistor is connected to the drain of the tenth transistor, the drain of the twelfth transistor is grounded, wherein the phase detection signal current I is output from the source of the twelfth transistor P .

[0090] The thirteenth transistor M 13 , whose gate receives the first discrimination voltage V FN , the drain of the thirteenth transistor outputs the frequency discrimination signal current.

[0091] The fourteenth transistor M 14 , whose gate receives the second discrimination voltage V FP The source of the fourteenth transistor is connected to the source of the thirteenth transistor and to the current source, and the drain of the fourteenth transistor is grounded, wherein the second discrimination voltage V FP With the first discrimination voltage V FN The difference is the demodulation signal voltage.

[0092] In the embodiment of the present disclosure, the linear voltage-to-current converter 50 converts the input differential voltage V PP 、V PN After being converted into current, it passes through transistor M9-M 12 The current is replicated and the differential current is converted to a single-ended current, achieving an output current I P With input voltage V P The phase information obtained by the linear phase detector can be accurately input into the overall loop to accurately adjust the phase of the recovered clock REC_CLK.

[0093] The pulse voltage-to-current converter consists of a large current source and a transistor M 13 -M 14 When the frequency detector detects a frequency difference between the input data DATA_IN and the recovered clock REC_CLK, V FN 、V FP Will turn on transistor M 13 , turn off transistor M 14 To release the large current I F to the loop filter to reduce the frequency difference between DATA_IN and REC_CLK; when the frequency detector 11 does not detect the frequency difference between the input data DATA_IN and the recovered clock REC_CLK, V FN 、V FP Will turn on transistor M 14 , turn off transistor M9 to turn off the large current I FThe current generated by the current source is exported to the ground to avoid the leakage current being released into the loop filter, which would affect the device locking to the correct frequency and phase.

[0094] Figure 6 The circuit block diagram of the LC oscillator according to the embodiment of the present disclosure is schematically shown.

[0095] like Figure 6 As shown, according to an embodiment of the present disclosure, the LC oscillator includes:

[0096] The fifteenth transistor M 15 , with its drain connected to ground.

[0097] The sixteenth transistor M 16 , its drain is grounded, the gate of the sixteenth transistor is connected to the source of the fifteenth transistor, and the source of the sixteenth transistor is connected to the gate of the fifteenth transistor.

[0098] The seventeenth transistor M 17 , whose drain is connected to the source of the fifteenth transistor, and the source of the seventeenth transistor is connected to the voltage source.

[0099] The eighteenth transistor M 18 , its gate is connected to the drain of the first period transistor, the source of the eighteenth transistor is connected to the voltage source, and the drain of the eighteenth transistor is connected to the gate of the seventeenth transistor.

[0100] The first capacitor has one end connected to the drain of the seventeenth transistor.

[0101] The second capacitor has one end connected to the drain of the eighteenth transistor and the other end connected to the other end of the first capacitor.

[0102] A switch capacitor group has one end connected to the drain of the seventeenth transistor and the other end connected to the drain of the eighteenth transistor.

[0103] In the embodiment of the present disclosure, by controlling the input V C The capacitance of the first capacitor and the second capacitor is changed to control the frequency and phase of the quadrature clock generated by the LC oscillator 14. The control word P can select different frequency bands to traverse and search for frequencies through the switch capacitor group, thereby expanding the frequency locking range of the device.

[0104] A second aspect of the present disclosure provides a clock data recovery method based on a clock data recovery device without a reference clock, comprising:

[0105] When the startup circuit is powered on, it outputs a high level signal.

[0106] According to the high level signal, the control voltage of the control loop filter is discharged to zero, the loop is disconnected, and the orthogonal clock signal output by the control LC oscillator is controlled to have an initial frequency.

[0107] After the start-up circuit is powered on, it outputs a low-level signal and the control loop is closed.

[0108] Based on the input four-level pulse amplitude modulation data, the output phase-discrimination voltage signal and frequency-discrimination voltage signal are determined.

[0109] The first voltage-current converter is controlled to charge and discharge the loop according to the phase-detection voltage signal and the frequency-detection voltage signal, so that the device starts to lock until the phase-detection voltage signal and the frequency-detection voltage signal meet preset conditions respectively.

[0110] When the phase-discrimination voltage signal and the frequency-discrimination voltage signal meet preset conditions respectively, the output multi-phase clock signal is sampled and a thermometer code is generated.

[0111] Decode and buffer the thermometer code and output the data signal.

[0112] It should be noted that the principle of the clock data recovery method of this embodiment is the same as that of the above-mentioned clock data recovery device without reference clock, which has been described in detail above and will not be repeated here.

[0113] According to the embodiment of the present disclosure, after a period of time has passed since the startup circuit started, the output signal RST of the startup circuit becomes a low level, allowing the entire loop to start working, the linear phase detector and the frequency detector charge the loop filter control voltage Vc through the first voltage-to-current converter, and the reference clock-free clock data recovery circuit starts to lock and generate a clock with the required frequency and phase.

[0114] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0115] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A clock data recovery device without reference clock, characterized in that: include: A linear phase detector, used for performing phase detection processing on the received four-level pulse amplitude modulation data and outputting a phase detection signal voltage, wherein the phase detection signal voltage is used to represent the phase difference between the four-level pulse amplitude modulation data and the multi-phase clock signal; A frequency discriminator, used for performing frequency discrimination processing on the received phase discrimination voltage signal and outputting a frequency discrimination signal voltage, wherein the frequency discrimination signal voltage is used to represent the frequency difference between the four-level pulse amplitude modulation data and the multi-phase clock signal; a first voltage-to-current converter, used for converting the phase-discrimination signal voltage into a phase-discrimination signal current, and converting the frequency-discrimination signal voltage into a frequency-discrimination signal current, and outputting a pulse signal current according to the phase-discrimination signal current and the frequency-discrimination signal current; A loop filter, used for converting the pulse signal current into a control voltage; an LC oscillator, for converting the control voltage into a quadrature clock signal; A self-biased multi-phase clock generator, configured to output the multi-phase clock signal according to the orthogonal clock signal; The startup circuit is used to discharge the control voltage to zero when powered on, so that the orthogonal clock signal has an initial frequency, so as to realize ergodic search of the control voltage.

2. The device according to claim 1, characterized in that Also includes: A data sampler, used for sampling the output multi-phase clock signal to generate a thermometer code; A decoder, configured to decode the thermometer code to generate a first data signal; The output buffer is used to buffer the first data signal and output a second data signal.

3. The device according to claim 1, characterized in that The linear phase detector determines the phase difference using a Euclidean distance algorithm.

4. The device according to claim 1 or 3, characterized in that: The linear phase detector comprises: A first sampling and holding circuit is used to sample and output the input four-level pulse amplitude modulation data as a first data edge, a second data edge and a third data edge, wherein the third data edge is an intermediate data edge between the first data edge and the second data edge; a voltage-current conversion unit, configured to convert the first data edge, the second data edge and the third data edge into corresponding first data current, second data current and third data current respectively; a first resistor, configured to convert the first data current, the second data current and the third data current into a first voltage; A second sample-and-hold circuit, used for sampling the first voltage; The direction decision circuit is used to determine the edge direction of the sampled first voltage and output a phase-discrimination voltage signal according to the edge direction.

5. The device according to claim 4, characterized in that The linear phase detector also includes: a first low-pass filter, used to determine whether the sampled first voltage has a DC bias; The second voltage-to-current converter is used for eliminating the DC bias when the sampled first voltage has a DC bias, outputting a first current, and outputting the first current through the first resistor to update the first voltage.

6. The device according to claim 1, characterized in that The frequency discriminator includes: A current logic circuit, configured to output a first logic voltage and a second logic voltage; A comparator is used to determine a logic signal voltage according to the first logic voltage and the second logic voltage, output the discrimination signal voltage according to the logic signal voltage, and control the discrimination signal current using the discrimination signal voltage to reduce the frequency difference between the four-level pulse amplitude modulation data and the multi-phase clock signal.

7. The device according to claim 6, characterized in that The current logic circuit comprises: A second resistor and a third resistor connected in series, used to output the first logic voltage from a connection point between the second resistor and the third resistor; a fourth resistor and a fifth resistor connected in series, used to output a second logic voltage from a connection point between the third resistor and the fourth resistor, wherein a difference between the first logic voltage and the second logic voltage is the logic signal voltage; A first transistor, wherein a source of the first transistor is connected to an end of the third resistor away from the second resistor, and a gate of the first transistor is used for receiving an input first phase-discrimination voltage; A second transistor, wherein the source of the second transistor is connected to an end of the fifth resistor away from the fourth resistor, the drain of the second transistor is connected to the drain of the first transistor, and the gate of the second transistor is used to receive an input second phase-locking voltage, wherein the difference between the first phase-locking voltage and the second phase-locking voltage is the phase-locking signal voltage.

8. The device according to claim 1, characterized in that The self-biased multi-phase clock generator comprises: a phase detector, configured to receive the quadrature clock signal and output a phase difference between the quadrature clock signal and the multi-phase clock signal; A charge pump, used for generating a first multi-phase current from a phase difference output by the phase detector; a second low-pass filter, arranged to be connected to an output end of the charge pump, and configured to convert the first multi-phase current into a first multi-phase voltage; a third transistor, wherein a gate of the third transistor is connected to the output end of the second low-pass filter, the gate is used to receive the first multi-phase voltage, and output a second multi-phase current from the drain; a fourth transistor, wherein a gate of the fourth transistor is connected to the gate of the third transistor, a drain of the fourth transistor is connected to the charge pump, and is configured to output a third multi-phase current and use the third multi-phase current to regulate the first multi-phase current; a ring oscillator, arranged to be connected to the drain of the third transistor, and used for regulating the frequency and phase of the received second multi-phase current; The multi-phase clock circuit is used to output the regulated second multi-phase current as the multi-phase clock signal.

9. The device according to claim 8, characterized in that The phase differences of adjacent clock signals in the multi-phase clock signals are the same.

10. A clock data recovery method based on a clock data recovery device without a reference clock, characterized in that: include: When the start-up circuit is powered on, the start-up circuit outputs a high level signal; According to the high-level signal, the control voltage of the control loop filter is discharged to zero, the loop is disconnected, and the orthogonal clock signal output by the inductor-capacitor oscillator is controlled to have an initial frequency; After the start-up circuit is powered on, the start-up circuit outputs a low-level signal, and the control loop is closed; Based on the input four-level pulse amplitude modulation data, the output phase-discrimination voltage signal and the frequency-discrimination voltage signal are determined; Controlling the first voltage-to-current converter to charge and discharge the loop according to the phase-discrimination voltage signal and the frequency-discrimination voltage signal, so that the device starts to lock until the phase-discrimination voltage signal and the frequency-discrimination voltage signal respectively meet preset conditions; When the phase-discrimination voltage signal and the frequency-discrimination voltage signal respectively meet preset conditions, sampling the output multi-phase clock signal and generating a thermometer code; The thermometer code is decoded and buffered, and a data signal is output.

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