Capacitor calibration method and device, computer equipment, storage medium and program product

Abstract

The invention relates to the technical field of integrated circuits, and discloses a capacitor calibration method and device, computer equipment, a storage medium and a program product. The method is applied to a calibration module in a capacitor calibration system. The calibration module is electrically connected with the multiplication digital-to-analog converter; the multiplication digital-to-analog converter comprises 2n sampling capacitors, n sampling capacitors are connected to a first reference voltage, and the other n sampling capacitors are connected to a second reference voltage; the method comprises the following steps: aiming at an mth sampling capacitor, overturning a reference voltage of the mth sampling capacitor and a reference voltage of a sampling capacitor corresponding to the mth sampling capacitor, and determining a calibration value of the mth sampling capacitor according to output voltages of a multiplication digital-to-analog converter before and after overturning, so as to calibrate the mth sampling capacitor through a calibration module; and the sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected with different reference voltages. According to the scheme, when the capacitor calibration function is achieved, the scheme is simple and convenient, and reliability and accuracy are good.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a capacitance calibration method, device, computer equipment, storage medium and program product. Background Art

[0002] Capacitor mismatch refers to the deviation between the actual and designed sampling capacitor values. During the chip production process of high-precision pipeline analog-to-digital converters (Pipeline ADCs), sampling capacitor mismatch errors in the multiplying digital-to-analog converter (MDAC) are unavoidable, necessitating the introduction of a calibration algorithm to calibrate the capacitor mismatch.

[0003] In related technologies, a foreground calibration algorithm is used to calibrate capacitor mismatch, and the capacitor mismatch is calculated by calculating the weight at the comparison threshold voltage point. Additional analog circuits need to be added to complete the calibration function, such as adding additional calibration capacitors and switches, or fixing the input at a fixed level, which not only affects the area and power consumption, but also increases the complexity of the overall circuit.

[0004] Therefore, a simple and accurate capacitance calibration method is urgently needed. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a capacitance calibration method, apparatus, computer equipment, storage medium and program product to solve the problem that capacitance calibration is not simple and accurate enough.

[0006] In a first aspect, the present invention provides a capacitance calibration method, which is applied to a calibration module in a capacitance calibration system; the capacitance calibration system also includes a multiplying digital-to-analog converter, and the calibration module is electrically connected to the multiplying digital-to-analog converter; the multiplying digital-to-analog converter includes 2n sampling capacitors, wherein n of the 2n sampling capacitors are connected to a first reference voltage, and the other n sampling capacitors are connected to a second reference voltage; the method includes:

[0007] For an mth sampling capacitor, a reference voltage of the mth sampling capacitor and a reference voltage of a sampling capacitor corresponding to the mth sampling capacitor are flipped, and a calibration value of the mth sampling capacitor is determined based on output voltages of the multiplying digital-to-analog converter before and after the flipping, so as to calibrate the mth sampling capacitor through the calibration module; and a sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected to different reference voltages.

[0008] In an optional implementation, among the 2n sampling capacitors, the 1st to nth sampling capacitors are connected to a first reference voltage, and the n+1th to 2nth sampling capacitors are connected to a second reference voltage;

[0009] The step of flipping the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor, and determining a calibration value of the mth sampling capacitor based on the output voltages of the multiplying digital-to-analog converter before and after the flipping, includes:

[0010] Switching the first sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, switching the (n+1)th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage as a reference state, and obtaining a first output voltage of the multiplying digital-to-analog converter;

[0011] Switching the ath sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, and switching the a-1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, to obtain the ath inverted output voltage of the multiplication digital-to-analog converter; wherein a∈[2,n+1];

[0012] Obtaining a calibration value of the ath sampling capacitor based on the first output voltage and the ath inverted output voltage;

[0013] Resetting to the reference state; switching the bth sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, and switching the b-1th sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, to obtain the bth output voltage of the multiplication digital-to-analog converter; wherein b∈[n+2, 2n];

[0014] A calibration value of the bth sampling capacitor is obtained based on the (n+1)th inverted output voltage and the bth output voltage.

[0015] In an optional implementation, obtaining a calibration value of the ath sampling capacitor based on the first output voltage and the ath inverted output voltage includes:

[0016] The difference between the a-th inverted output voltage and the first output voltage is used as a calibration value of the a-th sampling capacitor.

[0017] In an optional implementation, obtaining a calibration value of the bth sampling capacitor based on the (n+1)th inverted output voltage and the bth output voltage includes:

[0018] The difference between the (n+1)th inverted output voltage and the (b)th output voltage is used as a calibration value of the (b)th sampling capacitor.

[0019] In a second aspect, the present invention provides a capacitance calibration system, the system comprising:

[0020] A multiplying digital-to-analog converter, comprising 2n sampling capacitors; wherein n of the 2n sampling capacitors are connected to a first reference voltage, and the other n sampling capacitors are connected to a second reference voltage;

[0021] The calibration module is electrically connected to the multiplying digital-to-analog converter and is used to:

[0022] For an mth sampling capacitor, a reference voltage of the mth sampling capacitor and a reference voltage of a sampling capacitor corresponding to the mth sampling capacitor are flipped, and a calibration value of the mth sampling capacitor is determined based on output voltages of the multiplying digital-to-analog converter before and after the flipping, so as to calibrate the mth sampling capacitor through the calibration module; and a sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected to different reference voltages.

[0023] In an optional implementation, the input end of the multiplying digital-to-analog converter is short-circuited.

[0024] In an optional embodiment, the capacitance calibration system further includes a pipeline analog-to-digital converter; the pipeline analog-to-digital converter includes at least two of the multiplication digital-to-analog converters.

[0025] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the capacitance calibration method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0026] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the capacitance calibration method of the first aspect or any corresponding embodiment thereof.

[0027] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the capacitance calibration method of the first aspect or any corresponding embodiment thereof.

[0028] The technical solution provided by the present invention can have the following beneficial effects:

[0029] The capacitance calibration method provided by the present invention first flips the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor connected to a different reference voltage than the mth sampling capacitor, and determines the calibration value of the mth sampling capacitor based on the output voltage of the multiplying digital-to-analog converter before and after the flip, thereby calibrating the mth sampling capacitor through a calibration module. The above scheme can simultaneously flip the sampling capacitors connected to different reference voltages during the capacitance calibration process and determine the calibration value of the sampling capacitor based on the difference in output voltage before and after the flip, without adding additional sampling capacitors or input voltages. The calibration value of the sampling capacitor is determined while ensuring that the output voltage of the multiplying digital-to-analog converter is stable within a certain range and without affecting the reliability and accuracy of the multiplying digital-to-analog converter. The scheme is simple, reliable, and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 is a flow chart of a capacitance calibration method according to an embodiment of the present invention;

[0032] Figure 2 is a schematic flow chart of another capacitance calibration method according to an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a capacitance calibration method in the related art is shown;

[0034] Figure 4 is a schematic diagram of a capacitance calibration method according to an embodiment of the present invention;

[0035] Figure 5 is a schematic diagram of the operation of a calibration module according to an embodiment of the present invention;

[0036] Figure 6 is a structural block diagram of a capacitance calibration system according to an embodiment of the present invention;

[0037] Figure 7 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0039] Capacitor mismatch refers to the deviation between the actual and designed sampling capacitor values. During the chip production process of high-precision pipeline analog-to-digital converters (Pipeline ADCs), sampling capacitor mismatch errors in the multiplying digital-to-analog converter (MDAC) are unavoidable, necessitating the introduction of a calibration algorithm to calibrate the capacitor mismatch.

[0040] In related technologies, a foreground calibration algorithm is used to calibrate capacitor mismatch, and the capacitor mismatch is calculated by calculating the weight at the comparison threshold voltage point. Additional analog circuits need to be added to complete the calibration function, such as adding additional calibration capacitors and switches, or fixing the input at a fixed level, which not only affects the area and power consumption, but also increases the complexity of the overall circuit.

[0041] Therefore, an embodiment of the present invention provides a capacitance calibration method, which improves the simplicity and accuracy of capacitance calibration by simultaneously flipping the reference voltages connected to two sampling capacitors.

[0042] According to an embodiment of the present invention, an embodiment of a capacitance calibration method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] In this embodiment, a capacitance calibration method is provided, which is applied to a calibration module in a capacitance calibration system. The capacitance calibration system also includes a multiplying digital-to-analog converter, and the calibration module is electrically connected to the multiplying digital-to-analog converter. The multiplying digital-to-analog converter includes 2n sampling capacitors, wherein n of the 2n sampling capacitors are connected to a first reference voltage, and the remaining n sampling capacitors are connected to a second reference voltage. The calibration module can be a laptop computer, a desktop computer, an industrial computer, a computer module, etc. Figure 1 is a flow chart of a capacitance calibration method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0044] Step S101: For an mth sampling capacitor, a reference voltage of the mth sampling capacitor and a reference voltage of a sampling capacitor corresponding to the mth sampling capacitor are flipped, and a calibration value of the mth sampling capacitor is determined based on the output voltages of the multiplying digital-to-analog converter before and after the flipping, so as to calibrate the mth sampling capacitor through the calibration module.

[0045] In actual application scenarios, since the sampling capacitor mismatch error in the multiplication digital-to-analog converter is difficult to avoid, the sampling capacitors in the multiplication digital-to-analog converter are calibrated by the calibration module in the present invention. The multiplication digital-to-analog converter includes 2n sampling capacitors, where n is a positive integer, that is, the multiplication digital-to-analog converter includes an even number of sampling capacitors. Since if the output voltage of the multiplication digital-to-analog converter varies too much or exceeds the normal operating range, it may cause output distortion, inability to accurately reflect the actual operating state, component damage, etc., which reduces the reliability and accuracy of the multiplication digital-to-analog converter. Therefore, half of the sampling capacitors in the multiplication digital-to-analog converter are connected to a first reference voltage, and the other half of the sampling capacitors are connected to a second reference voltage, thereby ensuring that the output voltage of the multiplication digital-to-analog converter is near 0V.

[0046] The mth sampling capacitor is one of the 2n sampling capacitors of the multiplying digital-to-analog converter. The sampling capacitor corresponding to the mth sampling capacitor is connected to a different reference voltage than the mth sampling capacitor. During capacitance calibration, the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor are simultaneously flipped, thereby ensuring that the output voltage of the multiplying digital-to-analog converter remains near 0V during the capacitance calibration process, ensuring the reliability and accuracy of the multiplying digital-to-analog converter, and thus ensuring the accuracy of capacitance calibration. The sampling capacitor corresponding to the mth sampling capacitor can be a sampling capacitor pre-selected as a reference among the sampling capacitors of the multiplying digital-to-analog converter. It should be noted that since capacitance mismatch in the multiplying digital-to-analog converter is primarily caused by different weights and mismatches between the sampling capacitors, the sampling capacitor used as the reference does not need to be an ideal sampling capacitor. Capacitance calibration only requires ensuring that there is no mismatch between the sampling capacitors. Due to the presence of sampling capacitor mismatch, the output voltage of the multiplying digital-to-analog converter differs before and after the flip. Based on the difference in output voltage before and after the flip, the difference between the mth sampling capacitor and the sampling capacitor corresponding to the mth sampling capacitor, i.e., the difference between the mth sampling capacitor and the reference sampling capacitor, is determined, thereby obtaining a calibration value for the mth sampling capacitor. The calibration module then performs capacitance calibration on the mth sampling capacitor based on the calibration value, bringing the performance of the mth sampling capacitor closer to that of the reference sampling capacitor. Repeating the above steps, capacitance calibration is performed on each sampling capacitor in the multiplying digital-to-analog converter, thereby completing capacitance calibration of the multiplying digital-to-analog converter.

[0047] The capacitance calibration method provided in this embodiment first flips the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor connected to a different reference voltage than the mth sampling capacitor. The calibration value of the mth sampling capacitor is determined based on the output voltage of the multiplying digital-to-analog converter before and after the flip, thereby calibrating the mth sampling capacitor via a calibration module. This method allows for simultaneously flipping the sampling capacitors connected to different reference voltages during the capacitance calibration process and determining the calibration value of the sampling capacitor based on the difference in output voltage before and after the flip. This method eliminates the need for adding additional sampling capacitors or input voltages. This method ensures that the output voltage of the multiplying digital-to-analog converter remains stable within a certain range and does not affect the reliability and accuracy of the multiplying digital-to-analog converter. The method is simple, reliable, and accurate.

[0048] In this embodiment, a capacitance calibration method is provided, which is applied to a calibration module in a capacitance calibration system. The capacitance calibration system also includes a multiplying digital-to-analog converter, and the calibration module is electrically connected to the multiplying digital-to-analog converter. The multiplying digital-to-analog converter includes 2n sampling capacitors, wherein n of the 2n sampling capacitors are connected to a first reference voltage, and the remaining n sampling capacitors are connected to a second reference voltage. The calibration module can be a laptop computer, a desktop computer, an industrial computer, a computer module, etc. Figure 2 is a flow chart of a capacitance calibration method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0049] Step S201: For an mth sampling capacitor, flip the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor, and determine a calibration value of the mth sampling capacitor based on the output voltages of the multiplying digital-to-analog converter before and after the flipping, so as to calibrate the mth sampling capacitor through the calibration module.

[0050] The sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected to different reference voltages.

[0051] Specifically, the above step S201 includes:

[0052] In step S2011, the first sampling capacitor is switched from being connected to the first reference voltage to being connected to the second reference voltage, and the n+1th sampling capacitor is switched from being connected to the second reference voltage to being connected to the first reference voltage as a reference state, and a first output voltage of the multiplying digital-to-analog converter is obtained.

[0053] Optionally, among the 2n sampling capacitors, the first to n sampling capacitors are connected to a first reference voltage, and the n+1 to 2n sampling capacitors are connected to a second reference voltage. With the first sampling capacitor as a reference, the first sampling capacitor and the n+1 sampling capacitor are simultaneously flipped to obtain the first output voltage of the current multiplying digital-to-analog converter. The current state (the first sampling capacitor, the n+2 to 2n sampling capacitors are connected to the second reference voltage, and the second to n+1 sampling capacitors are connected to the first reference voltage) is used as the reference state for capacitor calibration.

[0054] Optionally, the reference voltage is connected to the top plate of the sampling capacitor, that is, the top plates of the 1st to nth sampling capacitors are connected to the first reference voltage, and the top plates of the (n+1th) to 2nth sampling capacitors are connected to the second reference voltage.

[0055] It should be noted that, since the multiplying digital-to-analog converter is usually a differential structure, the first reference voltage and the second reference voltage are differential voltages. In the present invention, the first reference voltage is less than the second reference voltage as an example. The difference between the second reference voltage and the first reference voltage is the reference voltage of the multiplying digital-to-analog converter. The reference voltage usually represents the quantization range of the analog-to-digital converter ADC -V ref ~+V ref The first reference voltage and the second reference voltage can be set according to actual needs. The calibration module can control the reference voltage connected to each sampling capacitor by inputting a code, for example, inputting a 2n-bit binary code, where each bit of the code corresponds to a sampling capacitor. When the code bit corresponding to the sampling capacitor is 0, it means that the sampling capacitor is connected to the first reference voltage. When the code bit corresponding to the sampling capacitor is 1, it means that the sampling capacitor is connected to the second reference voltage. In addition, the calibration module can collect the output voltage of the multiplication converter and calculate the calibration value of the corresponding sampling capacitor based on the output voltage before and after the flip.

[0056] Step S2012: switching the ath sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, and switching the a-1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, to obtain the ath inverted output voltage of the multiplying digital-to-analog converter.

[0057] Where a∈[2,n+1]. When calibrating the ath sampling capacitor, the ath sampling capacitor and the a-1th sampling capacitor are simultaneously flipped. Similarly, when calibrating the a+1th sampling capacitor, the ath sampling capacitor is also flipped. That is, when the current sampling capacitor is flipped (switched from being connected to the first reference voltage to being connected to the second reference voltage), the sampling capacitor immediately preceding the current sampling capacitor is flipped back (the sampling voltage of the previous sequence was switched from being connected to the first reference voltage to being connected to the second reference voltage during the previous flip, and is switched from being connected to the second reference voltage to being connected to the first reference voltage during the current flip, returning to the connection state before the previous flip). That is, during the flipping, only one sampling capacitor originally connected to the first reference voltage is always switched to being connected to the second reference voltage, ensuring that the number of sampling capacitors simultaneously connected to the first reference voltage and the number of sampling capacitors connected to the second reference voltage are equal. This ensures that the output voltage of the multiplying digital-to-analog converter always remains near 0V, and the difference between the output voltage of the multiplying digital-to-analog converter after the current sampling capacitor flipping (the ath flipped output voltage, i.e., the output voltage of the multiplying digital-to-analog converter when the ath sampling capacitor is switched to being connected to the second reference voltage) and the first output voltage serving as the reference can be determined.

[0058] It should be noted that for the feasibility of the solution, the ath sampling capacitor and the a-1th sampling capacitor are flipped simultaneously each time. In fact, after each flip, only the 1st sampling capacitor and the ath sampling capacitor have changed compared to the coding in the reference state. Therefore, the calculated calibration value reflects the difference between the ath sampling capacitor and the 1st sampling capacitor of the seat reference.

[0059] Step S2013 , obtaining a calibration value of the a th sampling capacitor based on the first output voltage and the a th inverted output voltage.

[0060] Optionally, the difference between the ath inverted output voltage and the first output voltage is used as the calibration value of the ath sampling capacitor, thereby calibrating the ath sampling capacitor using the calibration value of the ath sampling capacitor, so that the state of the ath sampling capacitor can be close to that of the first sampling capacitor.

[0061] Step S2014 , resetting to the reference state, switching the bth sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, and switching the b-1th sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, and obtaining the bth output voltage of the multiplying digital-to-analog converter.

[0062] In the above steps, the process of switching the ath sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, and switching the a-1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage is repeated until the n+1th sampling capacitor is switched from being connected to the first reference voltage to being connected to the second reference voltage (i.e., the output voltages of the 1st to n+1st sampling capacitors are equal). After that, the sampling capacitors in the subsequent sequence are all sampling capacitors that have been pre-connected to the second reference voltage and cannot be switched from being connected to the first reference voltage to being connected to the second reference voltage. Therefore, the voltage values ​​of the inverted output voltages of the n+2nd to 2nth sampling capacitors are equal and are all equal to the inverted output voltage of the n+1th sampling capacitor. At this point, it is necessary to obtain the output voltages of the n+2nd to 2nth sampling capacitors when they are switched to being connected to the first reference voltage, i.e., the output voltages of the n+2nd to 2nth sampling capacitors, in order to obtain the calibration values ​​of the n+2nd to 2nth sampling capacitors.

[0063] Specifically, the voltage is reset to the reference state (the first sampling capacitor and the n+2 to 2n sampling capacitors are connected to the second reference voltage, and the second to n+1 sampling capacitors are connected to the first reference voltage). Then, the bth sampling capacitor and the b-1th sampling capacitor are simultaneously flipped to obtain the bth output voltage, where b∈[n+2, 2n].

[0064] Step S2015 , obtaining a calibration value of the bth sampling capacitor based on the (n+1)th inverted output voltage and the bth output voltage.

[0065] Optionally, the difference between the (n+1)th inverted output voltage and the (b)th output voltage is used as a calibration value of the (b)th sampling capacitor, thereby calibrating the (b)th sampling capacitor using the calibration value of the (b)th sampling capacitor, so that the state of the (b)th sampling capacitor can be close to that of the (1)th sampling capacitor.

[0066] In an optional embodiment, the input terminal of the multiplying digital-to-analog converter is short-circuited. By short-circuiting the input terminal of the multiplying digital-to-analog converter, it is possible to prevent the input terminal voltage of the multiplying digital-to-analog converter from affecting the capacitance calibration process.

[0067] In an optional embodiment, the capacitance calibration system further includes a pipelined analog-to-digital converter. The pipelined analog-to-digital converter includes at least two of the multiplying digital-to-analog converters. In other words, each multiplying digital-to-analog converter in the pipelined analog-to-digital converter can be calibrated using the capacitance calibration method of the present invention, thereby completing capacitance calibration of the pipelined analog-to-digital converter.

[0068] In an optional implementation, the capacitance values ​​of the sampling capacitors are equal.

[0069] It should be noted that in actual application scenarios, the number of sampling capacitors in the multiplying digital-to-analog converter is related to the number of bits of the multiplying digital-to-analog converter, and each sampling capacitor corresponds to a comparator. In the present invention, it is sufficient to ensure that the number of sampling capacitors is an even number, and the number of bits of the multiplying digital-to-analog converter is not specifically limited.

[0070] The capacitance calibration method provided in this embodiment first flips the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor connected to a different reference voltage than the mth sampling capacitor. The calibration value of the mth sampling capacitor is determined based on the output voltage of the multiplying digital-to-analog converter before and after the flip, thereby calibrating the mth sampling capacitor via a calibration module. This method allows for simultaneously flipping the sampling capacitors connected to different reference voltages during the capacitance calibration process and determining the calibration value of the sampling capacitor based on the difference in output voltage before and after the flip. This method eliminates the need for adding additional sampling capacitors or input voltages. This method ensures that the output voltage of the multiplying digital-to-analog converter remains stable within a certain range and does not affect the reliability and accuracy of the multiplying digital-to-analog converter. The method is simple, reliable, and accurate.

[0071] As one or more specific application examples of the embodiments of the present invention, the optimal implementation scheme or the solution that the inventor most wants to embody is described below in combination with specific application scenarios.

[0072] Figure 3 A schematic diagram of a capacitance calibration method in the related art is shown. Figure 4 is a schematic diagram of a capacitance calibration method according to an embodiment of the present invention.

[0073] Figure 3 and Figure 4 In this paper, a 3.5-bit multiplying DAC is taken as an example. The multiplying DAC contains 16 comparators (belonging to Figure 3 and Figure 4 The internal circuit of the Sub ADC in the multiplication digital-to-analog converter and the 16 sampling capacitors C corresponding to the 16 comparators are shown. s <0> to C s <15> , where the top plate of each sampling capacitor is connected to the first reference voltage V refn Or the second reference voltage V refp , where V refp -V refn =V ref . V IN Is the input voltage of the multiplying digital-to-analog converter. After the input terminal is short-circuited, the input voltage V IN =0. V OUTis the output voltage of the multiplying DAC, i.e. the output voltage of the residual amplifier. 2C is the capacitance of the feedback capacitor of the multiplying DAC. s It is a switch. force<15:0> is a 16-bit binary code that corresponds one-to-one with the 16 sampling capacitors. It is used to control the reference voltages connected to the 16 sampling capacitors. When the corresponding bit in the code is 0, the sampling capacitors are connected to the first reference voltage. When the corresponding bit in the code is 1, the sampling capacitors are connected to the second reference voltage.

[0074] like Figure 3 As shown, in the related art, when performing capacitance calibration, 16 sampling capacitors are set to eight 0s and eight 1s, and then one of the 0s is flipped to 1, and the mismatch of the corresponding capacitor is obtained by the output voltage difference. For example, before the flip, force<15:0>=0000 0000 1111 1111, and the corresponding output voltage is V out0 <15> , flip the 16th bit from 0 to 1. At this time, force<15:0>=1000 0000 1111 1111, and the corresponding output voltage is V out1 <15> , by flipping the output voltage difference V out1 <15> -V out0 <15> Get the sampling capacitor Cs corresponding to the 16th bit <15> Calibration value segment error <15> , that is, segment error <15> =V out1 <15> -V out0 <15> Among them, V out1 <x>Indicates the output voltage when the xth bit of the code is 1 (named as the flip output voltage in the above embodiment), that is, the xth flip output voltage, V out0 <x>= represents the output voltage when the xth bit of the code is 0, that is, the xth output voltage. However, since only one sampling capacitor is flipped, the output voltage of the multiplying digital-to-analog converter will jump from 0 to V ref , which can easily cause the op amp to exceed its normal output range (±V ref / 2), in order to prevent the capacitance calibration from being limited by the output range of the op amp, an additional sampling capacitor needs to be added, or an additional input voltage is required to set the input to a specific level to pull the output voltage back to the appropriate range. And because it is a differential structure, additional capacitors are added to both the in-phase and inverting terminals. Specifically, Figure 3 The dotted box in the figure is an additional sampling capacitor C cal ( Figure 3 The differential structure and the additional capacitors at the in-phase and inverting ends are not shown. When the multiplying DAC is in the sampling phase, the additional capacitors at the in-phase and inverting ends are connected to V cm When the multiplying DAC is in the amplifying phase, the additional capacitor at the in-phase terminal is connected to V refn , additional capacitor at the inverting end is connected to V refp ( Figure 3 Simplified as V refm ), the output voltage is brought into the normal range by charge transfer.

[0075] In the present invention, when performing capacitance calibration, one 0 and one 1 are flipped at the same time, and the flipped values ​​are kept as eight 0s and eight 1s. In this way, the output of the multiplication digital-to-analog converter is close to 0V before and after the flip. By calculating the difference in output voltage before and after the flip, the relative error between the current sampling capacitor and the first sampling capacitor can be obtained. Repeat this process 15 times to obtain the relative errors between the 15 sampling capacitors and the first sampling capacitor, completing the mismatch front-end calibration. Since the output of the op amp is always near 0 when the capacitance calibration method of the present invention is used, the calibration function can be completed without adding additional capacitance or voltage, ensuring the simplicity and reliability of the circuit and saving power consumption and area. For example, V out0 <13> The corresponding force<15:0>=1000 000011111111, V out1 <13> The corresponding force<15:0>=0010 0000 1111 1111, the calibration value of the sampling capacitor corresponding to the 13th bit code is relative error <13> =V out1 <13> -V out0 <13> .

[0076] Figure 5 : This is a working diagram of the calibration module according to an embodiment of the present invention. The calibration module can output force<15:0> to control the access of 16 sampling capacitors to the reference voltage, collect the output voltage of the multiplication digital-to-analog converter, and calculate the calibration value corresponding to each sampling capacitor. Specifically, when performing capacitor calibration, the calibration module first outputs force<15:0>=1000000001111111, sets the Sub ADC in the MDAC, and corresponds to the output voltage V of a multiplication digital-to-analog converter. out At this time, force<15:0> contains 8 0s and 8 1s, that is, 8 of the 16 sampling capacitors Cs<15:0> (15:0 represents 15 to 0) are connected to V refp , 8 V refn , so the reference voltage is at the middle level, and because the input of the multiplication DAC is short-circuited during the calibration process, the residual voltage after charge redistribution is 0 in the ideal state, and the output voltage V after the residual amplifier is amplified is out It should also be 0. However, due to the existence of capacitor mismatch, the residual voltage is not strictly equal to zero. For example, assuming that the sampling capacitor Cs <14> There is a mismatch, and force <14> =0, then the corresponding Then the output force<15:0> of the calibration module becomes 0100000001111111, that is, force <14> (referring to force<15:0> and the sampling capacitor Cs <14> The corresponding bit code) is flipped and force<15:0> still maintains 8 1s and 8 0s, then the corresponding Then The sampling capacitance Cs can be obtained <14> The corresponding calibration value c <14> Where C is the capacitance value of each sampling capacitor, V ref is the reference voltage of the multiplying DAC, V ref =V refp -V refn , ΔC is the capacitance change before and after flipping. Then, repeat this process to calculate the calibration value c<14:0> corresponding to Cs<14:0> and perform capacitance calibration on each sampling capacitor. It should be noted that V out0 <14:7> (i.e. V out0 <7> To V out0 <14> )The corresponding force<15:0> are all 1000 0000 0111 1111, so V out0 <14:7> are equal, but from V out0 <6> To start, in order to still maintain 8 0s and 8 1s, we need to force <7> Always 1, V out0 <6> The corresponding force<15:0> is 1000 0000 1011 1111, V out0 <5> The corresponding force<15:0> is 1000 0000 1101 1111, and so on, then V out0 <6:0> are all different. V out1 <14:0> is similar, V out1 <14:8> is different, and V out1 <7:0> are the same and correspond to force<15:0>0000 0000 1111 1111.

[0077] This embodiment also provides a capacitance calibration system. The calibration module in this system is used to implement the above-mentioned embodiments and preferred embodiments. Details already described are omitted for clarity. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the calibration module described in the following embodiments is preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0078] This embodiment provides a capacitance calibration system, such as Figure 6 Shown, including:

[0079] A multiplying digital-to-analog converter, comprising 2n sampling capacitors; wherein n of the 2n sampling capacitors are connected to a first reference voltage, and the other n sampling capacitors are connected to a second reference voltage;

[0080] The calibration module is electrically connected to the multiplying digital-to-analog converter and is used to:

[0081] For an mth sampling capacitor, a reference voltage of the mth sampling capacitor and a reference voltage of a sampling capacitor corresponding to the mth sampling capacitor are flipped, and a calibration value of the mth sampling capacitor is determined based on output voltages of the multiplying digital-to-analog converter before and after the flipping, so that the mth sampling capacitor is calibrated by the calibration module; and the sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected to different reference voltages.

[0082] In an optional embodiment, in the 2n sampling capacitors, the 1st to nth sampling capacitors are connected to the first reference voltage, and the n+1th to 2nth sampling capacitors are connected to the second reference voltage; the calibration module is further used to: convert the 1st sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, convert the n+1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage as a reference state, and obtain the first output voltage of the multiplication digital-to-analog converter; convert the ath sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, and convert the a-1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage. Inputting a first reference voltage to obtain an ath inverted output voltage of the multiplying digital-to-analog converter; wherein a∈[2, n+1]; obtaining a calibration value of the ath sampling capacitor based on the first output voltage and the ath inverted output voltage; resetting to the reference state; switching the bth sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, and switching the b-1th sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, to obtain a bth output voltage of the multiplying digital-to-analog converter; wherein b∈[n+2, 2n]; obtaining a calibration value of the bth sampling capacitor based on the n+1th inverted output voltage and the bth output voltage.

[0083] In an optional implementation, obtaining the calibration value of the ath sampling capacitor based on the first output voltage and the ath inverted output voltage includes: using the difference between the ath inverted output voltage and the first output voltage as the calibration value of the ath sampling capacitor.

[0084] In an optional embodiment, obtaining the calibration value of the bth sampling capacitor based on the (n+1)th inverted output voltage and the (b)th output voltage includes: using the difference between the (n+1)th inverted output voltage and the (b)th output voltage as the calibration value of the bth sampling capacitor.

[0085] In an optional implementation, the input terminal of the multiplying digital-to-analog converter is short-circuited.

[0086] In an optional embodiment, the capacitance calibration system further includes a pipeline analog-to-digital converter; the pipeline analog-to-digital converter includes at least two of the multiplication digital-to-analog converters.

[0087] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0088] The capacitance calibration device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0089] The embodiment of the present invention also provides a computer device having the above Figure 7 Capacitance calibration setup shown.

[0090] See also Figure 7 , Figure 7 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0091] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0092] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0093] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0094] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0095] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The bus connection is taken as an example.

[0096] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0097] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0098] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0099] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations shall fall within the scope of protection of the present invention.< / x> < / x>

Claims

1. A capacitance calibration method, characterized in that: A calibration module applied to a capacitance calibration system; the capacitance calibration system further includes a multiplication digital-to-analog converter, the calibration module is electrically connected to the multiplication digital-to-analog converter; the multiplication digital-to-analog converter includes 2n sampling capacitors, wherein n sampling capacitors of the 2n sampling capacitors are connected to a first reference voltage, and the other n sampling capacitors are connected to a second reference voltage; the method includes: For the mth sampling capacitor, the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor are flipped, and the calibration value of the mth sampling capacitor is determined according to the output voltage of the multiplication digital-to-analog converter before and after the flipping, so as to calibrate the mth sampling capacitor through the calibration module; the sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected to different reference voltages.

2. The method according to claim 1, characterized in that Among the 2n sampling capacitors, the 1st to nth sampling capacitors are connected to a first reference voltage, and the n+1st to 2nth sampling capacitors are connected to a second reference voltage; The step of flipping the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor, and determining the calibration value of the mth sampling capacitor according to the output voltage of the multiplication digital-to-analog converter before and after the flipping, comprises: Converting the first sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, converting the n+1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage as a reference state, and obtaining a first output voltage of the multiplication digital-to-analog converter; Convert the ath sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, and convert the a-1th sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, to obtain the ath flipped output voltage of the multiplication digital-to-analog converter; wherein a∈[2, n+1]; Obtaining a calibration value of the ath sampling capacitor based on the first output voltage and the ath inverted output voltage; Reset to the reference state; convert the bth sampling capacitor from being connected to the second reference voltage to being connected to the first reference voltage, and convert the b-1th sampling capacitor from being connected to the first reference voltage to being connected to the second reference voltage, to obtain the bth output voltage of the multiplication digital-to-analog converter; wherein b∈[n+2, 2n]; A calibration value of the bth sampling capacitor is obtained based on the (n+1)th inverted output voltage and the bth output voltage.

3. The method according to claim 2, characterized in that The step of obtaining a calibration value of the ath sampling capacitor based on the first output voltage and the ath inverted output voltage includes: The difference between the ath inverted output voltage and the first output voltage is used as a calibration value of the ath sampling capacitor.

4. The method according to claim 2, characterized in that: The step of obtaining a calibration value of the bth sampling capacitor based on the n+1th inverted output voltage and the bth output voltage includes: The difference between the n+1th inverted output voltage and the bth output voltage is used as a calibration value of the bth sampling capacitor.

5. A capacitance calibration system, characterized in that: The system comprises: A multiplication digital-to-analog converter, comprising 2n sampling capacitors; wherein n sampling capacitors among the 2n sampling capacitors are connected to a first reference voltage, and the other n sampling capacitors are connected to a second reference voltage; A calibration module is electrically connected to the multiplying digital-to-analog converter and is used to: For the mth sampling capacitor, the reference voltage of the mth sampling capacitor and the reference voltage of the sampling capacitor corresponding to the mth sampling capacitor are flipped, and the calibration value of the mth sampling capacitor is determined according to the output voltage of the multiplication digital-to-analog converter before and after the flipping, so as to calibrate the mth sampling capacitor through the calibration module; the sampling capacitor corresponding to the mth sampling capacitor and the mth sampling capacitor are connected to different reference voltages.

6. The system according to claim 5, characterized in that The input terminal of the multiplying digital-to-analog converter is short-circuited.

7. The system according to claim 5 or 6, characterized in that: The capacitance calibration system also includes a pipeline analog-to-digital converter; The pipeline analog-to-digital converter includes at least two multiplication digital-to-analog converters.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the capacitance calibration method according to any one of claims 1 to 4 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the capacitance calibration method according to any one of claims 1 to 4.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the capacitance calibration method according to any one of claims 1 to 4.

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