Arbitrary non-integer multiple multipoint parallel downsampling device based on FPGA

Abstract

The invention discloses an arbitrary non-integer multiple multipoint parallel downsampling device based on an FPGA (Field Programmable Gate Array), which is characterized in that a parallel data reading module reads N-point sampling data in parallel, and a data register set is used for reading the last data of the last clock period and the N-point parallel data of the current clock period; the position ordinal number counter group is used for storing a position ordinal number count value of N-point parallel data in the current clock period, the point extraction accumulation coefficient counter group is used for recording a point extraction accumulation coefficient, and the two values are updated according to the point extraction condition of the previous clock period; each comparator group in the comparator module is used for comparing the point extraction accumulation coefficient and the position ordinal count value to judge whether the corresponding point extraction unit executes point extraction operation or not, and the point extraction control module is used for controlling the multi-point parallel downsampling process. According to the invention, non-integral multiple downsampling is realized through multi-point parallel extraction, and the downsampling efficiency is effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of digital signal processing, and more specifically, relates to an arbitrary non-integer multiple multi-point parallel downsampling device based on FPGA. Background Art

[0002] Reducing the interference of harmonic components is an important issue in industrial production. Harmonic analysis of input voltage and current signals is one of the most important functions of oscilloscope power analyzers.

[0003] In the industry, the most mainstream harmonic analysis method is still based on the Fast Fourier Transform (FFT). As we all know, if the data frame of an FFT is not a full-cycle waveform, spectrum leakage will inevitably occur. Therefore, in a high-precision oscilloscope power analyzer, in order to suppress spectrum leakage as much as possible, it is necessary to first extract a full-cycle waveform of the input signal and then perform FFT analysis.

[0004] In a system with a fixed sampling frequency, after extracting a frame of full-cycle data of an input waveform using a synchronous acquisition method based on DDR SDRAM (hereafter referred to as DDR) cache, since the frequency of the input signal is unknown, the number of sampling points of the extracted full-cycle waveform data also changes with the input frequency. Figure 1 This is an example of a whole cycle statistical interval with a fixed sampling frequency. However, the FFT performed by the system is generally a fixed-point FFT (generally a power of 2, such as 4096 points, 8192 points, etc., and non-powers of 2 are also possible, such as 5120 points, etc.), so it is necessary to extract these changing points (whole cycle data) into a fixed number of points specified by the system, and then send the extracted points to the FFT module for calculation.

[0005] Data sampling can be divided into integer multiple sampling and non-integer multiple sampling. Integer multiple sampling refers to sampling with an integer sampling coefficient. For example, if a piece of data with 4096 points needs to be extracted into 512 points, then the sampling coefficient is 4096 / 512=8, which means that one point is extracted for every 8 points. Non-integer multiple sampling refers to sampling with a decimal sampling coefficient. For example, if a frame of data has 7813 points and needs to be extracted into 512 points, then the sampling coefficient is 7813 / 512=15.259765625, which means that one point is extracted for every 15.259765625 points.

[0006] In the existing non-integer multiple data extraction, only the FPGA serial implementation of fractional sampling is discussed. These existing methods either use non-uniformly spaced fractional sampling or fractional sampling based on linear interpolation, but without exception, they all describe low-cost implementations of simple serial sampling architectures. Figure 2This is a diagram of the theoretical architecture of serial sampling with fractional sampling. Since the harmonic analysis accuracy of the power analyzer is relatively high, the non-equally spaced fractional sampling method will bring unacceptable harmonic errors. In addition, although the serial sampling implementation architecture based on linear interpolation is relatively simple, its sampling efficiency is low because it can only process and judge one sampling point at a time.

[0007] In theory, multi-point parallel sampling can speed up the processing of non-integer multiple sampling by several times. However, since the parallelization of this type of algorithm is not a simple multi-path parallel superposition, but also needs to consider the relationship between adjacent parallel points in the same clock cycle, as well as the relationship between two adjacent points before and after two adjacent clock cycles, this undoubtedly increases the difficulty of designing the general architecture of the algorithm when parallelizing.

[0008] Figure 3 It is a schematic diagram of the data acquisition structure based on multi-point parallel sampling. Figure 4 This is a theoretical architecture diagram of non-integer multiple parallel sampling. Figure 3 and Figure 4 As shown, in actual engineering applications, there is such a scenario: under the synchronous acquisition method based on DDR cache, assuming that when the data of a certain channel is written to the memory, the data bit width of the write DMA module is M bits (that is, the data bit width of 1 sampling point is M bits), and the bit width of the DDR interface IP is K bits, where K is an integer multiple of M, and the multiple is N (that is, K = M × N). Then, in order to achieve high efficiency of subsequent data processing and high utilization of DDR data reading bandwidth, it is still necessary to read out the data in parallel according to Kbit, that is, read out N points in one shot, and it is also necessary to use N-point parallel decimal sampling to accelerate processing. If the serial decimal sampling method is still used after the N-point parallel reading, then in the ultra-long data stream, the data will inevitably accumulate in the FIFO until the back pressure, then the N-point parallel reading will be meaningless, and its processing efficiency is the same as the serial reading. Therefore, it is necessary to propose a multi-point parallel sampling to more efficiently realize non-integer multiple sampling. Summary of the invention

[0009] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an arbitrary non-integer multiple multi-point parallel downsampling device based on FPGA, which realizes non-integer multiple downsampling by performing multi-point parallel sampling, thereby effectively improving the downsampling efficiency.

[0010] In order to achieve the above-mentioned invention object, the FPGA-based arbitrary non-integer multiple multi-point parallel downsampling device of the present invention comprises a parallel data reading module, a data register group, a position ordinal counter group, a sampling point accumulation coefficient counter group, a comparator module, a sampling point module and a sampling point control module, wherein:

[0011] After receiving the data reading instruction sent by the sampling control module, the parallel data reading module reads the sampled data in parallel from the DDR, reads N data in each clock cycle to form N-bit parallel data x[N-1:0], and generates an N-bit parallel data valid signal Valid_Bus[N-1:0] according to the data valid signal of the current N-point parallel data, wherein Valid_Bus[n]=1 indicates that the nth data x[n] in the current N data is valid, and Valid_Bus[n]=0 indicates that the nth data x[n] in the current N data is invalid, and n=0,1,…,N-1; sends the N-point parallel data x[N-1:0] to the data register group, and sends the N-bit parallel data valid signal Valid_Bus[N-1:0] to the data register group and the position sequence counter group;

[0012] The data register group includes N+1 data registers Reg i , i = 0, 1, ..., N, under the control of the control module, the N-point parallel data x[N-1:0] is stored, where the data register Reg0 is used to store the N-1th data in the N-point parallel data read in the previous clock cycle, and the data register Reg j Used to store the j-1th data x[j-1] among the N-point parallel data read in this clock cycle, where j=1, 2, ..., N;

[0013] The position ordinal counter group includes N+1 position ordinal counters, which are used to store the position ordinal count values ​​CNT i , where the position sequence count value CNT0 is used to count the data valid signal of the data in the data register Reg0, and the position sequence count value CNT j Used to count the data valid signal Valid_Bus[j-1] of data x[j-1] in N-point parallel data; position sequence count value CNT i The initial value of is set by the control module, and then the N sampling point identification signals f output by the comparator module are j Update the count. The specific method is as follows:

[0014] The sampling point identification signal with the largest serial number is selected from all the sampling point identification signals with a value of 1, and its corresponding serial number is recorded as k. Each position sequence counter reads the value ACC of the kth sampling point accumulation coefficient counter in the previous clock cycle from the sampling point accumulation coefficient counter group. k ' Perform count updates in parallel, the specific method is as follows:

[0015] If k≠0, the following formula is used for cumulative counting:

[0016]

[0017] Among them, CNT i ′ represents the value of the ordinal counter of the i-th position in the previous clock cycle, and INT() represents obtaining an integer;

[0018] If k = 0, the following formula is used for cumulative counting:

[0019]

[0020] The sampling accumulation coefficient counter group includes N sampling accumulation coefficient counters, which are used to record the sampling accumulation coefficient ACC. j , sampling accumulation coefficient ACC j Used to record the sampling accumulation coefficient of the jth extracted data point; sampling accumulation coefficient ACC j The initial value of is set by the control module, and then the N sampling point identification signals f output by the comparator module are j Update the count. The specific method is as follows:

[0021] The sampling point identification signal with the largest serial number is selected from all the sampling point identification signals with a value of 1, and its corresponding serial number is recorded as k. Each sampling point accumulation coefficient counter is based on the value ACC of the kth sampling point accumulation coefficient counter in the previous clock cycle. k 'To update the count, the specific cumulative counting formula is as follows:

[0022]

[0023] Among them, ACC j ′ represents the value of the j-th sampling accumulation coefficient counter in the previous clock cycle, and M represents the sampling coefficient;

[0024] The comparator module includes N parallel comparator groups, and the jth comparator group includes D j Comparator D j =N-j+1 and OR gate circuit, where:

[0025] The jth comparator group is used to read D from the position sequence counter group. j Position ordinal count value Read the sample accumulation coefficient ACC from the sample accumulation coefficient counter group j ,i d The original serial number representing the ordinal count value of the dth position, d = 1, 2, ..., D j ,i d =j+d-1; D in the jth comparator group j The comparators compare the data in parallel and get D j Comparison result signal The data comparison logic is: If The comparison result signal Otherwise, the comparison result signal Then D j Comparison result signal Output to the OR gate circuit and the jth sampling unit;

[0026] OR gate circuit is used to j Comparison result signal Perform an OR operation to obtain the sampling point identification signal f j And sent to the position sequence counter group, the sampling point accumulation coefficient counter group and the jth sampling point unit;

[0027] The sampling module includes N sampling units, wherein the jth sampling unit receives D j Comparison result signal and the sampling point identification signal f j After that, determine the sampling point identification signal f j Is it 0? If so, the sampling unit does not need to be sampled. If not, all comparison result signals that are 1 are used. Filter out the sequence number i d The largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Then from the data register of the data register group and The data are read as [CNT A ] and [CNT B ], read the sampling accumulation coefficient ACC from the sampling accumulation coefficient counter group j , the sampling data DATA[j-1] is calculated using the following formula:

[0028] DATA[j-1]=(1-frac(ACC j ))×[CNT A ]+frac(ACC j )×[CNT B ]

[0029] Among them, frac() means to obtain the decimal part;

[0030] After completing the above linear interpolation calculation, each sampling unit outputs its sampling data DATA[j-1] and the corresponding valid signal Valid_Bus_Out[j-1]. When the jth sampling unit completes a sampling calculation, the sampling data DATA j is the calculated sampling data, and the corresponding valid signal Valid_Bus_Out[j-1] is set to 1; when the jth sampling unit does not perform sampling calculation, the sampling data DATA jKeep the data or initial value of the last sampling output, and set the corresponding valid signal Valid_Bus_Out[j-1]=0;

[0031] The sampling control module is used to control the multi-point parallel downsampling process. The specific method is:

[0032] First, the entire multi-point parallel downsampling device is set to the idle state IDLE. When the sampling start signal Start_Draw is detected to be pulled high for one clock cycle, it jumps from the idle state IDLE to the loading state LOAD. At this time, the sampling coefficient M of the next data stream is loaded, and the sampling accumulation coefficient counter group ACC is initialized. j , and send the data read instruction to the parallel data read module at the same time; the initialization formula of the sampling accumulation coefficient is as follows:

[0033] ACC j =j×M

[0034] In the loading state LOAD, when it is detected that the N-bit parallel input data valid signal Valid_Bus[N-1:0] of a certain clock cycle is not all 0, the first valid data is directly output, and the position ordinal counter group is initialized, and then the loading state LOAD jumps to the sampling state DRAW; the specific method of initializing the position ordinal counter group is: from the data valid signal with a value of 1 in the parallel data valid signal Valid_Bus[N-1:0], select the data valid signal with the lowest number of bits, record its number of bits as w, and use the following formula to initialize the position ordinal count value:

[0035]

[0036] In the sampling state DRAW, the sampling situation is monitored, and when the sampling end condition is reached, the entire multi-point parallel downsampling device returns to the idle state IDLE to wait for the next sampling start signal Start_Draw.

[0037] The present invention is based on an arbitrary non-integer multiple multi-point parallel downsampling device of FPGA, a parallel data reading module reads N-point sampling data in parallel, a data register group is used for the last data of the previous clock cycle and the N-point parallel data of the current clock cycle, a position ordinal counter group is used to save the position ordinal count value of the N-point parallel data of the current clock cycle, a sampling point accumulation coefficient counter group is used to record the sampling point accumulation coefficient, these two values ​​are updated according to the sampling situation of the previous clock cycle, each comparator group in the comparator module is used to compare the sampling point accumulation coefficient and the position ordinal count value to determine whether the corresponding sampling point unit performs the sampling operation, and the sampling point control module is used to control the multi-point parallel downsampling process.

[0038] The present invention is different from the existing serial architecture. Regardless of the coefficient value of the non-integer multiple sampling coefficient, the present invention can simultaneously process multiple continuous data points of a data stream in parallel. Especially for ultra-long data streams, this architecture can exponentially speed up the non-integer multiple sampling processing with extremely low resource consumption, thereby improving the downsampling efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is an example diagram of the whole cycle statistical interval with a fixed sampling frequency;

[0040] Figure 2 It is a theoretical framework diagram of serial sampling of fractional multiple sampling;

[0041] Figure 3 It is a schematic diagram of the data acquisition structure based on multi-point parallel sampling;

[0042] Figure 4 This is a theoretical architecture diagram of non-integer multiple multi-point parallel sampling;

[0043] Figure 5 This is an example diagram of 4-point parallel decimal sampling;

[0044] Figure 6 This is an example diagram of a possible situation of 4-point parallel decimal sampling;

[0045] Figure 7 It is a specific implementation structure diagram of the multi-point parallel down-sampling FPGA device of any non-integer multiple in the fixed-point number format of the present invention;

[0046] Figure 8 is an example diagram of a data register group in which N=4 in this embodiment;

[0047] Fig. 9 is a structural diagram of a comparator module in the present invention;

[0048] Fig.10 : is a structural diagram of the sampling unit in this embodiment;

[0049] Fig.11 This is an example diagram of initializing the position ordinal count value of 4-point parallel downsampling in this embodiment;

[0050] Fig.12 is a structural diagram of the sampling unit 1 in the 4-point parallel down-sampling FPGA device in this embodiment;

[0051] Fig.13 is a structural diagram of the sampling unit 2 in the 4-point parallel down-sampling FPGA device in this embodiment;

[0052] Fig.14 It is a structural diagram of the sampling unit 3 in the 4-point parallel down-sampling FPGA device in this embodiment;

[0053] Fig.15 is a structural diagram of the sampling unit 4 in the 4-point parallel down-sampling FPGA device in this embodiment;

[0054] Fig.16 is a graph showing changes in each count value in 4-point parallel downsampling with a sampling factor of 2.3 in this embodiment;

[0055] Fig.17 It is a simulation diagram of 4-point parallel downsampling with a sampling factor of 2.3 in this embodiment. DETAILED DESCRIPTION

[0056] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0057] In order to better illustrate the technical solution of the present invention, the technical principle of the present invention is first briefly described.

[0058] Assume that the ADC sampling rate is f s , the measured signal frequency is f x , then the number of points in one cycle of the signal to be synchronized is N1 = f s / f x Now we need to synchronize the signal to a period with N2 points (N1≥N2), and take J consecutive periods to send to the FFT module for calculation. Then in the synchronous acquisition solution based on DDR cache, we need to read the original data of this frame from DDR again, and calculate the sampling coefficient based on the frequency measurement value, so that the number of sampling points in one period is reduced from N1 to N2 (sampling coefficient M=N1 / N2, that is, f s / (N2×f x )).

[0059] For ease of description, "[z]" is used to represent the numerical value of the sampling point data at the time sequence number z. Assume that after frequency measurement, the sampling coefficient of the frame data is calculated to be 2.3, that is, starting from the starting position 0, 1 point is sampled every 2.3 unit lengths, then the extracted values ​​are: [0], [2.3], [4.6], [6.9], [9.2]... and so on. It can be seen that the sampling positions of the above data are obtained by accumulating the sampling coefficients, so the present invention calls it the sampling accumulation coefficient. In the decimal sampling based on linear interpolation, [2.3] will be calculated using the linear interpolation of points [2] and [3], and [4.6] will be calculated using the linear interpolation of points [4] and [5]. The linear interpolation calculation formula for [4.6] is as follows:

[0060] [4.6] = [4] + ([5] - [4]) × mod (4.6, 1)

[0061] Among them, mod(4.6,1) is 4.6 modulo 1, which is the decimal part of 4.6, that is, 0.6, so we have:

[0062] [4.6] = [4] + ([5] - [4]) × 0.6

[0063] Right now:

[0064] [4.6] = (1-0.6) × [4] + [5] × 0.6

[0065] Therefore, for two adjacent sampling points [A] and [B], the fractional sampling accumulation coefficient is C, and the fractional part of C is D, then:

[0066] [C]=[A]+([B]-[A])×D

[0067] For the FPGA implementation of serial linear interpolation fractional sampling, two counters are used in the prior art, one for recording the position ordinal number (CNT) of each data in a set of data frames, that is, 0, 1, 2, 3, 4, 5, etc.; the other for recording the "sampling accumulation coefficient" (ACC), that is, 0, 2.3, 4.6, 6.9, 9.2, etc. Therefore, whenever CNT>ACC, A=CNT-1, B=CNT, C=ACC, D=the low-order fractional part of ACC, so the calculation formula becomes (mod(ACC,1) is actually taking the low-order fractional part of ACC):

[0068] [ACC]=(1-mod(ACC,1))×[CNT-1]+mod(ACC,1)×[CNT]

[0069] Then add the sampling coefficient to ACC to obtain the next sampling accumulation coefficient, and wait for the next time CNT>ACC.

[0070] As for multi-point parallel sampling based on linear interpolation, assuming that N points are in parallel, then according to the different sampling coefficients of the waveform data, 0 to N points may be extracted in parallel within one clock cycle.

[0071] Figure 5 This is an example diagram of 4-point parallel decimal sampling. Figure 5The figure shows the possible locations of the sampled data points for 4-point parallel decimal sampling. Because linear interpolation may be required between the last sampling point of the previous cycle and the first sampling point of the current cycle, the last data point of the previous cycle needs to be saved for the sampling calculation of the current cycle. For different decimal sampling coefficients, the number of sampling points in the current cycle may be 0 to 4, which can be any of the 4 sampling positions (as long as the sampling conditions are met).

[0072] For N-point parallel non-integer multiple downsampling based on linear interpolation, 0 to N points may be extracted at a time. Therefore, unlike the serial solution, the N-point parallel solution requires N+1 position ordinal counters and N sampling point accumulation coefficient counters. In the example of 4-point parallel decimal sampling, there are CNT0, CNT1, CNT2, CNT3, CNT4 and ACC1, ACC2, ACC3, ACC4, respectively, and there are:

[0073] CNT4=CNT3+1=CNT2+2=CNT1+3=CNT4+4

[0074] ACC4=ACC3+M=ACC2+2M=ACC1+3M

[0075] In the N-point parallel decimal sampling, an N-bit parallel data valid signal Valid_Bus[N-1:0] is set to indicate the validity of the N input points, where Valid_Bus[i]=1 indicates that the i-th data in the current N data is valid, and Valid_Bus[i]=0 indicates that the i-th data in the current N data is invalid. Since the data is read from DDR, the Valid_Bus[N-1:0] of the first and last beats of the target data stream are not all 1, that is, the data at both ends are not all valid for N points; and the Valid_Bus[N-1:0] of the data in the middle of the data stream is either all 1 or all 0, that is, the N data points in the middle of the data stream read from the DDR are all valid, and the N data points that are not read are all invalid.

[0076] Figure 6 This is an example of a possible situation of 4-point parallel decimal sampling. Figure 6As shown in the figure, when N=4, the possible binary values ​​of Valid_Bus[N-1:0] at the head of the data stream are "1111", "1110", "1100", and "1000", while the possible binary values ​​of Valid_Bus at the end of the data stream are "1111", "0111", "0011", and "0001", and the Valid_Bus in the middle has only "1111". The discussion of the case of "0000" is omitted here, because "0000" means that there is no valid data in the current clock cycle, that is, the data stream is disconnected, which is possible, but "0000" will not have any impact on the circuit because the data is invalid, and the circuit can maintain the current control state. For other N values, the same can be said.

[0077] In actual implementation, N registers Reg can be used i To store N sampling point data of a clock cycle, i = 1, 2, ..., N, where Reg0 is used to store the Nth sampling point data of the previous clock cycle (that is, the last point of the previous beat).

[0078] N-point parallel decimal sampling can extract N points at most at a time according to the different sampling coefficients, so N sampling units need to be set. In N-point parallel decimal sampling, if there is only one point to be extracted in the current clock cycle, then this point may be: Reg0 and Reg1, Reg1 and Reg2, Reg2 and Reg3, ..., Reg N-1 and Reg N The specific position needs to be calculated by CNT i and ACC j The extracted points are determined by the relative sizes of , and the extracted points will be output from "sampling unit 1"; in N-point parallel decimal sampling, if there are 2 points to be extracted in the current clock cycle, then the second point can only be: Reg1 and Reg2, Reg2 and Reg3, ..., Reg N-1 and Reg N The second point will be output from "sampling unit 2", and the first point will be output from "sampling unit 1"; if there are 3 points to be extracted in the current clock cycle, then the third point can only be: Reg2 and Reg3, Reg3 and Reg4, ..., Reg N-1 and Reg NThe third point will be output from "sampling unit 3", the second point will be output from "sampling unit 2", and the first point will be output from "sampling unit 1". Similarly, in N-point parallel decimal sampling, if there are N points to be extracted in the current clock cycle, then the Nth point can only use Reg N-1 and Reg N It is obtained by linear interpolation, and the Nth point will be output from the "point sampling unit N", and the previous points can be pushed back according to the above rules.

[0079] Based on the above principles, the present invention proposes an arbitrary non-integer multiple multi-point parallel downsampling device based on FPGA. Figure 7 This is a specific implementation structure diagram of the FPGA-based arbitrary non-integer multiple multi-point parallel downsampling device of the present invention. Figure 7 As shown, the FPGA-based arbitrary non-integer multiple multi-point parallel downsampling device of the present invention includes a parallel data reading module, a data register group, a position ordinal counter group, a sampling point accumulation coefficient counter group, a comparator module, a sampling point module and a sampling point control module. Each module is described in detail below.

[0080] 1) Parallel data reading module

[0081] After receiving the data read instruction sent by the sampling control module, the parallel data reading module reads the sampled data in parallel from the DDR, reads N data in each clock cycle to form N-bit parallel data x[N-1:0], and generates an N-bit parallel data valid signal Valid_Bus[N-1:0] according to the data valid signal of the current N-point parallel data, where Valid_Bus[n]=1 indicates that the nth data x[n] in the current N data is valid, and Valid_Bus[n]=0 indicates that the nth data x[n] in the current N data is invalid, n=0,1,…,N-1; the N-point parallel data x[N-1:0] is sent to the data register group, and the N-bit parallel data valid signal Valid_Bus[N-1:0] is sent to the data register group and the position sequence counter group.

[0082] 2) Data register group

[0083] The data register group includes N+1 data registers Reg i , i = 0, 1, ..., N, under the control of the control module, the N-point parallel data x[N-1:0] is stored, where the data register Reg0 is used to store the N-1th data in the N-point parallel data read in the previous clock cycle, and the data register Reg j Used to store the j-1th data x[j-1] among the N-point parallel data read in this clock cycle, where j=1, 2,…, N. Figure 8 4 is an example diagram of a data register group in this embodiment. Figure 8 As shown, in this embodiment, the data register group can store 5 points at a time, and then the sampling module can extract 4 points at most.

[0084] 3) Position ordinal counter group

[0085] The position ordinal counter group includes N+1 position ordinal counters, which are used to store the position ordinal count values ​​CNT i , where the position sequence count value CNT0 is used to count the data valid signal of the data in the data register Reg0, and the position sequence count value CNT j Used to count the data valid signal Valid_Bus[j-1] of data x[j-1] in N-point parallel data; position sequence count value CNT i The initial value of is set by the control module, and then the N sampling point identification signals f output by the comparator module are j Update the count. The specific method is as follows:

[0086] The sampling point identification signal with the largest serial number is selected from all the sampling point identification signals with a value of 1, and its corresponding serial number is recorded as k. Each position sequence counter reads the value ACC of the kth sampling point accumulation coefficient counter in the previous clock cycle from the sampling point accumulation coefficient counter group. k ' Perform count updates in parallel, the specific method is as follows:

[0087] If k≠0, the following formula is used for cumulative counting:

[0088]

[0089] Among them, CNT i ′ represents the value of the ordinal counter at the i-th position in the previous clock cycle, and INT() represents the integer. For fixed-point numbers, taking the integer part is actually intercepting the high bit of the binary number.

[0090] If k = 0, the following formula is used for cumulative counting:

[0091]

[0092] According to the above description, during the sampling process, the changes of the position sequence counter group of N-point parallel decimal sampling are as follows:

[0093] a) If only one point is extracted in the previous clock cycle, then the point corresponding to the value of ACC1 is extracted:

[0094] ① If the current input N-bit data valid signal Valid_Bus[N-1:0] is not all 0, that is, the data input in this clock cycle is valid, since the head end data has been processed before, then the N-bit data valid signal Valid_Bus[N-1:0] is either all 1 or tail end data, then the change of the position sequence count value is:

[0095] CNT N =CNT′ N +N-INT(ACC′1)

[0096] CNT N-1 =CNT′ N-1 +N-INT(ACC′1)

[0097]

[0098] CNT1=CNT′1+N-INT(ACC′1)

[0099] CNT0=CNT′0+N-INT(ACC′1)

[0100] ② If the current input N-bit data valid signal Valid_Bus[N-1:0] is all 0, that is, the data input in the next clock cycle is invalid, then the change of the position sequence count value is:

[0101] CNT N =CNT′ N -INT(ACC′1)

[0102] CNT N-1 =CNT′ N-1 -INT(ACC′1)

[0103]

[0104] CNT1=CNT′1-INT(ACC′1)

[0105] CNT0=CNT′0-INT(ACC′1)

[0106] b) If two points are extracted in the previous clock cycle, then the points corresponding to the values ​​of ACC1 and ACC2 are extracted:

[0107] ① If the current input N-bit data valid signal Valid_Bus[N-1:0] is not all 0, then the change of the position sequence count value is:

[0108] CNT N =CNT′ N +N-INT(ACC′2)

[0109] CNT N-1 =CNT′ N-1 +N-INT(ACC′2)

[0110]

[0111] CNT1=CNT1′+N-INT(ACC′2)

[0112] CNT0=CNT′0+N-INT(ACC′2)

[0113] ② If the current input N-bit data valid signal Valid_Bus[N-1:0] is all 0, then the change of the position sequence count value is:

[0114] CNT N =CNT′ N -INT(ACC′2)

[0115] CNT N-1 =CNT′ N-1 -INT(ACC′2)

[0116]

[0117] CNT1=CNT1′-INT(ACC′2)

[0118] CNT0=CNT′0-INT(ACC′2)

[0119] c) Similarly, if after comparison by the comparator group, it is determined that k points are currently extracted, then they must be ACC1, ACC2, ..., ACC k Points corresponding to the values ​​are extracted:

[0120] ① If the current input N-bit data valid signal Valid_Bus[N-1:0] is not all 0, then the change of the position sequence count value is:

[0121] CNT N =CNT′ N +N-INT(ACC′ k )

[0122] CNT N-1 =CNT′ N-1 +N-INT(ACC′ k )

[0123]

[0124] CNT1=CNT1′+N-INT(ACC′ k )

[0125] CNT0=CNT′0+N-INT(ACC′ k )

[0126] ② If the current input N-bit data valid signal Valid_Bus[N-1:0] is all 0, then the change of the position sequence count value is:

[0127] CNT N =CNT′ N -INT(ACC′ k )

[0128] CNT N-1 =CNT′ N-1 -INT(ACC′ k )

[0129]

[0130] CNT1=CNT1′-INT(ACC′ k )

[0131] CNT0=CNT′0-INT(ACC′ k )

[0132] d) If any points were extracted in the previous clock cycle:

[0133] ① If the current input N-bit data valid signal Valid_Bus[N-1:0] is not all 0, then the change of the position sequence count value is:

[0134] CNT N =CNT′ N +N

[0135] CNT N-1 =CNT′ N +N-1

[0136]

[0137] CNT1=CNT′ N +1

[0138] CNT0=CNT′ N +0

[0139] ② If the currently input N-bit data valid signal Valid_Bus[N-1:0] is all 0, then all position sequence count values ​​remain unchanged.

[0140] 4) Sampling point accumulation coefficient counter group

[0141] The sampling accumulation coefficient counter group includes N sampling accumulation coefficient counters, which are used to record the sampling accumulation coefficient ACC. j , sampling accumulation coefficient ACC j Used to record the sampling accumulation coefficient of the jth extracted data point; sampling accumulation coefficient ACC j The initial value of is set by the control module.

[0142] Subsequently, the N sampling point identification signals f output by the comparator module are j Update the count. The specific method is as follows:

[0143] The sampling point identification signal with the largest serial number is selected from all the sampling point identification signals with a value of 1, and its corresponding serial number is recorded as k. Each sampling point accumulation coefficient counter is based on the value ACC of the kth sampling point accumulation coefficient counter in the previous clock cycle. k 'To update the count, the specific cumulative counting formula is as follows:

[0144]

[0145] Among them, ACC j ′ represents the value of the j-th sampling accumulation coefficient counter in the previous clock cycle, and M represents the sampling coefficient.

[0146] According to the above description, in the sampling state DRAW, the changes of the sampling accumulation coefficient counter group of N-point parallel decimal sampling are as follows:

[0147] a) If only one point is extracted in the previous clock cycle, the change in the sampling accumulation coefficient count value is:

[0148]

[0149] In practical applications, the difference between two adjacent count values ​​is the sampling coefficient M, so the above calculation can also be implemented in a copying manner to save computing resources, that is:

[0150]

[0151] b) If two points are extracted in the previous clock cycle, the change in the sampling accumulation coefficient count value is:

[0152]

[0153] At this time, the formula for implementing the above calculation by copying is:

[0154]

[0155] c) Similarly, if k points are extracted in the previous clock cycle, the change in the sampling accumulation coefficient count value is:

[0156]

[0157] At this time, the formula for implementing the above calculation by copying is:

[0158]

[0159] d) If no point is extracted in the previous clock cycle, the point accumulation coefficient count value remains unchanged.

[0160] According to the above description, the position ordinal count value group and the sampling point accumulation coefficient count value group are not accumulated indefinitely, but the relative size between the position ordinal count value group and the sampling point accumulation coefficient count value group remains unchanged, and only the position ordinal count value CNT is accumulated. i Sum sampling accumulation coefficient ACC j The recorded value is "shifted to 0" so that CNT i and ACC j The value is maintained near 1 to N times the sampling coefficient, and will not continue to accumulate to overflow. Therefore, for the decimal sampling processing of ultra-long data frames, the position ordinal counter and the sampling accumulation coefficient counter can be set to a relatively small bit width, so that the timing is better during FPGA implementation.

[0161] 5) Comparator module

[0162] Fig. 9 It is a structural diagram of the comparator module in the present invention. Fig. 9 As shown, the comparator module in the present invention includes N groups of parallel comparator groups, and the first group of comparator groups includes D j Comparator D j =N-j+1 and OR gate circuit, where:

[0163] The jth comparator group is used to read D from the position sequence counter group. j Position ordinal count value CNT jd , read D from the sampling accumulation coefficient counter group j Sampling point accumulation coefficient j d The original serial number representing the ordinal count value or the sampling point accumulation coefficient at the dth position, d = 1, 2, ..., D j ,i d =j+d-1, we can see that i d =j,j+1,…,N. D in the jth comparator group j The comparators compare the data in parallel and get D j Comparison result signal The data comparison logic is: If The comparison result signal Otherwise, the comparison result signal Then D j Comparison result signal Output to the OR gate circuit and the jth sampling unit.

[0164] OR gate circuit is used to j Comparison result signal Perform an OR operation to obtain the sampling point identification signal f j And sent to the position sequence counter group, the sampling point accumulation coefficient counter group and the jth sampling point unit.

[0165] According to the above description, the first comparator group has N comparison items, the second comparator group has N-1 comparison items, and so on, the Nth comparator group has 1 comparison item. Therefore, there are (N+1)N / 2 comparison items in the N comparator groups, where:

[0166] Group 1 comparison items include: ACC1 <CNT1,ACC1<CNT2,ACC1<CNT3,……,ACC1<CNT N , corresponding to N comparison results.

[0167] Group 2 comparison items include: ACC2 <CNT2,ACC2<CNT3,ACC2<CNT4,……,ACC2<CNT N , corresponding to N-1 comparison results.

[0168] …………

[0169] The N-1 group of comparison items includes: ACC N-1 <CNT N-1 , ACC N-1 <CNT N , corresponding to 2 comparison results.

[0170] The Nth group of comparison items include: ACC N <CNT N , corresponding to 1 comparison result.

[0171] 6) Extraction module

[0172] The sampling module includes N sampling units, wherein the jth sampling unit receives D j Comparison result signal and the sampling point identification signal f j After that, determine the sampling point identification signal f j Is it 0? If so, the sampling unit does not need to be sampled. If not, all comparison result signals that are 1 are used. Filter out the sequence number i dThe largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Then from the data register of the data register group and The data are read as [CNT A ] and [CNT B ], read the sampling accumulation coefficient ACC from the sampling accumulation coefficient counter group j , the sampling data DATA[j-1] is calculated using the following formula:

[0173] DATA[j-1]=(1-frac(ACC j ))×[CNT A ]+frac(ACC j )×[CNT B ]

[0174] Among them, frac() means to obtain the decimal part. For fixed-point numbers, taking the decimal part is actually to intercept the low bit of the binary number.

[0175] After completing the above linear interpolation calculation, each sampling unit outputs its sampling data DATA[j-1] and the corresponding valid signal Valid_Bus_Out[j-1]. When the jth sampling unit completes a sampling calculation, the sampling data DATA j is the calculated sampling data, and the corresponding valid signal Valid_Bus_Out[j-1] is set to 1; when the jth sampling unit does not perform sampling calculation, the sampling data DATA j The data or initial value at the last sampling output is maintained, and the corresponding valid signal Valid_Bus_Out[j-1] is set to 0.

[0176] In order to implement sampling more efficiently, a sampling unit is designed in this embodiment according to the requirements of the present invention. Fig.10 : is a structural diagram of the sampling unit in this embodiment. Fig.10 As shown, in this embodiment, the sampling unit includes a first multiplexer MUX A , the second multiplexer MUX B , the first register Reg A , the second register Reg B , enable signal generation module, first sampling parameter register Reg_S A , the second sampling parameter register Reg_S B , linear interpolation calculation module, where:

[0177] The first multiplexer MUX A For use according to D j Comparison result signal Determine the data to be read. The specific method is: from all comparison result signals that are 1 Filter out the sequence number i d The largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Data register from data register bank Read data from and use it as data [CNT A ]Forwarded to the first register Reg A .

[0178] The second multiplexer MUX A For use according to D j Comparison result signal Determine the data to be read. The specific method is: from all comparison result signals that are 1 Filter out the sequence number i d The largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Data register from data register bank Read data from and use it as data [CNT B ]Forwarded to the second register Reg B .

[0179] The first register Reg A And the second register Reg B Used to identify the signal f according to the sampling point j The data is stored in the following way: when the sampling point identification signal f j =1, then the data is received and stored. When the sampling point identification signal f j =0, no operation is performed.

[0180] The enable signal generation module is used to generate a signal according to the sampling point identification signal f j Generate a multiplication enable signal and an addition enable signal and send them to the linear interpolation calculation module. The specific method is: j Beat a beat as the multiplication enable signal, and then beat another beat as the addition enable signal. It can be seen that only when the sampling point identification signal f j =1, the multiplication enable signal and addition enable signal are valid.

[0181] First sampling parameter register Reg_S A Used to identify the signal f at the sampling point j = 1, read the sampling accumulation coefficient from the sampling accumulation coefficient counter group Calculate the decimal part And sent to the linear interpolation calculation module.

[0182] Second sampling parameter register Reg_S B Used to identify the signal f at the sampling point j = 1, read the sampling accumulation coefficient from the sampling accumulation coefficient counter group Calculate the two's complement of its fractional part And sent to the linear interpolation calculation module.

[0183] The linear interpolation calculation module is used to calculate and output the sampling data DATA[j-1], including a first multiplier, a second multiplier and an adder, wherein:

[0184] When the multiplication enable signal is valid, the first multiplier obtains the value from the first register Reg A Read [CNT A ], and at the same time from the second sampling parameter register Reg_S B Read the two's complement of the decimal part And multiply to get the multiplication result And output to the adder.

[0185] When the multiplication enable signal is valid, the second multiplier obtains the value from the second register Reg B Read [CNT B ], and at the same time from the second sampling parameter register Reg_S A Read the decimal part And multiply to get the multiplication result And output to the adder.

[0186] The adder is used to multiply the multiplication result mul when the addition enable signal is valid. A and the multiplication result mul B The sampling data DATA[j-1] is obtained by addition. When the sampling data DATA[j-1] exists, a valid signal Valid_Bus_Out[j-1]=1 is output at the same time.

[0187] According to the above description, the priority of the comparator group with a smaller sequence number in the comparator module is greater than that of the comparator group with a larger sequence number. This is because:

[0188] a) If the comparison result output by the Nth group of comparators contains 1, that is, the sampling condition is met, then the comparison result output by the previous group of comparators must contain 1, and N points will be extracted in parallel from the N+1 data;

[0189] b) If the comparison results of the Nth group of comparators are all 0, but the comparison results of the N-1th group of comparators include 1, then the comparison results of the 1st to N-2th groups of comparators must also include 1. At this time, (N-1) points will be extracted in parallel from the N+1 sampling points;

[0190] c) Similarly, if the comparison results of the comparator outputs from the second to the Nth group are all 0, and the comparison results of the comparator outputs from the first group include 1, then only 1 point will be extracted from the N+1 points in this clock cycle;

[0191] d) If the comparison results output by all comparator groups are all 0, then no sampling will be performed in this clock cycle.

[0192] For D in group j j =N-j+1 comparison items. The smaller the position ordinal count value in the comparison item, the higher the priority. That is:

[0193] For the OR gate circuit output corresponding to the first group of comparators is 1, then there must be at least one ACC1 inside the first group of comparators. <CNT i Satisfies the condition, for i the smallest ACC1 that satisfies the condition <CNT i The item is taken as the highest priority item and the current data register Reg i-1 and Reg i The values ​​are loaded into the first register Reg of the sampling unit 1 A And the second register Reg B At the same time, the decimal part of the current ACC1 and its complement of the decimal part are loaded into the first sampling parameter register Reg_S A The second sampling parameter register Reg_S B and controls the multiplier and adder in the linear interpolation calculation module to complete the interpolation operation of the sampling unit 1.

[0194] If the output of the OR gate circuit corresponding to the jth group of comparators is 1, then there must be at least one ACC j <CNT i Satisfies the condition, for i the smallest ACC that satisfies the condition j <CNT i The item is taken as the highest priority item and the current data register Reg i-1 and Reg i The values ​​of A And the second register Reg B , and at the same time set the current ACC j The fractional part and its complement of the fractional part are loaded into the first sampling parameter register Reg_S A The second sampling parameter register Reg_S B In the process, the multiplier and adder of the linear interpolation calculation module are controlled to complete the interpolation operation of the sampling unit j.

[0195] 7) Extraction control module

[0196] The sampling control module is used to control the multi-point parallel downsampling process. The specific method is:

[0197] First, the entire multi-point parallel downsampling device is set to the idle state IDLE. When the sampling start signal Start_Draw is detected to be pulled high for one clock cycle, it jumps from the idle state IDLE to the loading state LOAD. At this time, the sampling coefficient M of the next data stream is loaded, and the sampling accumulation coefficient counter group ACC is initialized. j , and send the data read instruction to the parallel data read module at the same time; the initialization formula of the sampling accumulation coefficient is as follows:

[0198] ACC j =j×M

[0199] In the loading state LOAD, when it is detected that the N-bit parallel input data valid signal Valid_Bus[N-1:0] of a certain clock cycle is not all 0, the first valid data is directly output, and the position ordinal counter group is initialized, and then the loading state LOAD jumps to the sampling state DRAW; the specific method of initializing the position ordinal counter group is: from the data valid signal with a value of 1 in the parallel data valid signal Valid_Bus[N-1:0], select the data valid signal with the lowest number of bits, record its number of bits as w, and use the following formula to initialize the position ordinal count value:

[0200]

[0201] In the draw state DRAW, the draw situation is monitored. When the draw end condition is reached, the entire multi-point parallel downsampling device returns to the idle state IDLE and waits for the next draw start signal Start_Draw. In practical applications, the draw end condition can be receiving the draw end signal End_Draw, or the cumulative number of draw points reaches a preset threshold.

[0202] Next, the detailed implementation of each module in the present invention is described by taking 4-point parallel downsampling as an example. When the sampling control module detects that the sampling start signal Start_Draw is pulled high for one clock cycle, it jumps from the idle state IDLE to the loading state LOAD, and initializes the sampling accumulation coefficient counter group. Since the sampling coefficient in this embodiment is 2.3, the control module sets each sampling accumulation coefficient ACC j The initial values ​​are ACC1=2.3, ACC2=4.6, ACC3=6.9, ACC4=9.2 respectively.

[0203] When it is detected that the N-bit parallel input data valid signal Valid_Bus[3:0] of a certain clock cycle is not all 0, the position sequence counter group and the sampling point accumulation coefficient counter group are initialized. Fig.11 4 is an example diagram of initializing the position sequence count value of the 4-point parallel downsampling in this embodiment. Fig.11 As shown in the figure, when sampling starts, the position sequence number of the first point is 0. In the LOAD state, not all of the N sampling points detected are valid. If only w points are valid, the high w bits of Valid_Bus[N-1:0] are 1, and the low Nw bits are 0. If only w points of the header data in the LOAD state are valid, then N To CNT N-w+1 are loaded with w-1, w-2, ..., 2, 1, 0 respectively; and CNT N-w All the CNT0 are loaded with 0. Fig.10 As shown, if the binary value of Valid_Bus detected by the control module in the LOAD state is 1000, the initial value of the position ordinal count value CNT4=CNT3=CNT2=CNT1=CNT0=0 is set; if the binary value of Valid_Bus detected by the control module in the LOAD state is 1100, then CNT4=1, otherwise CNT3=CNT2=CNT1=CNT0=0; if the binary value of Valid_Bus detected in the LOAD state is 1110, then CNT4=2, CNT3=1, otherwise CNT2=CNT1=CNT0=0; if the binary value of Valid_Bus detected in the LOAD state is 1111, then CNT4=3, CNT3=2, CNT2=1, CNT1=CNT0=0.

[0204] Fig.12 4 is a structural diagram of the sampling unit 1 in the 4-point parallel down-sampling FPGA device in this embodiment. Fig.12 As shown, the first ACC (i.e., ACC1) corresponds to the first point extracted in the current clock cycle. It is necessary to compare ACC1 with CNT1 to CNT4 for subsequent judgment. ACC1 is input into four comparators respectively to judge: (ACC1 <CNT1)、(ACC1<CNT2)、(ACC1<CNT3)、(ACC1<CNT N ), when the four comparison result signals are not all 0, then at least one point is extracted in the current clock cycle. The four comparison result signals are ORed to obtain a sampling point identification signal, which is used as a multiplication enable signal in the linear interpolation calculation module and then as an addition enable signal in the linear interpolation calculation module. At the same time, when the sampling point identification signal = 1, the first sampling point parameter register Reg_SA and the second decimation point parameter register Reg_S B Read and save the fractional part of the current ACC1 and its complement of the fractional part for the calculation of linear interpolation.

[0205] The comparison results of ACC1 with the 4 comparators of CNT1 to CNT4 will be used as the selection terminal enabling of the multiplexer of the decimation unit 1, and the selection is as follows:

[0206] 1) The result of the first group of comparators has the highest priority. When ACC1 < CNT1, it means that [CNT1] and [CNT0], that is, the values of Reg0 and Reg1, can be used for decimation. Then the multiplexer of the decimation unit 1 will select Reg0 to enter Reg A , and select Reg1 to enter Reg B ;

[0207] 2) The result of the second group of comparators has a lower priority than the first group. When the output of the first group of comparison results is 0 and ACC1 < CNT2, the multiplexer of the decimation unit 1 will select the value of Reg1 to enter Reg A , the value of Reg2 to enter Reg B ;

[0208] And so on. When the comparison results of the previous 3 groups are all 0 and ACC1 < CNT4, the multiplexer of the decimation unit 1 will select the value of Reg3 to enter Reg A , the value of Reg4 to enter Reg B .

[0209] Fig.13 is the structural diagram of the decimation unit 2 in the 4-point parallel decimation FPGA device of this embodiment. As Fig.13 shown, the second ACC (i.e., ACC2) corresponds to the first point extracted in the current clock cycle. It is necessary to compare ACC2 with CNT2 to CNT4 for subsequent judgment. Input ACC2 into 3 comparators respectively to judge the situations of (ACC2 < CNT2), (ACC2 < CNT3), and (ACC2 < CNT4). When the 3 comparison result signals are not all 0, then in the current clock cycle, at least 1 point is extracted. Perform an OR operation on the 3 comparison result signals to obtain the decimation identification signal. Beat the decimation identification signal once as the multiplication enable signal in the linear interpolation calculation module, and beat it a second time as the addition enable signal in the linear interpolation calculation module. At the same time, when the decimation identification signal = 1, the first decimation point parameter register Reg_S A and the second decimation point parameter register Reg_S B Read and save the fractional part of the current ACC2 and its complement of the fractional part for the calculation of linear interpolation.

[0210] The comparison results of the three comparators of ACC2 with CNT2 to CNT4 will be used as the selection terminal enabling of the multiplexer of the decimation unit 2, and the selection is as follows:

[0211] 1) The result of the first group of comparators has the highest priority. When ACC2 < CNT2, it means that [CNT2] and [CNT1], that is, the values of Reg1 and Reg2, can be used for decimation. Then the multiplexer of the decimation unit 2 will select Reg1 to enter Reg A , and select Reg2 to enter Reg B ;

[0212] 2) The result of the second group of comparators has a lower priority than the first group. When the output of the first group of comparison results is 0 and ACC2 < CNT3, the multiplexer of the decimation unit 2 will select the value of Reg2 to enter Reg A , and the value of Reg3 to enter Reg B ;

[0213] 3) The result of the third group of comparators has a lower priority than the first and second groups. When the output of the first two groups of comparison results is 0 and ACC2 < CNT4, the multiplexer of the decimation unit 2 will select the value of Reg3 to enter Reg A , and the value of Reg4 to enter Reg B ;

[0214] Fig.14 is the structural diagram of the decimation unit 3 in the 4-point parallel decimation FPGA device of this embodiment. Fig.15 is the structural diagram of the decimation unit 4 in the 4-point parallel decimation FPGA device of this embodiment. The working processes of the decimation unit 3 and the decimation unit 4 are similar to those of the decimation units 1 and 2, so they will not be elaborated here.

[0215] Fig.16 is the diagram of the change of each count value in the 4-point parallel decimation with a decimation coefficient of 2.3 in this embodiment. Fig.17 is the simulation diagram of the 4-point parallel decimation with a decimation coefficient of 2.3 in this embodiment. Fig.16 Each grid in represents one clock cycle. As Fig.16 and Fig.17As shown, in the initial case, the values ​​of CNT and ACC are both 0, and then the ACC group completes the loading of the sampling coefficient in the LOAD state. Since the sampling coefficient is 2.3, the values ​​loaded from ACC1 to ACC4 are 2.3, 4.6, 6.9 and 9.2 respectively. Because the first Valid_Bus input in the LOAD state is 1110, indicating that there are three valid head-end data, 0, 1, and 2 are loaded in CNT2, CNT3 and CNT4 respectively, and the other CNTs are all 0. At the same time, the value of Reg2 is directly output as the first point extracted. At this time, Valid_Bus_Out is 0001.

[0216] In the DRAW state, the values ​​of CNT in the next round are CNT4+0 / +1 / +2 / +3 / +4 respectively. Based on the comparison with the ACC group, two points can be extracted in the current cycle - use Reg0 and Reg1 to calculate the linear interpolation data when ACC1 is 2.3, and use Reg2 and Reg3 to calculate the data when ACC2 is 4.6 (because CNT0 is 0 at this time, and CNT1 is 3 at this time, ACC1=2.3 is between these two numbers; CNT2 is 4 at this time, and CNT3 is 5 at this time, ACC2=4.6 is between these two numbers), and the interpolation proportional coefficients are 0.3, 0.7 and 0.6, 0.4 respectively. After the calculation is completed, Valid_Bus_Out will output 0011 in the subsequent corresponding cycles.

[0217] Since two points are extracted in this cycle, all CNT1 to CNT4 in the next cycle need to subtract the integer part 4 of ACC2. Since the input Valid_Bus is still 1111, CNT1 to CNT4 need to add N (N=4) on the basis of subtracting 4, and CNT0 is the integer part of CNT4 minus ACC2.

[0218] For the ACC group, since two points are extracted, the values ​​of ACC4 and ACC3 need to be shifted to ACC2 and ACC1. At the same time, ACC4 and ACC3 will add 2 times and 1 times the sampling coefficients to introduce new sampling coefficient accumulated values. In addition, the registers of all ACC groups need to subtract the integer part of ACC2 to keep the relative positions of the ACC group and the CNT group unchanged.

[0219] This process repeats until the last point is extracted and the system is reset to wait for the next round of data frames to arrive. The entire system forms a pipeline structure.

[0220] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. An arbitrary non-integer multiple multi-point parallel downsampling device based on FPGA, characterized in that: It includes a parallel data reading module, a data register group, a position sequence counter group, a sampling accumulation coefficient counter group, a comparator module, a sampling module and a sampling control module, wherein: After receiving the data reading instruction sent by the sampling control module, the parallel data reading module reads the sampled data in parallel from the DDR, reads N data in each clock cycle to form N-bit parallel data x[N-1:0], and generates an N-bit parallel data valid signal Valid_Bus[N-1:0] according to the data valid signal of the current N-point parallel data, wherein Valid_Bus[n]=1 indicates that the nth data x[n] in the current N data is valid, and Valid_Bus[n]=0 indicates that the nth data x[n] in the current N data is invalid, and n=0,1,…,N-1; sends the N-point parallel data x[N-1:0] to the data register group, and sends the N-bit parallel data valid signal Valid_Bus[N-1:0] to the data register group and the position sequence counter group; The data register group includes N+1 data registers Reg i , i = 0, 1, ..., N, under the control of the control module, the N-point parallel data x[N-1:0] is stored, where the data register Reg0 is used to store the N-1th data in the N-point parallel data read in the previous clock cycle, and the data register Reg j Used to store the j-1th data x[j-1] among the N-point parallel data read in this clock cycle, where j=1, 2, ..., N; The position ordinal counter group includes N+1 position ordinal counters, which are used to store the position ordinal count values ​​CNT i , where the position sequence count value CNT0 is used to count the data valid signal of the data in the data register Reg0, and the position sequence count value CNT j Used to count the data valid signal Valid_Bus[j-1] of data x[j-1] in N-point parallel data; position sequence count value CNT i The initial value of is set by the control module, and then the N sampling point identification signals f output by the comparator module are j Update the count. The specific method is as follows: The sampling point identification signal with the largest serial number is selected from all the sampling point identification signals with a value of 1, and its corresponding serial number is recorded as k. Each position sequence counter reads the value ACC of the kth sampling point accumulation coefficient counter in the previous clock cycle from the sampling point accumulation coefficient counter group. k ' Perform count updates in parallel, the specific method is as follows: If k≠0, the following formula is used for cumulative counting: Among them, CNT i ′ represents the value of the ordinal counter of the i-th position in the previous clock cycle, and INT() represents obtaining an integer; If k = 0, the following formula is used for cumulative counting: The sampling accumulation coefficient counter group includes N sampling accumulation coefficient counters, which are used to record the sampling accumulation coefficient ACC. j , sampling accumulation coefficient ACC j Used to record the sampling accumulation coefficient of the jth extracted data point; sampling accumulation coefficient ACC j The initial value of is set by the control module, and then the N sampling point identification signals f output by the comparator module are j Update the count. The specific method is as follows: The sampling point identification signal with the largest serial number is selected from all the sampling point identification signals with a value of 1, and its corresponding serial number is recorded as k. Each sampling point accumulation coefficient counter is based on the value ACC of the kth sampling point accumulation coefficient counter in the previous clock cycle. k 'To update the count, the specific cumulative counting formula is as follows: Among them, ACC j ′ represents the value of the j-th sampling accumulation coefficient counter in the previous clock cycle, and M represents the sampling coefficient; The comparator module includes N parallel comparator groups, and the jth comparator group includes D j Comparator D j =N-j+1 and OR gate circuit, where: The jth comparator group is used to read D from the position sequence counter group. j Position ordinal count value Read the sample accumulation coefficient ACC from the sample accumulation coefficient counter group j ,i d The original serial number representing the ordinal count value of the dth position, d = 1, 2, ..., D j ,i d =j+d-1; D in the jth comparator group j The comparators compare the data in parallel and get D j Comparison result signal The data comparison logic is: If The comparison result signal Otherwise the comparison result signal Then D j Comparison result signal Output to the OR gate circuit and the jth sampling unit; OR gate circuit is used to j Comparison result signal Perform an OR operation to obtain the sampling point identification signal f j And sent to the position sequence counter group, the sampling point accumulation coefficient counter group and the j-th sampling point unit; The sampling module includes N sampling units, wherein the jth sampling unit receives D j Comparison result signal and the sampling point identification signal f j After that, determine the sampling point identification signal f j Is it 0? If so, the sampling unit does not need to be sampled. If not, all comparison result signals that are 1 are used. Filter out the sequence number i d The largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Then from the data register of the data register group and The data are read as [CNT A ] and [CNT B ], read the sampling accumulation coefficient ACC from the sampling accumulation coefficient counter group j , the sampling data DATA[j-1] is calculated using the following formula: DATA[j-1]=(1-frac(ACC j ))×[CNT A ]+frac(ACC j )×[CNT B ] Among them, frac() means to obtain the decimal part; After completing the above linear interpolation calculation, each sampling unit outputs its sampling data DATA[j-1] and the corresponding valid signal Valid_Bus_Out[j-1]. When the jth sampling unit completes a sampling calculation, the sampling data DATA j is the calculated sampling data, and the corresponding valid signal Valid_Bus_Out[j-1] is set to 1; when the jth sampling unit does not perform sampling calculation, the sampling data DATA j Keep the data or initial value of the last sampling output, and set the corresponding valid signal Valid_Bus_Out[j-1]=0; The sampling control module is used to control the multi-point parallel downsampling process. The specific method is: First, the entire multi-point parallel downsampling device is set to the idle state IDLE. When the sampling start signal Start_Draw is detected to be pulled high for one clock cycle, it jumps from the idle state IDLE to the loading state LOAD. At this time, the sampling coefficient M of the next data stream is loaded, and the sampling accumulation coefficient counter group ACC is initialized. j , and send the data read instruction to the parallel data read module at the same time; the initialization formula of the sampling accumulation coefficient is as follows: ACC j =j×M In the loading state LOAD, when it is detected that the N-bit parallel input data valid signal Valid_Bus[N-1:0] of a certain clock cycle is not all 0, the first valid data is directly output, and the position ordinal counter group is initialized, and then the loading state LOAD jumps to the sampling state DRAW; the specific method of initializing the position ordinal counter group is: from the data valid signal with a value of 1 in the parallel data valid signal Valid_Bus[N-1:0], select the data valid signal with the lowest number of bits, record its number of bits as w, and use the following formula to initialize the position ordinal count value: In the sampling state DRAW, the sampling situation is monitored, and when the sampling end condition is reached, the entire multi-point parallel downsampling device returns to the idle state IDLE to wait for the next sampling start signal Start_Draw.

2. The multi-point parallel downsampling FPGA device according to claim 1, characterized in that: The sampling unit comprises a first multiplexer MUX A , the second multiplexer MUX B , the first register Reg A , the second register Reg B , enable signal generation module, first sampling parameter register Reg_S A , the second sampling parameter register Reg_S B , linear interpolation calculation module, where: The first multiplexer MUX A For use according to D j Comparison result signal Determine the data to be read. The specific method is: from all comparison result signals that are 1 Filter out the sequence number i d The largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Data register from data register bank Read data from and use it as data [CNT A ]Forwarded to the first register Reg A ; The second multiplexer MUX A For use according to D j Comparison result signal Determine the data to be read. The specific method is: from all comparison result signals that are 1 Filter out the sequence number i d The largest comparison result signal, the original serial number of the corresponding position sequence count value is recorded as Data register from data register bank Read data from and use it as data [CNT B ]Forwarded to the second register Reg B ; The first register Reg A And the second register Reg B Used to identify the signal f according to the sampling point j The data is stored in the following way: when the sampling point identification signal f j =1, then the data is received and stored. When the sampling point identification signal f j =0, no operation is performed; The enable signal generation module is used to generate a signal according to the sampling point identification signal f j Generate a multiplication enable signal and an addition enable signal and send them to the linear interpolation calculation module. The specific method is: j Strike once as a multiplication enable signal, then strike again as an addition enable signal; First sampling parameter register Reg_S A Used to identify the signal f at the sampling point j = 1, read the sampling accumulation coefficient from the sampling accumulation coefficient counter group Calculate the decimal part And sent to the linear interpolation calculation module; Second sampling parameter register Reg_S B Used to identify the signal f at the sampling point j = 1, read the sampling accumulation coefficient from the sampling accumulation coefficient counter group Calculate the two's complement of its fractional part And sent to the linear interpolation calculation module; The linear interpolation calculation module is used to calculate and output the sampling data DATA[j-1], including a first multiplier, a second multiplier and an adder, wherein: When the multiplication enable signal is valid, the first multiplier obtains the value from the first register Reg A Read [CNT A ], and at the same time from the second sampling parameter register Reg_S B Read the two's complement of the decimal part And multiply to get the multiplication result And output to the adder; When the multiplication enable signal is valid, the second multiplier obtains the value from the second register Reg B Read [CNT B ], and at the same time from the second sampling parameter register Reg_S A Read the decimal part And multiply to get the multiplication result And output to the adder; The adder is used to multiply the multiplication result mul when the addition enable signal is valid. A and the multiplication result mul B The sampling data DATA[j-1] is obtained by addition. When the sampling data DATA[j-1] exists, a valid signal Valid_Bus_Out[j-1]=1 is output at the same time.

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