A transmitter with adjustable local oscillator signal phase

Abstract

The present invention discloses a transmitter with adjustable local oscillator signal phase, which relates to wireless communication technology. The transmitter comprises an internal loopback circuit, a transmitting radio frequency front-end circuit and a register or a baseband signal unit. The transmitting radio frequency front-end circuit comprises a transmitting network ANT1, an up-mixer RF2, a second local oscillator phase calibration unit and a first digital-to-analog converter DAC1. The first baseband signal and a reference voltage Vref are simultaneously input into the second analog-to-digital converter ADC2 to output a control word COMP. <n:0>The second local oscillator phase calibration unit includes an inverter group, and a coarse tuning capacitor Cap1 and a fine tuning capacitor Cap2 are sequentially provided between the inverters INVk, and the coarse tuning capacitor Cap1 is provided with a switch signal receiving terminal Cap <n:0>, switch signal receiving end Cap <n:0>Used to receive the control word COMP <n:0>The second digital-to-analog converter DAC2 is used to receive a preset analog adjustment signal ADJ transmitted from a register or a baseband signal unit and convert the preset analog adjustment signal ADJ into a control signal Vctrl; the control signal Vctrl is input into the fine-tuning capacitor Cap2. The present invention does not require adjustment in the digital domain, saving resources.< / n:0>

Description

Technical Field

[0001] The present invention relates to wireless communication technology, and more particularly to a transmitter with adjustable local oscillator signal phase. Background Art

[0002] The transmitter RF front end is commonly used for signal mixing and amplification. Compared to modulation using a single signal, IQ (hereinafter referred to as IQ) modulation of the local oscillator signal has better sideband suppression and higher frequency resource utilization. However, on the RF transceiver chip, due to the path delay, the phase difference between the two IQ signals will deviate from 90°, resulting in low image suppression ratio and signal vector modulation error. The transmitter mainly uses a mixer to achieve up-conversion function. When using IQ two-way mixing, single-sideband mixing can be achieved. It is known that:

[0003]

[0004] Among them, ω LO is the local oscillator frequency signal, ω if It is a baseband frequency signal. However, when the local oscillator signal IQ is not completely orthogonal, the RF signal has not only an upper sideband signal, but also a lower sideband signal, which is unnecessary. So:

[0005]

[0006] in, is the orthogonal deviation.

[0007] Therefore, in order to ensure the quality of the transmitted signal, the IQ two paths need to be precisely orthogonal. The purpose of calibration is to make the IQ two paths reaching the down-mixer completely orthogonal and increase the image rejection ratio of the transmitter. IQ imbalance calibration is mainly done by observing the internal loop circuit composed of the receiver. [1] The phase shift can be reflected in the baseband signal through down-conversion and low-pass filtering. The baseband signal is then detected and the detected data is stored in a register. The main calibration method based on this is digital domain compensation.

[0008] The idea of digital domain compensation is to process the transmitted signal through the receiving channel, perform frequency domain analysis and parameter estimation after passing it through the ADC to calculate the deviation factor of the in-phase signal and the orthogonal signal, and then calibrate it in the digital domain based on the deviation factor to change the phase of the baseband signal, thereby changing the IQ imbalance of the transmitted signal to achieve a calibration purpose. [1] .

[0009] According to previous methods, IQ imbalance is often solved by compensating in the digital domain. [2][3][5] In addition, there is also an architecture for IQ pre-distortion calibration using a training sequence[4] These structures require complex structures and consume more power.

[0010] The references identified above are as follows:

[0011] [1]DJMcLaurin et al., "Ahighly reconfigurable 65nm CM RF-to-bitstransceiver for full-band multicarrier TDD / FDD 2G / 3G / 4G / 5G macrobasestations," 2018 IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco,CA,USA,2018,pp.162-164,doi:10.1109 / ISSCC.2018.8310234.

[0012] [2] Hakan Johnson. "Method and apparatus for compensating I / Q imbalance." CN102396199B. 2014-08-20.

[0013] [3] E. Nemer, and A. Seid. "Method and apparatus for compensating for I / Q imbalance in a receiver." CN1898932B. 2011-11-16.

[0014] [4] Wang Chen, Zhang Wen. A device and method for joint orthogonal modulation calibration between transmitter and receiver[P]. Shaanxi: CN201711289323.7, 2018-04-20.

[0015] [5] Wang Anyang, Huang Ying, Song Quanjun. Quadrature imbalance calibration scheme in direct up-conversion transmitter based on automatic temperature compensation[J]. Journal of Sensor Technology, 2022, 35(09): 1210-1214. Summary of the Invention

[0016] The technical problem to be solved by the present invention is to address the shortcomings of the existing technology and provide a transmitter with adjustable local oscillator signal phase. Based on the idea of adjusting the capacitor to change the phase, the intermediate frequency part of the multiplexed receiver is used for IQ calibration. The circuit architecture is simple and no digital domain compensation and training sequence are required for calibration.

[0017] A transmitter with adjustable local oscillator signal phase according to the present invention includes an internal loopback circuit, a transmitting radio frequency front-end circuit, and a register or baseband signal unit. The transmitting radio frequency front-end circuit includes a transmitting network ANT1, an up-mixer RF2, a second local oscillator phase calibration unit, and a first digital-to-analog converter DAC1. The first digital-to-analog converter DAC1 performs digital-to-analog conversion on a second baseband signal received from the register or baseband signal unit, inputs the converted signal to the up-mixer RF2, and mixes the converted signal with the local oscillator signal IQ processed by the second local oscillator phase calibration unit to output a radio frequency signal RF.

[0018] The internal loop circuit receives the radio frequency signal RF output by the transmitting radio frequency front-end circuit, and the internal loop circuit includes an attenuator ATT1, a down-mixer RF1, a first local oscillator phase calibration unit and a first analog-to-digital converter ADC1. The radio frequency signal RF and the external local oscillator signal LO after passing through the first local oscillator phase calibration unit are simultaneously input into the down-mixer RF1 to form a first baseband signal;

[0019] The internal loop circuit further includes a second analog-to-digital converter ADC2; the baseband signal and a reference voltage Vref are simultaneously input into the second analog-to-digital converter ADC2 for analog-to-digital conversion to output a control word COMP <n:0>The second local oscillator phase calibration unit includes an inverter group consisting of a plurality of inverters INVk connected in series, wherein a coarse tuning capacitor Cap1 and a fine tuning capacitor Cap2 are sequentially provided between the inverters INVk of the inverter group, and the coarse tuning capacitor Cap1 is provided with a switch signal receiving terminal Cap <n:0>, the switch signal receiving terminal Cap <n:0>Used to receive the control word COMP <n:0>;

[0020] The transmitting RF front-end circuit also includes a second digital-to-analog converter DAC2; the second digital-to-analog converter DAC2 is used to receive a preset analog adjustment signal ADJ transmitted from a register or a baseband signal unit, and convert the preset analog adjustment signal ADJ into a control signal Vctrl; the control signal Vctrl is input into the fine-tuning capacitor Cap2, and is used to change the capacitance product of the fine-tuning capacitor Cap2; wherein N is a natural number, and k is a natural number greater than 1.

[0021] As a further improvement, the coarse tuning capacitor Cap1 includes N analog capacitors 1 and N analog capacitors 2 connected in parallel.

[0022] Furthermore, the analog capacitor 1 is composed of a first field effect transistor PMn and a control switch Cap_P <n>The control switch Cap_P <n>Receive control word COMP <n:0>The gate of the first field effect transistor PMn is connected to the output end of the corresponding inverter INVk, and the source and drain of the first field effect transistor PMn are connected to the control switch Cap_P <n>A switch terminal of the control switch Cap_P <n>The other switch terminal is grounded, and the substrate of the first field effect transistor PMn is connected to the common terminal.

[0023] Furthermore, the analog capacitor 2 is composed of a second field effect transistor NMn and a control switch Cap_N <n>The control switch Cap_N <n>Receive control word COMP <n:0>The gate of the second field effect transistor NMn is connected to the output end of the corresponding inverter INVk, and the source and drain of the second field effect transistor NMn are connected to the control switch Cap_N <n>A switch end of the control switch Cap_N is connected, <n>The other switch terminal is grounded, and the substrate of the second field effect transistor NMn is connected to the reference terminal.

[0024] As a further improvement, the fine-tuning capacitor Cap2 includes a third field-effect transistor NMm, the gate of the third field-effect transistor NMm is connected to the output end of the corresponding inverter INVk, the source and drain of the third field-effect transistor NMm are simultaneously connected to the control signal Vctrl, and the substrate of the third field-effect transistor NMm is connected to the reference end, where m is a natural number.

[0025] As a further improvement, the second digital-to-analog converter DAC2 outputs a current signal according to the preset analog adjustment signal ADJ, and the signal output end of the second digital-to-analog converter DAC2 is grounded through a resistor to convert the current signal into a voltage signal through the resistor, and the voltage signal serves as the control signal Vctrl.

[0026] As a further improvement, the inverter group consists of five inverters INVk connected in series, a coarse adjustment capacitor Cap1 is provided between the three inverters INVk close to the signal input end LO_IN of the second local oscillator phase calibration unit, and a fine adjustment capacitor Cap2 is provided between the three inverters INVk close to the signal output end LO_OUT of the second local oscillator phase calibration unit.

[0027] As a further improvement, the radio frequency signal RF is input to one input terminal of the second analog-to-digital converter ADC2 after passing through the synchronous control switch 1 SB1, and the reference voltage Vref is input to the other input terminal of the second analog-to-digital converter ADC2 after passing through the synchronous control switch 2 SB2. The control terminals of the synchronous control switch 1 SB1 and the synchronous control switch 2 SB2 simultaneously receive the clock signal CLK. sample .

[0028] As a further improvement, the first digital-to-analog converter DAC1 is connected to the up-mixer RF2 via a second low-pass filter LPF2.

[0029] As a further improvement, the down-mixer RF1 is connected to the first analog-to-digital converter ADC1 via a low-pass filter LPF1.

[0030] Beneficial effects

[0031] The advantages of the present invention are:

[0032] 1. During the detection phase, an internal loopback structure is used to detect IQ phase offset. Instead of adjusting it in the digital domain, the phase can be adjusted through FPGA registers, saving resources.

[0033] 2. Two methods are used to perform phase calibration. One is to perform coarse adjustment by automatic calibration through the internal loop circuit structure, and the other is to fine-tune the phase by manually changing the capacitor threshold voltage of the field effect tube and changing the capacitor size. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of transmitter circuit structure in related technology;

[0035] Figure 2 Based on Figure 1 Schematic diagram of the internal loop mixing process structure;

[0036] Figure 3 Schematic diagram of the transmitter circuit structure of the present invention;

[0037] Figure 4 Schematic diagram of the ADC external circuit structure in the internal loop circuit of the present invention;

[0038] Figure 5 Schematic diagram of the circuit structure of the local oscillator phase calibration unit of the present invention;

[0039] Figure 6 This is a graph showing how the capacitance of the field effect tube of the present invention changes with voltage;

[0040] Figure 7 Schematic diagram of local oscillator phase calibration based on control words of the present invention;

[0041] Figure 8 Schematic diagram of local oscillator phase calibration based on field effect tube of the present invention;

[0042] Figure 9 Schematic diagram of the DAC external circuit structure of the present invention. DETAILED DESCRIPTION

[0043] The present invention will be further described below in conjunction with the embodiments, but this does not constitute any limitation to the present invention. Any limited number of modifications made by anyone within the scope of the claims of the present invention are still within the scope of the claims of the present invention.

[0044] See Figures 1-9 The present invention provides a transmitter with adjustable local oscillator signal phase, comprising an internal loopback circuit, a transmitting RF front-end circuit, and a register or baseband signal unit. The register or baseband signal unit is a general term for the register unit and baseband signal unit of an FPGA. The transmitting RF front-end circuit comprises a transmitting network ANT1, an up-mixer RF2, a second local oscillator phase calibration unit, and a first digital-to-analog converter DAC1. The first digital-to-analog converter DAC1 performs digital-to-analog conversion on the second baseband signal received from the register or baseband signal unit and inputs the converted signal into the up-mixer RF2, where it is mixed with the local oscillator signal IQ processed by the second local oscillator phase calibration unit to output a radio frequency signal RF. The internal loopback circuit receives the radio frequency signal RF output by the transmitting RF front-end circuit, and the internal loopback circuit comprises an attenuator ATT1, a down-mixer RF1, a first local oscillator phase calibration unit, and a first analog-to-digital converter ADC1. The internal loopback circuit includes an attenuator ATT1, a down-mixer RF1, a first local oscillator phase calibration unit, and a first analog-to-digital converter ADC1. The radio frequency signal RF and the external local oscillator signal LO, after passing through the first local oscillator phase calibration unit, are simultaneously input into the down-mixer RF1 to form a first baseband signal. The external local oscillator signal LO is a standard local oscillator signal without phase error. In this embodiment, the external local oscillator signal LO passes through a first phase-locked loop PLL1 before being input into the first local oscillator phase calibration unit. The transmitting network ANT1 comprises a balun and matching network. The two local oscillator phase calibration units in this embodiment have the same structure.

[0045] To address the problems in the prior art, the present invention implements the present invention by adding an analog-to-digital converter in the internal loopback circuit and a digital-to-analog converter in the transmitting radio frequency front-end circuit.

[0046] The internal loop circuit further includes a second analog-to-digital converter ADC2. The first baseband signal and a reference voltage Vref are simultaneously input into the second analog-to-digital converter ADC2 for analog-to-digital conversion to output a control word COMP. <n:0>. The second local oscillator phase calibration unit includes an inverter group composed of a plurality of inverters INVk connected in series, and the second local oscillator phase calibration unit accesses the local oscillator signal IQ through the second phase-locked loop PLL2. Specifically, the input end of the second phase-locked loop PLL2 inputs the local oscillator signal IQ and outputs the signal LO_I and the signal LO_P respectively. In the inverter group, the input end of the inverter INVk at the head end serves as an input end of the second local oscillator phase calibration unit. In this embodiment, the two input ends of the second local oscillator phase calibration unit respectively input the signal LO_I and the signal LO_P, which are collectively referred to as LO_IN. The output end of the inverter INVk at the end serves as the output end of the second local oscillator phase calibration unit, and the output signals are collectively referred to as LO_OUT, as shown in FIG. Figure 5 shown.

[0047] A coarse tuning capacitor Cap1 and a fine tuning capacitor Cap2 are sequentially provided between the inverters INVk of the inverter group. The coarse tuning capacitor Cap1 is provided with a switch signal receiving terminal Cap<6:0>, which is used to receive the control word COMP<6:0>. Figure 3 The Calibration circuit in the transmitter is used to transmit the control word COMP<6:0> from the register or baseband signal unit to the second local oscillator phase calibration unit. The transmit RF front-end circuit also includes a second digital-to-analog converter DAC2. The second digital-to-analog converter DAC2 is used to receive a preset analog adjustment signal ADJ transmitted from the register or baseband signal unit and convert the preset analog adjustment signal ADJ into a control signal Vctrl; the control signal Vctrl is input into the fine-tuning capacitor Cap2 to change the capacitance product of the fine-tuning capacitor Cap2.

[0048] Regarding the control signal Vctrl, specifically, the second digital-to-analog converter DAC2 outputs a current signal according to the preset analog adjustment signal ADJ, and the signal output end of the second digital-to-analog converter DAC2 is grounded through a resistor to convert the current signal into a voltage signal through the resistor, and the voltage signal serves as the control signal Vctrl.

[0049] In the up-conversion stage of the transmitter, due to the IQ imbalance of the local oscillator signal, in addition to the upper sideband component ω if +ω LO appears, and there is also a lower sideband component ω if -ω LO Appear, and the two sideband frequencies are close. This is a very common phenomenon in the transmitter RF front end. After the internal loop circuit is turned on, the RF signal RF will be attenuated by an attenuator ATT1. The attenuator ATT1 will only reduce the power of the signal and will not shift the frequency of the signal; after attenuation, it is mixed with the external local oscillator signal LO through the up-mixer RF2. Since the external local oscillator signal LO is an ideal orthogonal signal, the phase difference of the RF signal RF is moved to the baseband signal, and then the high-frequency signal is filtered out by the low-pass filter LPF1. The remaining signal is the first baseband signal with phase difference information. The internal loop mixing process is shown in the figure Figure 2 shown.

[0050] After the radio frequency signal RF is down-converted,

[0051]

[0052]

[0053] Where VOUTI and VOUTQ represent the RF signal RF+ and RF signal RF-, respectively. After passing through the down-mixer RF1, the RF signal RF passes through the low-pass filter LPF1. Therefore, the RF signal RF after passing through the low-pass filter LPF1 is:

[0054]

[0055] Right now Figure 4 VOUT is input to the second analog-to-digital converter ADC2 LPF = is the filtered RF signal RF. Thus, the phase error is reflected in the baseband signal. When detecting the baseband signal, the analog-to-digital converter (ADC) uses the different amplitudes of signals at different phases to determine the different charges stored on the capacitors when the baseband signal is sampled. Therefore, COMP<6:0> generated by the ADC reflects the phase of the baseband signal.

[0056] Specifically, the circuit structure diagram of the second analog-to-digital converter ADC2 in the internal loop circuit is as follows: Figure 4 As shown, the radio frequency signal RF passes through the synchronous control switch SB1 and is then input to the radio frequency signal input terminal of the second analog-to-digital converter ADC2. The reference voltage Vref passes through the synchronous control switch SB2 and is then input to the reference voltage input terminal of the second analog-to-digital converter ADC2. The control terminals of the synchronous control switch SB1 and the synchronous control switch SB2 simultaneously receive the clock signal CLK. sample .

[0057] The seven-bit control word COMP<6:0> output by the second analog-to-digital converter ADC2 is stored in the register of the FPGA, and the local oscillator phase calibration unit is controlled by the register to calibrate the IQ phase of the local oscillator signal. Figure 5 shown.

[0058] exist Figure 5 In the example, the inverter group consists of five inverters INV1-5 connected in series. A coarse tuning capacitor Cap1 is provided between each of the three inverters INVk (i.e., INV1-3) near the signal input terminal LO_IN of the second local oscillator phase calibration unit. A fine tuning capacitor Cap2 is provided between each of the three inverters INVk (i.e., INV3-5) near the signal output terminal LO_OUT of the second local oscillator phase calibration unit. In other words, there are two coarse tuning capacitors Cap1 and two fine tuning capacitors Cap2.

[0059] Specifically, the coarse adjustment capacitor Cap1 includes 6 analog capacitors 1 and 6 analog capacitors 2 connected in parallel. The analog capacitor 1 is composed of a first field effect transistor PMn and a control switch Cap_P <n>Composition, control switch Cap_P <n>Receive control word COMP <n:0>The gate of the first field effect transistor PMn is connected to the output end of the corresponding inverter INVk, and the source and drain of the first field effect transistor PMn are connected to the control switch Cap_P <n>Connect one switch end to control the switch Cap_P <n>The other switch terminal is grounded, and the substrate of the first field effect transistor PMn is connected to the common terminal. The analog capacitor 2 is composed of the second field effect transistor NMn and the control switch Cap_N <n>Composition, control switch Cap_N <n>Receive control word COMP <n:0>The gate of the second field effect transistor NMn is connected to the output end of the corresponding inverter INVk, and the source and drain of the second field effect transistor NMn are connected to the control switch Cap_N <n>Connect one switch end to control switch Cap_N <n>The other switch terminal is grounded, and the substrate of the second field-effect transistor NMn is connected to the reference terminal. The fine-tuning capacitor Cap2 includes a third field-effect transistor NMm. The gate of the third field-effect transistor NMm is connected to the output terminal of the corresponding inverter INVk. The source and drain of the third field-effect transistor NMm are simultaneously connected to the control signal Vctrl. The substrate of the third field-effect transistor NMm is connected to the reference terminal. Where n is any natural number from 1 to 6, and m is 2_1 or 2_2, corresponding to the two fine-tuning capacitors respectively.

[0060] The present invention adopts a compensation method through an analog-to-digital converter, using a register or a baseband signal unit to control the control switch of the capacitor array in the coarse adjustment capacitor Cap1, thereby changing the number of capacitors on the local oscillator path, that is, by changing the size of the capacitor on the path, the time for charging the capacitor to a specific voltage is changed, thereby changing the delay of the local oscillator path, and ultimately changing the phase of the local oscillator signal IQ. In addition, the present invention also uses a current steering array based on a digital-to-analog converter and a resistor, which converts the current into a voltage through the resistor, and changes the source-drain voltage of the third field-effect transistor NMm through the voltage, thereby changing the threshold voltage of the field-effect transistor. Among them, the source and drain of the field-effect transistor are short-circuited, and changing the threshold voltage will change the size of the integral capacitance of the field-effect transistor capacitor. The higher the threshold voltage, the smaller the integral capacitance. The purpose of changing the capacitance is to adjust the time constant on the local oscillator path, and then adjust the phase of the local oscillator signal IQ, thereby achieving local oscillator signal IQ phase calibration.

[0061] The IQ phase imbalance of the local oscillator signal is calibrated by changing the time constant τ = RC in the local oscillator path. The relationship between the time constant and the phase change is:

[0062]

[0063] Among them, f LO is the frequency of the local oscillator signal.

[0064] In this embodiment, the local oscillator phase calibration unit, through the design of coarse-tuning capacitor Cap1 and fine-tuning capacitor Cap2, can perform both coarse and fine-tuning calibration. COMP<6:0> is connected to Cap<6:0>, enabling the analog-to-digital converter to detect the RF signal and automatically adjust the phase of the local oscillator signal IQ, achieving coarse phase adjustment of the local oscillator signal IQ. The control signal Vctrl, on the other hand, changes the threshold voltage of the third field-effect transistor NMm, thereby adjusting the value of the integrating capacitor, achieving fine phase adjustment of the local oscillator signal IQ.

[0065] exist Figure 5 In the circuit, since all capacitors are MOS capacitors, it is necessary to first determine the value of the MOS capacitor. The local oscillator signal IQ jumps between 0 and AVDD voltages, so the MOS integral capacitor is used as the capacitance value:

[0066]

[0067] The seven-bit control word generated by the analog-to-digital converter ADC is output in the form of 0000000, 0000001, 0000011...1111111, so eight gear adjustments can be achieved, such as Figure 7 The following table shows the relationship between the control word and phase adjustment.

[0068] Control Word Relative delay (ps) Relative delay step (ps) Relative phase delay (°) 0000000 0 --- 0 0000001 0.43 0.43 0.46 0000011 0.84 0.41 0.91 0000111 1.24 0.4 1.34 0001111 1.64 0.4 1.77 0011111 2.03 0.39 2.19 0111111 2.42 0.39 2.61 1111111 2.81 0.39 3.03

[0069] In addition to the above-mentioned automatic coarse calibration, the phase of the local oscillator signal can also be changed through fine calibration.

[0070] According to the influence of body effect on threshold voltage, the formula is as follows:

[0071]

[0072] The threshold voltage of the FET increases with V SB As the Figure 8 The red line shows the change. When Vt increases, the interval with smaller capacitance value is extended, the interval with larger capacitance value is shortened, and the overall equivalent capacitance is reduced. Figure 5 The control signal Vctrl in the circuit reduces the integrating capacitance of the third field effect transistor NMm, which can change the delay of the local oscillator path and thus fine-tune the local oscillator phase. Therefore, the present invention uses a current steering array based on a digital-to-analog converter and a resistor to control the IQ two-phase current, and then converts the current into a voltage through a resistor to change Vctrl. Figure 5 and Figure 9 As shown, after the preset analog adjustment signal ADJ is input to the second digital-to-analog converter DAC2, it outputs two current signals. After conversion, the two current signals are converted into two control signals, Vctrl_I and Vctrl_Q. Vctrl_I and Vctrl_Q are used to control the fine-tuning capacitors Cap2_1 and Cap2_2, respectively. The preset analog adjustment signal ADJ is output from a register in the FPGA and is stored in the register.

[0073] The above is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several modifications and improvements can be made without departing from the structure of the present invention. These modifications and improvements will not affect the effect of the implementation of the present invention and the practicality of the patent.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A transmitter with adjustable local oscillator signal phase, comprising an internal loopback circuit, a transmitting radio frequency front-end circuit, and a register or baseband signal unit; the transmitting radio frequency front-end circuit comprising a transmitting network (ANT1), an up-mixer (RF2), a second local oscillator phase calibration unit, and a first digital-to-analog converter (DAC1); the first digital-to-analog converter (DAC1) performs digital-to-analog conversion on a second baseband signal received from the register or baseband signal unit, and then inputs the converted signal into the up-mixer (RF2), where the up-mixer mixes the converted signal with the local oscillator signal (IQ) processed by the second local oscillator phase calibration unit to output a radio frequency signal RF; The internal loopback circuit includes an attenuator (ATT1), a down-mixer (RF1), a first local oscillator phase calibration unit, and a first analog-to-digital converter (ADC1); the radio frequency signal (RF) and the external local oscillator signal (LO) after passing through the first local oscillator phase calibration unit are simultaneously input into the down-mixer (RF1) to form a first baseband signal; and is characterized in that: The internal loopback circuit further includes a second analog-to-digital converter (ADC2); the first baseband signal and a reference voltage (Vref) are simultaneously input into the second analog-to-digital converter (ADC2) for analog-to-digital conversion to output a control word (COMP <n:0>); The second local oscillator phase calibration unit includes an inverter group consisting of a plurality of inverters (INVk) connected in series, wherein a coarse tuning capacitor (Cap1) and a fine tuning capacitor (Cap2) are sequentially provided between the inverters (INVk) of the inverter group, and the coarse tuning capacitor (Cap1) is provided with a switch signal receiving terminal (Cap <n:0>), the switch signal receiving end (Cap <n:0>) is used to receive the control word (COMP <n:0> )；< / n:0> The transmitting RF front-end circuit also includes a second digital-to-analog converter (DAC2); the second digital-to-analog converter (DAC2) is used to receive a preset analog adjustment signal (ADJ) transmitted from a register or a baseband signal unit, and convert the preset analog adjustment signal (ADJ) into a control signal (Vctrl); the control signal (Vctrl) is input into the fine-tuning capacitor (Cap2) to change the capacitance product of the fine-tuning capacitor (Cap2); wherein N is a natural number, and k is a natural number greater than 1.

2. The transmitter with adjustable local oscillator signal phase according to claim 1, characterized in that: The coarse adjustment capacitor (Cap1) includes N analog capacitors 1 and N analog capacitors 2 connected in parallel.

3. The transmitter with adjustable local oscillator signal phase according to claim 2, characterized in that: The analog capacitor 1 is composed of a first field effect transistor (PMn) and a first control switch (Cap_P <n>), the first control switch (Cap_P <n>)Receive control word (COMP <n:0>), the gate of the first field effect transistor (PMn) is connected to the output end of the corresponding inverter (INVk), and the source and drain of the first field effect transistor (PMn) are simultaneously connected to the first control switch (Cap_P <n>) is connected to a switch end of the first control switch (Cap_P <n> ) is grounded, and the substrate of the first field effect transistor (PMn) is connected to the common terminal.< / n> < / n> < / n> < / n> 4. The transmitter with adjustable local oscillator signal phase according to claim 2, characterized in that: The analog capacitor 2 is composed of a second field effect transistor (NMn) and a second control switch (Cap_N <n>), the second control switch (Cap_N <n>)Receive control word (COMP <n:0>), the gate of the second field effect tube (NMn) is connected to the output end of the corresponding inverter (INVk), and the source and drain of the second field effect tube (NMn) are simultaneously connected to the second control switch (Cap_N <n>) is connected to a switch terminal of the second control switch (Cap_N <n> ) is grounded, and the substrate of the second field effect transistor (NMn) is connected to the reference terminal.< / n> < / n> < / n> < / n> 5. The transmitter with adjustable local oscillator signal phase according to claim 1, characterized in that: The fine-tuning capacitor (Cap2) includes a third field-effect transistor (NMm), the gate of the third field-effect transistor (NMm) is connected to the output end of the corresponding inverter (INVk), the source and drain of the third field-effect transistor (NMm) are simultaneously connected to the control signal (Vctrl), and the substrate of the third field-effect transistor (NMm) is connected to the reference end, wherein m is a natural number.

6. A transmitter with adjustable local oscillator signal phase according to claim 1 or 5, characterized in that: The second digital-to-analog converter (DAC2) outputs a current signal according to a preset analog adjustment signal (ADJ), and a signal output terminal of the second digital-to-analog converter (DAC2) is grounded via a resistor so as to convert the current signal into a voltage signal via the resistor, and the voltage signal serves as a control signal (Vctrl).

7. A transmitter with adjustable local oscillator signal phase according to any one of claims 1 to 5, characterized in that: The inverter group consists of five inverters (INVk) connected in series. A coarse adjustment capacitor (Cap1) is provided between each of the three inverters (INVk) close to the signal input end (LO_IN) of the second local oscillator phase calibration unit, and a fine adjustment capacitor (Cap2) is provided between each of the three inverters (INVk) close to the signal output end (LO_OUT) of the second local oscillator phase calibration unit.

8. The transmitter with adjustable local oscillator signal phase according to claim 1, characterized in that: The radio frequency signal RF is input to one input terminal of the second analog-to-digital converter (ADC2) after passing through the synchronous control switch 1 (SB1), and the reference voltage (Vref) is input to the other input terminal of the second analog-to-digital converter (ADC2) after passing through the synchronous control switch 2 (SB2). The control terminals of the synchronous control switch 1 (SB1) and the synchronous control switch 2 (SB2) simultaneously receive the clock signal (CLK sample ).

9. The transmitter with adjustable local oscillator signal phase according to claim 1, characterized in that: The first digital-to-analog converter (DAC1) is connected to the up-mixer (RF2) via a second low-pass filter (LPF2).

10. The transmitter with adjustable local oscillator signal phase according to claim 1, characterized in that: The down-mixer (RF1) is connected to a first analog-to-digital converter (ADC1) via a low-pass filter 1 (LPF1).

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