High-speed interface stable transmission system based on multi-level resetting and monitoring

Abstract

The invention discloses a high-speed interface stable transmission system based on multi-level resetting and monitoring. The high-speed interface stable transmission system comprises a GTX transceiver, a high-speed interface and a high-speed interface, wherein the GTX transceiver is used for realizing data transmission based on FGPA programming; the reset signal module is responsible for generating a reset signal and carrying out initialization reset on the optical fiber hardware link module; the link monitoring module is responsible for monitoring the communication state of the optical fiber hardware link module; the optical fiber hardware link module is responsible for realizing optical fiber data transmission of a physical layer; the starting of the high-speed interface stable transmission system comprises the following steps: after judging that a system clock generated in the FPGA is stabilized to a first specified duration, pulling up a global reset signal, and carrying out initialization reset on an optical fiber hardware link module; after the initialization resetting reaches a second specified duration, resetting the IP core of the GTX transceiver for a third specified duration; a signal enters the GTX transceiver structure, and a receiving terminal net mask layer and a physical medium layer are reset for a fourth specified duration; and the high-speed interface stable transmission system also comprises an exception handling module for realizing real-time monitoring.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed data transmission, and in particular to a high-speed interface stable transmission system based on multi-level reset and monitoring. Background Art

[0002] With the rapid development of wireless communications, radar systems, high-speed instruments and other fields, high-speed data transmission technology is facing more and more challenges. In high-precision terminal guidance detection systems, large bandwidth and complex signal waveforms are required, so the reliability of data transmission is very high. When faced with complex electromagnetic environments, poor hardware compatibility, and inter-code crosstalk, traditional high-speed serial data transmission methods often have problems such as unstable data transmission, high bit error rate, and frequent link disconnection, which seriously affects the overall performance of the system.

[0003] In the prior art, some methods for improving fault tolerance have been proposed for the link disconnection and data packet loss problems of non-cognate clock GTX communication links. For example, Chinese patent CN110995479B proposes a method for periodically detecting the bit error state and data frame state, and re-establishing the connection according to the bit error threshold and error frame threshold. This method improves the fault tolerance of the system by detecting the link status in real time and resetting it in time when an abnormality occurs. However, this method is mainly aimed at the application scenarios of non-cognate clock GTX communication links, and the reset mechanism is relatively simple, which cannot effectively deal with problems such as complex electromagnetic environments and poor hardware compatibility.

[0004] In order to solve the above problems, the present invention proposes a high-speed interface stable transmission solution based on multi-level reset and monitoring, aiming to improve the stable transmission capability of the high-speed interface. By resetting and monitoring the high-speed interface at multiple levels, it is compatible with different communication link hardware, reduces inter-code crosstalk, improves data transmission stability, and realizes stable and reliable transmission of complex waveform data. Summary of the invention

[0005] The technical solution of the present invention is as follows:

[0006] A high-speed interface stable transmission system based on multi-level reset and monitoring, the system comprising:

[0007] GTX transceiver: data transmission based on FGPA programming;

[0008] Reset signal module: responsible for generating a reset signal to initialize and reset the optical fiber hardware link module;

[0009] Link monitoring module: responsible for monitoring the communication status of the optical fiber hardware link module;

[0010] Optical fiber hardware link module: responsible for realizing optical fiber data transmission at the physical layer;

[0011] The initialization reset refers to: performing initial configuration and state recovery on the optical fiber hardware link module during system startup or reset; the system generates a reset signal through the reset signal module, and after the optical fiber hardware link module receives the reset signal, its internal circuit is reset to the initial state, clearing any remaining error state or abnormal state, and after the reset is completed, the system loads the predefined configuration parameters into the optical fiber hardware link module;

[0012] The startup of the high-speed interface stable transmission system includes: after determining that the system clock generated inside the FPGA is stable to a first specified time length, pulling up a global reset signal to initialize and reset the optical fiber hardware link module;

[0013] After the initialization reset reaches the second specified time, the GTX transceiver IP core is reset for a third specified time;

[0014] The signal enters the GTX transceiver structure and resets the receiving terminal netmask layer and the physical medium layer for a fourth specified time period respectively;

[0015] The high-speed interface stable transmission system also includes a method for performing exception processing when implementing real-time monitoring.

[0016] The configuration of the GTX transceiver is: use the aurora serial transmission protocol, the receiving and transmitting rates are both 8Gbps, the system clock is 200MHz, the encoding method is 8B10B encoding, the external data bit width is 32 bits, check RXPCSRESET and RXPMARESET, select K28.5 for the control code, the corresponding hexadecimal value is 0xBC, and the alignment method is four-byte alignment.

[0017] The reset signals include: a system reset signal, a fiber optic module reset signal, a GTX IP core reset signal, a RX-PCS reset signal, and a RX-PMA reset signal.

[0018] The specific exception handling during the real-time monitoring is as follows: after completing the first round of reset, the system monitors the link communication status in real time through the link monitoring module. If the error flag signal is detected to be high, the physical media layer of the receiving end is reset again, and the status of other ports remains unchanged.

[0019] The monitoring of the link communication status is achieved by reading the link communication status information provided by the GTX transceiver, and the link communication status information includes the status of the error flag signal, the detection error rate, the link connection status and the data transmission rate.

[0020] The system realizes the generation of multi-level reset signals and the real-time monitoring and reporting of abnormal states of high-speed interfaces through FPGA programming algorithms.

[0021] The beneficial effects of the present invention are:

[0022] 1. Significantly improve the stability and reliability of signal transmission: The multi-level reset strategy is designed to deal with various fault conditions. Since the transmission and reception of data depends on hardware, and there are differences between different hardware components, a single-level reset often cannot completely restore communication. For this reason, the present invention introduces physical layer reset, hardware fiber reset, and GTX transceiver reset. These multi-level reset measures can effectively deal with a variety of abnormal situations; real-time monitoring and exception handling functions can detect and handle link abnormalities in a timely manner to ensure the stability and reliability of signal transmission.

[0023] 2. Greatly improve fault detection and recovery capabilities: The link monitoring module can monitor the link communication status in real time and detect bit errors and link failures in a timely manner; the multi-level reset signal generation function can quickly recover from link failures, greatly improving the system's fault detection and recovery capabilities.

[0024] 3. Effectively reduce inter-code interference: Through multi-level reset and real-time monitoring, inter-code interference is effectively reduced, and the stability and reliability of data transmission are improved.

[0025] 4. Enhance the system's anti-interference ability: The multi-level reset signal generation function of the GTX transceiver enables the system to perform targeted reset processing when facing different types of interference, thereby enhancing the system's anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural block diagram of a receiving module of a GTX transceiver of the present invention;

[0027] Figure 2 It is a PMA reset signal generation logic diagram of the present invention;

[0028] Figure 3 It is a multi-level reset timing diagram of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings:

[0030] The present invention provides a high-speed interface stable transmission system based on multi-level reset and monitoring to solve the problems of high inter-code crosstalk, low data transmission stability, poor hardware compatibility, etc. existing in the traditional high-speed serial data transmission method in complex application scenarios, including the following modules:

[0031] GTX transceiver: The GTX transceiver of Xilinx K7 series FPGA is used to realize data transmission based on FGPA programming. The specific configuration is as follows: using aurora serial transmission protocol, the receiving and sending rates are both 8Gbps, the system clock is 200MHz, the encoding method is 8B10B encoding, the external data bit width is 32 bits, and other items are checked RXPCSRESET (RX-PCS reset signal, high effective), RXPMARESET (RX-PMA reset signal, high effective), the control code is K28.5 (0xBC), and the alignment method is four-byte alignment. The receiving module structure in the GTX transceiver is as follows Figure 1 The configuration of the GTX transceiver ensures the stability and reliability of high-speed data transmission, and further improves the system's anti-interference and fault recovery capabilities through the generation of multi-level reset signals.

[0032] Reset signal module: This module is responsible for generating a reset signal when the system starts, and initializing and resetting the fiber optic hardware link module. The specific process includes: when the system clock is stable for 50 microseconds, the reset signal generation module pulls up the global reset signal to initialize and reset the fiber optic hardware link module. This design ensures that the system can quickly enter a stable state at the initial startup, avoiding signal transmission problems caused by unstable initial state. The multi-level reset in the present invention includes: fiber optic hardware link reset, GTX IP core FPGA software reset, GTX receiving end PCS subnet mask layer reset, GTX receiving end PMA physical media layer reset, so the present invention designs corresponding reset signals, including: system reset signal, fiber optic module reset signal, GTX IP core reset signal, RX-PCS reset signal and RX-PMA reset signal. Among them, the system needs to judge the validity of the data before generating the PMA (RX-PMA) reset signal, generate and update the valid counter according to the value of the data validity, and generate a PMA reset signal according to the valid counter. The PMA reset signal generation logic is as follows: Figure 2 As shown, T is the counter of the state machine that generates the PMA signal, and KC is the flag for controlling the clearing of the valid counter.

[0033] Link monitoring module: This module monitors the link communication status in real time, including the status of the error flag signal, the detection error rate, the link connection status, and the data transmission rate. By reading the link communication status information provided by the GTX transceiver, the link monitoring algorithm module can detect link anomalies in time and trigger the corresponding anomaly handling mechanism. This design greatly improves the system's fault detection capability and ensures the reliability and stability of data transmission.

[0034] Fiber optic hardware link module: This module is responsible for fiber optic data transmission at the physical layer and is an important part of the system.

[0035] Initialization reset refers to: initial configuration and status recovery of the fiber optic hardware link module during system startup or reset; the system generates a reset signal through the reset signal module. After the fiber optic hardware link module receives the reset signal, its internal circuit is reset to the initial state, clearing any remaining error state or abnormal state. After the reset is completed, the system loads the predefined configuration parameters into the fiber optic hardware link module.

[0036] The startup of the high-speed interface stable transmission system includes: after determining that the system clock generated inside the FPGA is stable for a first specified time, pulling up the global reset signal to initialize and reset the optical fiber hardware link module; after the initialization reset reaches a second specified time, resetting the GTX transceiver IP core for a third specified time; the signal enters the GTX transceiver structure, resetting the receiving terminal network mask layer and the physical medium layer for a fourth specified time respectively; the high-speed interface stable transmission system also includes a method for performing exception handling when implementing real-time monitoring.

[0037] In this embodiment, Figure 3 As shown in the figure, the system startup process includes:

[0038] When the system clock is stable for 50us, the global reset signal is pulled high to initialize and reset the fiber hardware link module; 1ms later, the GTX transceiver IP core is reset for 5us; finally, the signal enters the GTX transceiver structure and resets the receiving terminal network mask layer and physical media layer for 5us respectively.

[0039] The present invention also includes real-time monitoring and exception handling functions: after completing the first round of reset, the system monitors the link communication status in real time through the link monitoring module. If the error flag signal is detected to be high, the receiving end physical medium layer is reset again, and the states of other ports remain unchanged. The monitoring of the link communication status is achieved by reading the link communication status information provided by the GTX transceiver, including the state of the error flag signal, the detection error rate, the link connection status and the data transmission rate.

[0040] The present invention provides a high-speed interface stable transmission system based on multi-level reset and monitoring, which realizes the generation of multi-level reset signals and real-time monitoring and reporting of abnormal states of high-speed interfaces through FPGA programming algorithms, monitors link communication states in real time and adjusts and optimizes them, is compatible with different communication link hardware, improves the stability of system transmission, reduces inter-code interference, and in actual projects, through system verification, realizes high-speed stable and reliable transmission of terminal guidance detection systems.

Claims

1. A high-speed interface stable transmission system based on multi-level reset and monitoring, characterized in that: The system comprises: GTX transceiver: data transmission based on FGPA programming; Reset signal module: responsible for generating a reset signal to initialize and reset the optical fiber hardware link module; Link monitoring module: responsible for monitoring the communication status of the optical fiber hardware link module; Optical fiber hardware link module: responsible for realizing optical fiber data transmission at the physical layer; The initialization reset refers to: performing initial configuration and state recovery on the optical fiber hardware link module during system startup or reset; the system generates a reset signal through the reset signal module, and after the optical fiber hardware link module receives the reset signal, its internal circuit is reset to the initial state, clearing any remaining error state or abnormal state, and after the reset is completed, the system loads the predefined configuration parameters into the optical fiber hardware link module; The startup of the high-speed interface stable transmission system includes: after determining that the system clock generated inside the FPGA is stable to a first specified time length, pulling up a global reset signal to initialize and reset the optical fiber hardware link module; After the initialization reset reaches the second specified time, the GTX transceiver IP core is reset for a third specified time; The signal enters the GTX transceiver structure and resets the receiving terminal netmask layer and the physical medium layer for a fourth specified time period respectively; The high-speed interface stable transmission system also includes a method for performing exception processing when implementing real-time monitoring.

2. The high-speed interface stable transmission system according to claim 1, characterized in that: The configuration of the GTX transceiver is: use the aurora serial transmission protocol, the receiving and transmitting rates are both 8Gbps, the system clock is 200MHz, the encoding method is 8B10B encoding, the external data bit width is 32 bits, check RXPCSRESET and RXPMARESET, select K28.5 for the control code, the corresponding hexadecimal value is 0xBC, and the alignment method is four-byte alignment.

3. The high-speed interface stable transmission system according to claim 1, characterized in that: The reset signals include: a system reset signal, a fiber optic module reset signal, a GTX IP core reset signal, a RX-PCS reset signal, and a RX-PMA reset signal.

4. The high-speed interface stable transmission system according to claim 1, characterized in that: The specific exception handling during the real-time monitoring is as follows: after completing the first round of reset, the system monitors the link communication status in real time through the link monitoring module. If the error flag signal is detected to be high, the physical media layer of the receiving end is reset again, and the status of other ports remains unchanged.

5. The high-speed interface stable transmission system according to claim 4, characterized in that: The monitoring of the link communication status is achieved by reading the link communication status information provided by the GTX transceiver, and the link communication status information includes the status of the error flag signal, the detection error rate, the link connection status and the data transmission rate.

6. The high-speed interface stable transmission system according to claim 1, characterized in that: The system realizes the generation of multi-level reset signals and the real-time monitoring and reporting of abnormal states of high-speed interfaces through FPGA programming algorithms.

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