Device and method for realizing wireless high-precision time synchronization based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a device for realizing wireless high-precision time synchronization based on an FPGA (Field Programmable Gate Array), and also discloses a method for realizing wireless high-precision time synchronization based on the FPGA. According to the invention, a time sequence can be strictly controlled by adopting a method for recording a timestamp by adopting hardware at an FPGA end, and the sending time delay is eliminated; besides, the position for recording the sending timestamp is close to the radio frequency end, so that accumulated time delay caused by sending processing time delay can be reduced, and delay uncertainty caused by clock domain crossing of processing data can be reduced. And finally, a sequence detection method is adopted after the filter module is matched, and the arrival time of the timestamp of the receiving end is judged at the first time, so that the uncertainty time delay caused by an algorithm existing in receiving processing can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of time synchronization, and in particular relates to a device for realizing wireless high-precision time synchronization based on FPGA, and also relates to a method for realizing wireless high-precision time synchronization based on FPGA. Background Art

[0002] The process of unifying clocks in various places to standard time through the transmission of standard time information is called timing. As people's demand for time continues to increase, the means of time measurement have evolved from astronomical time measurement to atomic time, and the accuracy of time synchronization has developed from seconds and milliseconds to today's nanoseconds, sub-nanoseconds and even higher. High-precision time standards are crucial to cutting-edge industries such as aerospace, navigation, and guidance, and also play a key role in modern warfare. At present, high-precision wireless time synchronization solutions mainly rely on navigation satellite timing, but the cost of satellite reconstruction and maintenance is high, and satellite signals cannot work properly in satellite denial environments. These limitations have prompted researchers to explore more flexible and economical solutions, among which wireless time synchronization technology has gradually become an important research direction.

[0003] Software radio has the advantages of flexibility in the RF end. Among them, AD9361 is a high-performance RF agile transceiver chip launched by ADI in the United States. It is mainly designed to provide good application solutions for 3G and 4G communication base stations and equipment terminals. It has the advantages of high integration, low power consumption, good programmability, and large supported bandwidth. AD9361 integrates the frequency synthesizer, low noise amplifier, analog filter, mixer, digital-to-analog and analog-to-digital converter modules of the RF transceiver channel into a small chip, including most of the processing modules required to convert digital baseband signals to RF analog signals.

[0004] Among them, the timestamp is used to mark the key moment when the node processes the relevant frame data. The timestamp can be marked at the network layer, MAC layer, and physical layer. The accuracy of the timestamp marking at different levels is also different. Therefore, when the timestamp is marked at the physical layer, the closer the timestamp is to the RF front end of the transmitter and the receiver, the less delay and uncertainty caused by other intermediate modules in the transmission link, and the more accurately the actual transmission or reception time is reflected. In addition, the use of bit synchronization and sequence detection methods can also improve the accuracy of the received timestamp, thereby improving the master-slave time synchronization accuracy of wireless time synchronization to a certain extent. Summary of the invention

[0005] The purpose of the present invention is to provide a device for realizing wireless high-precision time synchronization based on FPGA and a method for realizing wireless high-precision time synchronization based on FPGA in view of the above-mentioned problems existing in the prior art.

[0006] The above-mentioned purpose of the present invention is achieved by the following technical means:

[0007] A device for realizing wireless high-precision time synchronization based on FPGA, comprising a master end and a slave end, wherein the master end and the slave end both comprise a sending link, a receiving link, and a radio frequency transceiver;

[0008] The transmission link includes a real-time clock module, a QPSK baseband modulation module, a first sequence detection module, and a first intermediate frequency module; the real-time clock module generates a message carrying timestamp data, the message carrying timestamp data passes through the QPSK baseband modulation module to obtain I branch baseband transmission data and Q branch baseband transmission data, the I branch baseband transmission data and the Q branch baseband transmission data pass through the first intermediate frequency module to obtain I branch intermediate frequency transmission data and Q branch intermediate frequency transmission data, the I branch intermediate frequency transmission data and the Q branch intermediate frequency transmission data are respectively up-converted by the radio frequency transceiver to obtain the I branch radio frequency transmission signal and the Q branch radio frequency transmission signal and then respectively transmitted;

[0009] The first sequence detection module detects and records the arrival time of the I branch baseband transmission data or the Q branch baseband transmission data in the transmission link as the arrival time of the message in the transmission link;

[0010] The receiving link includes a second intermediate frequency module, a matching filter module, a QPSK baseband demodulation module, and a second sequence detection module. The radio frequency transceiver receives and obtains an I-branch radio frequency receiving signal and a Q-branch radio frequency receiving signal and performs down-conversion respectively to obtain an I-branch intermediate frequency receiving signal and a Q-branch intermediate frequency receiving signal. The I-branch intermediate frequency receiving signal and the Q-branch intermediate frequency receiving signal are respectively passed through the second intermediate frequency module and the matching filter module in sequence to obtain an I-branch baseband receiving data and a Q-branch baseband receiving data. The I-branch baseband receiving data and the Q-branch baseband receiving data are passed through the QPSK baseband demodulation module to obtain a timestamp.

[0011] The second sequence detection module detects and records the arrival time of the I-branch baseband receiving data or the Q-branch baseband receiving data in the receiving link as the arrival time of the message in the receiving link.

[0012] As described above, the QPSK baseband modulation module includes a differential encoding module, a serial-to-parallel conversion module, and a shaping filter module. The message carrying the timestamp data passes through the differential encoding module, the serial-to-parallel conversion module, and the shaping filter module in sequence to obtain the I branch baseband data and the Q branch baseband data.

[0013] As described above, the QPSK baseband demodulation module includes a carrier synchronization module, a bit synchronization module, a data merging module, and a data judgment module. The I-branch baseband received data and the Q-branch baseband received data are sequentially passed through the carrier synchronization module, the bit synchronization module, the data merging module, and the data judgment module to obtain a timestamp.

[0014] As described above, the receiving link of the slave end further includes a difference calculation module, which calculates the delay of the sending link and the receiving link.

[0015] A method for realizing wireless high-precision time synchronization based on FPGA, using the device for realizing wireless high-precision time synchronization based on FPGA as described above, comprises the following steps:

[0016] Step 1: Set the format of the message carrying timestamp data generated by the real-time clock modules of the master and slave ends, and set the first bit of the frame header of the message to 1;

[0017] Step 2: The sending link of the master end generates and sends the first frame message, and detects and records the arrival time t1 of the first frame message;

[0018] Step 3: The sending link of the master end generates a second frame message carrying the arrival time t1, and sends the second frame message after the set delay time;

[0019] Step 4: The receiving link of the slave end detects and records the arrival time t2 of the first frame message; the receiving link of the slave end receives the second frame message, and decodes the arrival time t1 carried in the second frame message;

[0020] Step 5: The sending link of the slave end generates and sends a third frame message carrying the arrival time t2, and detects and records the arrival time t3 of the third frame message;

[0021] Step 6: The receiving link of the master end detects and records the arrival time t4 of the third frame message, and then the sending link of the master end generates and sends the fourth frame message carrying the arrival time t4;

[0022] Step 7: The receiving link of the slave receives the fourth frame message, and decodes the arrival time t1 carried in the fourth frame message. Finally, the slave calculates the clock deviation according to the recorded arrival times t1, t2, t3, and t4, and finally calibrates the slave clock according to the calculated clock deviation.

[0023] The clock skew is calculated based on the following formula:

[0024] offset=[(t1-t2)+(t4-t3)] / 2

[0025] In the formula, offset is the clock deviation, / is the division sign;

[0026] Step 8: The master and slave start a 1s counter at the same time, and repeat steps 1-7 with a period of 1s, performing clock calibration on the slave once a second.

[0027] As described above, the format of the message in step 1 includes a frame header, a type, a synchronization cycle number, a synchronization message, a synchronization message check, timestamp data, timestamp data check 1, and timestamp data check 2.

[0028] As described above, the sending link of the master end in step 2 or the sending link of the slave end in step 5 detects the arrival time of the message in the following manner:

[0029] First, the real-time clock module of the sending link sets the flag data_flag, then generates and sends the first frame message, and pulls the level of the flag data_flag high;

[0030] Secondly, the first sequence detection module of the sending link sets the flag mod_flag. The first sequence detection module of the sending link detects and records the arrival time of the first falling edge after the level data_flag is pulled high, and obtains the current timestamp as the arrival time corresponding to the message, and then pulls the level of the flag mod_flag of the first sequence detection module of the sending link high.

[0031] As described above, the receiving link of the slave end in step 4 and the receiving link of the slave end in step 6 detect and record the arrival time of the message in the following manner:

[0032] First, the matched filter module of the receiving link obtains the best decision point sync_flag through the garden ring bit synchronization, and uses the best decision point sync_flag to detect the valid data of the message. After the valid data of the message is detected, each bit of the message is sent to the second sequence detection module;

[0033] Secondly, the second sequence detection module of the receiving link sets the flag bit demod_flag. The second sequence detection module of the receiving link detects the entire data sequence of the frame header of the message through the state machine. When the frame header of the message is detected, the level of the flag bit demod_flag is pulled high, and the current timestamp is recorded as the arrival time corresponding to the message;

[0034] Finally, if the data judgment module of the receiving link detects that the frame header, timestamp data check 1, and timestamp data check 2 are all correct, the arrival time recorded by the second sequence detection module of the receiving link is valid.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The present invention can strictly control the timing and eliminate the transmission delay by adopting the method of recording the timestamp by hardware; in addition, by making the location of recording the transmission timestamp close to the radio frequency end, the cumulative delay caused by the transmission processing delay and the delay uncertainty caused by processing data across the clock domain can be reduced. Finally, by adopting the sequence detection method after the matched filter module, the time when the timestamp of the receiving link arrives can be judged at the first time, which can reduce the uncertainty delay caused by the algorithm in the receiving process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the structure of the device of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of the message format of embodiment 2 of the present invention;

[0039] Figure 3 It is a corresponding relationship diagram of the I branch transmission data of the present invention and the I branch baseband transmission data I_filtered after passing through the shaping filter module;

[0040] Figure 4 is a detection diagram at the arrival time t1 in Embodiment 2 of the present invention;

[0041] Figure 5 : is a detection diagram at time t2 in Embodiment 3 of the present invention (state is the state position of the state machine);

[0042] Figure 6 A schematic diagram of the calculation clock deviation of the present invention;

[0043] Figure 7 It is a state transition diagram of a state machine when the second sequence detection module of the slave end detects the first frame message in Embodiment 3 of the present invention;

[0044] Reference numerals and corresponding component names:

[0045] 1—real-time clock module; 2—differential encoding module; 3—serial-to-parallel conversion module; 4—shaping filter module; 5—first sequence detection module; 6—first intermediate frequency module; 7—RF transceiver; 8—second intermediate frequency module; 9—matched filter module; 11—second sequence detection module; 10—carrier synchronization module; 12—bit synchronization module; 13—data merging module; 14—data judgment module; 15—difference calculation module. DETAILED DESCRIPTION

[0046] In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below in conjunction with embodiments. The embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0047] Embodiment 1:

[0048] A device for realizing wireless high-precision time synchronization based on FPGA, comprising a master end (Master) and a slave end (Slave), wherein the master end and the slave end both comprise an AD9361 transmission link, an AD9361 reception link, and a radio frequency transceiver 7;

[0049] In this embodiment, the RF transceivers 7 of the master end and the slave end both use AD9361 chips;

[0050] The transmission link includes a real-time clock module 1, a QPSK baseband modulation module, a first sequence detection module 5, and a first intermediate frequency module 6; the real-time clock module 1 generates a message para_Tx carrying timestamp data, and the message para_Tx carrying timestamp data passes through the QPSK baseband modulation module to obtain I branch baseband transmission data I_filtered and Q branch baseband transmission data, and the I branch baseband transmission data I_filtered and the Q branch baseband transmission data Q_filtered pass through the first intermediate frequency module 6 to obtain I branch intermediate frequency transmission data qp sk_i and Q branch intermediate frequency transmission data qpsk_q (specifically: the first intermediate frequency module 6 multiplies the I branch intermediate frequency transmission data I_filtered with the cos carrier signal to obtain the I branch intermediate frequency transmission data qpsk_i, and the first intermediate frequency module 6 multiplies the I branch baseband transmission data Q_filtered with the sin carrier signal to obtain the Q branch intermediate frequency transmission data qpsk_q), the I branch intermediate frequency transmission data and the Q branch intermediate frequency transmission data are respectively up-converted by the radio frequency transceiver 7 to obtain the I branch radio frequency transmission signal and the Q branch radio frequency transmission signal and then respectively transmitted;

[0051] The QPSK baseband modulation module includes a differential encoding module 2, a serial-to-parallel conversion module 3, and a shaping filter module 4. The real-time clock module 1 generates a message para_Tx carrying timestamp data and outputs it to the differential encoding module 2. The differential encoding module 2 obtains a data frame para_in by differentially encoding the input data stream, and inputs the data frame para_in to the serial-to-parallel conversion module 3. The serial-to-parallel conversion module 3 converts the parallel data into serial data, and divides the serial data into orthogonal and co-directional data according to the parity position in the converted serial data, and performs bipolar conversion respectively to obtain I branch transmission data and Q branch transmission data. The serial-to-parallel conversion module 3 inputs the I branch transmission data and the Q branch transmission data into the shaping filter module 4 respectively, and the shaping filter module 4 filters the I branch transmission data and the Q branch transmission data respectively, wherein the shaping filter module 4 obtains the I branch baseband transmission data I_filtered after filtering the I branch transmission data, and obtains the Q branch baseband transmission data Q_filtered after filtering the Q branch data. The shaping filter module 4 inputs the I branch baseband transmission data I_filtered and the Q branch baseband transmission data Q_filtered into the first intermediate frequency module 6 respectively.

[0052] The first sequence detection module 5 detects and records the arrival time of the I-branch baseband transmission data I_filtered or the Q-branch baseband transmission data Q_filtered in the transmission link as the arrival time of the message in the transmission link;

[0053] The receiving link includes a second intermediate frequency module 8, a matched filter module 9, a QPSK baseband demodulation module, and a second sequence detection module 11. The radio frequency transceiver 7 receives the I branch radio frequency receiving signal and the Q branch radio frequency receiving signal and performs down-conversion respectively to obtain the I branch intermediate frequency receiving signal qpsk_i′ and the Q branch intermediate frequency receiving signal qpsk_q′. The I branch intermediate frequency receiving signal qpsk_i′ and the Q branch intermediate frequency receiving signal qpsk_q′ respectively pass through the second intermediate frequency module 8 and the matched filter module 9 in turn to obtain the I branch baseband receiving data I′_filtered and the Q branch baseband receiving data Q′_fi ltered (specifically: the second intermediate frequency module 8 inputs the signal obtained by multiplying the I branch intermediate frequency receiving signal qpsk_i′ and the cos carrier signal into the matching filter module 9 for filtering to obtain the I branch baseband receiving data I′_filtered, and inputs the signal obtained by multiplying the Q branch intermediate frequency receiving signal qpsk_q′ and the sin carrier signal into the matching filter module 9 to obtain the Q branch baseband receiving data Q′_filtered), the I branch baseband receiving data I′_filtered and the Q branch baseband receiving data Q′_filtered are timestamped by the QPSK baseband demodulation module;

[0054] The QPSK baseband demodulation module includes a carrier synchronization module 10, a bit synchronization module 12, a data merging module 13, and a data judgment module 14. The I-branch baseband receiving data and the Q-branch baseband receiving data are sequentially passed through the carrier synchronization module 10, the bit synchronization module 12, the data merging module 13, and the data judgment module 14 to obtain a timestamp;

[0055] Due to the power-on time of the sending link or the receiving link, or the crystal oscillator offset, or the environmental influence in the actual communication, it is necessary to perform phase detection and loop filtering on the I branch baseband receiving data I′_filtered and the Q branch baseband receiving data Q′_filtered. Therefore, the matching filter module 9 inputs the I branch baseband receiving data I′_filtered and the Q branch baseband receiving data Q′_filtered to the carrier synchronization module 10 respectively, and obtains the I branch demodulation signal and the Q branch demodulation signal, and then the I branch demodulation signal is input to the carrier synchronization module 10. The modulation signal and the Q branch demodulation signal are respectively input into the bit synchronization module 12 to obtain accurate I branch single-bit data and Q branch single-bit data, and the I branch single-bit data and the Q branch single-bit data are input into the data merging module 13 to be merged into one data frame. The data merging module 13 inputs the merged data frame into the data judgment module 14. The data judgment module 14 deciphers the arrival time carried in the merged data frame, and judges the frame header, timestamp data check 1, timestamp data check 2, and timestamp data check of the merged data frame.

[0056] The second sequence detection module 11 detects and records the arrival time of the I-branch baseband receiving data I′_filtered or the Q-branch baseband receiving data I′_filtered in the receiving link as the arrival time of the message in the receiving link.

[0057] The receiving link of the slave end further includes a difference calculation module 15, the input end of the difference calculation module 15 is connected to the output end of the first sequence detection module 5 of the slave end and the second sequence detection module 11 of the slave end, and the difference calculation module 15 calculates the delay of the sending link and the receiving link.

[0058] The present invention adds a first sequence detection module 5 to the qpsk baseband modulation, detects the I-branch baseband transmission data I_filtered (or the Q-branch baseband transmission data Q_filtered) through the first sequence detection module 5, and when the I-branch baseband transmission data I_filtered (or the Q-branch baseband transmission data Q_filtered) is detected, the arrival time of the I-branch baseband transmission data I_filtered (or the Q-branch baseband transmission data Q_filtered) is recorded;

[0059] The first sequence detection module 5 of the present invention only needs to detect one of the I-branch baseband transmission data I_filtered and the Q-branch baseband transmission data Q_filtered to obtain the data frame position at this time, because the timing of the I-branch baseband transmission data I_filtered and the Q-branch baseband transmission data Q_filtered is aligned, so they arrive at the same time, and the frame headers of the two signals of the I-branch baseband transmission data I_filtered and the Q-branch baseband transmission data Q_filtered are also the same, so only one of them needs to be detected.

[0060] Embodiment 2:

[0061] A method for realizing wireless high-precision time synchronization based on FPGA, using the device for realizing wireless high-precision time synchronization based on FPGA described in the above embodiment 1, comprises the following steps:

[0062] Step 1, setting the format of the message carrying timestamp data generated by the real-time clock module 1 of the master end and the slave end, and setting the first bit of the frame header of the message to 1;

[0063] The message in this embodiment is 180 bits, and the message includes a 16-bit frame header, a 2-bit type, a 10-bit synchronization cycle number, a 64-bit synchronization message, an 8-bit synchronization message check, a 64-bit timestamp data, an 8-bit timestamp data check 1, and an 8-bit timestamp data check 2. The 2-bit type is used to indicate which frame of the message it is, where 00 represents the first frame message (First frame), 01 represents the second frame message (Second frame), 10 represents the third frame message (ThirdFrame), and 11 represents the fourth frame message (Fourth frame).

[0064] The present invention sends invalid data 0 when no message is sent.

[0065] Step 2: The sending link of the master end generates and sends the first frame message, and detects and records the arrival time t1 of the first frame message, which specifically includes the following steps:

[0066] The arrival time t1 is the time when the first frame message arrives at the first sequence detection module 5 of the sending link of the master end;

[0067] Step 2.1, the real-time clock module 1 of the sending link of the master end sets the flag bit data_flag, then generates and sends the first frame message, and pulls up the level of the flag bit data_flag of the real-time clock module 1 of the sending link of the master end;

[0068] Step 2.2, the first sequence detection module 5 of the sending link of the master end sets the flag bit mod_flag, the first sequence detection module 5 of the sending link of the master end detects and records the arrival time of the first falling edge after the level of the flag bit data_flag of the real-time clock module 1 of the sending link of the master end is pulled high, and obtains the current timestamp as the arrival time t1 of the first frame message, and then pulls the level of the flag bit mod_flag of the first sequence detection module 5 of the sending link of the master end high.

[0069] Step 3: The sending link of the master end generates a second frame message carrying the arrival time t1, and sends the second frame message after the set delay time;

[0070] Step 4: The receiving link of the slave end detects and records the arrival time t2 of the first frame message; the receiving link of the slave end receives the second frame message, and decodes the arrival time t1 carried in the second frame message, which specifically includes the following steps:

[0071] The arrival time t2 is the time when the first frame message arrives at the second sequence detection module 11 of the receiving link of the slave end;

[0072] Step 4.1, the matched filter module 9 of the receiving link of the slave end obtains the best decision point sync_flag through the garden ring bit synchronization, and uses the best decision point sync_flag to detect the valid data of the first frame message. After the valid data of the first frame message is detected, each bit of the first frame message is sent to the second sequence detection module 11 of the receiving link of the slave end;

[0073] Step 4.2, the second sequence detection module 11 of the receiving link of the slave end sets the flag bit demod_flag, and the second sequence detection module 11 of the receiving link of the slave end detects the entire data sequence of the frame header of the first frame message through the state machine. When the frame header of the first frame message is detected, the level of the flag bit demod_flag of the second sequence detection module 11 of the receiving link of the slave end is pulled high, and the current timestamp is recorded as the arrival time t2 of the first frame message;

[0074] Step 4.3, if the data judgment module 14 of the receiving link of the slave end detects that the frame header, timestamp data check 1, and timestamp data check 2 of the first frame message are all correct, then the arrival time t2 of the first frame message recorded by the second sequence detection module 11 of the receiving link of the slave end is valid;

[0075] Step 4.4: The data decision module 14 of the receiving link of the slave end extracts the arrival time t1 carried in the second frame message.

[0076] Step 5: The sending link of the slave end generates and sends a third frame message carrying the arrival time t2, and detects and records the arrival time t3 of the third frame message, which specifically includes the following steps:

[0077] The arrival time t3 is the time when the third frame message arrives at the first sequence detection module 5 of the sending link of the slave end;

[0078] Step 5.1, the real-time clock module 1 of the sending link of the slave end sets the flag bit data_flag, then generates and sends the third frame message, and pulls up the level of the flag bit data_flag of the real-time clock module 1 of the sending link of the slave end;

[0079] Step 5.2, the first sequence detection module 5 of the sending link of the slave end sets the flag bit mod_flag, the first sequence detection module 5 of the sending link of the slave end detects and records the arrival time of the first falling edge of the flag bit data_flag of the real-time clock module 1 of the sending link of the slave end after the level is pulled high, and obtains the arrival time t3 of the third frame message with the current timestamp, and then pulls the level of the flag bit mod_flag of the first sequence detection module 5 of the sending link of the slave end high.

[0080] Step 6: The receiving link of the master end detects and records the arrival time t4 of the third frame message, and then the sending link of the master end generates and sends the fourth frame message carrying the arrival time t4, which specifically includes the following steps:

[0081] Arrival time t4 is the time when the third frame message arrives at the second sequence detection module 11 of the receiving link of the master end;

[0082] Step 6.1, the matched filter module 9 of the receiving link of the master end obtains the best decision point sync_flag through the garden ring position synchronization, and uses the best decision point sync_flag to detect the valid data of the third frame message. After the valid data of the third frame message is detected, each bit of the third frame message is sent to the second sequence detection module 11 of the receiving link of the master end;

[0083] Step 6.2, the second sequence detection module 11 of the receiving link of the master end sets the flag bit demod_flag, and the second sequence detection module 11 of the receiving link of the master end detects the entire data sequence of the frame header of the third frame message through the state machine. When the frame header of the third frame message is detected, the level of the flag bit demod_flag of the second sequence detection module 11 of the receiving link of the master end is raised, and the current timestamp is recorded as the arrival time t4 of the third frame message;

[0084] Step 6.3, if the data judgment module 14 of the receiving link of the master end detects that the frame header, timestamp data check 1 and timestamp data check 2 of the third frame message are all correct, then the arrival time t4 of the third frame message recorded by the second sequence detection module 11 of the receiving link of the master end is valid;

[0085] Step 6.4: The sending link of the master end generates and sends the fourth frame message carrying the arrival time t4.

[0086] Step 7: The receiving link of the slave receives the fourth frame message, and decodes the arrival time t1 carried in the fourth frame message. Finally, the slave calculates the clock deviation according to the recorded arrival times t1, t2, t3, and t4, and finally calibrates the slave clock according to the calculated clock deviation.

[0087] The clock skew is calculated based on the following formula:

[0088] offset=[(t1-t2)+(t4-t3)] / 2 Formula (1)

[0089] In the formula, offset is the clock deviation and / is the division sign.

[0090] Step 8: The master and slave start the 1s counter at the same time, and repeat steps 1-7 with a period of 1s, and calibrate the clock of the slave once a second to ensure time synchronization between the master and slave.

[0091] Among them, when the third frame message carrying the arrival time is generated, the timestamp of the arrival time is attached to the timestamp data of the corresponding message, and the corresponding CRC check 1 (cyclic redundancy check) and CRC check 2 are calculated and attached to the timestamp data check 1 and timestamp data check 2 of the corresponding message respectively.

[0092] The key point of the present invention is how to detect the arrival time of the first message in the molding filter module 4 of the transmission link when detecting the arrival time of t1 and t3. Since the process of the message data passing through the molding filter module 4 can be regarded as the process of convolution of the signal spectrum with the molding filter module 4 spectrum in the frequency domain, and can be regarded as the process of multiplying the signal with the waveform of the molding filter module 4 in the time domain. Therefore, after the data of the original message is bipolarly converted in the serial-to-parallel conversion module 3, 0 becomes 11 and 1 becomes 01, and the sign bits 1 and 0 of the I branch baseband transmission data I_filtered and the Q branch baseband transmission data Q_filtered obtained after multiplication with the molding filter module 4 represent the corresponding 0 and 1 of the data of the original message. Therefore, it is only necessary to detect the sign bit of the I-branch baseband transmission data I_filtered or the Q-branch baseband transmission data Q_filtered after passing through the shaping filter module 4, and to judge the data sequence, so as to judge the time when the frame header of the message arrives. Therefore, when no valid message is sent, the data sent by the transmitter is 0, and the data frame sequence obtained after passing through the shaping filter module 4 is all 1. The first data of the frame header of each valid message is set to 1, and the data frame obtained after passing through the shaping filter module 4 is 0. Therefore, in the step, it is only necessary to judge the position of the first falling edge after the sending link sends the signal at the first sequence detection module 5, and record the timestamp of the current moment to obtain the arrival time.

[0093] In the detection of arrival time t2 and t4 by the matched filter module 9 of the receiving link, the key is how to ensure that the receiving end is correctly synchronized to the data stream of the transmitting end. The present invention uses the garden ring position synchronization method, uses the peak symbol to replace the peak value to calculate the value of the timing error, and adjusts the loop filter according to the timing error, so as to obtain the position of the best decision point sync_flag, and then uses the best decision point sync_flag to judge the signal after passing through the matched filter module 9 of any branch in the same direction or orthogonal direction. When the valid signal of the best decision point sync_flag comes, it can represent that a valid data is detected. Since the received data is serial data, each bit of the obtained data is sent to the second sequence detection module 11, and the data sequence of the entire frame header is detected by the state machine. When the frame header is detected, the level of the flag bit demod_flag of the second sequence detection module 11 is raised, and the timestamp at this time is recorded as the arrival time. Then the data is sent to the subsequent decoding process. If the decoded data detects the frame header and the verification is correct through the data judgment module 14, it can be considered that the correct message has been received. Then the previously recorded timestamp is a valid timestamp. Otherwise, it is considered that the received timestamp is invalid due to a bit error. This way of timestamping can make the sending and receiving timestamps as close to the RF front end as possible. Therefore, the higher the timestamp accuracy, the higher the time synchronization accuracy. In addition, it can reduce the transmission delay and processing delay caused by data processing, as well as the jitter and delay uncertainty introduced by cross-clock, thereby improving the accuracy of the timestamp.

[0094] In wireless time synchronization, factors that affect timestamp accuracy include transmission delay, transmission processing delay, and reception processing delay. Transmission delay is the time required for synchronization information to reach the access layer from the network layer. This delay may be random due to the influence of operating system calls and data transmission queues. Transmission processing delay is the time it takes for the sending node to transmit synchronization information, including the cumulative delay caused by data processing processes such as data packaging, modulation, and shaping filtering. Reception processing delay is the time required for the receiving node to receive the entire synchronization information. The algorithm may be affected, resulting in randomness in this delay.

[0095] The present invention can strictly control the timing and eliminate the transmission delay by adopting the method of recording the timestamp by hardware at the FPGA end; in addition, by making the location of recording the transmission timestamp close to the radio frequency end, the cumulative delay caused by the transmission processing delay and the delay uncertainty caused by processing data across the clock domain can be reduced. Finally, by adopting the sequence detection method at the matched filter end, the time when the timestamp of the receiving end arrives can be judged at the first time, which can reduce the uncertainty delay caused by the algorithm in the receiving process.

[0096] Embodiment 3:

[0097] A method for realizing wireless high-precision time synchronization based on FPGA, comprising the following steps:

[0098] Execute step 1 of Example 2. In this embodiment, the frame header of the first frame message is C3FC, the frame header of the second frame message is F3C0, and the frame headers of the third frame message and the fourth frame message are both F300.

[0099] In this embodiment, the working clocks of the real-time clock module 1, the first sequence detection module 5, the second sequence detection module 11, and the difference calculation module 15 are The frequency is 100MHz, the working clock C of the differential encoding module 2, the serial-to-parallel conversion module 3, the shaping filter module 4, the first intermediate frequency module 6, the second intermediate frequency module 8, the matching filter module 9, the carrier synchronization module 10, the bit synchronization module 12, the data merging module 13, and the data judgment module 14 ′ 10M The frequency is 10MHz;

[0100] Execute step 2 of Example 2, the real-time clock module 1 of the sending link of the master end sets the flag bit data_flag, the master end generates and sends the first frame message, and pulls up the level of the flag bit data_flag of the real-time clock module 1 of the sending link of the master end, and the duration is 180us. At this time, the timestamp number, timestamp data check 1, and timestamp data check 2 in the first frame message are all 0, and the first sequence detection module 5 of the sending link of the master end detects and records the arrival time of the first falling edge of the flag bit data_flag of the real-time clock module 1 of the sending link of the master end after the level is pulled high, and obtains the current timestamp as the arrival time t1 of the first frame message;

[0101] Among them, the frame header of the first frame message becomes FCCF after differential encoding, and then the serial-to-parallel conversion is divided into two paths, IQ. At this time, the frame headers of the I branch and the Q branch are both 1110_1011, and then pass through the shaping filter module 4 respectively, and the sign bits of the frame headers of the I branch baseband transmission data I_filtered and the Q branch baseband transmission data Q_filtered output by the shaping filter module 4 are both 0001_0100. When the valid data of the message does not arrive, 0 is sent, and the sign bit output of the shaping filter module 4 is all 1. In the transmission link, it is only necessary to find the moment when the first falling edge comes during the high level of the flag bit data_flag of the real-time clock module 1 of the transmission link of the master end. Therefore, by beating the sign bit of one of the signals, the falling edge is found, and the current timestamp is recorded as the arrival time t1.

[0102] Execute step 3 of embodiment 2, the real-time clock module 1 of the master end writes the arrival time t1 into the second frame message, delays 2ms, and sends the second frame message;

[0103] Execute step 4 of embodiment 2, detect and record the arrival time t2 of the first frame message from the receiving link of the end; receive the second frame message from the receiving link of the end, and decode the arrival time t1 carried in the second frame message;

[0104] The second sequence detection module 11 at the slave end uses a state machine to detect the data sequence of the entire frame header of the first frame message, and records the arrival time t2 of the first frame message after detecting the complete data sequence of the frame header of the first frame message; the slave end receives the second frame message sent by the master end, and decodes the timestamp data of the arrival time t1 carried in the second frame message through the data judgment module 14 at the slave end.

[0105] Among them, after the matching filter module 9 of the slave end, the second sequence detection module 11 of the receiving link of the slave end detects whether the sign bit of the I branch baseband transmission data I_filtered (or the Q branch baseband transmission data Q_filtered) after passing through the matching filter module 9 is 1111_0001_0100. Since the AD9361 data transmission is serial transmission, the sequence detection method is adopted, in which the front 1111 represents the future temporary valid data, and 0001_0100 represents the frame header of the first frame message. In this embodiment, the second sequence detection module 11 adopts the state machine method, such as Figure 7 As shown, when state s12 is detected, it is considered that the first frame message is received from the end, and the current timestamp is recorded as the arrival time t2, and the data is sent to the subsequent decoding process. If the subsequent data stream passes through the judgment module to determine that the data is valid, it can be considered that the correct data frame is received and the recorded timestamp is valid. Otherwise, it is considered that there is a bit error causing the received timestamp to be invalid. Continue to receive the second frame of data. Since the frame header is different from the first frame, the second frame of data will not be detected after the matched filter module 9, but directly sent to the subsequent demodulation module. If the demodulation is correct, its data frame [79:16] is extracted as the timestamp t1.

[0106] Then, step 5 and step 6 of embodiment 1 are sequentially performed to obtain the arrival time t3 and the arrival time t4;

[0107] Execute step 7 of embodiment 1, send t1, t2, t3, t4 obtained from the slave end to the difference calculation module 15 to calculate the difference and obtain the clock deviation, wherein the entire difference calculation module 15 is implemented by FPGA. Send the clock deviation back to the real-time clock module 1 of the slave end, calibrate the clock of the slave end, and achieve clock synchronization between the master end and the slave end;

[0108] Execute step 8 of embodiment 1, start a 1s counter at the master end and the slave end, repeat steps 1-7 with a period of 1s, and perform clock calibration of the slave end once a second to ensure time synchronization between the master end and the slave end.

[0109] It should be noted that the embodiments described in the present invention are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the described embodiments or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the attached claims.

Claims

1. A device for realizing wireless high-precision time synchronization based on FPGA, comprising a master end and a slave end, characterized in that: Both the master end and the slave end include a transmission link, a reception link, and a radio frequency transceiver (7); The transmission link comprises a real-time clock module (1), a QPSK baseband modulation module, a first sequence detection module (5), and a first intermediate frequency module (6); The real-time clock module (1) generates a message carrying time stamp data, the message carrying time stamp data is modulated by a QPSK base frequency modulation module to obtain I branch base frequency transmission data and Q branch base frequency transmission data, the I branch base frequency transmission data and the Q branch base frequency transmission data are respectively modulated by a first intermediate frequency module (6) to obtain I branch intermediate frequency transmission data and Q branch intermediate frequency transmission data, the I branch intermediate frequency transmission data and the Q branch intermediate frequency transmission data are respectively up-converted by a radio frequency transceiver (7) to obtain an I branch radio frequency transmission signal and a Q branch radio frequency transmission signal, and then respectively transmitted; The first sequence detection module (5) detects and records the arrival time of the I-branch baseband transmission data or the Q-branch baseband transmission data in the transmission link as the arrival time of the message in the transmission link; The receiving link comprises a second intermediate frequency module (8), a matching filter module (9), a QPSK baseband demodulation module, and a second sequence detection module (11); the radio frequency transceiver (7) receives an I-branch radio frequency receiving signal and a Q-branch radio frequency receiving signal and performs down-conversion respectively to obtain an I-branch intermediate frequency receiving signal and a Q-branch intermediate frequency receiving signal; the I-branch intermediate frequency receiving signal and the Q-branch intermediate frequency receiving signal respectively pass through the second intermediate frequency module (8) and the matching filter module (9) in sequence to obtain an I-branch baseband receiving data and a Q-branch baseband receiving data; the I-branch baseband receiving data and the Q-branch baseband receiving data pass through the QPSK baseband demodulation module to obtain a timestamp; The second sequence detection module (11) detects and records the arrival time of the I-branch baseband receiving data or the Q-branch baseband receiving data in the receiving link as the arrival time of the message in the receiving link.

2. The device for realizing wireless high-precision time synchronization based on FPGA according to claim 1, characterized in that: The QPSK baseband modulation module comprises a differential encoding module (2), a serial-to-parallel conversion module (3), and a shaping filter module (4); a message carrying timestamp data passes through the differential encoding module (2), the serial-to-parallel conversion module (3), and the shaping filter module (4) in sequence to obtain I-branch baseband data and Q-branch baseband data.

3. The device for realizing wireless high-precision time synchronization based on FPGA according to claim 2, characterized in that: The QPSK baseband demodulation module comprises a carrier synchronization module (10), a bit synchronization module (12), a data merging module (13), and a data judgment module (14); the I-branch baseband received data and the Q-branch baseband received data are sequentially passed through the carrier synchronization module (10), the bit synchronization module (12), the data merging module (13), and the data judgment module (14) to obtain a timestamp.

4. The device for realizing wireless high-precision time synchronization based on FPGA according to claim 3, characterized in that: The receiving link of the slave end further comprises a difference calculation module (15), and the difference calculation module (15) calculates the delay of the sending link and the receiving link.

5. A method for realizing wireless high-precision time synchronization based on FPGA, using the device for realizing wireless high-precision time synchronization based on FPGA as claimed in claim 4, characterized in that: The following steps are involved: Step 1, setting the format of the message carrying timestamp data generated by the real-time clock module (1) of the master end and the slave end, and setting the first bit of the frame header of the message to 1; Step 2: The sending link of the master end generates and sends the first frame message, and detects and records the arrival time t1 of the first frame message; Step 3: The sending link of the master end generates a second frame message carrying the arrival time t1, and sends the second frame message after the set delay time; Step 4: The receiving link of the slave end detects and records the arrival time t2 of the first frame message; the receiving link of the slave end receives the second frame message, and decodes the arrival time t1 carried in the second frame message; Step 5: The sending link of the slave end generates and sends a third frame message carrying the arrival time t2, and detects and records the arrival time t3 of the third frame message; Step 6: The receiving link of the master end detects and records the arrival time t4 of the third frame message, and then the sending link of the master end generates and sends the fourth frame message carrying the arrival time t4; Step 7: The receiving link of the slave receives the fourth frame message, and decodes the arrival time t1 carried in the fourth frame message. Finally, the slave calculates the clock deviation according to the recorded arrival times t1, t2, t3, and t4, and finally calibrates the slave clock according to the calculated clock deviation. The clock skew is calculated based on the following formula: offset=[(t1-t2)+(t4-t3)] / 2 In the formula, offset is the clock deviation, / is the division sign; Step 8: The master and slave start a 1s counter at the same time, and repeat steps 1-7 with a period of 1s, performing clock calibration on the slave once a second.

6. According to claim 5, a method for realizing wireless high-precision time synchronization based on FPGA, characterized in that: The format of the message in step 1 includes a frame header, a type, a synchronization cycle number, a synchronization message, a synchronization message check, timestamp data, timestamp data check 1, and timestamp data check 2.

7. The method for realizing wireless high-precision time synchronization based on FPGA according to claim 6, characterized in that: The sending link of the master end in step 2 or the sending link of the slave end in step 5 detects the arrival time of the message in the following manner: First, the real-time clock module (1) of the sending link sets the flag bit data_flag, then generates and sends the first frame message, and pulls up the level of the flag bit data_flag; Secondly, the first sequence detection module (5) of the sending link sets the flag bit mod_flag, detects and records the arrival time of the first falling edge after the level data_flag is pulled high, obtains the current timestamp as the arrival time corresponding to the message, and then pulls the level of the flag bit mod_flag of the sending link first sequence detection module (5) high.

8. The method for realizing wireless high-precision time synchronization based on FPGA according to claim 7, characterized in that: The receiving link of the slave end in step 4 and the receiving link of the slave end in step 6 detect and record the arrival time of the message in the following manner: First, the matched filter module (9) of the receiving link obtains the best decision point sync_flag through the garden ring bit synchronization, and uses the best decision point sync_flag to detect the valid data of the message. After the valid data of the message is detected, each bit of the message data is sent to the second sequence detection module (11); Secondly, the second sequence detection module (11) of the receiving link sets a flag bit demod_flag. The second sequence detection module (11) of the receiving link detects the entire data sequence of the frame header of the message through a state machine. When the frame header of the message is detected, the level of the flag bit demod_flag is raised, and the current timestamp is recorded as the arrival time corresponding to the message; Finally, if the data judgment module (14) of the receiving link detects that the frame header, timestamp data check 1 and timestamp data check 2 are all correct, the arrival time recorded by the second sequence detection module (11) of the receiving link is valid.

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