Topological structure identification method, device and equipment

Abstract

The invention relates to a topological structure identification method, device and equipment, and is applied to a target GPU node connected with a management node through a plurality of connectors, and the method comprises the steps: obtaining electric signal combinations corresponding to the plurality of connectors when it is detected that a topological structure between the target GPU node and the management node is switched, each electric signal in the electric signal combination corresponds to a plurality of pins in the corresponding connector; for each connector, determining port information corresponding to the connector based on the first truth table and the electric signal combination corresponding to the connector; based on the port information corresponding to the plurality of connectors, determining a target topology type corresponding to the switched topology structure; and the target configuration file corresponding to the target topology type is obtained, and the target configuration file is loaded in the PCIE Switch in the target GPU node, so that the influence of topological structure switching on task execution on the server and the maintenance cost are reduced.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a topology structure identification method, device and equipment. Background Art

[0002] In the field of server technology, with the development of cloud computing and big data technology, the demand for server computing resources is increasing. In order to adapt to a variety of big data application scenarios, a GPU (Graphics Processing Unit) can be connected to the server to improve the overall computing resources of the server. In the specific implementation, after the PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) resource expansion is performed in the GPU node through the PCIE Switch, the interconnection between the management node (i.e., the server) and multiple GPUs is performed.

[0003] To meet the needs of different application scenarios, different topologies can be used to manage the interconnection between the node and the GPU node. In implementation, since the configuration files corresponding to the PCIE Switch in the GPU node are different under different topologies, the configuration files of the PCIE Switch need to be modified after the topology is switched.

[0004] In the related art, after the topology is switched, it is necessary to manually determine the topology based on the current cable connection status, obtain the configuration file corresponding to the topology result, and then re-burn the configuration file of the PCIe Switch. Since re-burning the configuration file takes a long time, it will have a great impact on the execution of tasks on the server and increase the maintenance cost of the server. Summary of the invention

[0005] The present invention provides a topology structure identification method, device and equipment, which are used to solve the problem in the related art that the configuration file burning time is long after the topology switching, resulting in the influence of server task execution and high maintenance cost.

[0006] In a first aspect, an embodiment of the present application provides a topology structure identification method, which is applied to a target graphics processor GPU node, wherein the target GPU node is connected to a management node via multiple connectors, and the method includes:

[0007] When a topology switch between the target GPU node and the management node is detected, electrical signal combinations corresponding to the plurality of connectors are obtained, wherein each electrical signal in the electrical signal combination corresponds to a plurality of pins in the corresponding connector;

[0008] For each connector, based on a first truth table and an electrical signal combination corresponding to the connector, determine the port information corresponding to the connector; the first truth table stores: a correspondence between different electrical signal combinations and port information;

[0009] Based on the port information respectively corresponding to the above-mentioned multiple connectors, determine the target topology type corresponding to the switched topology structure;

[0010] A target configuration file corresponding to the target topology type is obtained, and the target configuration file is loaded into a high-speed serial computer expansion bus standard interface expansion switch chip PCIE Switch in the target GPU node.

[0011] The above method automatically identifies the connection topology between the management node and the target GPU node based on the electrical signal combination of the connector at the target GPU node, and notifies the PCIe Switch to automatically load the corresponding configuration file, thereby reducing the server maintenance cost, improving work efficiency, and enhancing adaptability.

[0012] In a possible implementation, the electrical signal combination includes: a first electrical signal corresponding to a pin associated with the target GPU node, and a second electrical signal corresponding to a pin associated with the management node; the first truth table stores: a first electrical signal corresponding to each port type, and a second electrical signal corresponding to each port information under each port type;

[0013] The determining of the port information corresponding to the connector based on the first truth table and the electrical signal combination corresponding to the connector includes:

[0014] Matching the first electrical signal corresponding to the connector with the first electrical signals corresponding to each port type in the first truth table to obtain a target port type corresponding to the connector;

[0015] The second electrical signal corresponding to the connector is matched with each second electrical signal corresponding to the target port type in the first truth table to obtain port information corresponding to the connector.

[0016] The above method improves the query efficiency of port signals by querying the target port type corresponding to the connector based on the first electrical signal corresponding to the connector and the target GPU node, and then querying the port information from each second electrical signal corresponding to the target port type in the first truth table based on the second electrical signal corresponding to the connector and the management node.

[0017] In a possible implementation, the target GPU includes a plurality of PCIE switches, and the management node includes a plurality of central processing units (CPUs);

[0018] Based on the port information corresponding to the above multiple connectors, a target topology type corresponding to the switched topology structure is determined, including:

[0019] For each PCIE Switch, based on the port information of each connector corresponding to the PCIE Switch, the connection information of the PCIE Switch is determined; the connection information includes: the port identifier and the port number of the CPU connected to the PCIE Switch;

[0020] Determine a target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table;

[0021] The second truth table records the corresponding relationship between each topology type and the connection information of the PCIE Switch.

[0022] The above method determines the connection information of the PCIE Switch based on the port information of each connector corresponding to the PCIE Switch, and then determines the target topology type based on the connection information of each PCIE Switch, thereby ensuring the accuracy of topology type determination.

[0023] In a possible implementation manner, the plurality of PCIE switches are a first PCIE Switch and a second PCIE Switch;

[0024] The above-mentioned determination of the target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table includes:

[0025] If it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are connected to different CPUs respectively, the first PCIE Switch is connected to a port of a CPU, and the second PCIE Switch is connected to a port of a CPU, then it is determined that the target topology type is a balanced mode;

[0026] If, based on the connection information, it is determined that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to two ports of one CPU, and the second PCIE Switch is connected to two ports of one CPU, then it is determined that the target topology type is a dual uplink mode.

[0027] The above method provides a specific balancing mode and a method for determining the corresponding topology type of the dual uplink mode, thereby improving the accuracy of topology type determination.

[0028] In a possible implementation manner, the plurality of PCIE switches are a first PCIE Switch and a second PCIE Switch;

[0029] The above-mentioned determination of the target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table includes:

[0030] If it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different ports of the same CPU, then the target topology type is determined to be a general mode;

[0031] If it is determined based on the connection information that the first PCIE Switch is connected to a port of a CPU, and the first PCIE Switch and the second PCIE Switch are connected to each other, then it is determined that the target topology type is a serial mode.

[0032] The above method provides a specific general mode and a method for determining the topology type corresponding to the serial mode, thereby improving the accuracy of topology type determination.

[0033] In a possible implementation, the target GPU node further includes: a complex programmable control logic device CPLD and a baseboard management controller BMC, the BMC is connected to the CPLD and the PCIE Switch respectively, and the target configuration file corresponding to the target topology type is obtained, and the target configuration file is loaded in the PCIE Switch in the GPU node, including:

[0034] The BMC reads the target topology type from the CPLD, and searches for a target configuration file corresponding to the target topology type from configuration files corresponding to each stored topology type;

[0035] The BMC sends the queried target configuration file to the PCIE Switch;

[0036] The PCIE Switch receives and loads the target configuration file.

[0037] The above method facilitates subsequent direct query of the configuration file corresponding to the target topology type in the configuration files corresponding to each topology type stored in the BMC, improves the efficiency of obtaining the configuration file, and realizes automatic loading of the configuration file.

[0038] In a possible implementation manner, the BMC is connected to the management node, and after determining the target topology type corresponding to the switched topology structure based on the port information corresponding to the multiple connectors, the method further includes:

[0039] The BMC sends the target topology type to the management node, so that after receiving the target topology type, the management node controls the server corresponding to the management node to start.

[0040] In the above method, the BMC sends the above target topology type to the above management node, thereby ensuring synchronization of target topology information between the management node and the target GPU node.

[0041] In a second aspect, an embodiment of the present application provides a topology structure identification device, which is applied to a target graphics processor GPU node, wherein the target GPU node is connected to a management node via multiple connectors, and the device comprises:

[0042] An acquisition module, configured to acquire electrical signal combinations corresponding to the plurality of connectors respectively when detecting that a topology switch occurs between the target GPU node and the management node, wherein each electrical signal in the electrical signal combination corresponds to a plurality of pins in the corresponding connector respectively;

[0043] A first determination module is used to determine, for each connector, port information corresponding to the connector based on a first truth table and an electrical signal combination corresponding to the connector; the first truth table stores: a correspondence between different electrical signal combinations and ports;

[0044] A second determination module, configured to determine a target topology type corresponding to the switched topology structure based on the port information corresponding to the plurality of connectors;

[0045] The loading module is used to obtain a target configuration file corresponding to the target topology type and load the target configuration file in the PCIE Switch in the target GPU node.

[0046] In a possible implementation, the electrical signal combination includes: a first electrical signal corresponding to a pin associated with the target GPU node, and a second electrical signal corresponding to a pin associated with the management node; the first truth table stores: a first electrical signal corresponding to each port type, and a second electrical signal corresponding to each port information under each port type;

[0047] The first determination module is specifically used for:

[0048] Matching the first electrical signal corresponding to the connector with the first electrical signals corresponding to each port type in the first truth table to obtain a target port type corresponding to the connector;

[0049] The second electrical signal corresponding to the connector is matched with each second electrical signal corresponding to the target port type in the first truth table to obtain port information corresponding to the connector.

[0050] In a possible implementation, the target GPU includes a plurality of PCIE switches, and the management node includes a plurality of CPUs;

[0051] The second determination module is specifically used for:

[0052] For each PCIE Switch, based on the port information of each connector corresponding to the PCIE Switch, the connection information of the PCIE Switch is determined; the connection information includes: the port identifier and the port number of the CPU connected to the PCIE Switch;

[0053] Determine a target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table;

[0054] The second truth table records the corresponding relationship between each topology type and the connection information of the PCIE Switch.

[0055] In a possible implementation manner, the plurality of PCIE switches are a first PCIE Switch and a second PCIE Switch;

[0056] The second determination module is specifically configured to: if it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to a port of a CPU, and the second PCIE Switch is connected to a port of a CPU, then determine that the target topology type is a balanced mode;

[0057] If, based on the connection information, it is determined that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to two ports of one CPU, and the second PCIE Switch is connected to two ports of one CPU, then it is determined that the target topology type is a dual uplink mode.

[0058] In a possible implementation manner, the plurality of PCIE switches are a first PCIE Switch and a second PCIE Switch;

[0059] The second determination module is specifically configured to: if it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different ports of the same CPU, then determine that the target topology type is a general mode;

[0060] If it is determined based on the connection information that the first PCIE Switch is connected to a port of a CPU, and the first PCIE Switch and the second PCIE Switch are connected to each other, then it is determined that the target topology type is a serial mode.

[0061] In a possible implementation, the target GPU node further includes: a complex programmable control logic device CPLD and a baseboard management controller BMC, wherein the BMC is connected to the CPLD and the PCIE Switch respectively; and the loading module is specifically used to:

[0062] The BMC reads the target topology type from the CPLD, and searches for a target configuration file corresponding to the target topology type from configuration files corresponding to each stored topology type;

[0063] The BMC sends the queried target configuration file to the PCIE Switch;

[0064] The PCIE Switch receives and loads the target configuration file.

[0065] In a possible implementation manner, the BMC is connected to the management node, and the second determining module is further configured to:

[0066] The BMC sends the target topology type to the management node, so that after receiving the target topology type, the management node controls the server corresponding to the management node to start.

[0067] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in the topology structure identification method when executing the computer program.

[0068] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-mentioned topological structure identification method of the present application.

[0069] In the fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which is stored in a computer-readable storage medium; when the processor of a memory access device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the memory access device executes the steps in the above-mentioned topology structure identification method of the present application.

[0070] For each of the above-mentioned second to fifth aspects and the technical effects that may be achieved by each of the above-mentioned aspects, please refer to the above-mentioned description of the technical effects that can be achieved by the first aspect or various possible schemes in the first aspect, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0072] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0073] Figure 2 A schematic diagram of a topology structure identification method provided in an embodiment of the present application;

[0074] Figure 3 A schematic diagram of a possible general mode topology provided in an embodiment of the present application;

[0075] Figure 4 A schematic diagram of a possible serial mode topology provided in an embodiment of the present application;

[0076] Figure 5 A schematic diagram of a possible balancing mode topology provided in an embodiment of the present application;

[0077] Figure 6 A schematic diagram of a possible dual uplink mode topology provided in an embodiment of the present application;

[0078] Figure 7 A schematic diagram of an example of topological structure identification provided in an embodiment of the present application;

[0079] Figure 8 A schematic diagram of a topology structure identification device provided in an embodiment of the present application;

[0080] Fig. 9 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be arbitrarily combined with each other. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0082] The terms "first" and "second" in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any of their variations are intended to cover non-exclusive protection. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices. "Multiple" in the present application can mean at least two, for example, two, three or more, and the embodiments of the present application are not limited.

[0083] The following is a description of exemplary embodiments of the present application in conjunction with the accompanying drawings, including various details of the embodiments of the present application to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present application. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description. It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, which should be considered as exemplary, and their purpose is only to illustrate the feasibility of the implementation of the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0084] In the technical solution of this application, the acquisition, transmission, storage, and use of data are in compliance with the requirements of relevant national laws and regulations.

[0085] In order to facilitate those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the following is a brief description of the professional terms involved:

[0086] (1) GPU (Graphics Processing Unit): A coprocessor used to process images and graphics operations, widely used in personal computers, workstations and some mobile devices (such as smartphones, tablets, etc.).

[0087] (2) CPLD (Complex Programmable Logic Device): implements specific logic and completes monitoring and control functions.

[0088] (3) BMC (Baseboard Management Controller): A device used for remote out-of-band management.

[0089] (4) PCIE Switch: PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) interface expansion switch chip.

[0090] (5) MCIO (Multi-Chip Interconnect): A connector interface form defined by a standard.

[0091] (6)I2C (Inter-Integrated Circuit, bidirectional two-wire synchronous serial) bus: a serial communication bus.

[0092] In the field of server technology, with the development of cloud computing and big data technology, the demand for server computing resources is increasing. In order to adapt to a variety of big data application scenarios, GPUs can be connected to servers to improve the overall computing resources of the server. In specific implementations, the separate node where the GPU is located is called a GPU node. After the PCIE resource is expanded through PCIE switch in the GPU node, the interconnection between the management node (i.e., server) and multiple GPUs is performed.

[0093] To meet the needs of different application scenarios, different topologies can be used to interconnect the management node and the GPU node. Since different topologies correspond to different interconnection relationships, the cable connection method between the management node and the GPU node needs to be changed when switching the topology. In addition, the port configurations in the PCIE Switch configuration files corresponding to different topologies are different. Therefore, after the topology is switched, the PCIE Switch configuration file cannot be fully reused and needs to be modified.

[0094] In the related art, after the topology is switched, it is necessary to manually determine the topology based on the current cable connection status, obtain the configuration file corresponding to the topology result, and then re-burn the configuration file of the PCIE Switch. Since it takes a long time to re-burn the configuration file, it will have a great impact on the execution of tasks on the server and increase the maintenance cost of the server.

[0095] To overcome the above problems, the embodiments of the present application provide a topology structure identification method, device and equipment, which can automatically identify the topology structure type after the switch when the topology result switches, and determine the corresponding configuration file based on the identified topology structure type, and load it into the PCIE Switch, thereby improving the loading efficiency of the configuration file, thereby reducing the impact of the topology structure switching on the task execution on the server and the maintenance cost.

[0096] Before introducing the topology structure identification method provided in the embodiment of the present application, the application scenarios to which the method is applicable are first introduced.

[0097] like Figure 1 As shown, this scenario specifically includes a management node and a GPU node, wherein the management node is located in the server, and the number of GPU nodes is not limited, and only one is used as an example for illustration.

[0098] In a specific implementation, the management node and the GPU node are interconnected via a PCIE link through a connector. Optionally, the connector may be a MCIO connector.

[0099] In the management node, there are BMC and multiple CPUs, and each CPU includes multiple ports, wherein each CPU port corresponds to multiple MCIO connectors. Figure 1 As shown, each CPU port corresponds to two MCIOs, for example, the PE1 port of CPU1 corresponds to PE1 A MCIO and PE1 C MCIO, and the PE2 port of CPU1 corresponds to PE2 A MCIO and PE2 C MCIO.

[0100] In the GPU node, there are BMC, PLCD and multiple PCIE switches, such as Figure 1As shown, the GPU node includes two PCIE switches, namely SW1 and SW2. Among them, every two MCIOs correspond to a PCIE Switch port, and each MCIO includes multiple pins, which are used to interconnect with the CPLD. Each pin corresponds to an electrical signal (i.e., MCIO ID signal). For example, it can be set that each MCIO includes 6 MCIO ID signals. The BMC in the GPU node is interconnected with the CPLD, PCIE Switch, and management node BMC to complete I2C communication.

[0101] The present application is further described in detail below in conjunction with the accompanying drawings. Figure 2 As shown, it is a flow chart of a topology structure identification method provided in an embodiment of the present application, which is applied to a target GPU node, the target GPU node is connected to a management node through multiple connectors, and the management node includes multiple central processing units CPU, and its specific implementation process is as follows:

[0102] Step S201, when it is detected that the topology structure between the target GPU node and the management node is switched, the electrical signal combinations corresponding to the multiple connectors are obtained;

[0103] Wherein, each electrical signal in the above electrical signal combination corresponds to a plurality of pins in the corresponding connector;

[0104] In some embodiments, the steps described in steps S201-S203 in the present application are applied to the CPLD in the target GPU node. Optionally, after the server completes the topology switching between the target CPU node and the management node, a switching indication can be sent to the CPLD in the GPU node to trigger the CPLD to execute subsequent topology identification methods.

[0105] In the embodiment of the present application, the connector may be an MCIO connector, and the number of the connectors is not limited in the embodiment of the present application. Optionally, the target GPU node includes multiple PCIE switches, and the ports of each PCIE switch correspond to a preset number of connectors, wherein the multiple PCIE switches may be a first PCIE switch and a second PCIE switch, and the preset number may be 2.

[0106] In the embodiment of the present application, each connector includes a plurality of pins, and each pin corresponds to an electrical signal. Optionally, the plurality of pins may include a pin associated with a GPU node and a pin associated with a management node, which is used to characterize the configuration corresponding to the corresponding node based on the electrical signal. In this case, the electrical signal combination includes: a first electrical signal corresponding to the pin associated with the target GPU node, and a second electrical signal corresponding to the pin associated with the management node.

[0107] Optionally, each connector may include 6 pins, and among the 6 pins, 2 pins are pins associated with the GPU node, and the remaining 4 pins are pins associated with the management node. For example, assuming that the connector includes 6 pins ID0-ID5, ID0 and ID1 may be set as pins associated with the GPU node, and ID2-ID5 may be set as pins associated with the management node.

[0108] It should be noted that the association relationship corresponding to each pin in the embodiment of the present application, that is, the correspondence between each pin associated with a GPU node or a management node, and the correspondence between the electrical signal combination corresponding to each pin and the port information, needs to be configured in advance based on demand.

[0109] In the embodiment of the present application, the value of each electrical signal includes 1 and 0, which are used to represent a high level and a low level, respectively.

[0110] Step S202, for each connector, based on the first truth table and the electrical signal combination corresponding to the connector, determining the port information corresponding to the connector;

[0111] The first truth table stores: the corresponding relationship between different electrical signal combinations and port information;

[0112] In an embodiment of the present application, a correspondence between different electrical signal combinations and port information is pre-set, that is, a first truth table. After the first truth table is set, when each topology structure between the target GPU node and the management node is switched, a cable connection between the target GPU node and the management node can be performed based on the first truth table and the records in the subsequent second truth table. After the switch is completed, the GPU node can automatically identify the type of topology after the switch based on the truth table.

[0113] In a possible implementation manner, the first truth table stores: a first electrical signal corresponding to each port type, and a second electrical signal corresponding to each port information under each port type;

[0114] Optionally, the port types may include two types: the first type is that the connector is connected to the CPU in the management node, and the second type is that the connector is not connected to the CPU of the management node, that is, it indicates that the PCIE Switches in the target GPU are connected to each other.

[0115] The determining of the port information corresponding to the connector based on the first truth table and the electrical signal combination corresponding to the connector includes:

[0116] Matching the first electrical signal corresponding to the connector with the first electrical signals corresponding to each port type in the first truth table to obtain a target port type corresponding to the connector;

[0117] The second electrical signal corresponding to the connector is matched with each second electrical signal corresponding to the target port type in the first truth table to obtain port information corresponding to the connector.

[0118] In an embodiment of the present application, the above-mentioned port information includes: a CPU identifier corresponding to the connector and a port identifier of the CPU; the following table is an example of a possible first truth table. The following is combined with Table 1 to illustrate the process of determining the above-mentioned port information with a specific example. In this example, the management node includes 2 CPUs, namely CPU1 and CPU2, each CPU corresponds to a plurality of 2 connectors, and each connector includes 6 electrical signals, namely ID[5:0].

[0119] In this example, it is assumed that the electrical signal combination corresponding to a connector is 100001, that is, it corresponds to ID5-ID0 in sequence. When determining the port information corresponding to the connector, firstly, the corresponding first electrical signal, that is, ID1-ID0:01, is matched with the first electrical signal corresponding to each port type in the first truth table, so that it can be determined that the connector is connected to the CPU port; then the corresponding second electrical signal, that is, ID5-ID2:1000, is matched with the first electrical signal corresponding to each CPU port in the first truth table, so that the port information corresponding to the connector can be obtained as the PE3 port of CPU1.

[0120] Table 1 First truth table

[0121]

[0122] Step S203, determining a target topology type corresponding to the switched topology structure based on the port information corresponding to the plurality of connectors;

[0123] In a possible implementation, the target GPU includes a plurality of PCIE switches, and the management node includes a plurality of CPUs;

[0124] Based on the port information corresponding to the above multiple connectors, a target topology type corresponding to the switched topology structure is determined, including:

[0125] For each PCIE Switch, based on the port information of each connector corresponding to the PCIE Switch, the connection information of the PCIE Switch is determined; the connection information includes: the port identifier and the port number of the CPU connected to the PCIE Switch;

[0126] Determine a target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table;

[0127] The second truth table records the corresponding relationship between each topology type and the connection information of the PCIE Switch.

[0128] In the embodiment of the present application, the above-mentioned multiple PCIE Switches are a first PCIE Switch and a second PCIE Switch, and each PCIE Switch corresponds to two connectors. For any PCIE Switch, based on the port information of the two connectors corresponding to the PCIE Switch, it can be determined how many CPUs the PCIE Switch is connected to, which CPU ports are specifically connected, and whether there is an interconnection between the first PCIE Switch and the second PCIE Switch; then, matching is performed based on the second truth table and the connection information of the PCIE switch to achieve identification of the target topology type.

[0129] In the embodiment of the present application, according to the connection information corresponding to the first PCIE Switch and the second PCIE Switch, that is, which CPU ports the PCIE resources of the two PCIE Switches come from or come from different PCIE Switches, the topology types can be divided into the following four types: general mode, series mode, balanced mode and dual uplink mode. Figure 4-7 , several topology types are described.

[0130] like Figure 4 In the common mode, the PCIE resources of the first PCIE Switch and the second PCIE Switch are derived from the same CPU, that is, the ports of the two PCIE Switches are respectively connected to different ports of the same CPU.

[0131] like Figure 5 As shown, in the case-case mode, the PCIE resources of the first PCIE Switch and the second PCIE Switch are derived from the CPU and the PCIE Switch, that is, the two PCIE Switches are connected in series, and a port of one PCIE Switch is connected to a port of the CPU.

[0132] like Figure 6 As shown, in the Balance Mode, the PCIE resources of the first PCIE Switch and the second PCIE Switch are derived from two CPUs, that is, the ports of the two PCIE Switches are connected to different CPUs respectively, and each PCIE switch is only connected to one port of the CPU;

[0133] like Figure 7 As shown, dual uplink mode: based on the topological connection in the balanced mode, each PCIE Switch has two uplink ports connected to the CPU of the management node, that is, the ports of the two PCIE Switches are connected to different CPUs respectively, and each PCIE Switch is only connected to two ports of the CPU.

[0134] Table 2 below is an example of a possible second truth table, which is determined based on the topological structures corresponding to the above-mentioned different topological types.

[0135] Table 2 Second truth table

[0136]

[0137] It should be noted that the above-mentioned CPU1 and CPU2 are only examples of two different CPUs and do not represent a specific CPU, and PEm and PEn are only examples of two different CPU ports and do not represent a specific CPU port.

[0138] In a possible implementation manner, the above-mentioned determining the target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table includes:

[0139] If it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different ports of the same CPU, then the target topology type is determined to be a general mode (eg Figure 3 shown);

[0140] If it is determined based on the connection information that the first PCIE Switch is connected to a port of a CPU, and the first PCIE Switch is connected to the second PCIE Switch, then the target topology type is determined to be a serial mode (e.g. Figure 4 shown).

[0141] If, based on the connection information, it is determined that the first PCIE Switch and the second PCIE Switch are connected to different CPUs respectively, the first PCIE Switch is connected to a port of a CPU, and the second PCIE Switch is connected to a port of a CPU, then the target topology type is determined to be a balanced mode (e.g. Figure 5 shown);

[0142] If, based on the connection information, it is determined that the first PCIE Switch and the second PCIE Switch are connected to different CPUs respectively, the first PCIE Switch is connected to two ports of one CPU, and the second PCIE Switch is connected to two ports of one CPU, then it is determined that the target topology type is a dual uplink mode (e.g. Figure 6 shown).

[0143] In conjunction with Table 2, the process of determining the target topology type is described below with a specific example. In this example, the management node includes two CPUs, namely CPU1 and CPU2, each CPU corresponds to a plurality of two connectors, and each connector includes six electrical signals, namely ID[5:0]. The target GPU node includes two PCIE Switches, namely a first PCIE Switch and a second PCIE Switch, and each PCIE Switch corresponds to two connectors.

[0144] In this example, assuming that the electrical signal combinations of the two connectors corresponding to the first PCIE Switch are: 000001 and 001001 (corresponding to ID5-ID0 in sequence), it can be determined that the first PCIE Switch is connected to the PE1 port of CPU1; the electrical signal combinations of the two connectors corresponding to the second PCIE switch are: 100001 and 101001 (corresponding to ID5-ID0 in sequence), it can be determined that the first PCIE Switch is connected to the PE3 port of CPU1, that is, the first PCIE Switch and the second PCIE Switch are respectively connected to different ports (PE1 and PE3) of the same CPU, and the target topology type is determined to be the general mode.

[0145] Step S204, obtaining a target configuration file corresponding to the target topology type, and loading the target configuration file into the PCIESwitch in the target GPU node.

[0146] In a possible implementation, the target GPU node further includes: a complex programmable control logic device CPLD and a baseboard management controller BMC, the BMC is connected to the CPLD and the PCIE Switch respectively, and the target configuration file corresponding to the target topology type is obtained, and the target configuration file is loaded in the PCIE Switch in the GPU node, including:

[0147] The BMC reads the target topology type from the CPLD, and searches for a target configuration file corresponding to the target topology type from configuration files corresponding to each stored topology type;

[0148] The BMC sends the queried target configuration file to the PCIE Switch;

[0149] The PCIE Switch receives and loads the target configuration file.

[0150] In the present application embodiment, Figure 1 The target GPU node includes PCLD, BMC and PCIE Switch (i.e. Figure 1 SW1 and SW2 in the BMC), wherein the BMC is connected to the PCLD and each PCIE Switch respectively through an I2C link. Optionally, the above steps S201-204 are implemented by the CPLD. After the CPLD identifies the target topology type based on the electrical signal of the connector, the target topology type can be stored in a designated area; the BMC reads the target topology type from the designated area of ​​the PCLD through the I2C bus, and queries the target configuration file corresponding to the target topology type from the configuration files corresponding to each stored topology type, and sends the queried target configuration file to the above PCIE Switch; the PCIE Switch performs a loading operation after receiving the target configuration file.

[0151] In a possible implementation manner, the BMC is connected to the management node, and after determining the target topology type corresponding to the switched topology structure based on the port information corresponding to the multiple connectors, the method further includes:

[0152] The BMC sends the target topology type to the management node, so that after receiving the target topology type, the management node controls the server corresponding to the management node to start (ie, boot up).

[0153] In the present application embodiment, Figure 1The BMC in the management node and the BMC in the target GPU node are previously connected to the BMC in the management node via an I2C bus. Optionally, after the BMC in the target GPU node obtains the target topology type, the target topology type can be sent to the BMC of the management node via the I2C bus to achieve synchronization of the target topology type.

[0154] The above method provides a topology automatic identification method suitable for GPU BOX servers, which can solve the problem of server task execution being affected and high maintenance costs caused by switching the connection topology between the CPU and PCIE Switch. This application uses CPLD to identify the connection topology between the management node and the target GPU node based on the electrical signal combination of the connector, notifies the management node and PCIE Switch before the server is turned on, and loads the corresponding PCIE Switch configuration file, which reduces the server maintenance cost, improves work efficiency, and enhances adaptability.

[0155] In the embodiment of the present application, after the server completes the topology switch between the target GPU node and the management node, the topology update can also be completed by manually changing the DIP switch. After the DIP switch is updated, the target GPU node automatically identifies the target topology type after the switch based on the value of the DIP switch, and notifies the PCIE Switch of the target topology type through the BMC, and the PCIE Switch loads the corresponding configuration file according to the target topology type.

[0156] The specific process of the target GPU node automatically identifying the target topology type after switching based on the value of the DIP switch is described in the above steps S202-204, which will not be repeated here.

[0157] The following combination Figure 7 , the above topology structure identification process is described in detail with a specific example, and the process specifically includes the following steps:

[0158] Step S701, when it is detected that the topology structure between the target GPU node and the management node is switched, the electrical signal combinations corresponding to the multiple connectors are obtained;

[0159] Step S702: for each connector, matching the first electrical signal corresponding to the connector with the first electrical signal corresponding to each port type in the first truth table to obtain a target port type corresponding to the connector;

[0160] The electrical signal combination includes: a first electrical signal corresponding to a pin associated with a target GPU node, and a second electrical signal corresponding to a pin associated with a management node; the first truth table stores: a first electrical signal corresponding to each port type, and a second electrical signal corresponding to each port information under each port type;

[0161] Step S703, matching the second electrical signal corresponding to the connector with each second electrical signal corresponding to the target port type in the first truth table to obtain port information corresponding to the connector;

[0162] Step S704: for each PCIE Switch, determining the connection information of the PCIE Switch based on the port information of each connector corresponding to the PCIE Switch;

[0163] The connection information includes: the port ID and port number of the CPU connected to the PCIE Switch;

[0164] Step S705, determining a target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table;

[0165] The second truth table records: the corresponding relationship between each topology type and the connection information of the PCIE Switch.

[0166] Step S706, sending the target topology type to the management node, so that the management node controls the server corresponding to the management node to start up;

[0167] Step S707, searching for a target configuration file corresponding to the target topology type from the configuration files corresponding to the stored topology types;

[0168] Step S708, loading the target configuration file into the PCIE Switch in the target GPU node.

[0169] Based on the same inventive concept, the present application also provides a topological structure identification device 800, see Figure 8 , applied to a target GPU node, the target GPU node is connected to a management node via a plurality of connectors, the device comprises:

[0170] The acquisition module 801 is used to acquire the electrical signal combinations corresponding to the multiple connectors respectively when detecting that the topology structure between the target GPU node and the management node is switched, wherein each electrical signal in the electrical signal combination corresponds to a plurality of pins in the corresponding connector respectively;

[0171] A first determination module 802 is used to determine, for each connector, port information corresponding to the connector based on a first truth table and an electrical signal combination corresponding to the connector; the first truth table stores: a correspondence between different electrical signal combinations and ports;

[0172] A second determination module 803, configured to determine a target topology type corresponding to the switched topology structure based on the port information corresponding to the plurality of connectors;

[0173] The loading module 804 is used to obtain a target configuration file corresponding to the target topology type, and load the target configuration file in a PCIE Switch in the target GPU node.

[0174] In a possible implementation, the electrical signal combination includes: a first electrical signal corresponding to a pin associated with the target GPU node, and a second electrical signal corresponding to a pin associated with the management node; the first truth table stores: a first electrical signal corresponding to each port type, and a second electrical signal corresponding to each port information under each port type;

[0175] The first determining module 802 is specifically configured to:

[0176] Matching the first electrical signal corresponding to the connector with the first electrical signals corresponding to each port type in the first truth table to obtain a target port type corresponding to the connector;

[0177] The second electrical signal corresponding to the connector is matched with each second electrical signal corresponding to the target port type in the first truth table to obtain port information corresponding to the connector.

[0178] In a possible implementation, the target GPU includes a plurality of PCIE switches, and the management node includes a plurality of CPUs;

[0179] The second determining module 803 is specifically used for:

[0180] For each PCIE Switch, based on the port information of each connector corresponding to the PCIE Switch, the connection information of the PCIE Switch is determined; the connection information includes: the port identifier and the port number of the CPU connected to the PCIE Switch;

[0181] Determine a target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table;

[0182] The second truth table records the corresponding relationship between each topology type and the connection information of the PCIE Switch.

[0183] In a possible implementation manner, the plurality of PCIE switches are a first PCIE Switch and a second PCIE Switch;

[0184] The second determination module 803 is specifically used to: if it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to a port of a CPU, and the second PCIE Switch is connected to a port of a CPU, then determine that the target topology type is a balanced mode;

[0185] If, based on the connection information, it is determined that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to two ports of one CPU, and the second PCIE Switch is connected to two ports of one CPU, then it is determined that the target topology type is a dual uplink mode.

[0186] In a possible implementation manner, the plurality of PCIE switches are a first PCIE Switch and a second PCIE Switch;

[0187] The second determination module 803 is specifically configured to: if it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different ports of the same CPU, then determine that the target topology type is a general mode;

[0188] If it is determined based on the connection information that the first PCIE Switch is connected to a port of a CPU, and the first PCIE Switch and the second PCIE Switch are connected to each other, then it is determined that the target topology type is a serial mode.

[0189] In a possible implementation, the target GPU node further includes: a complex programmable control logic device CPLD and a baseboard management controller BMC, wherein the BMC is connected to the CPLD and the PCIE Switch respectively; and the loading module 804 is specifically used to:

[0190] The BMC receives the target topology type sent by the CPLD, and searches for a target configuration file corresponding to the target topology type from configuration files corresponding to each stored topology type;

[0191] The BMC sends the queried target configuration file to the PCIE Switch;

[0192] The PCIE Switch receives and loads the target configuration file.

[0193] In a possible implementation manner, the BMC is connected to the management node, and the second determining module 803 is further configured to:

[0194] The BMC sends the target topology type to the management node, so that after receiving the target topology type, the management node controls the server corresponding to the management node to start.

[0195] Based on the same inventive concept, an electronic device is also provided in the embodiment of the present application, and the electronic device can realize the function of the aforementioned topological structure identification device, referring to Fig. 9 , the electronic device comprises:

[0196] At least one processor 901, and a memory 902 connected to the at least one processor 901. The specific connection medium between the processor 901 and the memory 902 is not limited in the embodiment of the present application. Fig. 9 In the example, the processor 901 and the memory 902 are connected via a bus 900. Fig. 9 The bus 900 is represented by a bold line, and the connection between other components is only for schematic illustration and is not intended to be limiting. The bus 900 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. Alternatively, the processor 901 can also be called a controller, and there is no limitation on the name.

[0197] In the embodiment of the present application, the memory 902 stores instructions that can be executed by at least one processor 901. The at least one processor 901 can execute the topology structure identification method discussed above by executing the instructions stored in the memory 902. The processor 901 can implement Figure 8 The functions of each module in the device shown.

[0198] Among them, processor 901 is the control center of the device, and can use various interfaces and lines to connect various parts of the entire control device. By running or executing instructions stored in memory 902 and calling data stored in memory 902, various functions of the device and processing data, the device can be monitored as a whole.

[0199] In one possible design, the processor 901 may include one or more processing units, and the processor 901 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor 901. In some embodiments, the processor 901 and the memory 902 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on separate chips.

[0200] Processor 901 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the topological structure identification method disclosed in the embodiments of the present application can be directly embodied as a hardware processor to execute, or the hardware and software modules in the processor can be combined and executed.

[0201] The memory 902 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 902 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. The memory 902 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 902 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0202] By designing and programming the processor 901, the code corresponding to the application anomaly detection method described in the above embodiment can be fixed into the chip, so that the chip can execute the code when running. Figure 2The steps of the topology structure identification method of the embodiment shown are as follows: How to design and program the processor 901 is a technology well known to those skilled in the art and will not be described in detail here.

[0203] An embodiment of the present application also provides a computer-readable storage medium that stores computer-executable instructions required to execute the above-mentioned processor, which includes a program required to execute the above-mentioned processor.

[0204] In some possible implementations, various aspects of the topology structure identification method provided in the present application may also be implemented in the form of a program product, which includes a program code. When the above-mentioned program product is run on an electronic device, the above-mentioned program code is used to enable the above-mentioned electronic device to execute the steps of the topology structure identification method according to various exemplary implementations of the present application described above in this specification.

[0205] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0206] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (apparatus), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0207] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0208] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0209] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0210] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for identifying a topological structure, characterized in that: Applied to a target graphics processing unit (GPU) node, the target GPU node is connected to a management node via a plurality of connectors, the method comprising: When it is detected that the topology structure between the target GPU node and the management node switches, the electrical signal combinations corresponding to the multiple connectors are acquired, where each electrical signal in the electrical signal combination corresponds to a plurality of pins in the corresponding connector; For each connector, based on a first truth table and an electrical signal combination corresponding to the connector, determine the port information corresponding to the connector; the first truth table stores: a correspondence between different electrical signal combinations and port information; Determining a target topology type corresponding to the switched topology structure based on the port information respectively corresponding to the plurality of connectors; A target configuration file corresponding to the target topology type is obtained, and the target configuration file is loaded into a high-speed serial computer expansion bus standard interface expansion switch chip PCIE Switch in the target GPU node.

2. The method according to claim 1, characterized in that The electrical signal combination includes: a first electrical signal corresponding to a pin associated with the target GPU node, and a second electrical signal corresponding to a pin associated with the management node; the first truth table stores: a first electrical signal corresponding to each port type, and a second electrical signal corresponding to each port information under each port type; The determining, based on the first truth table and the electrical signal combination corresponding to the connector, the port information corresponding to the connector includes: Matching the first electrical signal corresponding to the connector with the first electrical signals corresponding to each port type in the first truth table to obtain a target port type corresponding to the connector; The second electrical signal corresponding to the connector is matched with each second electrical signal corresponding to the target port type in the first truth table to obtain port information corresponding to the connector.

3. The method according to claim 1, characterized in that The target GPU includes a plurality of PCIE switches, and the management node includes a plurality of central processing units (CPUs); Determining a target topology type corresponding to the switched topology structure based on the port information respectively corresponding to the plurality of connectors includes: For each PCIE Switch, determining connection information of the PCIE Switch based on port information of each connector corresponding to the PCIE Switch; the connection information includes: a port identifier and a port number of a CPU connected to the PCIE Switch; Determine a target topology type corresponding to the switched topology structure based on the connection information corresponding to each PCIE Switch and the second truth table; The second truth table records: the corresponding relationship between each topology type and the connection information of the PCIE Switch.

4. The method according to claim 3, characterized in that The multiple PCIE Switches are a first PCIE Switch and a second PCIE Switch; The determining, based on the connection information corresponding to each PCIE Switch and the second truth table, a target topology type corresponding to the switched topology structure includes: If it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to a port of a CPU, and the second PCIE Switch is connected to a port of a CPU, then the target topology type is determined to be a balanced mode; If it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different CPUs, the first PCIE Switch is connected to two ports of one CPU, and the second PCIE Switch is connected to two ports of one CPU, then it is determined that the target topology type is a dual uplink mode.

5. The method according to claim 3, characterized in that: The multiple PCIE Switches are a first PCIE Switch and a second PCIE Switch; The determining, based on the connection information corresponding to each PCIE Switch and the second truth table, a target topology type corresponding to the switched topology structure includes: If it is determined based on the connection information that the first PCIE Switch and the second PCIE Switch are respectively connected to different ports of the same CPU, then the target topology type is determined to be a general mode; If it is determined based on the connection information that the first PCIE Switch is connected to a port of a CPU, and the first PCIE Switch and the second PCIE Switch are connected to each other, then it is determined that the target topology type is a serial mode.

6. The method according to any one of claims 1 to 5, characterized in that: The target GPU node further includes: a complex programmable control logic device CPLD and a baseboard management controller BMC, wherein the BMC is connected to the CPLD and PCIE Switch respectively, and the acquiring of a target configuration file corresponding to the target topology type and the loading of the target configuration file in the PCIE Switch in the GPU node include: The BMC reads the target topology type from the CPLD, and queries a target configuration file corresponding to the target topology type from configuration files corresponding to each stored topology type; The BMC sends the queried target configuration file to the PCIE Switch; The PCIE Switch receives and loads the target configuration file.

7. The method according to claim 6, characterized in that The BMC is connected to the management node, and after determining the target topology type corresponding to the switched topology structure based on the port information corresponding to the multiple connectors, the method further includes: The BMC sends the target topology type to the management node, so that after the management node receives the target topology type, it controls the server corresponding to the management node to start.

8. A topological structure recognition device, characterized in that: Applied to a target graphics processing unit (GPU) node, the target GPU node is connected to a management node via a plurality of connectors, and the device comprises: an acquisition module, configured to acquire, when detecting that a topology switch occurs between the target GPU node and the management node, electrical signal combinations corresponding to the plurality of connectors, wherein each electrical signal in the electrical signal combination corresponds to a plurality of pins in the corresponding connector; A first determination module is used to determine, for each connector, port information corresponding to the connector based on a first truth table and an electrical signal combination corresponding to the connector; the first truth table stores: a correspondence between different electrical signal combinations and ports; A second determination module, configured to determine a target topology type corresponding to the switched topology structure based on the port information respectively corresponding to the plurality of connectors; A loading module is used to obtain a target configuration file corresponding to the target topology type and load the target configuration file in a PCIE Switch in the target GPU node.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to implement the method according to any one of claims 1 to 7 when executing a computer program stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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