Memory device

Abstract

A memory device is provided. The memory device includes: a plurality of sub-array regions arranged at intervals in a first horizontal direction and a second horizontal direction, and each of the sub-array regions including a plurality of memory cells, the first horizontal direction crossing the second horizontal direction; the dummy areas are arranged among the plurality of sub-array areas; the dummy region includes a first metal pattern extending in a first horizontal direction at the first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0137041 filed on October 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to electronic devices, and more particularly, to a memory device for arranging at least part of wiring of a peripheral circuit in a dummy region. Background Art

[0003] Semiconductor memories are widely used to store data in various electronic devices such as computers and wireless communication devices. Dynamic random access memory (DRAM), which is a type of semiconductor memory, operates by writing and reading data due to the charge stored in the cell capacitor of the memory cell. In DRAM, a memory cell array is connected to a bit line and a word line. The bit line is connected to a sense amplifier, and the word line is connected to a word line driver circuit. Summary of the invention

[0004] One or more example embodiments provide a memory device in which at least part of wirings of a peripheral circuit are arranged in a dummy region, which may allow for increased memory integration.

[0005] According to an aspect of an example embodiment, a memory device includes: a subarray region extending in a first horizontal direction and a second horizontal direction and including a plurality of memory cells, the first horizontal direction intersecting the second horizontal direction; a dummy region adjacent to the subarray region in the second horizontal direction, the dummy region including a first metal pattern extending in the second horizontal direction through a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

[0006] According to another aspect of the example embodiment, a memory device includes: a subarray region including a plurality of memory cells; a dummy region adjacent to the subarray region, the dummy region including a first power metal pattern extending in a first horizontal direction through a first layer, a first lower contact extending in a vertical direction on the first power metal pattern, a second power metal pattern extending in a second horizontal direction through a second layer, and a second lower contact extending in a vertical direction on the second power metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first power circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second power circuit connected to the second upper contact.

[0007] According to another aspect of the example embodiment, a memory device includes: a subarray region including a plurality of memory cells; a dummy region adjacent to the subarray region, the dummy region including a first metal pattern extending in a first horizontal direction through a first layer, a first via contact extending in a vertical direction on the first metal pattern, a second metal pattern contacting the first via contact at a second layer and extending in a second horizontal direction, a first lower contact extending in a vertical direction on the first metal pattern, and a second lower contact extending in the vertical direction on the second metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first test circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second test circuit connected to the second upper contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects will become more apparent from the following description of example embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram of a structure of a memory device according to an example embodiment; Figure 2 It is along Figure 1 A cross-sectional view of the memory device taken along line A1-A2; Figure 3 is a diagram for explaining signal movement within a peripheral circuit according to some example embodiments; Figure 4 It is along Figure 3 A cross-sectional view of the memory device taken along line B1-B2; Figure 5 is a diagram for explaining signal movement within a peripheral circuit according to other example embodiments; Figure 6 It is along Figure 5 A cross-sectional view of the memory device taken along line C1-C2; Figure 7 It is along Figure 5 A cross-sectional view of the memory device taken along line D1-D2; Figure 8 is a diagram for explaining a power network according to an example embodiment; Fig. 9 It is along Figure 8 A cross-sectional view of the memory device taken along line E1-E2; Fig.10 It is along Figure 8 A cross-sectional view of the memory device taken along line F1-F2; Fig.11 and Fig.12 is a cross-sectional view of a semiconductor device according to some example embodiments; Fig.13 and Fig.14 are cross-sectional views of other semiconductor devices according to other example embodiments; Fig.15 and Fig.16 is a cross-sectional view of a semiconductor device according to other example embodiments; and Fig.17 and Fig.18 is a cross-sectional view of a semiconductor device according to other example embodiments. DETAILED DESCRIPTION

[0009] Hereinafter, the exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. Throughout the specification, the same components are represented by the same reference numerals, and their repeated descriptions are omitted. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to" or "bonded to" another element or layer, it may be directly on another element or layer, directly connected to or directly bonded to another element or layer, or there may be an intermediate element or layer. In contrast, when an element or layer is referred to as "directly" on another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. The embodiments described herein are exemplary embodiments, and therefore the present disclosure is not limited thereto, and may be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude association with one or more features of other examples or other exemplary embodiments that are also provided herein or not provided herein but consistent with the present disclosure.

[0010] Figure 1 is a schematic diagram of a structure of a memory device 100 according to example embodiments.

[0011] Reference Figure 1, the memory device 100 corresponds to a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, or a Rambus DRAM (RDRAM).

[0012] The memory device 100 may include a cell array structure CAS and a peripheral circuit structure PCS. The cell array structure CAS may be disposed on the peripheral circuit structure PCS in a vertical direction (e.g., Z direction) relative to the peripheral circuit structure PCS. In this regard, the peripheral circuit structure PCS may be buried in a direction perpendicular to the cell array structure CAS and disposed below the cell array structure CAS. According to an example embodiment, the cell array structure CAS and the peripheral circuit structure PCS may be attached to each other in a vertical direction (e.g., Z direction) via a pad. The attachment may be achieved, for example, by bonding between copper (Cu) pads, but example embodiments are not limited thereto.

[0013] The cell array structure CAS may include a plurality of sub-array regions 110 , 111 , 112 , 113 , 114 , and 115 and a dummy region 120 .

[0014] Each of the plurality of sub-array regions 110, 111, 112, 113, 114, and 115 may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. The bit lines BL included in each sub-array region may each extend in a first horizontal direction (e.g., Y direction) and may be arranged side by side in a second horizontal direction (e.g., X direction). The word lines WL included in each sub-array region may each extend in a second horizontal direction (e.g., X direction) and may be arranged side by side in a first horizontal direction (e.g., Y direction). Each of the plurality of memory cells may be connected to the bit lines BL and the word lines WL. Each of the plurality of memory cells may include a cell transistor and a cell capacitor. Each of the plurality of memory cells formed in the plurality of sub-array regions 110, 111, 112, 113, 114, and 115 may include a cell transistor and a cell capacitor connected to the bit lines BL and the word lines WL. Each of the plurality of sub-array regions 110, 111, 112, 113, 114, and 115 may include a plurality of memory blocks. Memory cells connected to a plurality of word lines WL may constitute a memory block. Each of a plurality of sub-array regions 110, 111, 112, 113, 114, and 115 may be arranged so that at least one side of each of the plurality of sub-array regions 110, 111, 112, 113, 114, and 115 may be spaced apart from another sub-array region. Each of the plurality of sub-array regions 110, 111, 112, 113, 114, and 115 may include a plurality of pads formed so that the peripheral circuit structure PCS is connected to each of the bit lines and word lines. For example, each sub-array region may include a first pad and a second pad. The first pad may connect the bit line sense amplifier BLSA of the peripheral circuit structure PCS to the bit line BL. The second pad may connect the sub-word line driver SWD of the peripheral circuit structure PCS to the word line WL.

[0015] The dummy region 120 may be disposed between the plurality of sub-array regions 110, 111, 112, 113, 114, and 115. For example, the dummy region 120 may be disposed between two different sub-array regions. The dummy region 120 may be disposed side by side with the corresponding sub-array region in the first horizontal direction and the second horizontal direction. The dummy region 120 may include a plurality of pads connected to the peripheral circuit structure PCS. According to an example embodiment, the dummy region 120 may not include a plurality of bit lines, a plurality of word lines, and a plurality of memory cells.

[0016] The peripheral circuit structure PCS may include a peripheral circuit region in which a peripheral circuit is formed. Some peripheral circuits may be formed in a portion of the peripheral circuit region. Some other peripheral circuits may be formed in other portions of the peripheral circuit region. The peripheral circuit may be configured to apply a word line drive voltage to a word line (e.g., WL) selected from a plurality of word lines. The peripheral circuit may be configured to sense data through at least one bit line selected from a plurality of bit lines. For example, the peripheral circuit may include a row decoder R / D (e.g., a row decoder circuit) and a column decoder C / D (e.g., a column decoder circuit).

[0017] For example, in the middle area MIDDLE of the peripheral circuit structure PCS, although Figure 1100 , but may include a command decoder (e.g., a command decoder circuit), a mode register set / extended mode register set (MRS / EMRS) circuit, an address buffer, a data input / output circuit, a voltage generating circuit, a text circuit, and the like. The command decoder may receive command signals applied by an external source, and decode these signals to generate commands internally according to the decoded command signals. The MRS / EMRS circuit may set an internal mode resistor in response to both an MRS / EMRS command and an address signal for specifying an operation mode of the memory device 100. Data input through the data input / output circuit may be written to each sub-array, or data read from each sub-array may be output to the outside through the data input / output circuit. The address buffer may temporarily store an address signal input from an external source. The voltage generating circuit may generate various internal voltages for driving the circuits of the memory device 100. The voltage generating circuit may generate a high voltage (e.g., VPP), a negative voltage (e.g., VBB), a bit line precharge voltage (e.g., VEQ), an internal power supply voltage (e.g., VINTA), and the like by using a power supply voltage (e.g., VDD) applied from the outside of the memory device 100. A high voltage (e.g., VPP) may be provided to a row decoder R / D, may have a higher voltage level than a power supply voltage (e.g., VDD), and may be used in a word line driver circuit to turn on an N-type metal oxide semiconductor (NMOS) cell transistor connected to a word line WL. A negative voltage (e.g., VBB) may have a negative (-) voltage level lower than a power supply voltage (e.g., VDD), and may be used to increase data retention time by increasing a threshold voltage (e.g., Vth) of an NMOS transistor. A negative voltage (e.g., VBB) may be applied to a well region in which an NMOS transistor is formed, and may generally be referred to as a bulk bias voltage or a reverse bias voltage. Before a bit line sense amplifier BLSA senses a voltage difference between a bit line BL and a complementary bit line (e.g., BIT LINE BAR), a bit line precharge voltage (e.g., VEQ) may be used to equalize the voltage of the bit line BL with the voltage of the complementary bit line. The internal power supply voltage (e.g., VINTA) may be provided to a first sensing drive voltage line and a second sensing drive voltage line (e.g., LA and LAB) of the bit line sense amplifier BLSA. The bit line sense amplifier BLSA may sense and amplify a voltage difference between the bit line BL and the complementary bit line according to the first sensing drive voltage line and the second sensing drive voltage line (e.g., LA and LAB). The test circuit may perform a test operation within the memory device 100. For example, the test circuit may be a tester that outputs a test mode signal. As another example, the test circuit may include a test MRS (TMRS) fuse box that outputs a TMRS signal for TMRS.

[0018] For example, each of the regions other than the middle region MIDDLE of the peripheral circuit structure PCS may include a row decoder R / D, a column decoder C / D, and a memory body BANK. The memory body BANK may include one or more mat regions MAT. The mat region may be referred to as a mat. One mat region MAT may include a bit line sense amplifier BLSA and a sub-word line driver SWD. One mat region MAT may also include a junction corresponding to the intersection of the bit line sense amplifier BLSA and the sub-word line driver SWD. The junction may include a switch for driving the bit line sense amplifier BLSA and the sub-word line driver SWD. The row decoder R / D may decode the row address among the address signals output by the address buffer so as to specify the word line connected to the memory cell to which data is to be input or output, and the word line may be selected. The row decoder R / D may generate a word line drive voltage to be applied to the word line corresponding to the row address. The row decoder R / D may be connected to the sub-word line driver SWD. The sub-word line driver SWD may be connected to a plurality of word lines formed in each sub-array region. The sub-word line driver SWD may drive at least a portion of the plurality of word lines by sending a word line driving voltage to the word line. The column decoder C / D may select at least one bit line corresponding to the column address. The column decoder C / D may decode the column address among the address signals output by the address buffer so as to specify the bit line connected to the memory cell to which data is to be input or output. The column decoder C / D may be connected to the bit line sense amplifier BLSA. The bit line sense amplifier BLSA may be connected to a plurality of bit lines formed in each sub-array region, and may read data from the memory cell formed in each sub-array region or write data to the memory cell formed in each sub-array region.

[0019] Because the memory device 100 includes a cell array structure CAS and a peripheral circuit structure PCS of a stacked structure, the word line can be extended without being interrupted by a circuit configuration other than the memory cell in the cell array structure CAS. In other words, the memory device 100 may include a cell array structure CAS and a peripheral circuit structure PCS of a stacked structure, and the word line can be extended without being interrupted by a circuit configuration other than the memory cell in the cell array structure CAS.

[0020] Figure 2 It is along Figure 1 1 is a cross-sectional view of the memory device 100 taken along line A1 - A2 .

[0021] Reference Figure 2, the memory device 100 may include a cell array structure CAS and a peripheral circuit structure PCS bonded to each other in a vertical direction (e.g., Z direction). Because the cell array structure CAS may include a plurality of subarray regions 110, 111, 112, 113, 114, and 115, and the peripheral circuit structure PCS may include a peripheral circuit, the memory device 100 may have a structure in which a subarray is disposed above a peripheral circuit (i.e., a cell-on-periphery (CoP) structure).

[0022] According to an example embodiment, the cell array structure CAS may include a memory cell including a vertical channel transistor. However, example embodiments are not limited thereto, and the cell array structure CAS may include a memory cell including a transistor of a different type from the vertical channel transistor. The bit line BL may extend in a first horizontal direction (e.g., a Y direction), and the word line WL may extend in a second horizontal direction (e.g., an X direction). Each of the number of memory cells, the number of bit lines, and the number of word lines may be a plural number.

[0023] The peripheral circuit structure PCS may include a semiconductor substrate. The peripheral circuit may be formed by forming a semiconductor device (such as a transistor) and a pattern for wiring the semiconductor device on the semiconductor substrate. After the peripheral circuit is formed in the peripheral circuit structure PCS, a cell array structure CAS including a plurality of sub-array regions 110, 111, 112, 113, 114, and 115 and a dummy region 120 may be formed, and a pattern may be formed to electrically connect the word line WL and the bit line BL of each sub-array region to the peripheral circuit formed in the peripheral circuit structure PCS.

[0024] The peripheral circuit structure PCS may include a substrate 210, a first interlayer insulating layer 215, a plurality of circuit devices 211a and 211b formed on the substrate 210, first metal patterns 212a and 212b respectively connected to the plurality of circuit devices 211a and 211b, second metal patterns 214a and 214b formed on the first metal patterns 212a and 212b, a third metal pattern 216 formed on the second metal pattern 214b, a fourth metal pattern 218 formed on the third metal pattern 216, a fifth metal pattern 220 formed on the fourth metal pattern 218, and a first contact pad 222 formed on the fifth metal pattern 220.

[0025] Despite Figure 2214a, but example embodiments are not limited thereto, and at least one metal pattern may be further formed on the second metal pattern 214a. The metal pattern may also be referred to as a metal layer. According to an example embodiment, the metal pattern may include one or more metal lines each extending in one horizontal direction and arranged side by side in another horizontal direction. Figure 2 2 , only the first metal pattern 212 b, the second metal pattern 214 b, the third metal pattern 216, the fourth metal pattern 218, and the fifth metal pattern 220 are shown, but example embodiments are not limited thereto. Less than five metal patterns may be stacked, or at least one metal pattern may be further formed on the fifth metal pattern 220. According to an example embodiment, the first metal patterns 212 a and 212 b may be formed of tungsten having a relatively high resistance, and the second metal patterns 214 a and 214 b may be formed of copper having a relatively low resistance. At least a portion of the one or more metal patterns formed above the second metal patterns 214 a and 214 b may be formed of a metal having a lower resistance than the copper used to form the second metal patterns 214 a and 214 b.

[0026] The first interlayer insulating layer 215 may be disposed on the substrate 210. The first interlayer insulating layer 215 may cover the plurality of circuit devices 211a and 211b, the first metal patterns 212a and 212b, the second metal patterns 214a and 214b, the third metal pattern 216, the fourth metal pattern 218, the fifth metal pattern 220, and the first contact pad 222. The first interlayer insulating layer 215 may be formed of an insulating material such as silicon oxide or silicon nitride.

[0027] The plurality of circuit devices 211a and 211b may be connected to at least one of the circuit devices constituting the peripheral circuit. For example, the first circuit device 211a may be one of the transistors included in the sub-word line driver SWD. The second circuit device 211b may be any one of the transistors included in the bit line sense amplifier BLSA. However, example embodiments are not limited thereto.

[0028] The first contact pad 222 may be disposed on a metal pattern disposed at the uppermost (or topmost, highest) layer of the peripheral circuit structure PCS, and may be bonded to the second contact pad 232. The second contact pad 232 may be formed of copper, but example embodiments are not limited thereto. The first contact pad 222 and the second contact pad 232 may each include a plurality of layers having different widths. The intermediate layers of the contact pads 222 and 232 may have varying widths.

[0029] The cell array structure CAS may include a second contact pad 232, a plurality of metal patterns 234, 236, 238 and 240 stacked on the second contact pad 232, a second interlayer insulating layer 225, a conductive line 230 disposed on the second interlayer insulating layer 225, a cell structure CS disposed on the conductive line 230, and a capacitor structure 290 disposed on the cell structure CS.

[0030] The second contact pad 232 may be disposed under a metal pattern disposed at a lowermost (or lowest, bottom) layer of the cell array structure CAS and may be bonded to the first contact pad 222. The second contact pad 232 may be formed of copper, but example embodiments are not limited thereto.

[0031] exist Figure 2 , the cell array structure CAS includes four metal patterns 234, 236, 238, and 240. However, example embodiments are not limited thereto, and less than four metal patterns may be stacked, or at least one metal pattern may be further formed on the second contact pad 232 and under the conductive line 230. According to example embodiments, the plurality of metal patterns 234, 236, 238, and 240 may be formed of a material having a specific resistance, such as copper, tungsten, or aluminum.

[0032] The second interlayer insulating layer 225 may be formed to cover the side surface of the second contact pad 232, the respective side surfaces of the plurality of metal patterns 234, 236, 238, and 240, and the lower surface and the side surface of the conductive line 230. The second interlayer insulating layer 225 may be formed to fill the space between the second contact pad 232, the plurality of metal patterns 234, 236, 238, and 240, and the conductive line 230.

[0033] The conductive line 230 may extend in a first horizontal direction (eg, Y direction). A plurality of conductive lines including the conductive line 230 may be spaced apart from each other in a second horizontal direction (eg, X direction) intersecting the first horizontal direction (eg, Y direction). The conductive line 230 may be used as a bit line BL of the memory device 100.

[0034] An isolation insulating layer 235 may be formed on the conductive line 230. The isolation insulating layer 235 may include a channel trench 235T, and may include a plurality of insulating patterns spaced apart from each other by the channel trench 235T. A channel layer 246 may be formed in each of the channel trenches 235T. The channel layer 246 may extend along the side surface and the lower surface of the channel trench 235T, and may be electrically connected to the conductive line 230. A gate dielectric layer 242 may be formed on the channel layer 246 in the channel trench 235T. The gate dielectric layer 242 may be disposed between the channel layer 246 and the gate electrode 250. The gate electrode 250 may be formed on the gate dielectric layer 242 in the channel trench 235T. According to an example embodiment, the gate electrode 250 may include a first gate electrode 250A and a second gate electrode 250B facing each other in one channel trench 235T. In this case, each channel layer 246 may implement two transistor structures. The first gate electrode 250A may be used as a first word line of the subarray, and the second gate electrode 250B may be used as a second word line of the subarray. According to an example embodiment, the first gate electrode 250A may be used as a front gate electrode of a cell transistor connected to a word line, and the second gate electrode 250B may be used as a back gate electrode of the cell transistor.

[0035] According to an example embodiment, a blocking insulating layer 262 and a gap-filling insulating layer 264 may be formed between the first gate electrode 250A and the second gate electrode 250B. The first gate electrode 250A and the second gate electrode 250B may be separated from each other by the blocking insulating layer 262 and the gap-filling insulating layer 264. The gap-filling insulating layer 264 may be formed on the blocking insulating layer 262 to fill a region between the first gate electrode 250A and the second gate electrode 250B.

[0036] According to an example embodiment, the unit structure CS may include a structure of a vertical channel transistor. However, the example embodiment is not limited thereto. In some cases, the unit structure CS may include a structure of a transistor different from the vertical channel transistor. The vertical channel transistor according to the example embodiment may represent a structure in which the channel length of the channel layer 246 extends in a vertical direction (e.g., Z direction) perpendicular to the upper surface of the substrate 210. The vertical channel transistor may include a channel layer 246, a gate electrode 250, and a gate dielectric layer 242 disposed between the channel layer 246 and the gate electrode 250. The channel layer 246 of the vertical channel transistor may include a first source / drain region and a second source / drain region arranged in a vertical direction (e.g., Z direction). For example, the lower portion of the channel layer 246 may be used as the first source / drain region, and the upper portion of the channel layer 246 may be used as the second source / drain region. The portion of the channel layer 246 between the first source / drain region and the second source / drain region may be used as a channel region.

[0037] A contact layer 270 connected to an upper surface of the channel layer 246 may be formed on the channel layer 246. The contact layer 270 may connect the channel layer 246 to the capacitor structure 290. An upper surface of the channel layer 246 adjacent to the first gate electrode 250A may be connected to one contact layer 270, and an upper surface of the channel layer 246 adjacent to the second gate electrode 250B may be connected to another contact layer 270.

[0038] The capacitor structure 290 may be formed on the isolation insulating layer 235 and the contact layer 270. The capacitor structure 290 may be connected to respective upper surfaces of the contact layer 270. The capacitor structure 290 may be controlled by a signal conducted through the conductive line 230 and the gate electrode 250 to store data. The capacitor structure 290 may include a lower electrode 292, a capacitor dielectric layer 294, and an upper electrode 296. The capacitor structure 290 may store charges in the capacitor dielectric layer 294 by using a potential difference generated between the lower electrode 292 and the upper electrode 296.

[0039] Because one of the plurality of vertical channel transistor structures and one of the capacitor structures 290 may constitute a memory cell, the cell array structure CAS may include a plurality of memory cells constituted by the plurality of cell structures CS and the plurality of capacitor structures 290 .

[0040] As high-performance and highly integrated memory devices are required, the integration and complexity of the peripheral circuits within the peripheral circuit structure PCS will increase, and the complexity of the wiring for signal communication between circuits (e.g., row decoder R / D and column decoder C / D) will also increase. In order to increase the signal speed between circuits of high-performance peripheral circuits, it is necessary to set the wiring for signal communication relatively simply. However, due to the limitation of the physical size of the peripheral circuit structure PCS, the location (or space) for arranging the wiring for connecting the circuits to each other within the peripheral circuit structure PCS may be insufficient. In order to solve this situation, it is necessary to set the wiring for connecting the circuits of the peripheral circuit structure PCS in the dummy area 120 of the cell array structure CAS.

[0041] Figure 3 is a diagram for explaining signal movement within a peripheral circuit according to example embodiments. Figure 4 It is along Figure 3 1 is a cross-sectional view of the memory device 300 taken along line B1 - B2 .

[0042] Reference Figure 3, the wiring for signal transmission between the circuits of the peripheral circuit structure PCS may be arranged in the dummy area 320 of the cell array structure CAS. For example, the wiring for conducting the signal indicating the address from the address buffer included in the middle area MIDDLE to the row decoder R / D may be set in the dummy area 320. However, the example embodiments are not limited thereto. The signal SIG output by the first circuit located at the first point P1 may be sent to the second circuit through the wiring. The path of the signal SIG sent through the wiring may be, for example, a path through the first point P1, the second point P2, the third point P3, and the fourth point P4. For example, a specific circuit device included in the address buffer of the middle area MIDDLE may send a signal SIG corresponding to the address from the first point P1 to the second point P2, and the signal SIG may move from the second point P2 to the fourth point P4 via the third point P3. A specific circuit device of the row decoder R / D located at the fourth point P4 may receive the signal SIG.

[0043] Reference Figure 3 and Figure 4 , the peripheral circuit region of the peripheral circuit structure PCS may include a substrate 410, a first circuit device 411a, a second circuit device 411b, a first interlayer insulating layer 415, a first upper contact UPC1, and a second upper contact UPC2.

[0044] The substrate 410 and the first interlayer insulating layer 415 may be Figure 2 The substrate 210 and the first interlayer insulating layer 215 are the same.

[0045] The first circuit device 411a may be a device included in the first circuit. The second circuit device 411b may be a device included in the second circuit. For example, the first circuit device 411a may be a transistor included in the address buffer, and the second circuit device 411b may be a transistor included in the row decoder R / D. However, example embodiments are not limited thereto.

[0046] The first upper contact UPC1 may be disposed on the first circuit device 411a. The first upper contact UPC1 may be attached to the first lower contact LWC1. According to an example embodiment, the first upper contact UPC1 may include a contact pad 422a, and at least one contact metal pattern that contacts the first circuit device 411a and is stacked in a direction toward the dummy region 320. For example, the first upper contact UPC1 may include a first contact metal pattern 412a, a second contact metal pattern 414a, a third contact metal pattern 416a, a fourth contact metal pattern 418a, and a fifth contact metal pattern 420a, and a contact pad 422a. The first contact metal pattern 412a may be disposed on the first circuit device 411a. For example, one surface of the first contact metal pattern 412a may contact the first circuit device 411a. The other surface of the first contact metal pattern 412a may contact the second contact metal pattern 414a. The second contact metal pattern 414a, the third contact metal pattern 416a, the fourth contact metal pattern 418a, and the fifth contact metal pattern 420a may be stacked in a vertical direction (e.g., Z direction). The contact pad 422a may be disposed on the fifth contact metal pattern 420a. For example, one surface of the contact pad 422a may contact the fifth contact metal pattern 420a, and the other surface of the contact pad 422a may contact the contact pad 432a of the first lower contact LWC1. The contact pad 422a may be formed of copper, but example embodiments are not limited thereto. The contact pad 422a may include a plurality of layers having different widths. The middle layer of the contact pad 422a may have a varying width.

[0047] The second upper contact UPC2 may be disposed on the second circuit device 411b. The second upper contact UPC2 may be attached to the second lower contact LWC2. According to an example embodiment, the second upper contact UPC2 may include a contact pad 422b, and at least one contact metal pattern that contacts the second circuit device 411b and is stacked in a direction toward the dummy region 320. For example, the second upper contact UPC2 may include a first contact metal pattern 412b, a second contact metal pattern 414b, a third contact metal pattern 416b, a fourth contact metal pattern 418b, and a fifth contact metal pattern 420b, and a contact pad 422b. The first contact metal pattern 412b may be disposed on the second circuit device 411b. For example, one surface of the first contact metal pattern 412b may contact the second circuit device 411b. The other surface of the first contact metal pattern 412b may contact the second contact metal pattern 414b. The second contact metal pattern 414b, the third contact metal pattern 416b, the fourth contact metal pattern 418b, and the fifth contact metal pattern 420b may be stacked in a vertical direction (e.g., Z direction). The contact pad 422b may be disposed on the fifth contact metal pattern 420b. For example, one surface of the contact pad 422b may contact the fifth contact metal pattern 420b, and the other surface of the contact pad 422b may contact the contact pad 432b of the second lower contact LWC2. The contact pad 422b may be formed of copper, but example embodiments are not limited thereto. The contact pad 422b may include a plurality of layers having different widths. The middle layer of the contact pad 422b may have a varying width.

[0048] The dummy region 320 may include a second interlayer insulating layer 425 , a first lower contact LWC1 , a second lower contact LWC2 , a first metal pattern 440 , and a third interlayer insulating layer 435 .

[0049] The second interlayer insulating layer 425 may be formed to cover the side surfaces of the first lower contact LWC1, the second lower contact LWC2, and the lower and side surfaces of the first metal pattern 440. The second interlayer insulating layer 425 may be formed to fill the space between the first lower contact LWC1, the second lower contact LWC2, and the first metal pattern 440.

[0050] The first lower contact LWC1 may be disposed on the first upper contact UPC1 and may be attached to the first upper contact UPC1. According to an example embodiment, the first lower contact LWC1 may include a contact pad 432a and a contact metal pattern 434a. The contact pad 432a may be disposed on the contact pad 422a of the first upper contact UPC1. For example, one surface of the contact pad 432a may contact the contact pad 422a of the first upper contact UPC1, and the other surface of the contact pad 432a may contact the contact metal pattern 434a. The contact pad 432a may be formed of copper, but example embodiments are not limited thereto. The contact pad 432a may include a plurality of layers having different widths. The middle layer of the contact pad 432a may have a varying width. The contact metal pattern 434a may be disposed on the contact pad 432a. The contact metal pattern 434a may be stacked on a first portion of the first metal pattern 440 in a direction toward the peripheral circuit region of the peripheral circuit structure PCS.

[0051] The second lower contact LWC2 may be disposed on the second upper contact UPC2 and may be attached to the second upper contact UPC2. According to an example embodiment, the second lower contact LWC2 may include a contact pad 432b and a contact metal pattern 434b. The contact pad 432b may be disposed on the contact pad 422b of the second upper contact UPC2. For example, one surface of the contact pad 432b may contact the contact pad 422b of the second upper contact UPC2, and the other surface of the contact pad 432b may contact the contact metal pattern 434b. The contact pad 432b may be formed of copper, but example embodiments are not limited thereto. The contact pad 432b may include a plurality of layers having different widths. The middle layer of the contact pad 432b may have a varying width. The contact metal pattern 434b may be disposed on the contact pad 432b. The contact metal pattern 434b may be stacked on the second portion of the first metal pattern 440 in a direction toward the peripheral circuit region of the peripheral circuit structure PCS.

[0052] The first metal pattern 440 may extend at the first layer in a horizontal direction. Figure 4 For example, the first layer may be located between the second insulating layer 425 and the third insulating layer 435, and the first metal pattern 440 may extend in a first horizontal direction (eg, a Y direction). However, example embodiments are not limited thereto. Figure 4 In contrast, for example, the first metal pattern 440 may extend in the second horizontal direction (eg, X direction). One or more first metal patterns 440 may be provided. Figure 4 and Figure 5, for example, two or more first metal patterns 440 may be arranged side by side in a second horizontal direction (e.g., X direction). At least one first metal pattern 440 may be composed of a metal line, but example embodiments are not limited thereto. The first lower contact LWC1 may contact a first portion of the first metal pattern 440. The second lower contact LWC2 may contact a second portion of the first metal pattern 440. The first metal pattern 440 may be formed of a material having a relatively low resistance (e.g., copper or aluminum). The signal SIG between the first circuit device 411a and the second circuit device 411b may be transmitted through the first metal pattern 440.

[0053] The third interlayer insulating layer 435 may be formed to cover top and side surfaces of the first metal patterns 440 and fill a space between one first metal pattern 440 and another first metal pattern 440 .

[0054] As discussed above, by disposing at least a portion of wirings of the peripheral circuit structure PCS in the dummy region 320 of the cell array structure CAS, the integration degree of the memory device 300 is increased, and the efficiency of the peripheral circuit region is improved.

[0055] Furthermore, by arranging wirings having relatively low resistance in a simple pattern in the dummy region 320 of the cell array structure CAS, the signal speed of the peripheral circuit is increased and the performance of the memory device 300 is improved.

[0056] For resource efficiency (e.g., physical size of the peripheral circuit structure PCS), the wiring for the peripheral circuit can be more Figure 4 Alternatively, the test circuit included in the memory device 300 may operate by relatively slow signal communication. In this case, even when the wiring for the test circuit is arranged in the dummy area 320 in a relatively complex pattern, the test circuit may operate smoothly.

[0057] Figure 5 is a diagram for explaining signal movement within a peripheral circuit according to other example embodiments. Figure 6 It is along Figure 5 5 is a cross-sectional view of the memory device 500 taken along line C1 - C2 . Figure 7 It is along Figure 5 5 is a cross-sectional view of the memory device 500 taken along line D1 - D2 .

[0058] Reference Figure 5, wiring for connecting the circuits of the peripheral circuit structure PCS to each other may be arranged in the dummy area 520 of the cell array structure CAS. For example, wiring for conducting a signal indicating an address from an address buffer included in the middle area MIDDLE to a column decoder C / D may be provided in the dummy area 520. As another example, wiring used by a TMRS fuse box included in the middle area MIDDLE to send a TMRS signal to another circuit may be provided in the dummy area 520. A signal SIG output by a first circuit located at a first point P1 may be sent to a third circuit through the wiring. The path of the signal SIG sent through the wiring may be, for example, a path through the first point P1, the second point P2, the third point P3, the fourth point P4, and the fifth point P5.

[0059] Reference Figure 5 and Figure 6 The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 610, a first circuit device 611, a first interlayer insulating layer 615, and a first upper contact UPC1. The substrate 610 and the first interlayer insulating layer 615 may be the same as those described above. Figure 2 and Figure 4 The substrate is the same as the first interlayer insulating layer.

[0060] According to an example embodiment, the first circuit device 611 may be included in a Figure 4 In the first circuit of the first circuit device 411a. For example, the first circuit device 611 may be a transistor included in the address buffer. However, example embodiments are not limited thereto, and the first circuit device 611 may be included in a first circuit of the first circuit device 411a. Figure 4 The first circuit is a different circuit.

[0061] According to other example embodiments, the first circuit device 611 may be included in a test circuit. The test circuit may be, for example, a TMRS fuse box, but example embodiments are not limited thereto. A circuit device included in the test circuit may be referred to as a test circuit device.

[0062] The first upper contact UPC1 may be disposed on the first circuit device 611 and may be attached to the first lower contact LWC1. According to an example embodiment, the first upper contact UPC1 may include a contact pad 622, and at least one contact metal pattern that contacts the first circuit device 611 and is stacked in a direction toward the dummy region 520. For example, the first upper contact UPC1 may include a first contact metal pattern 612, a second contact metal pattern 614, a third contact metal pattern 616, a fourth contact metal pattern 618, and a fifth contact metal pattern 620, and a contact pad 622. The first contact metal pattern 612 may be disposed on the first circuit device 611. For example, one surface of the first contact metal pattern 612 may contact the first circuit device 611. The other surface of the first contact metal pattern 612 may contact the second contact metal pattern 614. The second contact metal pattern 614, the third contact metal pattern 616, the fourth contact metal pattern 618, and the fifth contact metal pattern 620 may be stacked in a vertical direction (e.g., Z direction). The contact pad 622 may be disposed on the fifth contact metal pattern 620. For example, one surface of the contact pad 622 may contact the fifth contact metal pattern 620, and the other surface of the contact pad 622 may contact the contact pad 632 of the first lower contact LWC1. The contact pad 622 may be formed of copper, but example embodiments are not limited thereto. The contact pad 622 may include a plurality of layers having different widths. The middle layer of the contact pad 622 may have a varying width.

[0063] The dummy region 520 may include a second interlayer insulating layer 625 , a first lower contact LWC1 , at least one first metal pattern 640 , a via contact 650 , a third interlayer insulating layer 635 , and at least one second metal pattern (eg, 660 , 662 , 664 , 666 , and / or 668 ).

[0064] The second interlayer insulating layer 625 may be formed to cover the side surface of the first lower contact LWC1 and the lower and side surfaces of the first metal pattern 640 . The second interlayer insulating layer 625 may be formed to fill a space between the first lower contact LWC1 and the first metal pattern 640 .

[0065] The first lower contact LWC1 may be disposed on the first upper contact UPC1 and may be attached to the first upper contact UPC1. The first lower contact LWC1 may be disposed in a vertical direction (e.g., Z direction) relative to the first metal pattern 640. According to an example embodiment, the first lower contact LWC1 may include a contact pad 632 and a contact metal pattern 634. The contact pad 632 may be disposed on the contact pad 622 of the first upper contact UPC1. For example, one surface of the contact pad 632 may contact the contact pad 622 of the first upper contact UPC1, and the other surface of the contact pad 632 may contact the contact metal pattern 634. The contact pad 632 may be formed of copper, but example embodiments are not limited thereto. The contact pad 632 may include a plurality of layers having different widths. The middle layer of the contact pad 632 may have a varying width. The contact metal pattern 634 may be stacked on the first portion of the first metal pattern 640 on the contact pad 632 in a direction toward the peripheral circuit region of the peripheral circuit structure PCS.

[0066] The first metal pattern 640 may extend at the first layer in a horizontal direction. Figure 6 For example, the first metal pattern 640 may extend in a first horizontal direction (eg, Y direction), and two or more first metal patterns 640 may be arranged side by side in a second horizontal direction (eg, X direction). However, example embodiments are not limited thereto. The first lower contact LWC1 may contact a first portion of the first metal pattern 640.

[0067] The via contact 650 may be disposed in a vertical direction (e.g., Z direction) relative to the first metal pattern 640. For example, the via contact 650 may be disposed in a second portion of the first metal pattern 640 that is different from a first portion of the first metal pattern 640 that contacts the first lower contact LWC1. The via contact 650 may extend in a vertical direction (e.g., Z direction).

[0068] The third interlayer insulating layer 635 may be formed to cover the first metal pattern 640, the via contact 650, and the plurality of second metal patterns 660, 662, 664, 666, and 668. The third interlayer insulating layer 635 may be formed to fill spaces between the first metal pattern 640, the via contact 650, and the plurality of second metal patterns 660, 662, 664, 666, and 668. For example, the third interlayer insulating layer 635 may cover an upper surface of the first metal pattern 640, a side surface of the via contact 650, respective side surfaces of the plurality of second metal patterns 660, 662, 664, 666, and 668, respective upper surfaces of the plurality of second metal patterns 660, 662, 664, 666, and 668, and respective lower surfaces of the plurality of second metal patterns 660, 662, 664, 666, and 668.

[0069] At least one second metal pattern may extend in a second layer different from the first layer in a horizontal direction (a second horizontal direction (e.g., an X direction)) different from the horizontal direction (a first horizontal direction (e.g., a Y direction)) in which the first metal pattern 640 extends. For example, the second layer may be located in the third interlayer insulating layer 635 and above the first layer. Figure 6 As shown in , there may be a plurality of second metal patterns, but the number of second metal patterns is not limited thereto. For example, a plurality of second metal patterns 660, 662, 664, 666, and 668 may each extend in a second horizontal direction (e.g., X direction) and may be arranged side by side in a first horizontal direction (e.g., Y direction). The second metal pattern 666 may contact the via contact 650 at the second layer.

[0070] Although referenced Figure 5 and Figure 6 It is explained that the second layer is on the first layer, but example embodiments are not limited thereto and the first layer may be disposed on the second layer.

[0071] Reference Figure 5 , Figure 6 and Figure 7 The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 710, a second circuit device 711, a first interlayer insulating layer 715, and a second upper contact UPC2. The substrate 710 and the first interlayer insulating layer 715 may be connected to Figure 6 The substrate 610 and the first interlayer insulating layer 615 are the same.

[0072] According to an example embodiment, the second circuit device 711 may be included in the first circuit of the peripheral circuit structure PCS. For example, the second circuit device 711 may be a transistor included in the column decoder C / D. Example embodiments are not limited thereto. According to other example embodiments, the second circuit device 711 may be included in a circuit that operates during a test operation.

[0073] The second upper contact UPC2 may be disposed on the second circuit device 711 and may be attached to the second lower contact LWC2. According to an example embodiment, the second upper contact UPC2 may include a contact pad 722, and at least one contact metal pattern (e.g., a first contact metal pattern 712, a second contact metal pattern 714, a third contact metal pattern 716, a fourth contact metal pattern 718, and a fifth contact metal pattern 720) that contacts the second circuit device 711 and is stacked in a direction toward the dummy region 520. The contact pad 722 may be disposed on the uppermost contact metal pattern (e.g., the fifth contact metal pattern 720) included in the second upper contact UPC2. The contact pad 722 may be formed of copper, but example embodiments are not limited thereto. The contact pad 722 may include a plurality of layers having different widths. The middle layer of the contact pad 722 may have a varying width.

[0074] The dummy region 520 may include a second lower contact LWC2 , a plurality of first metal patterns 740 , 742 , 744 , and 746 , a via contact 750 , a second interlayer insulating layer 725 , a third interlayer insulating layer 735 , and at least one second metal pattern 760 .

[0075] The second lower contact LWC2 may be disposed on the second upper contact UPC2 and may be attached to the second upper contact UPC2. The second lower contact LWC2 may extend in a vertical direction (e.g., Z direction) relative to the second metal pattern 760. According to an example embodiment, the first lower contact LWC1 may include a contact pad 732 and at least one contact metal pattern (e.g., 734, 736, and / or 738). The contact pad 732 may be disposed on the contact pad 722 of the second upper contact UPC2. For example, one surface of the contact pad 732 may contact the contact pad 722 of the second upper contact UPC2, and the other surface of the contact pad 732 may contact the contact metal pattern 734. The contact pad 732 may be formed of copper, but example embodiments are not limited thereto. The contact pad 732 may include a plurality of layers having different widths. The middle layer of the contact pad 732 may have a varying width. A plurality of contact metal patterns 734 , 736 , and 738 may be stacked on the first portion of the second metal pattern 760 in a direction toward the peripheral circuit region of the peripheral circuit structure PCS on the contact pad 732 .

[0076] The plurality of first metal patterns 740 , 742 , 744 , and 746 may each extend in a first horizontal direction (eg, the Y direction), and may be arranged side by side in a second horizontal direction (eg, the X direction).

[0077] The via contact 750 may be disposed over one first metal pattern (eg, 742 ) among the plurality of first metal patterns 740 , 742 , 744 , and 746 .

[0078] The second interlayer insulating layer 725 may be formed to cover the second lower contact LWC2 , the plurality of first metal patterns 740 , 742 , 744 , and 746 , and the via contact 750 .

[0079] The at least one second metal pattern 760 may extend in a second horizontal direction (eg, X direction) at the second layer. The via contact 750 may make contact with a portion of the at least one second metal pattern 760 .

[0080] The third interlayer insulating layer 735 may be formed to cover the upper surface and side surfaces of the at least one second metal pattern 760 .

[0081] According to an example embodiment, the respective resistances of the first metal pattern and the second metal pattern may be the same as each other. Figure 6 , for example, the resistances of the first metal pattern 640 and the second metal pattern 666 may be the same as each other. Figure 7 , for example, the respective resistances of the first metal pattern 742 and the second metal pattern 760 may be the same as each other. According to example embodiments, the first metal pattern and the second metal pattern may be formed of a material having a relatively high resistance (e.g., tungsten). The signal SIG between the first circuit device 611 and the second circuit device 711 may be transmitted through the first metal pattern (e.g., 640 or 742), the via contact (e.g., 650 or 750), and the second metal pattern (e.g., 666 or 760).

[0082] As described above, by disposing at least some wirings of the peripheral circuit structure PCS in each of different layers of the dummy area 520 of the cell array structure CAS, the integration degree of the memory device 500 is increased within limited resources.

[0083] As the complexity of the wiring of the peripheral circuits within the peripheral circuit structure PCS increases, designing a power network through which the power supply voltage to be provided to the peripheral circuits is generated may become more complicated. The power network may be composed of power lines to which the power supply voltage is applied, wherein the power lines are arranged in a mesh form. Therefore, for resource efficiency, the power network may be placed in the dummy area 520 of the cell array structure CAS to increase integration.

[0084] Figure 8 is a diagram for explaining a power network according to an example embodiment. Fig. 9 It is along Figure 8 8 is a cross-sectional view of the memory device 800 taken along line E1 - E2 . Fig.10 It is along Figure 8 8 is a cross-sectional view of the memory device 800 taken along line F1 - F2 .

[0085] Reference Figure 8, the power network may be formed in the dummy area 820. The first power lines PWL1 of the power network may each extend in a first horizontal direction (e.g., Y direction) and may be arranged side by side in a second horizontal direction (e.g., X direction). The second power lines PWL2 of the power network may each extend in a second horizontal direction (e.g., X direction) and may be arranged side by side in a first horizontal direction (e.g., Y direction).

[0086] According to an example embodiment, the power network may be formed in a portion of the dummy area 820. Figure 8 , for example, the first power line PWL1 and the second power line PWL2 may be arranged only in an area having the same horizontal coordinates (e.g., coordinates in the X direction and the Y direction) as the middle area MIDDLE of the peripheral circuit structure PCS among the areas of the dummy area 820. The first power line PWL1 and the second power line PWL2 may not be arranged in an area having horizontal coordinates different from the horizontal coordinates of the middle area MIDDLE among the areas of the dummy area 820. However, example embodiments are not limited thereto. According to other example embodiments, a power network may be formed in the entire dummy area 820. The power network may be connected to the peripheral circuit structure PCS so that a voltage generated by a voltage generating circuit (e.g., a high voltage, a negative voltage, a bit line precharge voltage, and an internal power supply voltage) may be transmitted to the peripheral circuit through the power network.

[0087] Reference Figure 8 and Fig. 9 The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 910, a first power circuit device 911, a first interlayer insulating layer 915, and a first upper contact UPC1. The substrate 910 and the first interlayer insulating layer 915 may be the same as those described above. Figure 2 , Figure 4 and Figure 6 The substrate is the same as the first interlayer insulating layer.

[0088] The first power circuit device 911 may be connected to the first upper contact UPC1. The first power circuit device 911 may be included in the voltage generating circuit. According to an example embodiment, the first power circuit device 911 may control the transmission of the first power supply voltage. For example, when the first power circuit device 911 is turned on, the first power supply voltage may be applied to the first power metal pattern 940.

[0089] The first upper contact UPC1 may be disposed on the first power circuit device 911 and may be attached to the first lower contact LWC1. According to an example embodiment, the first upper contact UPC1 may include a contact pad 922 and at least one contact metal pattern. The at least one contact metal pattern may contact the first power circuit device 911 and may be stacked in a direction toward the dummy region 820. One surface of the contact pad 922 may contact the at least one contact metal pattern, and the other surface of the contact pad 922 may contact the contact pad 932 of the first lower contact LWC1. For example, the first upper contact UPC1 may include a first contact metal pattern 912, a second contact metal pattern 914, a third contact metal pattern 916, a fourth contact metal pattern 918, and a fifth contact metal pattern 920, and a contact pad 922. The contact pad 922 may be formed of copper, but example embodiments are not limited thereto. The contact pad 922 may include a plurality of layers having different widths. The middle layer of the contact pad 922 may have a varying width.

[0090] The dummy region 820 may include a second interlayer insulating layer 925 , a first lower contact LWC1 , at least one first power metal pattern 940 , at least one second power metal pattern (eg, 950 , 952 , 954 , and / or 956 ), and a third interlayer insulating layer 935 .

[0091] The second interlayer insulating layer 925 may be formed to cover the side surface of the first lower contact LWC1 , and the lower surface and the side surface of the first power metal pattern 940 .

[0092] The first lower contact LWC1 may be disposed in a vertical direction (e.g., Z direction) relative to the first power metal pattern 940. The first lower contact LWC1 may be disposed on the first upper contact UPC1 and may be attached to the first upper contact UPC1. According to an example embodiment, the first lower contact LWC1 may include a contact pad 932 and a contact metal pattern 934. One surface of the contact pad 932 may contact the contact metal pattern 934, and the other surface of the contact pad 932 may contact the contact pad 922 of the first upper contact UPC1. The contact pad 932 may include a plurality of layers having different widths. The middle layer of the contact pad 932 may have a varying width. The contact metal pattern 934 may be stacked on the first power metal pattern 940 in a direction toward the peripheral circuit region of the peripheral circuit structure PCS.

[0093] At least one first power metal pattern 940 may extend in a horizontal direction at the first layer. Figure 6For example, at least one first power metal pattern 940 may extend in a first horizontal direction (eg, Y direction), and two or more first power metal patterns 940 may be arranged side by side in a second horizontal direction (eg, X direction). However, example embodiments are not limited thereto.

[0094] The plurality of second power metal patterns 950 , 952 , 954 , and 956 may each extend in a second horizontal direction (eg, X direction) at a second layer different from the first layer, and may be arranged side by side in a first horizontal direction (eg, Y direction).

[0095] The third interlayer insulating layer 935 may be formed to cover the top surface and side surfaces of the at least one first power metal pattern 940 and the plurality of second power metal patterns 950 , 952 , 954 , and 956 , and fill spaces between the plurality of second power metal patterns 950 , 952 , 954 , and 956 .

[0096] Reference Figure 8 , Fig. 9 and Fig.10 The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1010, a second power circuit device 1011, a first interlayer insulating layer 1015, and a second upper contact UPC2. The substrate 1010 and the first interlayer insulating layer 1015 may be the same as those described above.

[0097] The second power circuit device 1011 may be connected to the second upper contact UPC2. The second power circuit device 1011 may be included in the voltage generating circuit. According to an example embodiment, the second power circuit device 1011 may control the transmission of the second power supply voltage. For example, when the second power circuit device 1011 is turned on, the second power supply voltage may be applied to at least one second power metal pattern 1050. According to an example embodiment, the voltage level of the first power supply voltage may be higher than the voltage level of the second power supply voltage. For example, the first power supply voltage may correspond to a power supply voltage (e.g., VDD), and the second power supply voltage may correspond to a ground voltage. However, example embodiments are not limited thereto.

[0098] The second upper contact UPC2 may be disposed on the second power circuit device 1011 and may be attached to the second lower contact LWC2. According to an example embodiment, the second upper contact UPC2 may include a contact pad 1022, and at least one contact metal pattern (e.g., a first contact metal pattern 1012, a second contact metal pattern 1014, a third contact metal pattern 1016, a fourth contact metal pattern 1018, and a fifth contact metal pattern 1020) contacting the second power circuit device 1011 and stacked in a direction toward the dummy region 820. The contact pad 1022 may be disposed on the uppermost contact metal pattern (e.g., the fifth contact metal pattern 1020) included in the second upper contact UPC2. The contact pad 1022 may be formed of copper, but example embodiments are not limited thereto. The contact pad 1022 may include a plurality of layers having different widths. The middle layer of the contact pad 1022 may have a varying width.

[0099] The second lower contact LWC2 may be disposed on the second upper contact UPC2 and may be attached to the second upper contact UPC2. The second lower contact LWC2 may extend in a vertical direction (e.g., Z direction) relative to the second power metal pattern 1050. According to an example embodiment, the second lower contact LWC2 may include a contact pad 1032 and at least one contact metal pattern (e.g., 1034, 1036, and / or 1038). The contact pad 1032 may be disposed on the contact pad 1022 of the second upper contact UPC2. The contact pad 1032 may be formed of copper, but example embodiments are not limited thereto. The contact pad 1032 may include a plurality of layers having different widths. The middle layer of the contact pad 1032 may have a varying width. A plurality of contact metal patterns 1034, 1036, and 1038 may be disposed on the contact pad 1032 and may be stacked on the second power metal pattern 1050 in a direction toward the peripheral circuit region of the peripheral circuit structure PCS.

[0100] The plurality of first power metal patterns 1040 , 1042 , 1044 , and 1046 may each extend in a first horizontal direction (eg, a Y direction), and may be arranged side by side in a second horizontal direction (eg, an X direction).

[0101] The second interlayer insulating layer 1025 may be formed to cover the first lower contact LWC1, the second lower contact LWC2, and the plurality of first power metal patterns 1040, 1042, 1044, and 1046. The second interlayer insulating layer 1025 may be formed to further cover Figure 7 At least one second metal pattern 760 is formed.

[0102] At least one second power metal pattern 1050 may extend in a second horizontal direction (eg, X direction) at the second layer. Because the first and second layers exemplarily show relative positions in a vertical direction (eg, Z direction), the second layer of the present disclosure may be located above the first layer of the present disclosure.

[0103] The third interlayer insulating layer 1035 may be formed to cover Figure 7 The upper surface and side surfaces of at least one second metal pattern 760 are formed.

[0104] According to an example embodiment, respective resistances of the first power metal pattern and the second power metal pattern may be the same as each other.A voltage level of a first power voltage applied to the first power metal pattern may be different from a voltage level of a second power voltage applied to the second power metal pattern.

[0105] As discussed above, by disposing the power network in each of the different layers of the dummy area 820 of the cell array structure CAS, the integration density of the memory device 800 is increased within limited resources.

[0106] Fig.11 and Fig.12 is a cross-sectional view of a semiconductor device according to an example embodiment. Specifically, Fig.11 is a cross-sectional view of the memory device 1100 taken along a line extending in a horizontal direction, and Fig.12 is along the Fig.11 The cross-sectional views of the memory device 1200 are taken along lines extending in different horizontal directions.

[0107] Reference Fig.11 , the memory device 1100 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1110, a first circuit device 1111a, a second circuit device 1111b, a first interlayer insulating layer 1115, a first upper contact UPC1, and a second upper contact UPC2.

[0108] The substrate 1110 and the first interlayer insulating layer 1115 may be the same as the substrate and the first interlayer insulating layer described above. According to one example embodiment, the first circuit device 1111a may be included in the first circuit, and the second circuit device 1111b may be included in the second circuit. According to other example embodiments, the first circuit device 1111a may be included in the first circuit, and the second circuit device 1111b may be included in the test circuit as a test circuit device.

[0109] The first upper contact UPC1 may be disposed on the first circuit device 111a and may be attached to the first lower contact LWC1. According to an example embodiment, the first upper contact UPC1 may include at least one contact metal pattern (e.g., a first contact metal pattern 1112a, a second contact metal pattern 1114a, a third contact metal pattern 1116a, a fourth contact metal pattern 1118a, and a fifth contact metal pattern 1120a). The first upper contact UPC1 may also include a contact pad 1122a. The contact pad 1122a may include a plurality of layers having different widths. The middle layer of the contact pad 1122a may have a varying width. The second upper contact UPC2 may be disposed on the second circuit device 1111b and may be attached to the second lower contact LWC2. According to an example embodiment, the second upper contact UPC2 may include at least one contact metal pattern (e.g., a first contact metal pattern 1112b, a second contact metal pattern 1114b, a third contact metal pattern 1116b, a fourth contact metal pattern 1118b, and a fifth contact metal pattern 1120b). The second upper contact UPC2 may further include a contact pad 1122b. The contact pads 1122a and 1122b may be formed of copper, but example embodiments are not limited thereto.

[0110] The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1125 , a first lower contact LWC1 , a second lower contact LWC2 , a first metal pattern 1140 , a second metal pattern 1150 , a via contact 1160 , a third metal pattern 1170 , and a third interlayer insulating layer 1135 .

[0111] The second interlayer insulating layer 1125 may be formed to cover the first lower contact LWC1, the second lower contact LWC2, the first metal pattern 1140, the second metal pattern 1150, the via contact 1160, and the third metal pattern 1170. The second interlayer insulating layer 1125 may be formed to fill spaces between the first lower contact LWC1, the second lower contact LWC2, the first metal pattern 1140, the second metal pattern 1150, the via contact 1160, and the third metal pattern 1170.

[0112] The first lower contact LWC1 may include a contact pad 1132a attached to the contact pad 1122a of the first upper contact UPC1 on the peripheral circuit structure PCS and a contact metal pattern 1134a stacked on the first metal pattern 1140 in a direction toward the peripheral circuit structure PCS. The contact pad 1132a may include a plurality of layers having different widths. The middle layer of the contact pad 1132a may have a varying width.

[0113] The second lower contact LWC2 may include a contact pad 1132b attached to the contact pad 1122b of the second upper contact UPC2 on the peripheral circuit structure PCS and a plurality of contact metal patterns 1134b, 1136b, and 1138b, which are stacked on the third metal pattern 1170 in a direction toward the peripheral circuit structure PCS. The contact pads 1132b and 1122b may each include a plurality of layers having different widths. The intermediate layers of the contact pads 1132b and 1122b may have varying widths.

[0114] The first metal pattern 1140 and the second metal pattern 1150 may each extend in a first horizontal direction (e.g., Y direction) at a first layer, and may be arranged side by side in a second horizontal direction (e.g., X direction). However, example embodiments are not limited thereto. Each of the first metal pattern 1140 and the second metal pattern 1150 may include a plurality of patterns. The via contact 1160 may be disposed on the second metal pattern 1150 in a vertical direction (e.g., Z direction). The third metal pattern 1170 may contact the via contact 1160 at a layer different from the first layer (e.g., second layer), and may extend in a second horizontal direction (e.g., X direction).

[0115] According to an example embodiment, the first metal pattern 1140 may correspond to the first metal pattern 440, the second metal pattern 1150 may correspond to the first metal pattern 640 (and / or any one of the plurality of first metal patterns 740, 742, 744, and 746), the via contact 1160 may correspond to the via contact 650 (and / or the via contact 750), and the third metal pattern 1170 may correspond to any one of the plurality of second metal patterns 660, 662, 664, 666, and 668 (and / or the second metal pattern 760).

[0116] According to an example embodiment, the first metal pattern 1140 may have a lower resistance than at least one of the second metal pattern 1150 and the third metal pattern 1170. For example, the first metal pattern 1140 may be formed of copper, and the second metal pattern 1150 and the third metal pattern 1170 may be formed of tungsten, but example embodiments are not limited thereto.

[0117] A third interlayer insulating layer 1135 may be formed to cover an upper surface of the third metal pattern 1170 .

[0118] Reference Fig.12, the memory device 1200 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1210, a first circuit device 1211a, a second circuit device 1211b, a first interlayer insulating layer 1215, a first upper contact UPC1, and a second upper contact UPC2. The substrate 1210, the first interlayer insulating layer 1215, the first upper contact UPC1, and the second upper contact UPC2 may be the same as the substrate, the first interlayer insulating layer, the first upper contact, and the second upper contact described above. According to an example embodiment, the first circuit device 1211a may be included in the third circuit, and the second circuit device 1211b may be included in the fourth circuit. According to other example embodiments, the first circuit device 1211a may be included in the test circuit as a test circuit device, and the second circuit device 1211b may be included in the fourth circuit.

[0119] The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1225, a first lower contact LWC1, a second lower contact LWC2, a plurality of first metal patterns 1240 and 1242, a second metal pattern 1250, a via contact 1260, a plurality of third metal patterns 1270, 1272, 1274, 1276, and 1278, and a third interlayer insulating layer 1235. Fig.11 Similar to the cell array structure CAS of FIG. 1 , a second interlayer insulating layer 1225, a first lower contact LWC1, a second lower contact LWC2, and a plurality of first metal patterns 1240 and 1242 may be formed. Fig.11 The cell array structure of CAS is different. Fig.12 The second metal pattern 1250 in the cell array structure CAS may be arranged in a layer different from the respective positions of the plurality of first metal patterns 1240 and 1242. For example, the plurality of first metal patterns 1240 and 1242 may be arranged at the first layer, and the second metal pattern 1250 may be arranged at the second layer. The via contact 1260 may be arranged on a third metal pattern (e.g., 1274) among the plurality of third metal patterns 1270, 1272, 1274, 1276, and 1278 in a vertical direction. The plurality of third metal patterns 1270, 1272, 1274, 1276, and 1278 may be arranged at a third layer different from the first layer and the second layer. The plurality of third metal patterns 1270, 1272, 1274, 1276, and 1278 may each extend in the same horizontal direction as the plurality of first metal patterns 1240 and 1242, and may be arranged in the same horizontal direction as the plurality of first metal patterns 1240 and 1242.

[0120] Fig.13 and Fig.14is a cross-sectional view of another semiconductor device according to another exemplary embodiment. Specifically, Fig.13 is a cross-sectional view of the memory device 1300 taken along a line extending in a horizontal direction, and Fig.14 is a cross-sectional view of the memory device 1400 taken along a line extending in a horizontal direction different from the one horizontal direction.

[0121] Reference Fig.13 , the memory device 1300 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1310, a first circuit device 1311a, a second circuit device 1311b, a third circuit device 1311c, a first interlayer insulating layer 1315, a first upper contact UPC1, a second upper contact UPC2, and a third upper contact UPC3. The substrate 1310 may be the same as the substrate described above. According to an example embodiment, the first circuit device 1311a may be included in the first circuit, the second circuit device 1311b may be included in the second circuit, and the third circuit device 1311c may be included in the voltage generating circuit as a power circuit device. However, example embodiments are not limited thereto. The first interlayer insulating layer 1315 may be formed to cover the first upper contact UPC1, the second upper contact UPC2, and the third upper contact UPC3. The first upper contact UPC1, the second upper contact UPC2, and the third upper contact UPC3 may each be vertically disposed on the substrate 1310, and may be disposed side by side in a horizontal direction.

[0122] The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1325, a first lower contact LWC1, a second lower contact LWC2, a third lower contact LWC3, a first metal pattern 1340, a first power metal pattern 1350, a second power metal pattern 1360, and a third interlayer insulating layer 1335. The first lower contact LWC1, the second lower contact LWC2, and the first metal pattern 1340 may be the same as those described above. Figure 4 The first lower contact, the second lower contact, and the first metal pattern described above are the same. The first power metal pattern 1350 and the second power metal pattern 1360 may be the same as those described above with reference to Figure 8 , Fig. 9 and Fig.10 The first power metal pattern and the second power metal pattern described are the same. The third lower contact LWC3 may be connected to the third upper contact UPC3 through a pad. The second power metal pattern 1360 may contact the uppermost layer of the third lower contact LWC3. According to an example embodiment, the first metal pattern 1340 may be disposed in the first layer, the first power metal pattern 1350 may be disposed in the second layer, and the second power metal pattern 1360 may be disposed in the third layer.

[0123] Reference Fig.14 , the memory device 1400 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1410, a first circuit device 1411a, a second circuit device 1411b, a first interlayer insulating layer 1415, a first upper contact UPC1 and a second upper contact UPC2. The substrate 1410 may be the same as the substrate described above. According to an example embodiment, the first circuit device 1411a may be included in a voltage generating circuit as a power circuit device, and the second circuit device 1411b may be included in a third circuit. However, example embodiments are not limited thereto. The first interlayer insulating layer 1415 may be formed to cover the first upper contact UPC1 and the second upper contact UPC2.

[0124] The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1425, a first lower contact LWC1, a second lower contact LWC2, a first metal pattern 1440, a first power metal pattern 1450, a second power metal pattern 1460, and a third interlayer insulating layer 1435. The first lower contact LWC1, the second lower contact LWC2, and the first metal pattern 1440 may be the same as those described above. Figure 4 The first lower contact, the second lower contact, and the first metal pattern described above are the same. The first power metal pattern 1450 and the second power metal pattern 1460 may be the same as those described above with reference to Figure 8 , Fig. 9 and Fig.10 The described first power metal pattern and the second power metal pattern are the same. According to an example embodiment, the first metal pattern 1440 may be disposed in a first layer, the first power metal pattern 1450 may be disposed in a second layer, and the second power metal pattern 1460 may be disposed in a third layer.

[0125] Fig.15 and Fig.16 is a cross-sectional view of a semiconductor device according to another exemplary embodiment. Specifically, Fig.15 is a cross-sectional view of the memory device 1500 taken along a line extending in a horizontal direction, and Fig.16 1 is a cross-sectional view of the memory device 1600 taken along a line extending in a horizontal direction different from the one horizontal direction. The same description as above will be omitted.

[0126] Reference Fig.15, the memory device 1500 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1510, a first circuit device 1511a, a second circuit device 1511b, a first interlayer insulating layer 1515, a first upper contact UPC1, and a second upper contact UPC2. According to an example embodiment, the first circuit device 1511a may be included in a test circuit as a test circuit device. However, example embodiments are not limited thereto. According to an example embodiment, the second circuit device 1511b may be included in a voltage generating circuit as a power circuit device. According to other example embodiments, the second circuit device 1511b may be included in a first circuit. However, example embodiments are not limited thereto.

[0127] The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1525, a first lower contact LWC1, a second lower contact LWC2, a first metal pattern 1540, a via contact 1550, a second metal pattern 1560, a first power metal pattern 1570, a second power metal pattern 1580, and a third interlayer insulating layer 1535. The first lower contact LWC1 may contact the first upper contact UPC1 and may contact the first power metal pattern 1570. The second lower contact LWC2 may contact the second upper contact UPC2 and may contact the first metal pattern 1540. The first metal pattern 1540 may contact the first power metal pattern 1570 as described above. Figure 5 , Figure 6 and Figure 7 The via contact 1550 may be arranged on the first metal pattern 1540 in a vertical direction and contact the first metal pattern 1540 and the second metal pattern 1560. According to an example embodiment, the first metal pattern 1540 may be disposed in a first layer, the second metal pattern 1560 may be disposed in a second layer, the first power metal pattern 1570 may be disposed in a third layer, and the second power metal pattern 1580 may be disposed in a fourth layer. According to an example embodiment, the first metal pattern 1540 and the second metal pattern 1560 may have the same resistance. For example, the first metal pattern 1540 and the second metal pattern 1560 may be formed of tungsten, but example embodiments are not limited thereto.

[0128] Reference Fig.16, the memory device 1600 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1610, a first circuit device 1611a, a second circuit device 1611b, a first interlayer insulating layer 1615, a first upper contact UPC1, and a second upper contact UPC2. According to an example embodiment, the first circuit device 1611a may be included in a voltage generating circuit as a power circuit device. However, the example embodiment is not limited thereto. The second circuit device 1611b may be included in a voltage generating circuit as a power circuit device. However, the example embodiment is not limited thereto.

[0129] The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1625, a first lower contact LWC1, a second lower contact LWC2, a first metal pattern 1640, a via contact 1650, a second metal pattern 1660, a first power metal pattern 1670, a second power metal pattern 1680, and a third interlayer insulating layer 1635. According to an example embodiment, the first metal pattern 1640, the second metal pattern 1660, the first power metal pattern 1670, and the second power metal pattern 1680 may be disposed in different layers. According to an example embodiment, the first metal pattern 1640 and the second metal pattern 1660 may have the same resistance.

[0130] Fig.17 and Fig.18 is a cross-sectional view of a semiconductor device according to other example embodiments. The same description as above will be omitted.

[0131] Reference Fig.17, the memory device 1700 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1710, a first circuit device 1711a, a second circuit device 1711b, a first interlayer insulating layer 1715, a first upper contact UPC1, and a second upper contact UPC2. The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1725, a first lower contact LWC1, a second lower contact LWC2, a first metal pattern 1740, a second metal pattern 1750, a via contact 1760, a third metal pattern 1770, a first power metal pattern 1780, a second power metal pattern 1790, a third interlayer insulating layer 1735, and a fourth interlayer insulating layer 1745. According to an example embodiment, the first metal pattern 1740 and the second metal pattern 1750 may be disposed in the same layer, the first metal pattern 1740 and the third metal pattern 1770 may be disposed in different layers, the second metal pattern 1750 and the third metal pattern 1770 may be disposed in different layers, and the first power metal pattern 1780 and the second power metal pattern 1790 may be disposed in different layers. According to an example embodiment, the first metal pattern 1740 may have a lower resistance than at least one of the second metal pattern 1750 and the third metal pattern 1770. For example, the first metal pattern 1740 may be formed of copper, and the second metal pattern 1750 and the third metal pattern 1770 may be formed of tungsten, but example embodiments are not limited thereto.

[0132] Reference Fig.18 , the memory device 1800 may include a cell array structure CAS and a peripheral circuit structure PCS. The peripheral circuit region of the peripheral circuit structure PCS may include a substrate 1810, a first circuit device 1811a, a second circuit device 1811b, a first interlayer insulating layer 1815, a first upper contact UPC1, and a second upper contact UPC2. The dummy region of the cell array structure CAS may include a second interlayer insulating layer 1825, a first lower contact LWC1, a second lower contact LWC2, a first metal pattern 1840, a second metal pattern 1850, a via contact 1860, a third metal pattern 1870, a first power metal pattern 1880, a second power metal pattern 1890, a third interlayer insulating layer 1835, and a fourth interlayer insulating layer 1845. According to an example embodiment, the first metal pattern 1840, the second metal pattern 1850, the third metal pattern 1870, the first power metal pattern 1880, and the second power metal pattern 1890 may be disposed in different layers. According to an example embodiment, the first metal pattern 1840 may have a lower resistance than at least one of the second metal pattern 1850 and the third metal pattern 1870 .

[0133] It will be understood that the structure of the present disclosure can be modified or changed in various ways without departing from the scope or technical spirit of the present disclosure. In view of the foregoing, when the changes and modifications of the present disclosure fall within the scope of the appended claims and their equivalents, the present disclosure is deemed to include these changes and modifications of the present disclosure.

[0134] The present disclosure has been specifically shown and described with reference to the exemplary embodiments of the present disclosure. The terms used herein are only for the purpose of describing the exemplary embodiments and are not intended to limit the present disclosure. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A memory device, comprising: A plurality of sub-array regions are arranged at intervals in a first horizontal direction and a second horizontal direction, and each sub-array region includes a plurality of memory cells, and the first horizontal direction intersects the second horizontal direction; a dummy region disposed between the plurality of sub-array regions, the dummy region comprising a first metal pattern extending in a first horizontal direction at a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; as well as The peripheral circuit region includes a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

2. The memory device according to claim 1, wherein: The fictitious area also includes: a second metal pattern adjacent to the first metal pattern and extending in a first horizontal direction; a first via contact, disposed on the second metal pattern and extending in a vertical direction; a third metal pattern contacting the first via contact at the second layer and extending in a second horizontal direction; a third lower contact disposed on the second metal pattern and extending in a vertical direction; and a fourth lower contact disposed on the third metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a third upper contact connected to the third lower contact; a third circuit connected to the third upper contact; a fourth upper contact connected to the fourth lower contact; and A fourth circuit is connected to the fourth upper contact.

3. The memory device according to claim 2, wherein: The first metal pattern has a lower resistance than at least one of the second metal pattern and the third metal pattern.

4. The memory device according to claim 1, wherein: The fictitious area also includes: a fourth metal pattern extending in the first horizontal direction at the second layer; a second via contact, disposed on the fourth metal pattern and extending in a vertical direction; a fifth metal pattern contacting the second via contact at the third layer and extending in a second horizontal direction; a fifth lower contact disposed on the fourth metal pattern and extending in a vertical direction; and a sixth lower contact disposed on the fifth metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a fifth upper contact connected to the fifth lower contact; a first test circuit connected to the fifth upper contact; a sixth upper contact connected to the sixth lower contact; and A second test circuit is connected to the sixth upper contact.

5. The memory device according to claim 4, wherein: The first metal pattern has a lower resistance than at least one of the fourth metal pattern and the fifth metal pattern.

6. The memory device according to claim 1, wherein: The fictitious area also includes: a first power metal pattern extending in a first horizontal direction at the second layer; a seventh lower contact disposed on the first power metal pattern and extending in a vertical direction; a second power metal pattern extending in a second horizontal direction at the third layer; and an eighth lower contact disposed on the second power metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a seventh upper contact connected to the seventh lower contact; a first power circuit connected to the seventh upper contact; an eighth upper contact connected to the eighth lower contact; and A second power circuit is connected to the eighth upper contact.

7. The memory device according to claim 1, wherein: The first lower contact comprises: a first contact metal pattern disposed on the first portion of the first metal pattern and extending toward the peripheral circuit region; and a first contact pad disposed between the first contact metal pattern and the first upper contact, and Wherein, the second lower contact comprises: a second contact metal pattern disposed on a second portion of the first metal pattern and extending toward the peripheral circuit region; and The second contact pad is disposed between the second contact metal pattern and the second upper contact.

8. The memory device according to claim 7, wherein: The first upper contact comprises: at least one third contact metal pattern contacting the first circuit and extending toward the dummy area; and a third contact pad disposed between the at least one third contact metal pattern and the first contact pad, and Wherein, the second upper contact comprises: at least one fourth contact metal pattern contacting the second circuit and extending toward the dummy area; and The fourth contact pad is disposed between the at least one fourth contact metal pattern and the second contact pad.

9. A memory device comprising: a plurality of sub-array regions, each sub-array region comprising a plurality of memory cells; a dummy region adjacent to the plurality of sub-array regions, the dummy region comprising a first power metal pattern extending in a first horizontal direction at a first layer, a first lower contact extending in a vertical direction on the first power metal pattern, a second power metal pattern extending in a second horizontal direction at a second layer, and a second lower contact extending in a vertical direction on the second power metal pattern; as well as The peripheral circuit region includes a first upper contact connected to the first lower contact, a first power circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second power circuit connected to the second upper contact.

10. The memory device according to claim 9, wherein: The fictitious area also includes: a first metal pattern extending in one of a first horizontal direction and a second horizontal direction at the third layer; a third lower contact disposed on the first portion of the first metal pattern and extending in a vertical direction; and a fourth lower contact disposed on the second portion of the first metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a third upper contact connected to the third lower contact; a first circuit connected to the third upper contact; a fourth upper contact connected to the fourth lower contact; and A second circuit is connected to the fourth upper contact.

11. The memory device according to claim 10, wherein: The fictitious area also includes: a second metal pattern adjacent to the first metal pattern in the third layer and extending in a first horizontal direction; a first via contact, disposed on the second metal pattern and extending in a vertical direction; a third metal pattern contacting the first via contact at the fourth layer and extending in a second horizontal direction; a fifth lower contact disposed on the second metal pattern and extending in a vertical direction; and a sixth lower contact disposed on the third metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a fifth upper contact connected to the fifth lower contact; a third circuit connected to the fifth upper contact; a sixth upper contact connected to the sixth lower contact; and A fourth circuit is connected to the sixth upper contact.

12. The memory device according to claim 9, wherein: The fictitious area also includes: a fourth metal pattern extending in the first horizontal direction at the third layer; a second via contact, disposed on the first metal pattern and extending in a vertical direction; a fifth metal pattern contacting the first via contact at the fourth layer and extending in a second horizontal direction; a seventh lower contact disposed on the fourth metal pattern and extending in a vertical direction; and an eighth lower contact disposed on the fifth metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a seventh upper contact connected to the seventh lower contact; a first test circuit connected to the seventh upper contact; an eighth upper contact connected to the eighth lower contact; and A second test circuit is connected to the eighth upper contact.

13. The memory device according to claim 12, wherein: The resistance of the fourth metal pattern is equal to the resistance of the fifth metal pattern.

14. The memory device according to claim 9, wherein: The resistance of the first power metal pattern is equal to the resistance of the second power metal pattern, and Herein, a voltage level of a first power voltage applied to the first power metal pattern is different from a voltage level of a second power voltage applied to the second power metal pattern.

15. The memory device according to claim 9, wherein: The first lower contact comprises: at least one first contact metal pattern disposed on the first power metal pattern and extending toward the peripheral circuit region; and a first contact pad disposed between the at least one first contact metal pattern and the first upper contact, and Wherein, the second lower contact comprises: at least one second contact metal pattern disposed on the second power metal pattern and extending toward the peripheral circuit region; and The second contact pad is disposed between the at least one second contact metal pattern and the second upper contact.

16. The memory device of claim 15, wherein: The first upper contact comprises: at least one third contact metal pattern contacting the first power circuit and extending toward the dummy area; and a third contact pad disposed between the at least one third contact metal pattern and the first contact pad, and Wherein, the second upper contact comprises: at least one fourth contact metal pattern contacting the second power circuit and extending toward the dummy area; and The fourth contact pad is disposed between the at least one fourth contact metal pattern and the second contact pad.

17. A memory device comprising: a plurality of sub-array regions, each sub-array region comprising a plurality of memory cells; a dummy region adjacent to the plurality of sub-array regions, the dummy region comprising a first metal pattern extending in a first horizontal direction at a first layer, a first via contact extending in a vertical direction on the first metal pattern, a second metal pattern contacting the first via contact and extending in a second horizontal direction at a second layer, a first lower contact extending in a vertical direction on the first metal pattern, and a second lower contact extending in the vertical direction on the second metal pattern; as well as The peripheral circuit region includes a first upper contact connected to the first lower contact, a first test circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second test circuit connected to the second upper contact.

18. The memory device of claim 17, wherein: The fictitious area also includes: a third metal pattern extending in a first horizontal direction at a third layer; a third lower contact disposed on the first portion of the third metal pattern and extending in a vertical direction; and a fourth lower contact disposed on the second portion of the third metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a third upper contact connected to the third lower contact; a first circuit connected to the third upper contact; a fourth upper contact connected to the fourth lower contact; and A second circuit is connected to the fourth upper contact.

19. The memory device of claim 18, wherein: The third metal pattern has a lower resistance than at least one of the first metal pattern and the second metal pattern.

20. The memory device of claim 17, wherein: The fictitious area also includes: a first power metal pattern extending in a first horizontal direction at a third layer; a fifth lower contact disposed on the first power metal pattern and extending in a vertical direction; a second power metal pattern extending in a second horizontal direction at the fourth layer; and a sixth lower contact disposed on the second power metal pattern and extending in a vertical direction, and Among them, the peripheral circuit area also includes: a fifth upper contact connected to the fifth lower contact; a first power circuit connected to the fifth upper contact; a sixth upper contact connected to the sixth lower contact; and A second power circuit is connected to the sixth upper contact.

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