Memory structure and method for forming the same

Abstract

A memory structure and a method for forming the same, the method comprising: forming a plurality of pad structures and an active layer on the surface of the pad structures on a substrate, wherein the pad structures are arranged in an array along a second direction and a first direction, the active layer covers the top of the pad structures and the sidewalls of the pad structures along the first direction, the active layer exposes the sidewalls of the pad structures along the second direction, and the active layer extends along the first direction and is arranged parallel to the second direction; forming an isolation structure between adjacent pad structures in the second direction and forming a plurality of floating gates on the surface of the active layer on each pad structure, wherein the top surface of the isolation structure is higher than or flush with the bottom surface of the active layer, and the floating gates are located between adjacent isolation structures in the second direction; forming a plurality of control gates on the surface of the floating gates and the surface of the isolation structure, wherein each control gate spans the plurality of floating gates along the second direction, and each control gate extends along the second direction and is arranged parallel to the first direction. The pad structures increase the channel length of the active layer, improving the short-channel effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and its formation method. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and greater circuit complexity. In the process of integrated circuit development, functional density typically increases while geometric dimensions gradually decrease, increasing the difficulty and complexity of integrated circuit manufacturing.

[0003] Flash memory has been rapidly adopted as a mainstream storage medium, and its technology has also developed rapidly. Flash memory is divided into NOR (Not Or, NOR) flash memory and NAND (Not And, NAND) flash memory. NOR flash memory, as a type of flash memory, has received widespread attention due to its high programming speed and erasing capability. Currently, NOR flash memory is widely used in personal computers, digital devices, mobile terminals, automotive components, and other products.

[0004] However, current NOR flash memory architectures still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a memory structure and a method for forming the same, so as to improve the performance of the memory structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of mutually discrete pad structures and an active layer located on the surface of the pad structures on the substrate, wherein each of the pad structures is arranged in an array along a second direction and a first direction, the first direction being perpendicular to the second direction, the active layer covering the top of the pad structure and the sidewalls of the pad structure along the first direction, the active layer exposing the sidewalls of the pad structure along the second direction, the active layer extending along the first direction and arranged parallel to the second direction; forming an isolation structure between adjacent pad structures in the second direction and forming a plurality of mutually discrete floating gates on the surface of the active layer on each pad structure, the top surface of the isolation structure being higher than or flush with the surface of the active layer, the floating gates being located between adjacent isolation structures in the second direction; forming a plurality of control gates on the surface of the floating gates and the surface of the isolation structures, each of the control gates spanning the plurality of floating gates along the second direction, each of the control gates extending along the second direction and arranged parallel to the first direction.

[0007] Optionally, the floating gate is formed before the isolation structure is formed, and the floating gate, the pad structure, and the active layer are formed simultaneously.

[0008] Optionally, the method for forming the pad structure, active layer, and floating gate includes: forming a pad material layer on the substrate surface; forming a first mask layer on the surface of the pad material layer, the first mask layer extending along a second direction and arranged parallel to a first direction, the first mask layer exposing a portion of the surface of the pad material layer; using the first mask layer as a mask, etching the pad material layer using a first etching process until the substrate surface is exposed, forming an initial pad layer and a plurality of first openings located between adjacent initial pad layers, each first opening extending along a second direction and arranged parallel to a first direction, each first opening having a first projection in a direction parallel to the substrate surface; forming an active material layer on the initial pad layer and the substrate surface; forming a second mask layer on the surface of the active material layer, the second mask layer extending along a second direction and arranged parallel to a first direction, the second mask layer exposing a portion of the surface of the active material layer; using the second ... an active material layer on the initial pad layer and the substrate surface; forming a second mask layer on the surface of the active material layer, the second mask layer extending along a second direction and arranged parallel to a first direction, the second mask layer exposing a portion of the surface of the active material layer The active material layer is etched using a second etching process to form an initial active layer and a plurality of second openings located between the initial active layers. Each second opening extends along a second direction and is arranged parallel to a first direction. Each second opening has a second projection in a direction parallel to the substrate surface, and the second projection is located within the first projection range. An initial floating gate layer is formed on the surface of the initial active layer. A third mask layer is formed on the surface of the initial floating gate layer. The third mask layer extends along a first direction and is arranged parallel to a second direction. The third mask layer exposes a portion of the surface of the initial floating gate layer. Using the third mask layer as a mask, the initial floating gate layer, the initial active layer, and the initial pad layer are etched using a third etching process until the substrate surface is exposed, forming the pad layer structure, the active layer, the floating gate, and the third opening located between the pad layer structure, the active layer, and the floating gate. Each third opening exposes the substrate surface and extends along a first direction.

[0009] Optionally, the cross-sectional shape of the cushion structure along the first direction includes a trapezoidal shape.

[0010] Optionally, before forming the initial floating gate layer and after forming the initial active layer, the method further includes: forming a first insulating layer on the surface of the initial active layer; the material of the first insulating layer includes: silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

[0011] Optionally, the method for forming the control gate includes: forming a control gate material layer on the surface of the isolation structure and the surface of the floating gate; forming a fourth mask layer on the surface of the control gate material layer, the fourth mask layer extending along a second direction and arranged parallel to a first direction, the fourth mask layer exposing a portion of the surface of the control gate material layer; using the fourth mask layer as a mask, etching the control gate material layer and the floating gate using a fourth etching process to form a fourth opening and a fifth opening located in the control gate material layer and the floating gate, each of the fourth openings and each of the fifth openings being located between adjacent pad structures and adjacent to each of the fourth openings and each of the fifth openings along the first direction, each of the fourth openings and each of the fifth openings extending along the second direction, and each of the fourth openings and each of the fifth openings exposing the surface of the first insulating layer.

[0012] Optionally, the fourth opening is larger in size in the first direction than the fifth opening in the first direction.

[0013] Optionally, the method for forming the isolation structure includes: forming an initial isolation structure that fills each of the third openings; performing a back-etching process on the initial isolation structure until the top surface of the initial isolation structure is flush with the bottom surface of the active layer, thereby forming the isolation structure.

[0014] Optionally, after forming the control gate, the method further includes: forming a fifth mask layer on the control gate surface and within the fifth opening, the fifth mask layer extending along a second direction and arranged parallel to a first direction, the fifth mask layer exposing the fourth opening; performing a drain light doping treatment on the active layer surface at the bottom of the fourth opening to form a drain lightly doped region; forming a sixth mask layer on the control gate surface and within the fourth opening, the sixth mask layer extending along a second direction and arranged parallel to a first direction, the sixth mask layer exposing the fifth opening; using the sixth mask layer as a mask, etching the first dielectric layer at the bottom of the fifth opening and the isolation structure at the bottom of the fifth opening using a fifth etching process; and after the fifth etching process, performing source heavy doping on the substrate surface and the active layer surface at the bottom of the fifth opening. The process involves forming source regions, connecting adjacent source regions parallel to a first direction to form a common source line parallel to a second direction, wherein the lightly doped drain region and the common source line are adjacent along the first direction and a pad structure exists between adjacent lightly doped drain regions and the common source line; a second dielectric layer is formed between adjacent control gates and on the surface of the control gates; a plurality of sixth openings are formed within the second dielectric layer, each sixth opening exposing the surface of the active layer, each sixth opening being located within the lightly doped drain region in the first direction and between adjacent pad structures in the first direction; the active layer surface at the bottom of each sixth opening is heavily doped with drain material; and a conductive plug is formed within each sixth opening, the conductive plug being connected to the lightly doped drain region.

[0015] Optionally, the light doping method of the drain electrode includes ion implantation; the parameters of the ion implantation include: arsenic and phosphorus ions, ion implantation energy between 10 keV and 50 keV, and ion implantation dose of 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 The source heavy doping method includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10 keV and 50 keV, and ion implantation dose is 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

[0016] Optionally, before forming the control gate material layer and after forming the isolation structure, the method further includes forming a first dielectric layer on the substrate surface of the isolation structure.

[0017] Accordingly, the present invention also provides a memory structure, comprising: a substrate; a plurality of mutually discrete pad structures located on the substrate, each of the pad structures being arranged in an array along a second direction and a first direction, the first direction being perpendicular to the second direction; an active layer located on the surface of the substrate and the surface of the pad structures, the active layer covering the top of the pad structures and the sidewalls of the pad structures along the first direction, the active layer exposing the sidewalls of the pad structures along the second direction, the active layer extending along the first direction and arranged parallel to the second direction; an isolation structure located between adjacent pad structures in the second direction, the top surface of the isolation structure being higher than or flush with the bottom surface of the active layer; a plurality of mutually discrete floating gates, each floating gate being located on the surface of the active layer on each pad structure, the floating gate being located between adjacent isolation structures in the second direction; and a plurality of control gates located on the surface of the floating gates and the surface of the isolation structures, each control gate spanning the plurality of floating gates along the second direction, each control gate extending along the second direction and arranged parallel to the first direction.

[0018] Optionally, the substrate material includes silicon, silicon carbide, gallium arsenide, and gallium nitride; the pad structure material includes silicon oxide, silicon nitride, and silicon oxynitride; the thickness of the pad structure ranges from 50 nm to 300 nm; and the angle formed by the pad structure and the substrate ranges from 30° to 90°.

[0019] Optionally, the cross-sectional shape of the cushion structure along the first direction includes a trapezoidal shape.

[0020] Optionally, it may also include: a first insulating layer located between the active layer and the floating gate; the material of the first insulating layer includes: silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

[0021] Optionally, it further includes: a plurality of fourth openings and a plurality of fifth openings located between adjacent control gates, each of the fourth openings and each of the fifth openings being located between adjacent pad structures and adjacent to each of the fourth openings and each of the fifth openings along a first direction, the fourth openings and the fifth openings exposing the surface of the first insulating layer, the dimension of the fourth openings along the direction parallel to the substrate surface being greater than the dimension of the fifth openings along the direction parallel to the substrate surface, and each of the fourth openings and each of the fifth openings extending along a second direction.

[0022] Optionally, it also includes: a lightly doped drain region located at the bottom of the fourth opening; a source region located at the bottom of the fifth opening; a common source line connecting adjacent source regions parallel to the first direction; the doping method of the lightly doped drain region includes ion implantation; the parameters of the ion implantation include: arsenic and phosphorus ions, ion implantation energy between 10 keV and 50 keV, and ion implantation dose of 5E13 atoms / cm 2 Up to 5E15 atoms / cm2 The doping method of the source region includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10 keV and 50 keV, and ion implantation dose is 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

[0023] Optionally, it further includes: a second dielectric layer located on the surface of the fourth opening, the fifth opening, and the control gate; a sixth opening located within the second dielectric layer, each of the sixth openings exposing the surface of the active layer, each of the sixth openings being located within the lightly doped drain region in a first direction and between adjacent pad structures in the first direction; a heavily doped drain region located at the bottom of each of the sixth openings; and a conductive plug located within each of the sixth openings, the conductive plug being connected to the lightly doped drain region.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] The memory structure of the present invention includes several mutually discrete pad structures on a substrate, and an active layer on the substrate and the pad structures. On one hand, there is an isolation structure between adjacent pad structures in a second direction. The pad structures are three-dimensional structures. Compared with two-dimensional planar structures, the presence of the pad structures effectively increases the channel length of the active layer and improves the short-channel effect. On the other hand, the shape of the pad structures is controllable, and the surface of the active layer has several floating gates, which can make the floating gates on the pad structures have sharp corners, thereby improving the erasure efficiency of the floating gates.

[0026] In the method for forming the memory structure of the present invention, a plurality of mutually discrete pad structures and an active layer located on the surface of the pad structures are formed on a substrate. On the one hand, an isolation structure is formed between adjacent pad structures in a second direction. The pad structure is a three-dimensional structure. Compared with a two-dimensional planar structure, the presence of the pad structure effectively increases the channel length of the active layer and improves the short-channel effect. On the other hand, the shape of the pad structure is controllable. A plurality of floating gates are formed on the surface of the active layer, which can make the floating gates formed on the pad structure have sharp corners, thereby improving the erasure efficiency of the floating gates. Attached Figure Description

[0027] Figures 1 to 53 This is a schematic diagram of the steps in the method for forming a memory structure according to an embodiment of the present invention. Detailed Implementation

[0028] As described in the background section, the existing NOT OR (NOR) type flash memory structure still has many problems.

[0029] In one embodiment of a flash memory, the flash memory requires a smaller process node, but the reduction in the geometry of the flash memory leads to a reduction in channel length, resulting in a short-channel effect.

[0030] To address the aforementioned technical problems, the present invention provides a memory structure and its formation method. A plurality of mutually discrete pad structures and an active layer located on the surface of the pad structures are formed on a substrate. On one hand, an isolation structure is formed between adjacent pad structures in a second direction. The pad structures are three-dimensional structures. Compared to two-dimensional planar structures, the presence of the pad structures effectively increases the channel length of the active layer and improves the short-channel effect. On the other hand, the shape of the pad structures is controllable. A plurality of floating gates are formed on the surface of the active layer, allowing the floating gates formed on the pad structures to have sharp corners, thereby improving the erasure efficiency of the floating gates.

[0031] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 53 This is a schematic diagram illustrating the formation process of the memory structure according to an embodiment of the present invention.

[0033] Please refer to Figure 1 Substrate 100 is provided.

[0034] The substrate 100 is made of materials including silicon, silicon carbide, gallium nitride, and gallium arsenide.

[0035] The substrate 100 provides a structural basis for the subsequent formation of the pad structure 109.

[0036] A plurality of mutually discrete pad structures 109 and an active layer 110 located on the surface of the pad structures 109 are formed on the substrate 100. Each pad structure 109 is arranged in an array along a second direction and a first direction, the first direction being perpendicular to the second direction. The active layer 110 covers the top of the pad structure 109 and the sidewalls of the pad structure 109 along the first direction, and exposes the sidewalls of the pad structure 109 along the second direction. The active layer 110 extends along the first direction and is arranged parallel to the second direction. (See details below.) Figures 2 to 17 .

[0037] Please refer to Figure 2 and Figure 3 , Figure 2 for Figure 3 Top view, Figure 3 yes Figure 2A cross-sectional view along the AA' direction shows a pad material layer 101 formed on the surface of the substrate 100; a first mask layer (not shown) is formed on the surface of the pad material layer 101, the first mask layer (not shown) extends along a second direction and is arranged parallel to the first direction, and the first mask layer (not shown) exposes a portion of the surface of the pad material layer 101.

[0038] The cushion material layer 101 provides a structural basis for the subsequent formation of the cushion structure 109.

[0039] The material of the padding material layer 101 includes silicon oxide, silicon nitride, and silicon oxynitride.

[0040] The thickness of the padding material layer 101 ranges from 50 nm to 300 nm.

[0041] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 Top view, Figure 5 yes Figure 4 A cross-sectional view along the AA' direction, using the first mask layer (not shown) as a mask, the pad material layer 101 is etched using the first etching process (e.g., ...). Figure 3 (As shown) until the surface of the substrate 100 is exposed, forming an initial pad 102 and a plurality of first openings 103 located between adjacent initial pads 102, each first opening 103 extending along a second direction and arranged in parallel along a first direction, each first opening 103 having a first projection a in a direction parallel to the surface of the substrate 100. The first etching process includes dry etching.

[0042] The materials of the initial pad 102 include silicon oxide, silicon nitride, and silicon oxynitride.

[0043] The thickness of the initial pad 102 ranges from 50 nm to 300 nm.

[0044] The shape of the cross section of the initial pad 102 along the first direction includes: trapezoidal, arc-shaped and square; specifically, in this embodiment, the shape of the cross section of the initial pad 102 along the first direction is trapezoidal.

[0045] The initial pad 102 provides a structural basis for the subsequent formation of the pad structure 109. On the one hand, it makes the subsequently formed pad structure 109 a three-dimensional structure. Compared with the two-dimensional planar structure, the presence of the pad structure 109 effectively increases the channel length of the subsequently formed active layer 110 and improves the short channel effect. On the other hand, the shape of the subsequently formed pad structure 109 is controllable, which allows the floating gate 111 located on the pad structure 109 to have sharp corners, thereby improving the erasure efficiency of the floating gate.

[0046] The depth range of the first opening 103 is 50nm to 300nm.

[0047] The first opening 103 provides the structural basis for the subsequent formation of the fourth opening 117 and the fifth opening 118.

[0048] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 Top view, Figure 7 yes Figure 6 A cross-sectional view along the AA' direction shows an active material layer 104 formed on the surfaces of the initial pad layer 102 and the substrate 100; a second mask layer (not shown) is formed on the surface of the active material layer 104, the second mask layer (not shown) extending along a second direction and arranged parallel to a first direction, the second mask layer (not shown) exposing a portion of the surface of the active material layer 104.

[0049] The active material layer 104 provides a structural basis for the subsequent formation of the initial active layer 105. The active material layer 104 is formed on the surface of the initial pad layer 102, and the cross-section of the initial pad layer 102 along the first direction is trapezoidal, so that the cross-section of the subsequently formed initial active layer 105 along the first direction has an obtuse angle, and the subsequently formed floating grid 111 has a sharp angle, thereby improving the erasure efficiency of the floating grid.

[0050] The active material layer 104 includes materials such as monocrystalline silicon, silicon carbide, polycrystalline silicon, gallium arsenide, and gallium nitride.

[0051] The thickness of the active material layer 104 ranges from 100 nm to 500 nm.

[0052] Please refer to Figure 8 and Figure 9 , Figure 8 for Figure 9 Top view, Figure 9 yes Figure 8 A cross-sectional view along the AA' direction, using the second mask layer (not shown) as a mask, shows the active material layer 104 etched using a second etching process (e.g., ...). Figure 7 As shown), an initial active layer 105 is formed and a plurality of second openings 106 are located between the initial active layer 105. Each second opening 106 extends along a second direction and is arranged in parallel along a first direction. Each second opening 106 has a second projection b in a direction parallel to the surface of the substrate 100, and the second projection b is located within the range of the first projection a.

[0053] The second etching process includes dry etching.

[0054] The materials of the initial active layer 105 include: single-crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide, and gallium nitride.

[0055] The thickness of the initial active layer 105 ranges from 100 nm to 500 nm.

[0056] The initial active layer 105 is formed on the surface of the initial pad layer 102 and the cross-section of the initial pad layer 102 along the first direction is trapezoidal, so that the cross-section of the initial active layer 105 along the first direction has an obtuse angle, so that the subsequently formed floating grid 111 has a sharp angle, thereby improving the erasure efficiency of the floating grid.

[0057] The depth range of the second opening 106 is 50nm to 300nm.

[0058] The second opening 106 provides the structural basis for the subsequent formation of the fourth opening 117 and the fifth opening 118.

[0059] Please refer to Figure 10 and Figure 11 , Figure 10 for Figure 11 Top view, Figure 11 yes Figure 10 A cross-sectional view along the AA' direction shows that a first insulating layer 107 is formed on the surface of the initial active layer 105.

[0060] The materials of the first insulating layer 107 include silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

[0061] The thickness of the first insulating layer 107 ranges from 2 nm to 15 nm.

[0062] The function of the first insulating layer 107 is to isolate the initial active layer 105 from the subsequently formed initial floating gate layer 108.

[0063] Please refer to Figure 12 and Figure 13 , Figure 12 for Figure 13 Top view, Figure 13 yes Figure 12 A cross-sectional view along the AA' direction shows an initial floating gate layer 108 formed on the surface of the initial active layer 105; a third mask layer (not shown) is formed on the surface of the initial floating gate layer 108, the third mask layer (not shown) extending along a first direction and arranged parallel to a second direction, the third mask layer (not shown) exposing a portion of the surface of the initial floating gate layer 108.

[0064] The initial floating gate layer 108 provides the structural basis for the subsequent formation of the floating gate 111. Since the cross-section of the initial active layer 105 along the first direction has an obtuse angle, the subsequently formed floating gate 111 has a sharp angle, which improves the erasure efficiency of the floating gate.

[0065] The material of the initial floating gate layer 108 includes polycrystalline silicon.

[0066] The thickness of the initial floating gate layer 108 ranges from 120 nm to 600 nm.

[0067] Please refer to Figures 14 to 17 , Figure 14 for Figures 15 to 17 Top view, Figure 15 yes Figure 14 A cross-sectional view along the AA' direction. Figure 16 yes Figure 14 A cross-sectional view along the BB' direction. Figure 17 yes Figure 14 A cross-sectional view along the CC' direction, using the third mask layer (not shown) as a mask, shows the initial floating gate layer 108 etched using a third etching process (e.g., ...). Figure 13 As shown), the initial active layer 105 (as shown) Figure 13 As shown), and the initial padding layer 102 (as shown) Figure 13 As shown), until the surface of the substrate 100 is exposed, the pad structure 109, the active layer 110, the floating gate 111, and the third opening 112 located between the pad structure 109, the active layer 110, and the floating gate 111 are formed, each of the third openings 112 exposing the surface of the substrate 100 and each of the third openings 112 extending along a first direction.

[0068] The cross-sectional shape of the cushion structure 109 along the first direction includes: square and trapezoidal.

[0069] Specifically, in this embodiment, the cross-sectional shape of the cushion structure 109 along the first direction includes a trapezoidal shape.

[0070] The thickness of the pad structure 109 ranges from 50 nm to 300 nm; the angle formed by the pad structure 109 and the substrate 100 ranges from 30° to 90°.

[0071] On the one hand, the pad structure 109 is a three-dimensional structure. Compared with the two-dimensional planar structure, the presence of the pad structure 109 effectively increases the channel length of the active layer 110 and improves the short channel effect. On the other hand, the cross section of the pad structure 109 along the first direction is trapezoidal, which allows the floating grid 111 formed on the pad structure 109 to have sharp corners, thereby improving the erasure efficiency of the floating grid.

[0072] Specifically, in this embodiment, the floating gate 111 is formed before the isolation structure 114 is formed, and the floating gate 111, the pad structure 109 and the active layer 110 are formed simultaneously.

[0073] The third etching process includes dry etching.

[0074] The active layer 110 is made of materials including: single-crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide, and gallium nitride.

[0075] The thickness of the active layer 110 ranges from 100 nm to 500 nm.

[0076] The active layer 110 is formed on the surface of the pad structure 109 and the cross-section of the pad structure 109 along the first direction is trapezoidal, so that the cross-section of the active layer 110 along the first direction has an obtuse angle, so that the subsequently formed floating grid 111 has a sharp angle, thereby improving the erasure efficiency of the floating grid.

[0077] The depth range of the third opening 112 is 150nm to 650nm.

[0078] The third opening 112 provides a structural basis for the subsequent formation of the isolation structure 114.

[0079] An isolation structure 114 is formed between adjacent pad structures 109 in the second direction, and a plurality of mutually independent floating gates 111 are formed on the surface of the active layer 110 on each pad structure 109. The top surface of the isolation structure 114 is higher than or flush with the bottom surface of the active layer 110, and the floating gates 111 are located between adjacent isolation structures 114 in the second direction. Please refer to [reference needed] for details. Figures 18 to 25 .

[0080] Please refer to Figures 18 to 21 , Figure 18 for Figures 19 to 21 Top view, Figure 19 yes Figure 18 A cross-sectional view along the AA' direction. Figure 20 yes Figure 18 A cross-sectional view along the BB' direction. Figure 21 yes Figure 18 A cross-sectional view along the CC' direction shows an initial isolation structure 113 forming within each of the third openings 112, filling the third opening 112.

[0081] The initial isolation structure 113 provides the structural basis for the subsequent formation of the isolation structure 114.

[0082] The materials of the initial isolation structure 113 include silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0083] Please refer to Figures 22 to 25 , Figure 22 for Figures 23 to 25 Top view, Figure 23 yes Figure 22 A cross-sectional view along the AA' direction. Figure 24 yes Figure 22 A cross-sectional view along the BB' direction. Figure 25 yes Figure 22 A cross-sectional view along the CC' direction, showing the initial isolation structure 113 (e.g.) Figure 21 (As shown) Perform back etching process until the top surface of the initial isolation structure 113 is flush with the bottom surface of the active layer 110 to form the isolation structure 114.

[0084] The etching method described is dry etching.

[0085] The materials of the isolation structure 114 include: silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0086] Specifically, in this embodiment, the top surface of the isolation structure 114 is higher than or flush with the bottom surface of the active layer 110.

[0087] Please refer to Figures 26 to 29 , Figure 26 for Figures 27 to 29 Top view, Figure 27 yes Figure 26 A cross-sectional view along the AA' direction. Figure 28 yes Figure 26 A cross-sectional view along the BB' direction. Figure 29 yes Figure 26 The cross-sectional view along the CC' direction, after the isolation structure 114 is formed, also includes: forming a first dielectric layer 115 on the surfaces of the isolation structure 114 and the substrate 100.

[0088] The material of the first dielectric layer 115 includes silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

[0089] The function of the first dielectric layer 115 is to isolate the floating gate 111 from the subsequently formed control gate material layer 116.

[0090] A plurality of control gates 119 are formed on the surface of the floating gate 111 and the surface of the isolation structure 114. Each control gate 119 spans the plurality of floating gates 111 along a second direction, and each control gate 119 extends along the second direction and is arranged parallel to the first direction. Please refer to the following for details. Figures 30 to 37 .

[0091] Please refer to Figures 30 to 33 , Figure 30 for Figures 31 to 33 Top view, Figure 31 yes Figure 30 A cross-sectional view along the AA' direction. Figure 32 yes Figure 30 A cross-sectional view along the BB' direction. Figure 33 yes Figure 30 A cross-sectional view along the CC' direction shows that a control gate material layer 116 is formed on the surface of the isolation structure 114 and the surface of the floating gate 111; a fourth mask layer (not shown) is formed on the surface of the control gate material layer 116, the fourth mask layer (not shown) extends along a second direction and is arranged parallel to the first direction, and the fourth mask layer (not shown) exposes a portion of the surface of the control gate material layer 116.

[0092] The material of the control gate material layer 116 includes polycrystalline silicon.

[0093] The control gate material layer 116 provides the structural basis for the subsequent formation of the control gate 119.

[0094] Please refer to Figures 34 to 37 , Figure 34 for Figures 35 to 37 Top view, Figure 35 yes Figure 34 A cross-sectional view along the AA' direction. Figure 36 yes Figure 34 A sectional view along the CC' direction. Figure 37 yes Figure 34 A cross-sectional view along the DD' direction, using the fourth mask layer (not shown) as a mask, shows the control gate material layer 116 etched using the fourth etching process (e.g., ...). Figure 31 (as shown) and floating gate 111 (as shown) Figure 31 As shown, a fourth opening 117 and a fifth opening 118 are formed within the control gate material layer 116 and the floating gate 111. Each of the fourth openings 117 and the fifth openings 118 is located between adjacent pad structures 109 and is adjacent to each other along a first direction. Each of the fourth openings 117 and the fifth openings 118 extends along a second direction and exposes the surface of the first insulating layer 107.

[0095] Specifically, in this embodiment, while forming the fourth opening 117 and the fifth opening 118, the control gate 119 is formed with the control gate material layer 116.

[0096] The control gate 119 spans several floating gates 111 along the second direction, and the control gate 119, the floating gates 111, the active layer 110, and the subsequently formed common source line 121 and drain lightly doped region 120 together form a word line.

[0097] The fourth etching process includes dry etching. The fourth etching process stops after etching to the bottom first dielectric layer 115, leaving the bottom isolation structure 114.

[0098] Specifically, in this embodiment, the fourth opening 117 is larger in size in the first direction than the fifth opening 118 is in size in the first direction.

[0099] The fourth opening 117 provides a structural basis for the subsequent formation of the drain lightly doped region 120; the fifth opening 118 provides a structural basis for the subsequent formation of the common source electrode line 121.

[0100] After forming the control gate 119, a fifth mask layer (not shown) is formed on the surface of the control gate 119 and within the fifth opening 118. The fifth mask layer (not shown) extends along a second direction and is arranged parallel to a first direction. The fifth mask layer (not shown) exposes the fourth opening 117. The surface of the active layer 110 at the bottom of the fourth opening 117 is lightly doped to form a lightly doped drain region 120. A sixth mask layer (not shown) is formed on the surface of the control gate 119 and within the fourth opening 117. The sixth mask layer (not shown) extends along a second direction and is arranged parallel to a first direction. The sixth mask layer (not shown) exposes the fifth opening 118. Using the sixth mask layer as a mask, a fifth etching process is used to etch the first dielectric layer 115 at the bottom of the fifth opening 118 and the isolation structure 114 at the bottom of the fifth opening 118. After the fifth etching process, the substrate 100 surface and the active layer 110 surface at the bottom of the fifth opening 118 are subjected to heavy source doping to form a source region. Adjacent source regions parallel to the first direction are connected together to form a common source line 121 parallel to the second direction. The lightly doped drain region 120 and the common source line 121 are adjacent along the first direction, and a pad structure 109 is provided between adjacent lightly doped drain regions 120 and the common source line 121. A layer is formed between adjacent control gates 119 and on the surface of the control gates 119. A second dielectric layer 122 is formed therein; a plurality of sixth openings 123 are formed therein, each of the sixth openings 123 exposing the surface of the active layer 110, each of the sixth openings 123 being located within the lightly doped drain region 120 in a first direction and between adjacent pad structures 109 in the first direction; the active layer surface at the bottom of each of the sixth openings is heavily doped for drain; a conductive plug 124 is formed within each of the sixth openings 123, the conductive plug 124 being connected to the lightly doped drain region 120. Please refer to [reference needed] for details. Figures 38 to 49 .

[0101] Please refer to Figures 38 to 41 , Figure 38 for Figures 39 to 41 Top view, Figure 39 yes Figure 38 A cross-sectional view along the AA' direction. Figure 40 yes Figure 38 A sectional view along the CC' direction. Figure 41 yes Figure 38 A cross-sectional view along the DD' direction shows a fifth mask layer (not shown) formed on the surface of the control gate 119 and within the fifth opening 118. The fifth mask layer (not shown) extends along the second direction and is arranged parallel to the first direction, exposing the fourth opening 117. The surface of the active layer 110 at the bottom of the fourth opening 117 is lightly doped to form a lightly doped drain region 120. A sixth mask layer (not shown) is formed on the surface of the control gate 119 and within the fourth opening 117. The sixth mask layer (not shown) extends along the second direction and is arranged parallel to the first direction, exposing the fifth opening 118. The sixth mask layer is used as a mask. The first dielectric layer 115 at the bottom of the fifth opening 118 and the isolation structure 114 at the bottom of the fifth opening 118 are etched using the fifth etching process. After the fifth etching process, the surface of the substrate 100 and the surface of the active layer 110 at the bottom of the fifth opening 118 are subjected to source doping treatment to form a source region. The source regions that are adjacent to each other in the first direction are connected together to form a common source line 121 that is parallel to the second direction. The drain lightly doped region 120 and the common source line 121 are adjacent to each other in the first direction and a pad structure 109 is provided between the drain lightly doped region 120 and the common source line 121.

[0102] The lightly doped drain electrode is achieved through ion implantation; the ion implantation parameters include: arsenic and phosphorus ions, an implantation energy between 10 keV and 50 keV, and an implantation dose of 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 The source heavy doping method includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10 keV and 50 keV, and ion implantation dose is 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

[0103] The lightly doped drain region 120 is connected to the subsequently formed conductive plug 124.

[0104] Please refer to Figures 42 to 45 , Figure 42 for Figures 43 to 45 Top view, Figure 43 yes Figure 42 A cross-sectional view along the AA' direction. Figure 44 yes Figure 42A cross-sectional view along the BB' direction. Figure 45 yes Figure 42 A cross-sectional view along the CC' direction shows that a second dielectric layer 122 is formed between adjacent control gates 119 and on the surface of the control gates 119.

[0105] The material of the second dielectric layer 122 includes silicon oxide.

[0106] The method for forming the second dielectric layer 122 includes: forming an initial second dielectric layer (not shown) between adjacent control gates 119 and on the surface of the control gates 119; performing planarization on the initial second dielectric layer (not shown), wherein the thickness of the second dielectric layer 122 after planarization is 100 nm above the surface of the control gates 119.

[0107] Please refer to Figures 46 to 49 , Figure 46 for Figures 47 to 49 Top view, Figure 47 yes Figure 46 A cross-sectional view along the AA' direction. Figure 48 yes Figure 46 A cross-sectional view along the BB' direction. Figure 49 yes Figure 46 A cross-sectional view along the CC' direction shows that a plurality of sixth openings 123 are formed in the second dielectric layer 122, each of the sixth openings 123 exposing the surface of the active layer 110, each of the sixth openings 123 being located in the first direction within the lightly doped drain region 120 and between adjacent pad structures 109 in the first direction; the surface of the active layer 110 at the bottom of each of the sixth openings 123 is heavily doped for drain.

[0108] The method for forming the sixth opening 123 includes: forming a seventh mask layer on the surface of the control gate 119, the seventh mask layer extending along a second direction and arranged parallel to a first direction, the seventh mask layer exposing a portion of the surface of the control gate 119; using the seventh mask layer (not shown) as a mask, etching the second dielectric layer 122 using a sixth etching process to form a plurality of sixth openings 123 located within the second dielectric layer 122.

[0109] The sixth opening 123 provides a structural basis for the subsequent formation of the conductive plug 124.

[0110] The projection of the sixth opening 123 in a direction parallel to the surface of the substrate 100 is located at the fourth opening 117 (e.g., Figure 39 (As shown) within the projection direction parallel to the surface of substrate 100.

[0111] The depth range of the sixth opening 123 is 200nm to 700nm.

[0112] The parameters for heavy doping of the sixth opening include: arsenic and phosphorus ions, ion implantation energy between 10 keV and 50 keV, and ion implantation dose of 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

[0113] Please refer to Figures 50 to 53 , Figure 50 for Figures 51 to 53 Top view, Figure 51 yes Figure 50 A cross-sectional view along the AA' direction. Figure 52 yes Figure 50 A cross-sectional view along the BB' direction. Figure 53 yes Figure 50 A cross-sectional view along the CC' direction shows that conductive plugs 124 are formed in each of the sixth openings 123, and the conductive plugs 124 are connected to the lightly doped drain region 120.

[0114] The conductive plug 124 is made of tungsten and copper.

[0115] Specifically, in this embodiment, the conductive plug 124 is connected to the lightly doped drain region 120, and is connected to the subsequently formed metal layer through the lightly doped drain region 120, the control gate 119, and the common source line 121, thereby realizing the programming, erasing, and read / write operations of the memory structure. On the one hand, the pad structure 109 is a three-dimensional structure, which effectively increases the channel length of the active layer 110 and improves the short-channel effect compared to the two-dimensional planar structure. On the other hand, the shape of the pad structure 109 is controllable, and a plurality of floating gates 111 are formed on the surface of the active layer 110, which can make the floating gates 111 formed on the pad structure 109 have sharp corners, thereby improving the erasing efficiency of the floating gates.

[0116] Accordingly, embodiments of the present invention also provide a memory structure, please refer to... Figures 50 to 53 , Figure 50 for Figures 51 to 53 Top view, Figure 51 yes Figure 50 A cross-sectional view along the AA' direction. Figure 52 yes Figure 50 A cross-sectional view along the BB' direction. Figure 53 yes Figure 50A cross-sectional view along the CC' direction includes: a substrate 100; a plurality of mutually discrete pad structures 109 located on the substrate 100, each of the pad structures 109 being arranged in an array along a second direction and a first direction, the first direction being perpendicular to the second direction; an active layer 110 located on the surface of the substrate 100 and the surface of the pad structures 109, the active layer 110 covering the top of the pad structures 109 and the sidewalls of the pad structures 109 along the first direction, the active layer 110 exposing the sidewalls of the pad structures 109 along the second direction, the active layer 110 extending along the first direction and arranged parallel to the second direction; an isolation junction. The isolation structure 114 is located between adjacent cushion structures 109 in a second direction, with its top surface higher than or flush with the bottom surface of the active layer 110; a plurality of mutually independent floating gates 111 are located on the surface of the active layer 110 on each cushion structure 109, with the floating gates 111 located between adjacent isolation structures 114 in a second direction; a plurality of control gates 119 are located on the surfaces of the floating gates 111 and the surfaces of the isolation structures 114, with each control gate 119 spanning the plurality of floating gates 111 in a second direction, and each control gate 119 extending in a second direction and arranged parallel to each other in a first direction.

[0117] The memory structure includes: substrate 100.

[0118] The substrate 100 is made of materials including silicon, silicon carbide, gallium nitride, and gallium arsenide.

[0119] The memory structure includes a plurality of mutually independent pad structures 109 located on the substrate 100, wherein each of the pad structures 109 is arranged in an array along a second direction and a first direction, and the first direction is perpendicular to the second direction.

[0120] The material of the pad structure 109 includes silicon oxide, silicon nitride, and silicon oxynitride; the thickness of the pad structure 109 ranges from 50 nm to 300 nm; and the angle formed by the pad structure 109 and the substrate 100 ranges from 30° to 90°.

[0121] The shape of the cross section of the cushion structure 109 along the first direction includes trapezoidal, arc-shaped and square; specifically, in this embodiment, the shape of the cross section of the cushion structure 109 along the first direction includes trapezoidal.

[0122] The memory structure includes an active layer 110 located on the surface of the substrate 100 and the surface of the pad structure 109. The active layer 110 covers the top of the pad structure 109 and the sidewalls of the pad structure 109 along a first direction. The active layer 110 exposes the sidewalls of the pad structure 109 along a second direction. The active layer 110 extends along the first direction and is arranged in parallel along the second direction.

[0123] The active layer 110 is made of materials including: single-crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide, and gallium nitride.

[0124] The thickness of the active layer 110 ranges from 100 nm to 500 nm.

[0125] The memory structure includes a first insulating layer 107 located between the active layer 110 and the floating gate 111.

[0126] The materials of the first insulating layer 107 include silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

[0127] The thickness of the first insulating layer 107 ranges from 2 nm to 15 nm.

[0128] The memory structure includes an isolation structure 114 located between adjacent pad structures 109 in a second direction, wherein the top surface of the isolation structure 114 is higher than or flush with the bottom surface of the active layer 110.

[0129] The materials of the isolation structure 114 include: silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0130] The memory structure includes: a plurality of mutually independent floating gates 111, each floating gate 111 being located on the surface of the active layer 110 on each pad structure 109, and the floating gate 111 being located between adjacent isolation structures 114 in a second direction.

[0131] The material of the floating gate 111 includes polycrystalline silicon.

[0132] The thickness of the floating gate 111 ranges from 120 nm to 600 nm.

[0133] The memory structure includes a plurality of control gates 119 located on the surface of the floating gate 111 and the surface of the isolation structure 114, each of the control gates 119 spanning the plurality of floating gates 111 along a second direction, and each of the control gates 119 extending along the second direction and arranged in parallel along a first direction.

[0134] The control gate 119 is made of polycrystalline silicon.

[0135] The memory structure includes a first dielectric layer 115 located between the floating gate 111 and the control gate 119.

[0136] The material of the first dielectric layer 115 includes silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

[0137] The memory structure includes: a plurality of fourth openings 117 located between adjacent control gates 119 (e.g., ... Figure 39 (as shown) and several fifth openings 118 (as shown) Figure 39 As shown, each of the fourth openings 117 and each of the fifth openings 118 are located between adjacent pad structures 109 and are adjacent to each other along a first direction. The fourth openings 117 and the fifth openings 118 expose the surface of the first insulating layer 107. The dimension of the fourth opening 117 along the direction parallel to the surface of the substrate 100 is larger than the dimension of the fifth opening 118 along the direction parallel to the surface of the substrate 100. Each of the fourth openings 117 and each of the fifth openings 118 extends along a second direction.

[0138] The memory structure includes: a lightly doped drain region 120 located on the bottom surface of the fourth opening 117; a source region located at the bottom of the fifth opening 118; and a common source line 121 connecting adjacent source regions parallel to the first direction. The doping method of the lightly doped drain region 120 includes ion implantation. The parameters of the ion implantation include: arsenic and phosphorus ions, an ion implantation energy between 10 keV and 50 keV, and an ion implantation dose of 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 The doping method of the source region includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10 keV and 50 keV, and ion implantation dose is 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

[0139] The memory structure includes: a second dielectric layer 122 located on the surfaces of the fourth opening 117, the fifth opening 118, and the control gate 119; a sixth opening 123 located within the second dielectric layer 122, each of the sixth openings 123 exposing the surface of the active layer 110, each of the sixth openings 123 being located within the lightly doped drain region 120 in a first direction and between adjacent pad structures 109 in the first direction; a heavily doped drain region located at the bottom of each of the sixth openings 123; and a conductive plug 124 located within each of the sixth openings 123, the conductive plug 124 being connected to the lightly doped drain region 120.

[0140] The material of the second dielectric layer 122 includes silicon oxide.

[0141] The depth range of the sixth opening 123 is 200nm to 700nm.

[0142] The drain heavy doping parameters of the sixth opening 123 include: arsenic and phosphorus ions, ion implantation energy between 10 keV and 50 keV, and ion implantation dose of 5E13 atoms / cm².2 Up to 5E15 atoms / cm 2 between.

[0143] The conductive plug 124 is made of tungsten and copper.

[0144] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory structure, characterized in that, include: Substrate; A plurality of mutually independent pad structures are located on the substrate, and each of the pad structures is arranged in an array along a second direction and a first direction, wherein the first direction is perpendicular to the second direction; An active layer is located on the surface of the substrate and the surface of the pad structure. The active layer covers the top of the pad structure and the sidewalls of the pad structure along a first direction. The active layer exposes the sidewalls of the pad structure along a second direction. The active layer extends along the first direction and is arranged in parallel along the second direction. An isolation structure is located between adjacent pad structures in a second direction, the top surface of the isolation structure being higher than or flush with the top surface of the active layer located on the substrate surface; A plurality of mutually independent floating gates, each floating gate being located on the active layer surface of each pad structure, wherein the floating gates are located between adjacent isolation structures in the second direction; A plurality of control gates are located on the surface of the floating gate and the surface of the isolation structure, each control gate spanning the plurality of floating gates along a second direction, and each control gate extending along the second direction and arranged in parallel along a first direction.

2. The memory structure as described in claim 1, characterized in that, The substrate is made of silicon, silicon carbide, gallium arsenide, and gallium nitride; the pad structure is made of silicon oxide, silicon nitride, and silicon oxynitride; the thickness of the pad structure ranges from 50 nm to 300 nm; and the angle between the pad structure and the substrate ranges from 30° to 90°.

3. The memory structure as described in claim 1, characterized in that, The cross-sectional shape of the cushion layer structure along the first direction includes a trapezoidal shape.

4. The memory structure as described in claim 1, characterized in that, Also includes: The first insulating layer is located between the active layer and the floating gate; The materials of the first insulating layer include silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

5. The memory structure as described in claim 4, characterized in that, Also includes: A plurality of fourth openings and a plurality of fifth openings are located between adjacent control gates, each of the fourth openings and each of the fifth openings being located between adjacent pad structures and adjacent to each of the fourth openings and each of the fifth openings along a first direction, the fourth openings and the fifth openings exposing the surface of the first insulating layer, the fourth openings having a larger dimension along the direction parallel to the substrate surface than the fifth openings having a larger dimension along the direction parallel to the substrate surface, and each of the fourth openings and each of the fifth openings extending along a second direction.

6. The memory structure as described in claim 5, characterized in that, Also includes: The drain lightly doped region is located at the bottom of the fourth opening; The source region located at the bottom of the fifth opening; Connect the common source pole line parallel to each adjacent source pole region in the first direction; The doping method of the lightly doped drain region includes ion implantation; the parameters of the ion implantation include: arsenic and phosphorus ions, ion implantation energy between 10 keV and 50 keV, and ion implantation dose of 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 The doping method of the source region includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10 keV and 50 keV, and ion implantation dose is 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

7. The memory structure as described in claim 6, characterized in that, Also includes: A second dielectric layer located on the surface of the fourth opening, the fifth opening, and the control gate; A sixth opening located within the second dielectric layer, each of the sixth openings exposing the surface of the active layer, each of the sixth openings being located within the lightly doped drain region in a first direction and being located between adjacent pad structures in the first direction; A heavily doped drain region located at the bottom of each of the sixth openings; a conductive plug located within each of the sixth openings, the conductive plug being connected to the lightly doped drain region.

8. A method for forming a memory structure, characterized in that, include: Provide substrate; A plurality of mutually discrete pad structures and an active layer located on the surface of the pad structures are formed on the substrate. Each pad structure is arranged in an array along a second direction and a first direction, the first direction being perpendicular to the second direction. The active layer covers the top of the pad structure and the sidewalls of the pad structure along the first direction, and exposes the sidewalls of the pad structure along the second direction. The active layer extends along the first direction and is arranged parallel to the second direction. An isolation structure is formed between adjacent pad structures in the second direction, and a plurality of mutually independent floating gates are formed on the active layer surface of each pad structure. The top surface of the isolation structure is higher than or flush with the top surface of the active layer located on the substrate surface, and the floating gates are located between adjacent isolation structures in the second direction. A plurality of control gates are formed on the surface of the floating gate and the surface of the isolation structure. Each control gate spans the plurality of floating gates along a second direction and extends along the second direction and is arranged in parallel along the first direction.

9. The method for forming the memory structure as described in claim 8, characterized in that, The floating gate is formed before the isolation structure is formed, and the floating gate, the padding structure, and the active layer are formed simultaneously.

10. The method for forming the memory structure as described in claim 8, characterized in that, The method for forming the pad structure, active layer, and floating gate includes: forming a pad material layer on the substrate surface; forming a first mask layer on the surface of the pad material layer, the first mask layer extending along a second direction and arranged parallel to the first direction, the first mask layer exposing a portion of the surface of the pad material layer; using the first mask layer as a mask, etching the pad material layer using a first etching process until the substrate surface is exposed, forming an initial pad layer and a plurality of first openings located between adjacent initial pad layers, each first opening extending along a second direction and arranged parallel to the first direction, each first opening having a first projection in a direction parallel to the substrate surface; forming an active material layer on the initial pad layer and the substrate surface; forming a second mask layer on the surface of the active material layer, the second mask layer extending along a second direction and arranged parallel to the first direction, the second mask layer exposing a portion of the surface of the active material layer; using the second ... an active material layer on the initial pad layer and the substrate surface; forming a second mask layer on the surface of the active material layer, the second mask layer extending along a second direction and arranged parallel to the first direction, the second mask layer exposing a portion of the surface of the active material layer; using the The active material layer is etched using a second etching process to form an initial active layer and a plurality of second openings located between the initial active layer. Each second opening extends along a second direction and is arranged parallel to a first direction. Each second opening has a second projection in a direction parallel to the substrate surface, and the second projection is located within the first projection range. An initial floating gate layer is formed on the surface of the initial active layer. A third mask layer is formed on the surface of the initial floating gate layer. The third mask layer extends along a first direction and is arranged parallel to a second direction. The third mask layer exposes a portion of the surface of the initial floating gate layer. Using the third mask layer as a mask, the initial floating gate layer, the initial active layer, and the initial pad layer are etched using a third etching process until the substrate surface is exposed, forming the pad layer structure, the active layer, the floating gate, and the third opening located between the pad layer structure, the active layer, and the floating gate. Each third opening exposes the substrate surface and extends along a first direction.

11. The method for forming the memory structure as described in claim 8, characterized in that, The cross-sectional shape of the cushion layer structure along the first direction includes a trapezoidal shape.

12. The method for forming the memory structure as described in claim 10, characterized in that, Before forming the initial floating gate layer and after forming the initial active layer, the method further includes: forming a first insulating layer on the surface of the initial active layer; the material of the first insulating layer includes: silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.

13. The method for forming the memory structure as described in claim 10, characterized in that, The method for forming the control gate includes: forming a control gate material layer on the surface of the isolation structure and the surface of the floating gate; forming a fourth mask layer on the surface of the control gate material layer, the fourth mask layer extending along a second direction and arranged parallel to a first direction, the fourth mask layer exposing a portion of the surface of the control gate material layer; using the fourth mask layer as a mask, etching the control gate material layer and the floating gate using a fourth etching process to form a fourth opening and a fifth opening located within the control gate material layer and the floating gate, each of the fourth openings and each of the fifth openings being located between adjacent pad structures and adjacent to each of the fourth openings and each of the fifth openings along the first direction, each of the fourth openings and each of the fifth openings extending along a second direction, and each of the fourth openings and each of the fifth openings exposing the surface of the first insulating layer.

14. The method for forming the memory structure as described in claim 13, characterized in that, The fourth opening is larger in size in the first direction than the fifth opening in the first direction.

15. The method for forming the memory structure as described in claim 10, characterized in that, The method for forming the isolation structure includes: forming an initial isolation structure that fills each of the third openings; performing a back etching process on the initial isolation structure until the top surface of the initial isolation structure is flush with the top surface of the active layer located on the substrate surface, thereby forming the isolation structure.

16. The method for forming the memory structure as described in claim 13, characterized in that, After forming the control gate, the method further includes: forming a fifth mask layer on the control gate surface and within the fifth opening, the fifth mask layer extending along a second direction and arranged parallel to a first direction, the fifth mask layer exposing the fourth opening; performing a drain light doping treatment on the active layer surface at the bottom of the fourth opening to form a drain lightly doped region; forming a sixth mask layer on the control gate surface and within the fourth opening, the sixth mask layer extending along a second direction and arranged parallel to a first direction, the sixth mask layer exposing the fifth opening; using the sixth mask layer as a mask, etching the first dielectric layer at the bottom of the fifth opening and the isolation structure at the bottom of the fifth opening using a fifth etching process; and after the fifth etching process, performing a source heavy doping treatment on the substrate surface and the active layer surface at the bottom of the fifth opening. To form a source region, adjacent source regions parallel to a first direction are connected together to form a common source line parallel to a second direction. The lightly doped drain region and the common source line are adjacent along the first direction, and a pad structure is formed between adjacent lightly doped drain regions and the common source line. A second dielectric layer is formed between adjacent control gates and on the surface of the control gates. A plurality of sixth openings are formed in the second dielectric layer, each of the sixth openings exposing the surface of the active layer. Each of the sixth openings is located in the lightly doped drain region in the first direction and is located between adjacent pad structures in the first direction. The active layer surface at the bottom of each of the sixth openings is heavily doped with drain material. A conductive plug is formed in each of the sixth openings, and the conductive plug is connected to the lightly doped drain region.

17. The method for forming the memory structure as described in claim 16, characterized in that, The lightly doped drain electrode is achieved through ion implantation; the ion implantation parameters include: arsenic and phosphorus ions, an ion implantation energy between 10 keV and 50 keV, and an ion implantation dose of 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 The source heavy doping method includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10 keV and 50 keV, and ion implantation dose is 5E13 atoms / cm². 2 Up to 5E15 atoms / cm 2 between.

18. The method for forming the memory structure as described in claim 12, characterized in that, Before forming the control gate material layer and after forming the isolation structure, the method further includes forming a first dielectric layer on the substrate surface of the isolation structure.

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