Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. An example semiconductor memory device includes: a cell region; and a peripheral circuit region electrically connected to the cell region. The cell region includes: a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction; and a channel structure extending in a vertical direction through the plurality of gate electrodes. The peripheral circuit region includes: a substrate; a first element isolation structure; a first gate structure on the first active region; a second element isolation structure; a second gate structure on the second active region; a third element isolation structure; and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0135810 filed in the Korean Intellectual Property Office on October 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor memory device. Background Art

[0004] In electronic systems that require data storage, semiconductor elements that can store high-capacity data are required. Therefore, methods that can increase the data storage capacity of semiconductor elements are being studied. For example, as a method for increasing the data storage capacity of semiconductor elements, a semiconductor element including a three-dimensionally arranged storage cell instead of a two-dimensionally arranged storage cell is proposed. Summary of the invention

[0005] The present disclosure relates to semiconductor memory devices, including semiconductor memory devices having improved performance and reliability.

[0006] However, the present disclosure is not limited to the contents described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] In some embodiments, a semiconductor memory device includes: a cell region; and a peripheral circuit region electrically connected to the cell region, wherein the cell region includes: a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction; and a channel structure penetrating the plurality of gate electrodes in a vertical direction, wherein the peripheral circuit region includes: a substrate; a first element isolation structure defining a first active region in the substrate and extending to a first depth; a first gate structure placed on the first active region; a second element isolation structure defining a second active region in the substrate and extending to a second depth deeper than the first depth; a second gate structure placed on the second active region; a third element isolation structure defining a third active region on the substrate and including a first element isolation pattern and a second element isolation pattern, the first element isolation pattern extending to a third depth, the second element isolation pattern extending inside the first element isolation pattern to a fourth depth deeper than the third depth; and a third gate structure placed on the third active region, wherein the first element isolation pattern and the second element isolation pattern include different materials from each other.

[0008] In some embodiments, a semiconductor memory device includes: a cell region; and a peripheral circuit region electrically connected to the cell region, wherein the cell region includes: a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction; and a channel structure penetrating the plurality of gate electrodes in a vertical direction, wherein the peripheral circuit region includes: a substrate having a first side and a second side opposite to each other; a first element isolation structure defining a first active region in the substrate and formed inside a first trench having a first width; a first gate structure extending in a direction intersecting the first active region and placed on the first active region; and a first gate structure extending in a direction intersecting the first active region and placed on the first active region. A second element isolation structure defines a second active region in the substrate and is formed in a second trench having a second width less than the first width; a second gate structure extends in a direction intersecting the second active region and is placed on the second active region; a third element isolation structure defines a third active region in the substrate and is formed in a third trench having a third width and a fourth trench having a fourth width less than the third width; and a third gate structure extends in a direction intersecting the third active region and is placed on the third active region, wherein a bottom side of the fourth trench is closer to the first side of the substrate than a bottom side of the second trench.

[0009] In some embodiments, a semiconductor memory device includes: a cell structure; and a peripheral circuit structure electrically connected to the cell structure, wherein the cell structure includes: a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction; a channel structure penetrating the plurality of gate electrodes in a vertical direction; and a bit line connected to the channel structure, wherein the peripheral circuit structure includes: a substrate including a first region and a second region, wherein different first peripheral circuit elements and second peripheral circuit elements are formed respectively; a first element isolation structure formed in the first region of the substrate and extending to a first depth; a second element isolation structure formed in the second region of the substrate and extending to a second depth deeper than the first depth. degree; and a third element isolation structure, which is formed in at least one of the first area and the second area of ​​the substrate and includes a first element isolation pattern and a second element isolation pattern, the first element isolation pattern extends to a third depth, and the second element isolation pattern extends inside the first element isolation pattern to a fourth depth deeper than the third depth, wherein the first width of the first element isolation structure is greater than the second width of the second element isolation structure, the third width of the first element isolation pattern is greater than the fourth width of the second element isolation pattern, the second width of the second element isolation structure is the same as the fourth width of the second element isolation pattern, and the first element isolation pattern and the second element isolation pattern include different materials from each other.

[0010] Specific details of other implementations are included in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a block diagram for explaining an example of a semiconductor memory device.

[0013] Figure 2 is an exemplary circuit diagram for explaining a semiconductor memory device.

[0014] Figure 3 is an exemplary cross-sectional view of a semiconductor memory device.

[0015] Figure 4 yes Figure 3 An example magnified view of region R.

[0016] Figure 5 is a plan view for explaining an example of a peripheral circuit structure of a semiconductor memory device.

[0017] Figure 6 is along Figure 5 Example cross-sectional view taken along line AA.

[0018] Figure 7 is along Figure 5 An example cross-sectional view taken along line BB.

[0019] Figure 8 is along Figure 5 Example cross-sectional view taken along line CC.

[0020] Fig. 9 and Fig.10 Along Figure 5 Example cross-sectional views taken along lines BB and CC.

[0021] Fig.11 is along Figure 5 Example cross-sectional view taken along line CC.

[0022] Fig.12 is along Figure 5 Example cross-sectional view taken along line CC.

[0023] Fig.13 is along Figure 5 Example cross-sectional view taken along line AA.

[0024] Fig.14 is along Figure 5 An example cross-sectional view taken along line BB.

[0025] Fig.15 is along Figure 5 Example cross-sectional view taken along line CC.

[0026] Fig.16 is an exemplary cross-sectional view of a semiconductor memory device.

[0027] Figures 17 to 22 is a diagram of an intermediate stage for illustrating an example method of manufacturing a semiconductor memory device.

[0028] Figure 23 to Figure 24 is a diagram of an intermediate stage for illustrating an example method of manufacturing a semiconductor memory device.

[0029] Figure 25 to Figure 29 is a diagram of an intermediate stage for illustrating an example method of manufacturing a semiconductor memory device.

[0030] Figure 30 to Figure 31 is a diagram of an intermediate stage for illustrating an example method of manufacturing a semiconductor memory device.

[0031] Figure 32 to Figure 33 is a diagram of an intermediate stage for illustrating an example method of manufacturing a semiconductor memory device.

[0032] Fig.34 is an example block diagram for illustrating an electronic system.

[0033] Fig.35 is an example perspective view for explaining an electronic system.

[0034] Fig.36 is along Fig.35 An example schematic cross-sectional view taken along line II. DETAILED DESCRIPTION

[0035] Although terms such as first and second are used in this specification to describe various elements or components, these elements or components are not limited by these terms. These terms are only used to distinguish a single element or component from other elements or components. Therefore, the first element or component mentioned below can be the second element or component within the technical concept of the present disclosure.

[0036] Hereinafter, in order to describe the present disclosure, some implementations of the present disclosure will be explained in more detail with reference to the accompanying drawings.

[0037] Figure 1 is a block diagram for explaining an example of a semiconductor memory device.

[0038] Reference Figure 1 , a semiconductor memory device 10 includes a memory cell array 20 and a peripheral circuit 30 .

[0039] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through the bit lines BL, the word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

[0040] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the semiconductor memory device 10, and may transmit and receive data DATA to and from an external device of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits such as an input / output circuit, a voltage generating circuit that generates various voltages required for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors of the data DATA read from the memory cell array 20.

[0041] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used within the semiconductor memory device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage levels supplied to the word lines WL and the bit lines BL when performing a storage operation such as a program operation or an erase operation.

[0042] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell blocks BLK1 to BLKn. In addition, the row decoder 33 may transmit a voltage for performing a storage operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

[0043] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, when performing a programming operation, the page buffer 35 may operate as a write driver and apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL. On the other hand, when performing a read operation, the page buffer 35 may operate as a sense amplifier and read out the data DATA stored in the memory cell array 20.

[0044] Figure 2 is an exemplary circuit diagram for explaining a semiconductor memory device.

[0045] Reference Figure 2 , a memory cell array of a semiconductor memory device (e.g., Figure 1 20) may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0046] The common source line CSL may extend along the first direction X. In some embodiments, a plurality of common source lines CSL may be arranged two-dimensionally. For example, a plurality of common source lines CSL may be spaced apart from each other, and each common source line CSL extends along the first direction X. The same voltage may be electrically applied to the common source lines CSL, or different voltages may be applied to the common source lines CSL, and the common source lines CSL may be individually controlled.

[0047] A plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL are spaced apart from each other, and each bit line BL extends along a second direction Y intersecting the first direction X. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be placed between the bit lines BL and the common source line CSL.

[0048] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT placed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series in a third direction Z. In some embodiments, the first direction X, the second direction Y, and the third direction Z may be substantially perpendicular to each other.

[0049] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL1 to WLn, and a string selection line SSL may be placed between the common source line CSL and the bit line BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, the word lines WL1 to WLn may be used as gate electrodes of the memory cell transistors MCT, and the string selection line SSL may be used as a gate electrode of the string selection transistor SST.

[0050] In some embodiments, the erase control transistor ECT may be placed between the common source line CSL and the ground selection transistor GST. The common source line CSL may be commonly connected to the source of the erase control transistor ECT. In addition, the erase control line ECL may be placed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistor ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

[0051] Figure 3 is an exemplary cross-sectional view of a semiconductor memory device. Figure 4 yes Figure 3 An example magnified view of region R.

[0052] Reference Figure 3 and Figure 4 , the semiconductor memory device includes a cell structure CELL and a peripheral circuit structure PERI.

[0053] In some embodiments, the cell structure CELL includes a cell substrate 100 , a mold structure MS, a cell interlayer insulating film 120 , a channel structure CH, a word line cutting structure WLC, a bit line BL, a plurality of cell contacts 153 , and through-contacts 155 .

[0054] The semiconductor memory device may include a cell array region CAR, an extension region EXR, and a pad region PAD. Although the cell array region CAR, the extension region EXR, and the pad region PAD are shown to be connected to each other, the technical idea of ​​the present disclosure is not limited thereto.

[0055] A memory cell array (eg, a plurality of memory cells) may be formed in the cell array region CAR. Figure 1 20). For example, a channel structure CH, a bit line BL, gate electrodes ECL, GSL, WL1 to WLn, and SSL, etc. (to be described below) may be placed in the cell array region CAR.

[0056] The extension region EXR may be placed around the cell array region CAR. Gate electrodes ECL, GSL, WL1 to WLn, and SSL (to be described below) may be stacked in a stepped manner in the extension region EXR. In addition, a plurality of cell contacts 153 (to be described below) and the like may be placed in the extension region EXR.

[0057] The pad area PAD may be placed inside the cell array area CAR and the extension area EXR, or may be placed outside the cell array area CAR and the extension area EXR. A through-contact 155 and the like to be described below may be placed in the pad area PAD.

[0058] The substrate may include a cell array region CAR, an extension region EXR, and a pad region PAD. The substrate may include, but is not limited to, a unit substrate 100 and an insulating pattern 101 .

[0059] The unit substrate 100 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the unit substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some embodiments, the unit substrate 100 may include impurities. For example, the unit substrate 100 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0060] The insulating pattern 101 may be disposed in the extension region EXR and the pad region PAD. The insulating pattern 101 may include, for example but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. Unlike the illustrated example, the insulating pattern 101 may be disposed in the unit substrate 100.

[0061] The mold structure MS may be disposed on a front side (e.g., an upper side) of the unit substrate 100. The mold structure MS may include a plurality of gate electrodes ECL, GSL, WL1 to WLn, and SSL alternately stacked on the unit substrate 100, and a plurality of mold insulating films 110. Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL and each mold insulating film 110 may have a layered structure extending in parallel to the upper side of the unit substrate 100. The gate electrodes ECL, GSL, WL1 to WLn, and SSL may be spaced apart from each other by the mold insulating film 110 and may be sequentially stacked on the unit substrate 100.

[0062] The gate electrodes ECL, GSL, WL1 to WLn, and SSL may be stacked in a stepped manner in the extended region EXR. For example, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may extend in different lengths along the first direction X and have steps. In some embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may have steps in the second direction Y. Therefore, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may be exposed from other gate electrodes. The exposed region may refer to a region where each of the plurality of cell contacts 153 and the gate electrode contact each other.

[0063] In some embodiments, the gate electrodes ECL, GSL, WL1 to WLn, and SSL include an erase control line ECL, a ground selection line GSL, and a plurality of word lines WL1 to WLn sequentially stacked on the unit substrate 100. In some embodiments, the erase control line ECL may be omitted.

[0064] The mold insulating film 110 may be stacked in the extension region EXR in a stepped manner. For example, the mold insulating film 110 may extend in different lengths along the first direction X and have steps. In some embodiments, the mold insulating film 110 may have steps in the second direction Y.

[0065] The gate electrodes ECL, GSL, WL1 to WLn, and SSL may each include a conductive material, for example, but not limited to, a metal (such as tungsten (W), cobalt (Co), and nickel (Ni)) or a semiconductor material the same as silicon. As an example, each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include tungsten (W). Unlike the illustrated example, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may be a plurality of films. For example, when the gate electrodes ECL, GSL, WL1 to WLn, and SSL are a plurality of films, the gate electrodes ECL, GSL, WL1 to WLn, and SSL may include a gate electrode barrier film and a gate electrode filling film. The gate electrode barrier film may include, for example, titanium nitride (TiN), and the gate electrode filling film may include tungsten (W), but the embodiment is not limited thereto.

[0066] The mold insulating film 110 may include, but is not limited to, an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the mold insulating film 110 may include silicon oxide.

[0067] The channel structure CH may be formed inside the mold structure MS of the cell array region CAR. The channel structure CH may extend in a vertical direction (third direction Z) intersecting the upper side of the cell substrate 100 and penetrate the mold structure MS and the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the channel structure CH may have a columnar shape (e.g., cylindrical) extending along the third direction Z. Therefore, the channel structure CH may intersect each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL.

[0068] The channel structure CH may include a semiconductor pattern 130 and an information storage film 132 .

[0069] The semiconductor pattern 130 may extend along the third direction Z and penetrate the mold structure MS. The semiconductor pattern 130 is only shown as having a cup shape, which is just an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular barrel shape, and a solid filler shape. The semiconductor pattern 130 may include, but is not limited to, semiconductor materials such as single crystal silicon, polycrystalline silicon, organic semiconductor substances, and carbon nanostructures.

[0070] The information storage film 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL. For example, the information storage film 132 may extend along the outer side of the semiconductor pattern 130. The information storage film 132 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0071] In some embodiments, the information storage film 132 may be formed of a plurality of films. Figure 4 As shown, the information storage film 132 may include a tunnel insulating film 132 a , a charge storage film 132 b , and a blocking insulating film 132 c sequentially stacked on the outer side of the semiconductor pattern 130 .

[0072] The tunnel insulating film 132a may include, for example, silicon oxide or a high dielectric constant material (eg, aluminum oxide (Al2O3)) having a dielectric constant higher than that of silicon oxide. 2 O 3 ) and hafnium oxide (HfO 2 )). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high dielectric constant material (for example, aluminum oxide (Al2O3)) having a dielectric constant higher than that of silicon oxide. 2 O 3 ) and hafnium oxide (HfO 2 )).

[0073] In some embodiments, the channel structure CH may further include a filling pattern 134. The filling pattern 134 may be formed to fill the inside of the cup-shaped semiconductor pattern 130. The filling pattern 134 may include, but is not limited to, an insulating material, for example, silicon oxide.

[0074] In some embodiments, the channel structure CH may further include a channel pad 136. The channel pad 136 may be formed to be connected to the semiconductor pattern 130. For example, the channel pad 136 may be formed inside a cell interlayer insulating film 120 to be described below, and connected to an upper portion of the semiconductor pattern 130. The channel pad 136 may include, for example, but not limited to, doped polysilicon.

[0075] In some embodiments, the source layer 102 and the source support layer 104 may be sequentially formed on the unit substrate 100. The source layer 102 and the source support layer 104 may be interposed between the unit substrate 100 and the mold structure MS. For example, the source layer 102 and the source support layer 104 may extend along the upper side of the unit substrate 100.

[0076] In some embodiments, the source layer 102 may be formed to be connected to the semiconductor pattern 130 of the channel structure CH. Figure 4 As shown, the source layer 102 may penetrate the information storage film 132 and contact the semiconductor pattern 130. Such a source layer 102 may be provided as a common source line (eg, Figure 2 The source layer 102 may include, for example but not limited to, doped polysilicon or metal.

[0077] In some embodiments, the channel structure CH may penetrate the source layer 102 and the source supporting layer 104. For example, a lower portion of the channel structure CH may penetrate the source layer 102 and the source supporting layer 104 and be embedded in the unit substrate 100.

[0078] In some embodiments, the source support layer 104 can be used as a support layer for preventing the mold stack from collapsing or falling during an alternative process for forming the source layer 102 .

[0079] Although not shown, a base insulating film may be interposed between the unit substrate 100 and the source layer 102. The base insulating film may include, for example but not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0080] In some embodiments, the insulating pattern 101 may be formed in the extension region EXR and the pad region PAD. Although the upper side of the insulating pattern 101 is only shown as being placed on the same plane as the upper side of the source support layer 104, this is merely an example. As another example, the upper side of the insulating pattern 101 may be higher than the upper side of the source support layer 104.

[0081] The word line cutting structure WLC may cut the mold structure MS. The mold structure MS may be cut by the word line cutting structure WLC to form a plurality of memory cell blocks (eg, Figure 1 For example, although not shown, two adjacent word line cutting structures WLC may define a single memory cell block therebetween. A plurality of channel structures CH may be placed in each memory cell block defined by the word line cutting structure WLC.

[0082] In some embodiments, the word line cutting structure WLC may cut the source layer 102 and the source support layer 104. Although the lower side of the word line cutting structure WLC is only shown as being placed on the same plane as the lower side of the source layer 102, this is only an example. As another example, the lower side of the word line cutting structure WLC may be lower than the lower side of the source layer 102.

[0083] In some embodiments, the word line cutting structure WLC may include an insulating material. For example, the insulating material may fill the word line cutting structure WLC. The insulating material may include, for example but not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0084] Although not shown, the string isolation structure may be provided in the mold structure MS. The string isolation structure may cut the string selection line SSL. Each memory cell block defined by the word line cutting structure WLC may be divided by the string isolation structure to form a plurality of string regions. For example, the string isolation structure may define two string regions located inside a single memory cell block.

[0085] The cell interlayer insulating film 120 may be placed on the mold structure MS. The cell interlayer insulating film 120 may cover the plurality of channel structures CH, the plurality of cell contacts 153, and the through-contacts 155. The cell interlayer insulating film 120 may include an oxide-based insulating material. The cell interlayer insulating film 120 may include, for example but not limited to, at least one of silicon oxide, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0086] The bit line BL may be placed on the substrate of the cell array region CAR. The bit line BL may be formed on the mold structure MS. The bit line BL may be a bit line of the semiconductor memory device ( Figure 2 The bit line BL may be placed in the cell interlayer insulating film 120. The bit line BL may extend along the second direction Y.

[0087] In addition, the bit line BL may be connected to a plurality of channel structures CH. For example, a first bit line contact 151 and a second bit line contact 161 may be formed in the cell interlayer insulating film 120 connected to the upper portion of each channel structure CH. The first bit line contact 151 is placed on the channel structure CH. The first bit line contact 151 may be connected to the channel pad 136. The second bit line contact 161 is placed on the first bit line contact 151. The second bit line contact 161 may be connected to the bit line BL. The second bit line contact 161 may be disposed between each bit line BL and the first bit line contact 151. The bit line BL may be electrically connected to the channel structure CH through the first bit line contact 151 and the second bit line contact 161.

[0088] The bit line BL may include a conductive material. For example, the bit line BL may include, but is not limited to, tungsten (W) or copper (Cu).

[0089] A plurality of cell contacts 153 may be provided on the substrate of the extension region EXR. The plurality of cell contacts 153 may extend in the extension region EXR along the third direction Z and penetrate the cell interlayer insulating film 120. Each of the plurality of cell contacts 153 may be connected to one of the plurality of gate electrodes ECL, GSL, WL1 to WLn and SSL. For example, each of the plurality of cell contacts 153 may land on a gate electrode placed at the highest level among the plurality of gate electrodes ECL, GSL, WL1 to WLn and SSL. That is, each of the plurality of cell contacts 153 may be electrically connected to a gate electrode placed at the highest level among the plurality of gate electrodes ECL, GSL, WL1 to WLn and SSL.

[0090] The upper side of each of the plurality of cell contacts 153 may all be placed on the same plane. In addition, the bottom side of each of the plurality of cell contacts 153 may be placed on the same plane. However, the technical concept of the present disclosure is not limited thereto.

[0091] A plurality of first metal patterns 170 may be placed on the substrate of the extension region EXR. A plurality of first metal patterns 170 may be placed on the mold structure MS. A plurality of first metal patterns 170 may be connected to each of a plurality of cell contacts 153. For example, a first via contact 163 may be formed between the plurality of first metal patterns 170 and each cell contact 153. A plurality of first metal patterns 170 and each cell contact 153 may be electrically connected through the first via contact 163.

[0092] The plurality of first metal patterns 170 may include a conductive material. For example, the plurality of first metal patterns 170 may include, but are not limited to, tungsten (W) or copper (Cu).

[0093] The through contact 155 may be disposed on the substrate of the pad region PAD. The through contact 155 may extend in the pad region PAD along the third direction Z and penetrate the unit interlayer insulating film 120. In addition, the through contact 155 may penetrate the insulating pattern 101. The through contact 155 may penetrate the insulating pattern 101 and be connected to the peripheral circuit element PT of the peripheral circuit structure PERI, which will be described below. The through contact 155 may be connected to the wiring pattern 290 of the peripheral circuit structure PERI, for example.

[0094] A plurality of second metal patterns 180 may be placed on the substrate of the pad region PAD. A plurality of second metal patterns 180 may be disposed in the unit interlayer insulating film 120. A plurality of second metal patterns 180 may be connected to the through-contacts 155. For example, a second via contact 165 may be formed between the plurality of second metal patterns 180 and the through-contacts 155. A plurality of second metal patterns 180 and the through-contacts 155 may be electrically connected through the second via contacts 165.

[0095] The plurality of second metal patterns 180 may include a conductive material. For example, the plurality of second metal patterns 180 may include, but are not limited to, tungsten (W) or copper (Cu).

[0096] In some embodiments, the peripheral circuit structure PERI may include a peripheral circuit board 200 , an element isolation film 205 , and a peripheral circuit element PT.

[0097] The peripheral circuit board 200 may be placed below the unit substrate 100. For example, an upper side 200_1 of the peripheral circuit board 200 may be opposite to a lower side of the unit substrate 100. The peripheral circuit board 200 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. Alternatively, the peripheral circuit board 200 may include a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, etc.

[0098] The peripheral circuit element PT may be formed on the peripheral circuit board 200. The peripheral circuit element PT may constitute a peripheral circuit (eg, Figure 1 30). For example, the peripheral circuit PT may include control logic (e.g., Figure 1 37), a row decoder (e.g., Figure 1 33), page buffer (e.g., Figure 1 35), etc. As an example, the peripheral circuit element PT may be a page buffer, and may control the operation of the bit line BL, but the technical concept of the present disclosure is not limited thereto.

[0099] In the following description, the first side 200_1 of the peripheral circuit board 200 where the peripheral circuit element PT is placed may be referred to as the upper side of the peripheral circuit board 200. Conversely, the second side 200_2 of the peripheral circuit board 200 opposite to the upper side 200_1 of the peripheral circuit board 200 may be referred to as the lower side of the peripheral circuit board 200.

[0100] The peripheral circuit element PT may include, for example, but not limited to, a transistor. For example, the peripheral circuit element PT may include not only various active elements such as a transistor, but also various passive elements such as a capacitor, a resistor, and an inductor.

[0101] In some embodiments, the back side of the unit substrate 100 may be opposite to the upper side 200_1 of the peripheral circuit board 200. For example, a peripheral circuit interlayer insulating film 210 covering the peripheral circuit element PT may be formed on the upper side 200_1 of the peripheral circuit board 200. The unit substrate 100 and / or the insulating pattern 101 may be stacked on the upper side of the peripheral circuit interlayer insulating film 210.

[0102] The plurality of second metal patterns 180 may be connected to the peripheral circuit element PT through the through-contacts 155. For example, a wiring pattern 290 connected to the peripheral circuit element PT may be formed in the peripheral circuit interlayer insulating film 210. Each of the gate electrodes ECL, GSL, WL1 to WLn, and SSL, the bit line BL, and / or the source layer 102 may be electrically connected to the peripheral circuit element PT through the wiring pattern 290.

[0103] The peripheral circuit element PT may be separated by an element isolation film 205. For example, the element isolation film 205 may be provided in the peripheral circuit board 200. The element isolation film 205 may be a shallow trench isolation (STI) film and / or a deep trench isolation film. The element isolation film 205 may define an active region of the peripheral circuit element PT. The element isolation film 205 may include an insulating material. The element isolation film 205 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0104] Will use Figures 5 to 8 The peripheral circuit element PT will be described in more detail. Figure 5 is a plan view for explaining an example of a peripheral circuit structure of a semiconductor memory device. Figure 6 is along Figure 5 Example cross-sectional view taken along line AA. Figure 7 is along Figure 5 An example cross-sectional view taken along line BB. Figure 8 is along Figure 5 Example cross-sectional view taken along line CC.

[0105] Reference Figures 5 to 8, the semiconductor memory device may include a peripheral circuit board 200, a first active region ACT_A, a first element isolation structure 205A, a first gate structure GS1, a second active region ACT_B, a second element isolation structure 205B, a second gate structure GS2, a third active region ACT_C, a third element isolation structure 205C, and a third gate structure GS3. Each of the first to third gate structures GS1, GS2, and GS3 may be included in first to third transistors included in the peripheral circuit element PT.

[0106] The peripheral circuit board 200 may include first to third regions S1, S2, and S3. Each of the first to third regions S1, S2, and S3 may represent a region where each of the first to third element isolation structures 205A, 205B, and 205C is formed. The first to third regions S1, S2, and S3 may represent a region corresponding to at least one of the cell array region CAR, the extension region EXR, and the pad region PAD.

[0107] In some embodiments, the first element isolation structure 205A may be formed in a region corresponding to at least one of the cell array region CAR, the extension region EXR, and the pad region PAD. The second element isolation structure 205B may be formed in a region corresponding to at least one of the extension region EXR and the pad region PAD. The third element isolation structure 205C may be formed in a region corresponding to at least one of the cell array region CAR, the extension region EXR, and the pad region PAD.

[0108] The first active region ACT_A may be placed on the peripheral circuit board 200. The first active region ACT_A may be used as a channel of a first transistor including a first gate structure GS1. The first gate structure GS1 may be placed on the first active region ACT_A. The first active region ACT_A may extend along a first direction X. The first direction X and the second direction Y may be directions parallel to the upper side 200_1 of the peripheral circuit board 200 and intersecting each other. The third direction Z may intersect each of the first direction X and the second direction Y. The third direction Z may be a direction perpendicular to the upper side of the peripheral circuit board 200. That is, the third direction Z may be a vertical direction.

[0109] The first gate structure GS1 may extend on the first active region ACT_A in the second direction Y. The first gate structure GS1 may extend to intersect the first active region ACT_A.

[0110] Although the drawing only shows that the first active region ACT_A extends along the first direction X and the first gate structure GS1 extends along the second direction Y, the embodiment is not limited thereto.

[0111] The first gate structure GS1 may include a gate insulating pattern 221, a gate pattern 222, and a gate capping pattern 223. The gate insulating pattern 221, the gate pattern 222, and the gate capping pattern 223 may be sequentially stacked in the third direction Z. The gate insulating pattern 221 is placed on the first active region ACT_A, the gate pattern 222 is placed on the gate insulating pattern 221, and the gate capping pattern 223 may be placed on the gate pattern 222.

[0112] The gate insulating pattern 221 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. Examples of high dielectric constant materials may include one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. As an example, the gate insulating pattern 221 may be formed of a silicon oxide film.

[0113] The gate pattern 222 may include a conductive material. For example, the gate pattern 222 may include, but is not limited to, a polysilicon film doped with impurities, tungsten (W), or a combination film thereof.

[0114] The gate capping pattern 223 may be formed of, for example, but not limited to, a silicon nitride film.

[0115] The spacer 230 may cover the first gate structure GS1. The spacer 230 may be placed on the first gate structure GS1. The spacer 230 may cover the upper side and sidewalls of the first gate structure GS1. The spacer 230 may include an insulating material. For example, the spacer 230 may be formed of, but not limited to, a silicon oxide film.

[0116] Although not specifically shown, the source / drain region may be placed in the first active area ACT_A. The source / drain region may be placed on at least one side of the first gate structure GS1. The source / drain region may be placed on both sides of the first gate structure GS1. The source / drain region may be a region doped with impurities. For example, if the first gate structure GS1 is a PMOS transistor, the source / drain region may be doped with p-type impurities. As another example, when the first gate structure GS1 is an NMOS transistor, the source / drain region may be doped with n-type impurities.

[0117] The second active region ACT_B may be placed on the peripheral circuit board 200. The second active region ACT_B may be used as a channel of a second transistor including a second gate structure GS2. The second gate structure GS2 may be placed on the second active region ACT_B. The second active region ACT_B may extend along the first direction X.

[0118] The second gate structure GS2 may extend on the second active region ACT_B in the second direction Y. The second gate structure GS2 may extend to intersect the second active region ACT_B.

[0119] The third active region ACT_C may be placed on the peripheral circuit board 200. The third active region ACT_C may be used as a channel of a third transistor including a third gate structure GS3. The third gate structure GS3 may be disposed on the third active region ACT_C. The third active region ACT_C may extend along the first direction X.

[0120] The third gate structure GS3 may extend on the third active region ACT_C in the second direction Y. The third gate structure GS3 may extend to intersect the third active region ACT_C.

[0121] The description of the first active region ACT_A and the first gate structure GS1 may also be similarly applied to the second active region ACT_B, the second gate structure GS2 , the third active region ACT_C and the third gate structure GS3 .

[0122] Reference Figure 6 , the first element isolation structure 205A may be formed in the first trench 205AT having a first width (any one of WA1, WA2, and WA3) based on the first direction X.

[0123] A plurality of first element isolation structures 205A having different widths from each other may be formed. The first element isolation structure 205A may include first to third element isolation patterns 205A1, 205A2, and 205A3 having different widths (any one of WA1, WA2, and WA3) from each other.

[0124] For example, the first element isolation structure 205A and the first trench 205AT may have a width of 2000 nm or less, but are not limited thereto.

[0125] The first trench 205AT and the first element isolation structure 205A may extend to a first depth D11 based on the third direction Z. For example, the first depth D11 may be equal to or less than More specifically, the first depth D11 may be equal to or less than to But it is not limited to this.

[0126] Reference Figure 7 , the second element isolation structure 205B may be formed in the second trench 205BT of the second width WB1 based on the first direction X. The second width WB1 may be smaller than the first width (any one of WA1, WA2, and WA3).

[0127] The second element isolation structure 205B may have a second width WB1 based on the first direction X. The first width (any one of WA1, WA2, and WA3) of the first element isolation structure 205A may be greater than the second width WB1 of the second element isolation structure 205B, but is not limited thereto. For example, the second element isolation structure 205B and the second trench 205BT may have a width of 150 nm or less.

[0128] The second trench 205BT and the second element isolation structure 205B may extend to a second depth D21 based on the third direction Z. The second depth D21 may be deeper than the first depth D11. For example, the second depth D21 may be equal to or less than More specifically, the second depth D21 may be equal to or less than to But it is not limited to this.

[0129] Reference Figure 8 The third element isolation structure 205C may be formed in the third trench 205CT1 of the third width (any one of WC1, WC2, and WC3) and the fourth trench 205CT2 of the fourth width WB1 based on the first direction X. The fourth width WB1 may be smaller than any one of the third widths WC1, WC2, and WC3.

[0130] The third element isolation structure 205C may include a first element isolation pattern 205C1 formed in the third trench 205CT1 and a second element isolation pattern 205C2 formed in the fourth trench 205CT2. The second element isolation pattern 205C2 may be formed in the first element isolation pattern 205C1. The third element isolation structure 205C has a funnel shape in which the second element isolation pattern 205C2 having a narrower width and a deeper depth is formed inside the first element isolation pattern 205C1 having a relatively wider width and a shallower depth.

[0131] The first element isolation pattern 205C1 may have a third width WC1, WC2, or WC3 based on the first direction X. The second element isolation pattern 205C2 may have a fourth width WB1 based on the first direction X. The fourth width WB1 of the second element isolation pattern 205C2 may be the same as the second width WB1 of the second element isolation structure 205B. The third width (any one of WC1, WC2, and WC3) of the first element isolation pattern 205C1 may be greater than the fourth width WB1 of the second element isolation pattern 205C2.

[0132] For example, each of the first element isolation pattern 205C1 and the third trench 205CT1 may have a width of 2000 nm or less. For example, each of the width WB1 of the second element isolation pattern 205C2 and the fourth trench 205CT2 may be 150 nm or less.

[0133] A plurality of first element isolation patterns 205C1 having different widths from one another may be formed. The first element isolation pattern 205C1 may include first to third element isolation patterns 205C11 , 205C12 , and 205C13 having different widths WC1 , WC2 , and WC3 from one another.

[0134] A plurality of second element isolation patterns 205C2 having the same width as one another may be formed. The second element isolation pattern 205C2 may include first to third element isolation patterns 205C21 , 205C22 , and 205C23 having the same width WB1 as one another.

[0135] The third trench 205CT1 and the first element isolation pattern 205C1 may extend a third depth D11 based on the third direction Z. The fourth trench 205CT2 and the second element isolation pattern 205C2 may extend a fourth depth D31 based on the third direction Z.

[0136] The first depth D11 of the third trench 205CT1 and the first element isolation structure 205A may be the same as the third depth D11 of the first trench 205AT and the first element isolation pattern 205C1. The fourth depth D31 of the fourth trench 205CT2 and the second element isolation pattern 205C2 may be the same as the second depth D21 of the second trench 205BT and the second element isolation structure 205B.

[0137] In this case, the bottom side of the first trench 205AT is placed on the same plane as the bottom side of the third trench 205CT1, and the bottom side of the second trench 205BT may be placed on the same plane as the bottom side of the fourth trench 205CT2 based on the third direction Z. The upper side of the first element isolation pattern 205C1 and the upper side of the second element isolation pattern 205C2 may be placed on the same plane as the upper side 200_1 of the peripheral circuit board 200.

[0138] However, in some embodiments to be described below, the fourth depth D31 of the second element isolation pattern 205C2 may be different from the second depth D21 of the second element isolation structure 205B.

[0139] The bottom side of the first trench 205AT may be closer to the upper side 200_1 of the peripheral circuit board 200 than the bottom side of the second trench 205BT based on the third direction Z. The bottom side of the third trench 205CT1 may be closer to the upper side 200_1 of the peripheral circuit board 200 than the bottom side of the fourth trench 205CT2.

[0140] The first element isolation structure 205A and the second element isolation structure 205B may include materials different from each other. For example, the first element isolation structure 205A and the second element isolation structure 205B may include materials with different physical properties from each other. For example, the first element isolation structure 205A and the second element isolation structure 205B may include impurities different from each other.

[0141] The first element isolation pattern 205C1 and the second element isolation pattern 205C2 may include materials different from each other. For example, the first element isolation pattern 205C1 and the second element isolation pattern 205C2 may include materials having different physical properties from each other. For example, the first element isolation pattern 205C1 and the second element isolation pattern 205C2 may include impurities different from each other.

[0142] The first element isolation structure 205A and the first element isolation pattern 205C1 may include the same material. The second element isolation structure 205B and the second element isolation pattern 205C2 may include the same material.

[0143] In the following, reference will be made to Figures 9 to 14 Semiconductor memory devices according to some embodiments of the present disclosure are described.

[0144] Fig. 9 and Fig.10 Along Figure 5 For ease of explanation, the following sections will be briefly described or omitted: Figures 1 to 8 Duplicate content of the description.

[0145] Reference Fig. 9 , in the semiconductor memory device, the fourth depth D32 of the second element isolation pattern 205C2 may be less than the second depth D22 of the second element isolation structure 205B. That is, the fourth depth D32 of the fourth trench 205CT2 may be less than the second depth D22 of the second trench 205BT. In this case, based on the third direction Z, the bottom side of the fourth trench 205CT2 may be placed closer to the upper side 200_1 of the peripheral circuit board 200 than the bottom side of the second trench 205BT.

[0146] Reference Fig.10, in the semiconductor memory device, the fourth depth D32 of the second element isolation pattern 205C2 may be deeper than the second depth D22 of the second element isolation structure 205B. That is, the fourth depth D32 of the fourth trench 205CT2 may be deeper than the second depth D22 of the second trench 205BT. In this case, based on the third direction Z, the bottom side of the second trench 205BT may be placed closer to the upper side 200_1 of the peripheral circuit board 200 than the bottom side of the fourth trench 205CT2.

[0147] Fig.11 is along Figure 5 For ease of explanation, the following sections will be briefly described or omitted. Figures 1 to 10 Duplicate content of the description.

[0148] Reference Fig.11 In the semiconductor memory device, the peripheral circuit board 200 may include a fence pattern 205CO formed in at least a portion between the first element isolation pattern 205C1 and the second element isolation pattern 205C2. The fence pattern 205CO may have a shape that is recessed toward the upper side 200_1 of the peripheral circuit board 200 between one sidewall of the first element isolation pattern 205C1 and one sidewall of the second element isolation pattern 205C2.

[0149] The width of the barrier pattern 205CO may become smaller toward the upper side 200_1 of the peripheral circuit board 200 based on the first direction X. The barrier pattern 205CO may include silicon (Si).

[0150] Fig.12 is along Figure 5 For ease of explanation, the following sections will be briefly described or omitted. Figures 1 to 11 Duplicate content of the description.

[0151] Reference Fig.12 , in the semiconductor memory device, the upper side of the first element isolation pattern 205C1 may be positioned closer to the upper side 200_1 of the peripheral circuit board 200 than the upper side of the second element isolation pattern 205C2.

[0152] The upper side 200_1 of the peripheral circuit board 200 and the upper side of the second element isolation pattern 205C2 are positioned a first distance D34 apart, and the upper side of the second element isolation pattern 205C2 and the bottom side of the fourth trench 205CT2 may be positioned a second distance D33 apart.

[0153] Fig.13 is along Figure 5 Example cross-sectional view taken along line AA. Fig.14 is along Figure 5An example cross-sectional view taken along line BB. Fig.15 is along Figure 5 For ease of explanation, the following sections will be briefly described or omitted. Figures 1 to 12 Duplicate content of the description.

[0154] Reference Figures 13 to 15 In the semiconductor memory device, a void 205AV is formed in at least a portion of the first element isolation structure 205A and the first element isolation pattern 205C1, and a void 205CV is formed in at least a portion of the first element isolation structure 205A and the first element isolation pattern 205C1.

[0155] As described below, the gap may have a structure in which the first element isolation structure 205A and the first element isolation pattern 205C1 are formed in a bottom-up manner.

[0156] In addition, a seam may be formed in at least a portion of the second element isolation structure 205B and the second element isolation pattern 205C2. A spacer 205BS is formed on at least a portion of the second element isolation structure 205B, and a spacer 205CS may be formed on at least a portion of the second element isolation pattern 205C2.

[0157] As described below, the spacer may have a structure in which the second element isolation structure 205B and the second element isolation pattern 205C2 are formed by an atomic layer deposition method.

[0158] The shapes, numbers, and positions of the gaps and spacers are not limited to those shown in the drawings.

[0159] Fig.16 is an example cross-sectional view of a semiconductor memory device. For ease of explanation, the description will be briefly described or omitted. Figures 1 to 15 Duplicate content of the description.

[0160] Reference Fig.16 , in the semiconductor memory device, the front side of the unit substrate 100 faces the upper side of the peripheral circuit board 200 .

[0161] For example, the semiconductor memory device may have a C2C (chip-to-chip) structure. The C2C structure may refer to a structure in which an upper chip including a cell structure CELL is manufactured on a first wafer (e.g., a cell substrate 100), and a lower chip including a peripheral circuit region PERI is manufactured on a second wafer (e.g., a peripheral circuit board 200) different from the first wafer, and then the upper chip and the lower chip are connected to each other by bonding.

[0162] As an example, the bonding method may refer to an electrical bonding method, which may include a bit line BL, a plurality of first metal patterns 170 and a second metal pattern 180 formed on the uppermost metal layer of the upper chip, and a first bonding metal to a third bonding metal 292, 293, and 294 formed on the uppermost metal layer of the lower chip. For example, when the bit line BL, the plurality of first metal patterns 170, the second metal pattern 180, and the first bonding metal to the third bonding metal 292, 293, and 294 are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. However, this is merely exemplary, and each of the bit line BL, the plurality of first metal patterns 170, the second metal pattern 180, and the first bonding metal to the third bonding metal 292, 293, and 294 may of course be formed of various other metals such as aluminum (Al) or tungsten (W).

[0163] Since the bit line BL is connected to the first bonding metal 292, the plurality of first metal patterns 170 are connected to the second bonding metal 293, and the second metal pattern 180 is connected to the third bonding metal 294, the cell structure CELL and the peripheral circuit structure PERI can be electrically connected. For example, the bit line BL and the wiring pattern 290, the plurality of first metal patterns 170 and the wiring pattern 290, and the second metal pattern 180 and the wiring pattern 290 can be electrically connected to each other through the first bonding metal to the third bonding metal 292, 293 and 294 and the through-hole contact 291, respectively. Therefore, each of the gate electrodes ECL, GSL, WL1 to WLn and SSL and / or the source layer 102 can be electrically connected to the peripheral circuit element PT.

[0164] In the following, reference will be made to Figures 17 to 22 A method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure is described. Figures 17 to 22 is a diagram of an intermediate stage for illustrating an example method of manufacturing a semiconductor memory device.

[0165] First, refer to Fig.17 , a peripheral circuit board 200 including first to third regions may be provided. Each of the first to third regions may represent a region where each of the above-mentioned first to third element isolation structures 205A, 205B, and 205C is formed. Each of the first to third regions may represent a region where each of the above-mentioned first to third transistors is formed.

[0166] Although not specifically shown, a mask may be formed on the peripheral circuit board 200. The mask may be formed on the first region and the third region of the peripheral circuit board 200, and may not be formed on the second region. The first trench 205AT and the third trench 205CT1 may be formed in the peripheral circuit board 200 using the mask. Thereafter, the mask may be removed.

[0167] The first trench 205AT and the third trench 205CT1 may have a first depth D11 based on the third direction Z. For example, the first depth D11 may be equal to or less than

[0168] A plurality of first trenches 205AT having different widths from one another may be formed based on the first direction X. A plurality of third trenches 205CT1 having different widths from one another may be formed based on the first direction X.

[0169] Reference Fig.18 , a first pre-insulating film P2051 may be formed in the first trench 205AT and the third trench 205CT1 to fill each of the first trench 205AT and the third trench 205CT1. The first pre-insulating film P2051 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first pre-insulating film P2051 may be formed in a bottom-up manner by, for example, but not limited to, a chemical vapor deposition (CVD) process.

[0170] Reference Fig.19 By removing at least a portion of the first pre-insulating film P2051 from the first region to the third region, a first element isolation structure 205A and a first element isolation pattern 205C1 can be formed. In this case, a portion of the first pre-insulating film P2051 can be removed using a chemical mechanical polishing (CMP) process so that the upper sides of the first element isolation structure 205A and the first element isolation pattern 205C1 are placed on the same plane.

[0171] Reference Fig. 20 , the first mask pattern MA1 may be formed in the first to third regions of the peripheral circuit board 200. The first mask pattern MA1 may be formed in the first to third regions except for the regions where the second trench 205BT and the fourth trench 205CT2 are formed. The second trench 205BT and the fourth trench 205CT2 may be formed in the peripheral circuit board 200 using the first mask pattern MA1.

[0172] The first mask pattern MA1 may be formed of at least one of a photoresist film, an ACL (amorphous carbon layer), a SOH (spin on hard mask), a SOC (spin on carbon), and a silicon nitride film.

[0173] The fourth trench 205CT2 may be formed to at least partially penetrate the inside of the first element isolation pattern 205C1 .

[0174] The second trench 205BT and the fourth trench 205CT2 may extend to a second depth D21 based on the third direction Z. For example, the second depth D21 may be equal to or less than

[0175] The widths WB1 of the second trench 205BT and the fourth trench 205CT2 may be equal to each other based on the first direction X. For example, each of the widths WB1 of the second trench 205BT and the fourth trench 205CT2 may be 150 nm or less.

[0176] Thereafter, the first mask pattern MA1 may be removed.

[0177] Reference Fig.21 , a second pre-insulating film P2052 may be formed in the second trench 205BT and the fourth trench 205CT2 to fill each of the second trench 205BT and the fourth trench 205CT2. The second pre-insulating film P2052 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. The second pre-insulating film P2052 may be formed by, for example, but not limited to, an atomic layer deposition (ATOM) process.

[0178] Reference Fig. 22 , at least a portion of the second pre-insulating film P2052 in the first region to the third region may be removed to form a second element isolation structure 205B and a second element isolation pattern 205C2. In this case, a chemical mechanical polishing process may be used to remove a portion of the second pre-insulating film P2052 so that the upper sides of the second element isolation structure 205B and the second element isolation pattern 205C2 are placed on the same plane.

[0179] Then, a first gate structure ( Figure 6 GS1), forming a second gate structure ( Figure 7 GS2), and a third gate structure ( Figure 8 GS3).

[0180] Thereafter, the first gate structure to the third gate structure may be formed ( Figure 6 GS1 Figure 7 GS2 and Figure 8 GS3) and a wiring pattern electrically connected to the first region to the third region ( Figure 3 290) and the peripheral circuit interlayer insulation film ( Figure 3 210).

[0181] Thereafter, the peripheral circuit interlayer insulating film ( Figure 3 210) is formed on the mold structure ( Figure 3 MS) and channel structure ( Figure 3 The unit structure of CH Figure 3 CELL).

[0182] Therefore, it is possible to use Figures 1 to 8 A semiconductor memory device is described.

[0183] According to some embodiments, a third element isolation structure 205C including both a shallow isolation pattern and a deep isolation pattern may be formed in the peripheral circuit region PERI of the semiconductor memory device. Therefore, peripheral circuit elements applicable to the peripheral circuit region PERI may be diversified.

[0184] According to some embodiments, the patterning process and the gap filling process for the shallow isolation pattern and the deep isolation pattern can be binary to form film qualities different from each other in the shallow isolation pattern and the deep isolation pattern. Therefore, the difficulty of the patterning process for forming each element isolation pattern can be reduced compared to the case where the shallow isolation pattern and the deep isolation pattern are formed at the same time.

[0185] According to some embodiments, the deep isolation pattern may be formed by an atomic layer deposition process, so that the deep isolation pattern is formed to have a width of 150 nm or less. Therefore, misalignment due to a material difference between the peripheral circuit board and the element isolation pattern may be prevented.

[0186] Figure 23 to Figure 24 is a diagram of an intermediate stage for explaining an exemplary method of manufacturing a semiconductor memory device. For ease of explanation, the following will be briefly described or omitted. Figures 17 to 22 Duplicate content of the description.

[0187] Reference Fig.23 , the fourth depth D32 of the fourth trench 205CT2 may be smaller than the second depth D22 of the second trench 205BT.

[0188] The material included in the peripheral circuit board 200 and the material included in the first element isolation pattern 205C1 may be different from each other. For example, the peripheral circuit board 200 may include silicon (Si), and the first element isolation pattern 205C1 may include oxide. In the process of patterning the fourth trench 205CT2 and the second trench 205BT, due to the difference in etching rate between the peripheral circuit board 200 and the first element isolation pattern 205C1, the depth of the fourth trench 205CT2 may be formed to be different from the depth of the second trench 205BT.

[0189] Reference Fig.24A pre-insulating film may be formed in the second trench 205BT and the fourth trench 205CT2 to fill each of the second trench 205BT and the fourth trench 205CT2. The pre-insulating film may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. The pre-insulating film may be formed, for example, by, but not limited to, an atomic layer deposition process.

[0190] Thereafter, at least a portion of the pre-insulating film may be removed by a chemical mechanical polishing process to form a second element isolation structure 205B and a second element isolation pattern 205C2. A fourth depth D32 of the second element isolation pattern 205C2 may be less than a second depth D22 of the second element isolation structure 205B.

[0191] Using a chemical mechanical polishing process, the upper sides of the second element isolation structure 205B and the second element isolation pattern 205C2 may be placed on the same plane.

[0192] Therefore, it is possible to use Fig. 9 A semiconductor memory device is described.

[0193] Figure 25 to Figure 29 is a diagram of an intermediate stage for explaining an exemplary method of manufacturing a semiconductor memory device. For ease of explanation, the following will be briefly described or omitted. Figures 17 to 24 Duplicate content of the description.

[0194] Reference Fig.25 , a peripheral circuit board 200 including first to third regions may be provided. Each of the first to third regions may indicate a region in which each of the above-described first to third element isolation structures 205A, 205B, and 205C is formed.

[0195] Although not specifically shown, a mask may be formed on the peripheral circuit board 200. The mask may be formed on the second and third regions of the peripheral circuit board 200, and may not be formed on the first region. The second trench 205BT and the fourth trench 205CT2 may be formed in the peripheral circuit board 200 using the mask.

[0196] Reference Fig.26 , a second pre-insulating film P2052 may be formed in the second trench 205BT and the fourth trench 205CT2 to fill each of the second trench 205BT and the fourth trench 205CT2. The second pre-insulating film P2052 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. The second pre-insulating film P2052 may be formed by, for example, but not limited to, an atomic layer deposition process.

[0197] Reference Fig. 27, at least a portion of the second pre-insulating film P2052 from the first region to the third region may be removed to form a second element isolation structure 205B and a second element isolation pattern 205C2. In this case, a portion of the second pre-insulating film P2052 may be removed using a chemical mechanical polishing process so that the upper sides of the second element isolation structure 205B and the second element isolation pattern 205C2 are placed on the same plane.

[0198] Reference Fig.28 , the second mask pattern MA2 may be formed in the first to third regions of the peripheral circuit board 200. The second mask pattern MA2 may be formed in the first to third regions, except for the regions where the first trench 205AT and the third trench 205CT1 are formed. The first trench 205AT and the third trench 205CT1 may be formed in the peripheral circuit board 200 using the second mask pattern MA2.

[0199] Thereafter, the second mask pattern MA2 may be removed.

[0200] Reference Fig.29 , a first pre-insulating film P2051 may be formed in the first trench 205AT and the third trench 205CT1 to fill each of the first trench 205AT and the third trench 205CT1. The first pre-insulating film P2051 may include, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first pre-insulating film P2051 may be formed in a bottom-up manner by, for example, but not limited to, a chemical vapor deposition process.

[0201] Thereafter, at least a portion of the first pre-insulating film P2051 of the first region to the third region may be removed to form a Fig. 22 The first element isolation structure 205A and the first element isolation pattern 205C1 are shown. In this case, a portion of the first pre-insulating film P2051 may be removed using a chemical mechanical polishing process so that the upper sides of the first element isolation structure 205A and the first element isolation pattern 205C1 are placed on the same plane.

[0202] Therefore, it is possible to use Figures 1 to 8 A semiconductor memory device is described.

[0203] Figure 30 to Figure 31 is a diagram of an intermediate stage for explaining an exemplary method of manufacturing a semiconductor memory device. For ease of explanation, the following will be briefly described or omitted. Figure 25 to Figure 29 Duplicate content of the description.

[0204] Reference Fig.30 and Fig.31The fence pattern 205CO may be formed in at least a portion between the first element isolation pattern 205C1 and the second element isolation pattern 205C2. The fence pattern 205CO may have a shape recessed toward the upper side 200_1 of the peripheral circuit board 200 between one sidewall of the first element isolation pattern 205C1 and one sidewall of the second element isolation pattern 205C2.

[0205] When the first element isolation pattern 205C1 is formed after the second element isolation pattern 205C2 is formed, the third trench 205CT1 may be formed using the etching selectivity of the material included in the peripheral circuit board 200 and the material included in the second element isolation pattern 205C2. For example, the peripheral circuit board 200 may include silicon (Si), and the second element isolation pattern 205C2 may include oxide. In this case, silicon (Si) may be further etched in the region adjacent to the sidewall of the second element isolation pattern 205C2. Thus, a trench defining the fence pattern 205CO may be formed.

[0206] The width of the barrier pattern 205CO may decrease toward the upper side 200_1 of the peripheral circuit board 200 based on the first direction X. The barrier pattern 205CO may include silicon (Si).

[0207] At least a portion of the first pre-insulating film P2051 of the first region to the third region is removed, and a first element isolation structure 205A and a first element isolation pattern 205C1 can be formed. In this case, a portion of the first pre-insulating film P2051 can be removed using a chemical mechanical polishing process so that the upper sides of the first element isolation structure 205A and the first element isolation pattern 205C1 are placed on the same plane.

[0208] Therefore, it is possible to use Fig.11 A semiconductor memory device is described.

[0209] Fig.32 and Fig.33 is a diagram of an intermediate stage for explaining an exemplary method of manufacturing a semiconductor memory device. For ease of explanation, the following will be briefly described or omitted. Figure 30 to Figure 31 Duplicate content of the description.

[0210] Reference Fig.32 and Fig.33 , the upper side of the first element isolation pattern 205C1 may be placed closer to the upper side 200_1 of the peripheral circuit board 200 than the upper side of the second element isolation pattern 205C2. The upper side of the second element isolation structure 205B may be placed closer to the upper side 200_1 of the peripheral circuit board 200 than the upper side of the second element isolation pattern 205C2. The depth D33 of the fourth trench 205CT2 may be less than the depth D23 of the second trench 205BT.

[0211] An upper side of the peripheral circuit board 200 and an upper side of the second element isolation pattern 205C2 may be spaced apart by a first distance D34, and an upper side of the second element isolation pattern 205C2 and a bottom side of the fourth trench 205CT2 may be spaced apart by a second distance D33.

[0212] At least a portion of the first pre-insulating film P2051 of the first region to the third region is removed, and a first element isolation structure 205A and a first element isolation pattern 205C1 can be formed. In this case, a portion of the first pre-insulating film P2051 can be removed using a chemical mechanical polishing process so that the upper sides of the first element isolation structure 205A and the first element isolation pattern 205C1 are placed on the same plane.

[0213] Therefore, it is possible to use Fig.12 A semiconductor memory device is described.

[0214] The following will refer to Figures 1 to 8 and Figure 34 to Figure 36 Electronic systems including semiconductor memory devices according to some embodiments of the present invention are described.

[0215] Fig.34 is an example block diagram for illustrating an electronic system. Fig.35 is an example perspective view for explaining an electronic system. Fig.36 is along Fig.35 An example schematic cross-sectional view taken along line II.

[0216] Reference Fig.34 , the electronic system 1000 may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be an SSD device (solid state drive device), a USB (universal serial bus), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0217] The semiconductor memory device 1100 may be, for example, a NAND flash memory device, and may be, for example, the one used above. Figures 1 to 15 The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0218] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 (eg, Figure 1 , a row decoder 33), a page buffer 1120 (eg, Figure 1110 and logic circuit 1130 (eg, Figure 1 control logic 37).

[0219] The second structure 1100S may include the above using Figure 2 The common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR are illustrated. The cell strings CSTR may be connected to the decoder circuit 1110 through word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell strings CSTR may be connected to the page buffer 1120 through the bit lines BL.

[0220] In some embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 through a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S.

[0221] In some embodiments, the bit line BL may be electrically connected to the page buffer 1120 through a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S. The page buffer 1120 may be a first structure 1100F or a second structure 1100S. Figures 1 to 15 The peripheral circuit components PT are described.

[0222] The semiconductor memory device 1100 can be connected to the logic circuit 1130 (eg, Figure 1 The I / O pads 1101 electrically connected to the control logic 37 of the first structure 1100F communicate with the controller 1200. The I / O pads 1101 may be electrically connected to the logic circuit 1130 through the I / O connection wiring 1135 extending from the inside of the first structure 1100F to the second structure 1100S.

[0223] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100 .

[0224] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0225] Reference Figure 34 to Figure 36 , the electronic system may include a main board 2001, a main controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0226] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. In the connector 2006, the number and position of the plurality of pins may vary according to the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host according to any of the interfaces such as M-Phy, PCI-Express (Peripheral Component Interconnect High Speed ​​Interface), SATA (Serial Advanced Technology Attachment), and UFS (Universal Flash Memory) for USB (Universal Serial Bus). In some embodiments, the electronic system 2000 may be operated by a power supply provided by an external host through the connector 2006. The electronic system 2000 may also include a PMIC (Power Management Integrated Circuit) that distributes the power provided by the external host to the main controller 2002 and the semiconductor package 2003.

[0227] The main controller 2002 may record data in the semiconductor package 2003 or read data from the semiconductor package 2003 , and may increase the operation speed of the electronic system 2000 .

[0228] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a cache memory, and may also provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0229] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 placed on the lower side of each package chip 220, a connection structure 2400 for electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 on the package substrate 2100 and the connection structure 2400.

[0230] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an I / O pad 2210. The I / O pad 2210 may correspond to Fig.34 I / O pad 1101.

[0231] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the I / O pad 1101 with the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through-electrode (through silicon via TSV) instead of a bonding wire type connection structure 2400.

[0232] In some embodiments, the main controller 2002 and the semiconductor chip 2200 may also be included in a single package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main board 2001 and the main controller 2002 and the semiconductor chip 2200 may also be connected to each other through wiring formed on the interposer substrate.

[0233] In some embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, a package upper pad 2130 placed on the upper side of the package substrate body portion 2120, a lower pad 2125 placed on the lower side of the package substrate body portion 2120 or exposed through the lower side, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body portion 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main board 2001 of the electronic system 2000 through a conductive connection 2800, such as Fig.35 shown.

[0234] Reference Fig.35 and 36 In the electronic system, each of the semiconductor chips 2200 may include the above using Figures 1 to 15 For example, each of the semiconductor chips 2200 may include a peripheral circuit structure PERI and a cell structure CELL stacked on the peripheral circuit structure PERI. As an example, the peripheral circuit structure PERI may include a peripheral circuit board 200 and a cell structure CELL stacked on the peripheral circuit structure PERI. Figures 1 to 15 In addition, as an example, the cell structure CELL may include the peripheral circuit element PT described above. Figure 3 and Figure 4 The illustrated unit substrate 100, the mold structure MS, the channel structure CH, the word line cutting structure WLC and the bit lines BL.

[0235] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of what can be claimed or any invention, but rather as descriptions of features that can be applied to a particular embodiment of a particular invention. In a single embodiment, certain features described in this specification in the context of separate embodiments can also be implemented in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments, respectively, or in appropriate sub-combinations. In addition, although features can be described above as working in certain combinations, one or more features from a combination can be deleted from the combination in some cases, and a combination can be directed to a sub-combination or a variant of a sub-combination.

[0236] Although the embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be manufactured in various different forms. It will be understood by those skilled in the art that the present disclosure can be embodied in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, the above embodiments should be understood as illustrative rather than restrictive in all aspects.

Claims

1. A semiconductor memory device, comprising: Unit area; as well as A peripheral circuit region is electrically connected to the cell region. Wherein, the unit area includes: a plurality of gate electrodes spaced apart from each other, the plurality of gate electrodes being stacked in a vertical direction, and a channel structure extending along the vertical direction through the plurality of gate electrodes, Wherein, the peripheral circuit area includes: Substrate, a first element isolation structure defining a first active region in the substrate, the first element isolation structure extending to a first depth, a first gate structure, on the first active region, a second element isolation structure defining a second active region in the substrate, the second element isolation structure extending to a second depth greater than the first depth, a second gate structure, on the second active region, a third element isolation structure defining a third active region in the substrate, the third element isolation structure comprising a first element isolation pattern and a second element isolation pattern, the first element isolation pattern extending to a third depth, and the second element isolation pattern extending inside the first element isolation pattern to a fourth depth greater than the third depth, and a third gate structure, on the third active region, The first element isolation pattern and the second element isolation pattern include different materials from each other.

2. The semiconductor memory device according to claim 1, in, The first depth of the first element isolation structure is the same as the third depth of the first element isolation pattern.

3. The semiconductor memory device according to claim 1, in, The fourth depth of the second element isolation pattern is less than or equal to the second depth of the second element isolation structure.

4. The semiconductor memory device according to claim 1, in, The width of the first element isolation structure is greater than the width of the second element isolation structure.

5. The semiconductor memory device according to claim 1, in, A width of the first element isolation pattern is greater than a width of the second element isolation pattern.

6. The semiconductor memory device according to claim 1, in, The width of the second element isolation structure is equal to the width of the second element isolation pattern.

7. The semiconductor memory device according to claim 1, in, The semiconductor memory device includes a plurality of first element isolation structures and a plurality of first element isolation patterns, the plurality of first element isolation structures having widths different from each other, and the plurality of first element isolation patterns having widths different from each other.

8. The semiconductor memory device according to claim 1, in, The first element isolation structure includes a different material from that of the second element isolation structure.

9. The semiconductor memory device according to claim 1, in, The substrate includes a fence pattern in at least a portion between the first element isolation pattern and the second element isolation pattern, and Wherein, the width of the fence pattern decreases toward the upper side of the substrate.

10. The semiconductor memory device according to claim 9, in, An upper side of the first element isolation pattern is closer to an upper side of the substrate than an upper side of the second element isolation pattern.

11. A semiconductor memory device comprising: Unit area; as well as A peripheral circuit region is electrically connected to the cell region. Wherein, the unit area includes: a plurality of gate electrodes spaced apart from each other, the plurality of gate electrodes being stacked in a vertical direction, and a channel structure extending along the vertical direction through the plurality of gate electrodes, Wherein, the peripheral circuit area includes: a substrate comprising a first side and a second side, the first side and the second side being opposite to each other, a first element isolation structure defining a first active region in the substrate, wherein the first element isolation structure is in a first trench having a first width, a first gate structure extending in a direction intersecting the first active region, the first gate structure being on the first active region, a second element isolation structure defining a second active region in the substrate, the second element isolation structure being in a second trench having a second width, the second width being smaller than the first width, a second gate structure extending in a direction intersecting the second active region, the second gate structure being on the second active region, a third element isolation structure defining a third active region in the substrate, the third element isolation structure being in a third trench having a third width and a fourth trench having a fourth width, the fourth width being smaller than the third width, and A third gate structure extends along a direction intersecting the third active region, and the third gate structure is on the third active region. The bottom side of the fourth trench is closer to the first side of the substrate than the bottom side of the second trench.

12. The semiconductor memory device according to claim 11, in, The depth of the first trench is the same as the depth of the third trench.

13. The semiconductor memory device according to claim 11, in, The depth of the fourth trench is smaller than the depth of the second trench.

14. The semiconductor memory device according to claim 11, in, The third element isolation structure comprises: a first element isolation pattern in the third trench, and a second element isolation pattern, in the fourth trench, The first element isolation pattern and the second element isolation pattern include different materials from each other.

15. The semiconductor memory device according to claim 14, in, The semiconductor memory device includes a plurality of first element isolation patterns and a plurality of second element isolation patterns, the plurality of first element isolation patterns having widths different from each other, and Wherein, the plurality of second element isolation patterns have the same width.

16. The semiconductor memory device according to claim 14, in, A gap exists in at least a portion of the first element isolation structure and at least a portion of the first element isolation pattern, and There is a seam between at least a portion of the second element isolation structure and at least a portion of the second element isolation pattern.

17. The semiconductor memory device according to claim 14, in, The width of the second element isolation structure is equal to the width of the second element isolation pattern.

18. The semiconductor memory device according to claim 17, in, The width of the second element isolation structure is less than or equal to 150 nm, and the width of the second element isolation pattern is less than or equal to 150 nm.

19. A semiconductor memory device comprising: Unit structure; as well as a peripheral circuit structure, electrically connected to the unit structure, Wherein, the unit structure comprises: A plurality of gate electrodes, spaced apart from each other, wherein the plurality of gate electrodes are stacked in a vertical direction; a channel structure extending along the vertical direction through the plurality of gate electrodes; and A bit line connected to the channel structure, Wherein, the peripheral circuit structure includes: a substrate including a first region and a second region, the first region including a first peripheral circuit element, the second region including a second peripheral circuit element, the first peripheral circuit element and the second peripheral circuit element being different from each other, a first element isolation structure, wherein in the first region of the substrate, the first element isolation structure extends to a first depth, a second element isolation structure, wherein in the second region of the substrate, the second element isolation structure extends to a second depth greater than the first depth, and a third element isolation structure, wherein in at least one of the first region or the second region of the substrate, the third element isolation structure comprises a first element isolation pattern and a second element isolation pattern, the first element isolation pattern extending to a third depth, and the second element isolation pattern extending inside the first element isolation pattern to a fourth depth greater than the third depth, wherein a first width of the first element isolation structure is greater than a second width of the second element isolation structure, wherein the third width of the first element isolation pattern is greater than the fourth width of the second element isolation pattern, wherein the second width of the second element isolation structure is the same as the fourth width of the second element isolation pattern, and The first element isolation pattern and the second element isolation pattern include different materials from each other.

20. The semiconductor memory device according to claim 19, in, The fourth depth of the second element isolation pattern is less than or equal to the second depth of the second element isolation structure.

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