RC buffer and manufacturing method thereof
By integrating diodes in the RC buffer, the problem of oscillation caused by parasitic inductance with the DC bus in high-frequency applications is solved, and better peak absorption and oscillation suppression is achieved, reducing EMI and process costs.
Patent Information
- Application Number
- CN202411950589.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-15
AI Technical Summary
When used in high frequency applications, existing RC buffers will oscillate due to parasitic inductance with the DC bus, resulting in voltage overstress, EMI and circuit jitter.
By connecting the diodes in series or parallel in an RC buffer and integrating their processes together, spikes and oscillations are suppressed.
Effectively absorb spikes, suppress oscillation, reduce EMI, prolong the life of MOSFET/IGBT, and reduce process costs.
Smart Images
Figure CN119835949A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an RC buffer. The present invention also relates to a manufacturing method of the RC buffer. Background Art
[0002] Power devices such as power MOSFET / IGBT in circuit applications will generate higher voltage overstress, electromagnetic interference (EMI), circuit jitter, and excessive power dissipation when used at high frequencies due to the presence of stray inductance and parasitic capacitance in the circuit. To alleviate this problem, a resistor-capacitor (RC) snubber circuit is usually required to "buffer" or suppress oscillations. By eliminating oscillations, voltage overstress can be reduced, thereby reducing potential EMI and extending the life of the MOSFET / IGBT.
[0003] The existing RC snubber is generally composed of a capacitor and a resistor, which has the advantages of simple circuit and low cost; the disadvantage is that as the power level increases, the snubber circuit will oscillate with the DC bus parasitic inductance. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide an RC snubber, which can realize connecting a diode in series or in parallel to the snubber and integrating the process together, so as to absorb the peak and suppress the oscillation, and also reduce the process cost. To this end, the present invention also provides a method for manufacturing the RC snubber.
[0005] In order to solve the above technical problems, the RC snubber provided by the present invention comprises:
[0006] A plurality of first capacitor unit structures are formed in the active area, wherein the first capacitor unit structures include a first conductive material layer and a first dielectric layer.
[0007] The top of the first conductive material layer is connected to an upper electrode plate composed of a front metal layer.
[0008] The first dielectric layer is isolated between the first conductive material layer and the first epitaxial layer heavily doped with the first conductivity type.
[0009] The first epitaxial layer is formed on a semiconductor substrate doped with a first conductivity type, and the doping concentration of the semiconductor substrate is lower than the doping concentration of the first epitaxial layer.
[0010] The back side of the semiconductor substrate is thinned, and a first electrode region heavily doped with a first conductivity type and a second electrode region heavily doped with a second conductivity type by back ion implantation are sequentially formed in the back side region of the thinned semiconductor substrate.
[0011] The capacitor of the buffer is composed of the first conductive material layer, the first dielectric layer and the first epitaxial layer.
[0012] The resistor structure of the buffer includes the first epitaxial layer between the first electrode region and the first dielectric layer and the semiconductor substrate.
[0013] A diode is formed by the first electrode region and the second electrode region.
[0014] A lower electrode plate composed of a back metal layer is formed on the back side of the semiconductor substrate.
[0015] The back surface of the second electrode region contacts the lower electrode.
[0016] The second electrode region is disposed between all regions of the first electrode region and the lower electrode plate, and the diode is connected in series to the buffer; or, the second electrode region is disposed between a portion of the first electrode region and the lower electrode plate, and another portion of the first electrode region is in contact with the lower electrode plate, and the diode is connected in parallel to the buffer.
[0017] A further improvement is that the first capacitor unit structure is a trench structure.
[0018] The first dielectric layer is formed on the inner surface of the first trench.
[0019] The first conductive material layer is filled in the first trench where the first dielectric layer is formed.
[0020] A further improvement is that the first conductive material layer includes a polysilicon layer.
[0021] The first dielectric layer includes an oxide layer.
[0022] A further improvement is that the resistivity of the semiconductor substrate is 40 ohm·cm to 60 ohm·cm.
[0023] The resistivity of the first epitaxial layer is 0.002 ohm·cm to 0.005 ohm·cm.
[0024] A further improvement is that the thickness of the first epitaxial layer is 35 microns to 40 microns.
[0025] A further improvement is that the width of the first groove is 0.5 micrometer to 1 micrometer, and the depth is 20 micrometer to 25 micrometer.
[0026] A further improvement is that the depth of the first electrode region is 1 micron to 4 microns, and the depth of the second electrode region is 0.5 micron to 3 microns.
[0027] A further improvement is that the first conductivity type is N type and the second conductivity type is P type; or the first conductivity type is P type and the second conductivity type is N type.
[0028] In order to solve the above technical problems, the manufacturing method of the RC buffer provided by the present invention comprises the following steps:
[0029] A plurality of first capacitor unit structures are formed in the active area, wherein the first capacitor unit structures include a first conductive material layer and a first dielectric layer; the first dielectric layer is isolated between the first conductive material layer and a first epitaxial layer heavily doped with a first conductive type; the first epitaxial layer is formed on a semiconductor substrate doped with a first conductive type, and the doping concentration of the semiconductor substrate is less than the doping concentration of the first epitaxial layer.
[0030] A second dielectric layer is formed on a surface of the first epitaxial layer outside the first capacitor unit structure.
[0031] A front metal layer is formed and an upper electrode plate is formed by the front metal layer; the top of the first conductive material layer is connected to the upper electrode plate.
[0032] After completing the front process, the following back process is performed:
[0033] The semiconductor substrate is thinned.
[0034] A first electrode region is formed in a backside region of the semiconductor substrate by performing backside ion implantation with heavy doping of the first conductivity type.
[0035] A second electrode region is formed in a backside region of the semiconductor substrate by performing backside ion implantation with heavy doping of the second conductivity type.
[0036] A back metal layer is formed on the back side of the semiconductor substrate and a lower electrode plate is formed by the back metal layer.
[0037] The capacitor of the buffer is composed of the first conductive material layer, the first dielectric layer and the first epitaxial layer.
[0038] The resistor structure of the buffer includes the first epitaxial layer between the first electrode region and the first dielectric layer and the semiconductor substrate.
[0039] A diode is formed by the first electrode region and the second electrode region.
[0040] The back surface of the second electrode region contacts the lower electrode.
[0041] The second electrode region is disposed between all regions of the first electrode region and the lower electrode plate, and the diode is connected in series to the buffer; or, the second electrode region is disposed between a portion of the first electrode region and the lower electrode plate, and another portion of the first electrode region is in contact with the lower electrode plate, and the diode is connected in parallel to the buffer.
[0042] A further improvement is that the first capacitor unit structure is a trench structure; the steps of forming the first capacitor unit structure include:
[0043] The first trench is formed in selected regions of the first epitaxial layer.
[0044] The first dielectric layer is formed on the inner surface of the first trench.
[0045] The first conductive material layer is filled in the first trench.
[0046] A further improvement is that the first dielectric layer is an oxide layer formed by an oxidation process, and after being formed, the first dielectric layer also extends to the surface of the first epitaxial layer outside the first trench. The second dielectric layer is composed of the first dielectric layer.
[0047] The first conductive material layer is a polysilicon layer. After the growth of the first conductive material layer is completed, the first trench is completely filled and extended to the surface of the first dielectric layer outside the first trench. After that, it also includes etching back using the first dielectric layer as a stop layer to remove the first conductive material layer outside the first trench.
[0048] A further improvement is that the resistivity of the semiconductor substrate is 40 ohm·cm to 60 ohm·cm.
[0049] The resistivity of the first epitaxial layer is 0.002 ohm·cm to 0.005 ohm·cm.
[0050] A further improvement is that the thickness of the first epitaxial layer is 35 microns to 40 microns.
[0051] A further improvement is that the width of the first groove is 0.5 micrometer to 1 micrometer, and the depth is 20 micrometer to 25 micrometer.
[0052] A further improvement is that the depth of the first electrode region is 1 micron to 4 microns, and the depth of the second electrode region is 0.5 micron to 3 microns.
[0053] A further improvement is that the front process further comprises:
[0054] A passivation layer is formed, and the passivation layer is pattern-etched to open the lead-out region of the upper electrode plate.
[0055] The component structure of the capacitor of the RC buffer of the present invention includes a first capacitor unit structure formed on the first epitaxial layer, and the component structure of the resistor includes the first epitaxial layer and the semiconductor substrate. By utilizing the back surface process of the semiconductor substrate, a diode composed of a first electrode area and a second electrode area is further formed in the back surface area of the semiconductor substrate. Therefore, the present invention can integrate the capacitor, the resistor and the diode together; through the graphic structure setting of the second electrode area, the first electrode area can be disconnected from the lower electrode plate or a part of the first electrode area can be connected to the lower electrode plate, thereby realizing the diode being connected in series or in parallel on the buffer formed by the capacitor and the resistor, so the present invention can realize the diode being connected in series or in parallel on the buffer and the process is integrated together; after the buffer and the diode are connected in series or in parallel, the spike is absorbed by the diode, which can achieve a better effect of absorbing the spike and thus better suppress the occurrence of oscillation; the diode of the present invention can be realized only by the back surface process, which can well realize process integration, so the process cost can be reduced.
[0056] In addition, the first capacitor unit structure of the RC buffer of the present invention can be implemented using the gate structure of a semiconductor power device. For example, when the first capacitor unit structure adopts a trench structure, the process of the trench structure can be integrated with the process of the trench gate of a trench gate semiconductor power device such as a trench gate power MOSFET or a power IGBT, which can further reduce the process cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0057] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0058] Figure 1A is a schematic cross-sectional structure diagram of an RC snubber according to a first embodiment of the present invention;
[0059] Figure 1B yes Figure 1A Circuit diagram of
[0060] Figure 2A is a schematic cross-sectional structural diagram of an RC snubber according to a second embodiment of the present invention;
[0061] Figure 2B yes Figure 2A Circuit diagram of
[0062] Figures 3A-3I is a schematic diagram of a cross-sectional structure of a device in each step of a method for manufacturing an RC snubber according to a first embodiment of the present invention;
[0063] Figure 4 It is a schematic diagram of the cross-sectional structure of the device in each step of the manufacturing method of the RC snubber according to the second embodiment of the present invention. DETAILED DESCRIPTION
[0064] The first embodiment of the present invention is an RC buffer:
[0065] like Figure 1A FIG. 1 is a schematic diagram of the cross-sectional structure of an RC buffer according to a first embodiment of the present invention. The RC buffer according to the first embodiment of the present invention comprises:
[0066] A plurality of first capacitor unit structures are formed in the active area 101 , wherein the first capacitor unit structure includes a first conductive material layer 3 and a first dielectric layer 2 .
[0067] A terminal region 102 is provided around the active region 101. Figure 1A In the embodiment, the active region 101 and the terminal region 102 are respectively located on both sides of the strip curve 103. In the top view, the terminal region 102 surrounds the periphery of the active region 101. The terminal region 102 is used to withstand the lateral voltage, and the structure of the terminal region 102 needs to be adjusted according to the specific application, which will not be described in detail in this application.
[0068] The top of the first conductive material layer 3 is connected to the upper electrode plate composed of the front metal layer 4 .
[0069] The first dielectric layer 2 is isolated between the first conductive material layer 3 and the first epitaxial layer 1 b heavily doped with the first conductivity type.
[0070] The first epitaxial layer 1 b is formed on a semiconductor substrate 1 a doped with a first conductivity type, and the doping concentration of the semiconductor substrate 1 a is lower than the doping concentration of the first epitaxial layer 1 b.
[0071] In some embodiments, the material of the semiconductor substrate 1 a includes silicon, and the material of the first epitaxial layer 1 b includes silicon.
[0072] In the first embodiment of the present invention, the first capacitor unit structure is a trench structure.
[0073] The first dielectric layer 2 is formed on the inner surface of the first trench.
[0074] The first conductive material layer 3 is filled in the first trench where the first dielectric layer 2 is formed.
[0075] The first conductive material layer 3 includes a polysilicon layer.
[0076] The first dielectric layer 2 includes an oxide layer. The first dielectric layer 2 is formed by an oxidation process, and the first dielectric layer 2 also extends to the surface of the first epitaxial layer 1b outside the first trench.
[0077] The back side of the semiconductor substrate 1a is thinned, and a first electrode region 6 heavily doped with a first conductivity type and a second electrode region 7 heavily doped with a second conductivity type are sequentially formed in the back side region of the thinned semiconductor substrate 1a by back side ion implantation.
[0078] In some examples, the resistivity of the semiconductor substrate 1 a is 40 ohm·cm to 60 ohm·cm.
[0079] The resistivity of the first epitaxial layer 1 b is 0.002 ohm·cm to 0.005 ohm·cm.
[0080] The thickness of the first epitaxial layer 1b is 35 micrometers to 40 micrometers. In the first embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type. The N type heavily doped impurity of the first epitaxial layer 1b is arsenic.
[0081] In other embodiments, the first conductivity type may be P type, and the second conductivity type may be N type.
[0082] The first groove has a width of 0.5 micrometer to 1 micrometer and a depth of 20 micrometers to 25 micrometers.
[0083] The thickness of the thinned wafer, ie, the stacked layer of the semiconductor substrate 1 a and the first epitaxial layer 1 b , is 60 μm to 100 μm.
[0084] The capacitor structure of the buffer includes a first conductive material layer 3, a first dielectric layer 2 and a first epitaxial layer 1b.
[0085] The resistor structure of the buffer includes a first epitaxial layer 1 b between the first electrode region 6 and the first dielectric layer 2 and a semiconductor substrate 1 a .
[0086] A diode is formed by the first electrode region 6 and the second electrode region 7 .
[0087] A lower electrode plate composed of a back metal layer 8 is formed on the back surface of the semiconductor substrate 1a.
[0088] The back surface of the second electrode region 7 is in contact with the lower electrode.
[0089] In the first embodiment of the present invention, a portion of the first electrode region 6 and the lower electrode plate are separated by the second electrode region 7, and another portion of the first electrode region 6 is in contact with the lower electrode plate, and the diode is connected in parallel to the buffer.
[0090] In some examples, the depth of the first electrode region 6 is 1 micrometer to 4 micrometers, and the depth of the second electrode region 7 is 0.5 micrometer to 3 micrometers.
[0091] Since the depth of the first electrode region 6 is greater than the depth of the second electrode region 7, the first electrode region 6 can be fully back-side ion implanted, while the second electrode region 7 requires patterned back-side ion implantation. In the area where the second electrode region 7 is not formed, the first electrode region 6 will directly contact the lower electrode plate, so that the resistor will also contact the lower electrode plate, realizing the parallel connection of the diode and the resistor.
[0092] like Figure 1B As shown, Figure 1A The buffer includes a capacitor 201a, a resistor 202a and a diode 203a. Figure 1A In the figure, capacitor 201a is also represented by C, resistor 202a is also represented by R, and diode 203a is also represented by VD. It can be seen that one end of resistor 202a is connected to the lower plate, and the other end is connected to capacitor 201a; one end of diode 203a is also connected to the lower plate, and the other end is connected to capacitor 201a; resistor 202a and diode 203a form a parallel structure, and the parallel connection of diode 203a is realized in the RC buffer of the embodiment of the present invention.
[0093] The capacitor structure of the RC buffer of the first embodiment of the present invention includes a first capacitor unit structure formed on the first epitaxial layer 1b, and the resistor structure includes the first epitaxial layer 1b and the semiconductor substrate 1a. By utilizing the back surface process of the semiconductor substrate 1a, a diode composed of a first electrode area 6 and a second electrode area 7 is further formed in the back surface area of the semiconductor substrate 1a. Therefore, the first embodiment of the present invention can integrate the capacitor, the resistor and the diode together; through the graphic structure setting of the second electrode area 7, a part of the first electrode area 6 is connected to the lower electrode plate, so that the diode is connected in parallel to the buffer formed by the capacitor and the resistor. Therefore, the first embodiment of the present invention can connect the diode in series or in parallel to the buffer and integrate the process together; after the buffer and the diode are connected in series or in parallel, the spike is absorbed by the diode, and compared with the buffer without a diode, a better effect of absorbing the spike can be achieved and thus the oscillation can be better suppressed; the diode of the first embodiment of the present invention can be realized only by the back surface process, which can well realize the process integration, so the process cost can be reduced.
[0094] In addition, the first capacitor unit structure of the RC buffer of the first embodiment of the present invention can be implemented using the gate structure of a semiconductor power device. For example, when the first capacitor unit structure adopts a trench structure, the process of the trench structure can be integrated with the process of the trench gate of a trench gate semiconductor power device such as a trench gate power MOSFET or a power IGBT, which can further reduce the process cost.
[0095] The second embodiment of the present invention is an RC buffer:
[0096] like Figure 2A FIG. 1 is a schematic diagram of the cross-sectional structure of the RC buffer according to the second embodiment of the present invention. The difference between the RC buffer according to the first embodiment of the present invention and the RC buffer according to the second embodiment of the present invention is that:
[0097] The second electrode region 7 is spaced between all regions of the first electrode region 6 and the lower electrode plate, and the diode is connected in series to the buffer.
[0098] The second electrode region 7 is formed by comprehensive back ion implantation like the first electrode region 6. Since the second electrode region 7 is formed on the back of the first electrode region 6, the first electrode region 6 will not directly contact the lower electrode plate, so the resistor will not contact the lower electrode plate, and the diode and the resistor are in series.
[0099] like Figure 2B As shown, Figure 2A Circuit diagram; the buffer includes: capacitor 201b, resistor 202b and diode 203b. In FIG1b, capacitor 201b is also represented by C, resistor 202b is also represented by R, and diode 203b is also represented by VD. It can be seen that one end of resistor 202b is connected to the lower plate, and the other end is connected to capacitor 201b; one end of diode 203b is also connected to the lower plate, and the other end is connected to capacitor 201b; resistor 202b and diode 203b form a parallel structure, and the parallel connection of diode 203b is realized in the RC buffer of the embodiment of the present invention.
[0100] The manufacturing method of the RC buffer of the first embodiment of the present invention:
[0101] like Figures 3A to 3I FIG. 1 is a schematic diagram of a cross-sectional structure of a device in each step of a method for manufacturing an RC buffer according to a first embodiment of the present invention. The method for manufacturing an RC buffer according to a first embodiment of the present invention comprises the following steps:
[0102] A plurality of first capacitor unit structures are formed in the active region 101, and the first capacitor unit structures include a first conductive material layer 3 and a first dielectric layer 2; the first dielectric layer 2 is isolated between the first conductive material layer 3 and the first epitaxial layer 1b heavily doped with the first conductive type. Figure 3A As shown, the first epitaxial layer 1 b is formed on a semiconductor substrate 1 a doped with a first conductivity type, and the doping concentration of the semiconductor substrate 1 a is lower than the doping concentration of the first epitaxial layer 1 b.
[0103] In some embodiment methods, the material of the semiconductor substrate 1 a includes silicon, and the material of the first epitaxial layer 1 b includes silicon.
[0104] A second dielectric layer is formed on the surface of the first epitaxial layer 1b outside the first capacitor unit structure.
[0105] In the method of the first embodiment of the present invention, the first capacitor unit structure is a trench structure; the steps of forming the first capacitor unit structure include:
[0106] like Figure 3B As shown, a first trench 104 is formed in a selected region of the first epitaxial layer 1b. In some examples, the step of forming the first trench 104 includes:
[0107] A dielectric layer is deposited on the surface of the first epitaxial layer 1b as a hard mask for etching the first trench 104. The dielectric layer is generally a silicon oxide film grown by a PE-TEOS process with a thickness of 10 to 15 microns. Then, a pattern is formed by photolithography, coating and development. Then, dry etching is performed to form the first trench 104 where the electrode plate needs to be grown. The width and depth of the first trench 104 can be designed according to the device performance. Then, wet etching is performed to completely remove the dielectric layer of the hard mask.
[0108] The formation of the first trench 104 is subject to the etching process, and the aspect ratio of the first trench 104 can be 20 to 50. In some examples, the first trench 104 can have a width of 0.5 micrometers to 1 micrometer and a depth of 20 to 25 micrometers.
[0109] A first dielectric layer 2 is formed on the inner surface of the first trench 104 .
[0110] In the method of the first embodiment of the present invention, Figure 3C As shown, the first dielectric layer 2 is an oxide layer formed by an oxidation process. After the first dielectric layer 2 is formed, it also extends to the surface of the first epitaxial layer 1b outside the first trench 104. The second dielectric layer is composed of the first dielectric layer 2. The thickness of the first dielectric layer 2 can be set according to the operating voltage and the capacitance. In some examples, such as 150V, 3nF / mm2 device corresponding to the first dielectric layer 2 is of the oxide layer.
[0111] like Figure 3D As shown, the first conductive material layer 3 is filled in the first trench 104 .
[0112] In the method of the first embodiment of the present invention, the first conductive material layer 3 is a polysilicon layer. After the growth of the first conductive material layer 3 is completed, the first trench 104 is completely filled and extended to the surface of the first dielectric layer 2 outside the first trench 104; and then the first dielectric layer 2 is used as a stop layer to perform etching back to remove the first conductive material layer 3 outside the first trench 104. The polysilicon of the first conductive material layer 3 is generally deposited using an LPCVD process, and then the first conductive material layer 3 is etched back through a wet etching process to remove the polysilicon on the silicon surface, that is, the surface of the first epitaxial layer 1b. Then, a step of high-temperature annealing of the polysilicon is performed.
[0113] In some examples, the resistivity of the semiconductor substrate 1 a is 40 ohm·cm to 60 ohm·cm.
[0114] The resistivity of the first epitaxial layer 1 b is 0.002 ohm·cm to 0.005 ohm·cm.
[0115] The thickness of the first epitaxial layer 1b needs to be adjusted according to the device application and diode characteristics. In some examples, the thickness of the first epitaxial layer 1b is 35 micrometers to 40 micrometers.
[0116] In the method of the first embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type. The N type heavily doped impurities of the first epitaxial layer 1b are arsenic.
[0117] In other embodiments, the first conductivity type may be P type, and the second conductivity type may be N type.
[0118] like Figure 3E As shown, a front metal layer 4 is formed and an upper electrode plate is formed by the front metal layer 4; the top of the first conductive material layer 3 is connected to the upper electrode plate. In some examples, the front metal layer 4 is made of AlCu, and the deposition thickness is set to 3-5 microns.
[0119] Complete the front process.
[0120] In the method of the first embodiment of the present invention, the front process further includes:
[0121] like Figure 3F As shown, a passivation layer 5 is formed, and the passivation layer 5 is patterned and etched to open the lead-out area of the upper electrode plate. In some examples, the deposition thickness of the passivation layer 5 is 1 to 2 microns, and the material of the passivation layer 5 uses a combination of one or more of SiN, SRN, SRO and SIO2; after the deposition of the passivation layer 5, the area where the electrode needs to be led out is opened by photolithography and dry etching processes. In other embodiments, the passivation layer 5 can further increase a layer of polyimide to further improve the reliability of the device.
[0122] Then the following back process is carried out:
[0123] like Figure 3G As shown, the semiconductor substrate 1a is thinned.
[0124] In some examples, the back side of the wafer is thinned by a Taiko grinding process, and the thickness of the thinned wafer, ie, the stacked layer of the semiconductor substrate 1 a and the first epitaxial layer 1 b , is 60 μm to 100 μm.
[0125] like Figure 3H As shown, a first electrode region 6 is formed in the back region of the semiconductor substrate 1 a by performing back ion implantation with heavy doping of the first conductivity type.
[0126] In the method of the first embodiment of the present invention, the first electrode region 6 is implanted with full back ion implantation. Since the first conductivity type is N type, the implanted impurities of the first electrode region 6 are generally P, and the implantation depth is 1 micron to 4 microns.
[0127] like Fig. 3I As shown, a second electrode region 7 is formed in the back region of the semiconductor substrate 1 a by performing back ion implantation with heavy doping of the second conductivity type.
[0128] The implanted impurities of the second electrode region 7 are generally B ions, with a depth of 0.5 to 3 micrometers. Then, the first electrode region 6 and the second electrode region 7 are activated by laser thermal ablation (LTA).
[0129] In the method of the first embodiment of the present invention, a part of the first electrode region 6 and the lower electrode plate are separated by the second electrode region 7, and another part of the first electrode region 6 is in contact with the lower electrode plate, and the diode is connected in parallel to the buffer.
[0130] The second electrode region 7 is implemented by patterned back ion implantation. The depth of the second electrode region 7 is greater than the depth of the first electrode region 6. In the area where the second electrode region 7 is not formed, the first electrode region 6 will directly contact the lower electrode plate, so that the resistor will also contact the lower electrode plate, realizing the parallel connection of the diode and the resistor.
[0131] like Figure 1A As shown, a back metal layer 8 is formed on the back side of the semiconductor substrate 1a and the lower electrode plate is composed of the back metal layer 8.
[0132] In some examples, the material of the back metal layer 8 can be AlNiAg, and the following combinations can be used according to thickness: Al, Ni, After the back metal layer 8 is deposited, the back metal is annealed, generally at 430° C. for 30 minutes.
[0133] The capacitor structure of the buffer includes a first conductive material layer 3, a first dielectric layer 2 and a first epitaxial layer 1b.
[0134] The resistor structure of the buffer includes a first epitaxial layer 1 b between the first electrode region 6 and the first dielectric layer 2 and a semiconductor substrate 1 a .
[0135] A diode is formed by the first electrode region 6 and the second electrode region 7 .
[0136] The back surface of the second electrode region 7 is in contact with the lower electrode.
[0137] In the first embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type. In other embodiments, the first conductivity type can be P type and the second conductivity type can be N type.
[0138] The manufacturing method of the RC buffer according to the second embodiment of the present invention:
[0139] like Figure 4 FIG. 1 is a schematic diagram of the cross-sectional structure of the device in each step of the manufacturing method of the RC snubber according to the second embodiment of the present invention; the difference from the manufacturing method of the RC snubber according to the first embodiment of the present invention is that in the manufacturing method of the RC snubber according to the second embodiment of the present invention:
[0140] In completion Figure 3H After the first electrode region 6 shown, Figure 4 The steps of forming the second electrode region 7 are shown. The second electrode region 7 is formed by comprehensive back ion implantation. Since the second electrode region 7 is formed on the back of the first electrode region 6, the first electrode region 6 will not directly contact the lower electrode plate. All areas of the first electrode region 6 and the lower electrode plate are separated by the second electrode region 7. In this way, the resistor will not contact the lower electrode plate. The diode and the resistor are in series, and the diode will be connected in series to the buffer.
[0141] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. An RC snubber, characterized in that: include: A plurality of first capacitor unit structures formed in the active area, wherein the first capacitor unit structures include a first conductive material layer and a first dielectric layer; The top of the first conductive material layer is connected to an upper electrode plate composed of a front metal layer; The first dielectric layer is isolated between the first conductive material layer and the first epitaxial layer heavily doped with the first conductivity type; A first epitaxial layer is formed on a semiconductor substrate doped with a first conductivity type, wherein the doping concentration of the semiconductor substrate is less than the doping concentration of the first epitaxial layer; The back side of the semiconductor substrate is thinned, and a first electrode region heavily doped with a first conductivity type and a second electrode region heavily doped with a second conductivity type by back ion implantation are sequentially formed in the back side region of the semiconductor substrate after the thinning; The capacitor of the buffer is composed of the first conductive material layer, the first dielectric layer and the first epitaxial layer; The resistor structure of the buffer includes the first epitaxial layer and the semiconductor substrate between the first electrode region and the first dielectric layer; forming a diode by the first electrode region and the second electrode region; A lower electrode plate composed of a back metal layer is formed on the back side of the semiconductor substrate; The back side of the second electrode region is in contact with the lower electrode; The second electrode region is disposed between all regions of the first electrode region and the lower electrode plate, and the diode is connected in series to the buffer; or, the second electrode region is disposed between a portion of the first electrode region and the lower electrode plate, and another portion of the first electrode region is in contact with the lower electrode plate, and the diode is connected in parallel to the buffer.
2. The RC snubber according to claim 1, wherein: The first capacitor unit structure is a trench structure; The first dielectric layer is formed on the inner surface of the first trench; The first conductive material layer is filled in the first trench where the first dielectric layer is formed.
3. The RC snubber according to claim 2, wherein: The first conductive material layer includes a polysilicon layer; The first dielectric layer includes an oxide layer.
4. The RC snubber according to claim 2, wherein: The resistivity of the semiconductor substrate is 40 ohm·cm to 60 ohm·cm; The resistivity of the first epitaxial layer is 0.002 ohm·cm to 0.005 ohm·cm.
5. The RC snubber according to claim 4, wherein: The thickness of the first epitaxial layer is 35 micrometers to 40 micrometers.
6. The RC snubber according to claim 2, wherein: The first groove has a width of 0.5 micrometer to 1 micrometer and a depth of 20 micrometers to 25 micrometers.
7. The RC snubber according to claim 2, wherein: The depth of the first electrode region is 1 micrometer to 4 micrometers, and the depth of the second electrode region is 0.5 micrometer to 3 micrometers.
8. The RC snubber according to any one of claims 1 to 7, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.
9. A method for manufacturing an RC buffer, characterized in that: The steps include: A plurality of first capacitor unit structures are formed in the active area, wherein the first capacitor unit structures include a first conductive material layer and a first dielectric layer; the first dielectric layer is isolated between the first conductive material layer and the first epitaxial layer heavily doped with the first conductive type; A first epitaxial layer is formed on a semiconductor substrate doped with a first conductivity type, wherein the doping concentration of the semiconductor substrate is less than the doping concentration of the first epitaxial layer; forming a second dielectric layer on a surface of the first epitaxial layer outside the first capacitor unit structure; forming a front metal layer and forming an upper electrode plate from the front metal layer; The top of the first conductive material layer is connected to the upper electrode plate; After completing the front process, the following back process is performed: Thinning the semiconductor substrate; Performing back ion implantation with heavy doping of the first conductivity type to form a first electrode region in the back region of the semiconductor substrate; Performing back ion implantation with heavy doping of the second conductivity type to form a second electrode region in the back region of the semiconductor substrate; forming a back metal layer on the back side of the semiconductor substrate and forming a lower electrode plate from the back metal layer; The capacitor of the buffer is composed of the first conductive material layer, the first dielectric layer and the first epitaxial layer; The resistor structure of the buffer includes the first epitaxial layer and the semiconductor substrate between the first electrode region and the first dielectric layer; forming a diode by the first electrode region and the second electrode region; The back side of the second electrode region is in contact with the lower electrode; The second electrode region is disposed between all regions of the first electrode region and the lower electrode plate, and the diode is connected in series to the buffer; or, the second electrode region is disposed between a portion of the first electrode region and the lower electrode plate, and another portion of the first electrode region is in contact with the lower electrode plate, and the diode is connected in parallel to the buffer.
10. The method for manufacturing an RC snubber according to claim 9, wherein: The first capacitor unit structure is a trench structure; The steps of forming the first capacitor unit structure include: forming the first trench in a selected region of the first epitaxial layer; forming the first dielectric layer on the inner surface of the first trench; The first conductive material layer is filled in the first trench.
11. The method for manufacturing an RC snubber according to claim 10, wherein: The first dielectric layer is an oxide layer formed by an oxidation process, and after being formed, the first dielectric layer also extends to the surface of the first epitaxial layer outside the first trench; the second dielectric layer is composed of the first dielectric layer; The first conductive material layer is a polysilicon layer. After the growth of the first conductive material layer is completed, the first trench is completely filled and extended to the surface of the first dielectric layer outside the first trench. After that, it also includes etching back using the first dielectric layer as a stop layer to remove the first conductive material layer outside the first trench.
12. The method for manufacturing an RC snubber according to claim 10, wherein: The resistivity of the semiconductor substrate is 40 ohm·cm to 60 ohm·cm; The resistivity of the first epitaxial layer is 0.002 ohm·cm to 0.005 ohm·cm.
13. The method for manufacturing an RC snubber according to claim 12, wherein: The thickness of the first epitaxial layer is 35 micrometers to 40 micrometers.
14. The method for manufacturing an RC snubber according to claim 10, wherein: The first groove has a width of 0.5 micrometer to 1 micrometer and a depth of 20 micrometers to 25 micrometers.
15. The method for manufacturing an RC snubber according to claim 10, wherein: The depth of the first electrode region is 1 micrometer to 4 micrometers, and the depth of the second electrode region is 0.5 micrometer to 3 micrometers.
16. The method for manufacturing an RC snubber according to claim 9, wherein: The front process also includes: A passivation layer is formed, and the passivation layer is pattern-etched to open the lead-out region of the upper electrode plate.