PGaN gate enhanced device and self-termination etching method thereof

Abstract

The invention discloses a pGaN gate enhanced device and a self-termination etching method thereof. The self-termination etching method comprises the following steps: sequentially growing a nucleating layer, a buffer layer, a channel layer, a barrier layer, a high Al component layer and a p-GaN layer on a substrate layer; etching the p-GaN layer except the gate electrode region to expose the high-Al component layer; f plasma surface treatment is conducted on the high-Al component layer so that an AlF3 layer can be formed on the upper surface of the high-Al component layer; etching the AlF3 layer in source and drain electrode areas at two ends of the device until the upper surface of the barrier layer, and forming a source electrode and a drain electrode on the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; the residual AlF3 layer is used as a passivation layer to protect the barrier layer; and forming a gate electrode on the upper surface of the p-GaN layer. According to the invention, the surface roughness of the barrier layer after etching is effectively improved, and meanwhile, the gate leakage current of the device is effectively inhibited.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a pGaN gate enhancement type device and a self-termination etching method thereof. Background Art

[0002] The unique material advantages of GaN make it show great potential and application prospects in the field of power devices, while GaN HEMT devices naturally tend to be depletion-type. In order to reduce costs, improve device safety and reliability, and promote the upgrading of related industries, it is necessary to develop enhancement-mode devices.

[0003] Among the several mainstream schemes for manufacturing enhancement-mode GaN HEMT devices, enhancement-mode devices made with p-GaN gates can provide low on-resistance and large positive threshold voltage. The current mainstream technical route is to form a PN junction structure under the gate electrode, and use p-GaN to deplete the 2DEG under the channel to achieve channel pinch-off. This device structure is also called a p-GaN gate enhancement-mode device. The necessary process steps for preparing p-GaN gate enhancement-mode devices are to etch away all the p-GaN layers outside the gate electrode area. Currently, inductively coupled plasma (ICP) etching is commonly used. The common GaN-ICP etching gas is BCl3 / Cl2, but the gas has a low etching selectivity for GaN / AlGaN. It is difficult to accurately control the etching time to achieve that the p-GaN layer is completely etched and the AlGaN barrier layer is not damaged. The p-GaN residue or the AlGaN barrier layer is etched and thinned, which will lead to a decrease in the concentration of the 2DEG below, thereby affecting the output characteristics of the device. The mainstream process of removing p-GaN from non-gate electrode areas by etching poses challenges in terms of roughness, uniformity, selectivity, etc. due to the characteristics of the etching process. Therefore, obtaining smaller surface etching damage and achieving p-GaN self-termination etching to ensure that p-GaN is completely etched and the AlGaN barrier layer is not damaged is the key difficulty in the preparation of p-GaN gate enhancement devices. The existing p-GaN etching process mainly improves the etching selectivity of GaN / AlGaN by adding auxiliary gases such as SF6 or O2 to the etching gas to form a barrier layer with the Al element in the AlGaN barrier layer.

[0004] However, in order to achieve a higher etching selectivity, it is often necessary to increase the proportion of auxiliary gas, and the increase of auxiliary gas will lead to an increase in adverse effects such as surface damage of GaF3 or Ga-O bonds. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a pGaN gate enhancement device and a self-termination etching method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a self-termination etching method based on a pGaN gate enhancement device, the self-termination etching method comprising:

[0007] A nucleation layer, a buffer layer, a channel layer, a barrier layer, a high Al composition layer and a p-GaN layer are sequentially grown on the substrate layer;

[0008] Etching away the p-GaN layer except for the gate electrode region to expose the high Al composition layer;

[0009] Performing F plasma surface treatment on the high Al composition layer to form an AlF3 layer on the upper surface of the high Al composition layer;

[0010] Etching the AlF3 layer in the source and drain electrode regions at both ends of the device until the upper surface of the barrier layer, and forming a source electrode and a drain electrode on the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; and the remaining AlF3 layer serves as a passivation layer to protect the barrier layer;

[0011] A gate electrode is formed on the upper surface of the p-GaN layer.

[0012] In one embodiment of the present invention, growing a high Al composition layer on the barrier layer comprises:

[0013] An AlGaN material with an Al component greater than 0.5 and a thickness of 1 nm to 2 nm is grown on the barrier layer to obtain a high Al component layer.

[0014] In one embodiment of the present invention, etching away the p-GaN layer except for the gate electrode region to expose the high Al composition layer includes:

[0015] Based on a fluorine-based gas, the p-GaN layer except for the gate electrode region is etched away to expose the high Al composition layer.

[0016] In one embodiment of the present invention, the high Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high Al composition layer, comprising:

[0017] The high Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high Al composition layer.

[0018] In one embodiment of the present invention, the high Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high Al composition layer, comprising:

[0019] The high Al component layer is subjected to F plasma surface treatment using ICP equipment to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high Al component layer; the ICP process parameters used include: ICP power of 150 W, RF power of 20 W, CF4 gas flow rate of 30 sccm, and processing time of 120 s.

[0020] In one embodiment of the present invention, before forming the source electrode and the drain electrode, the method further comprises:

[0021] The AlF3 layer at both ends of the device is etched to the upper surface of the buffer layer to form a mesa isolation.

[0022] In one embodiment of the present invention, etching the AlF3 layer at both ends of the device to the upper surface of the buffer layer includes:

[0023] Based on at least one gas selected from the group consisting of chlorine-based, fluorine-based, Ar, N2, and O2, the AlF3 layer at both ends of the device is etched until the upper surface of the buffer layer.

[0024] In a second aspect, an embodiment of the present invention provides a pGaN gate enhancement mode device, wherein the pGaN gate enhancement mode device is prepared by using the self-termination etching method of the pGaN gate enhancement mode device described in any one of the first aspects; the pGaN gate enhancement mode device comprises:

[0025] A substrate layer, and a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a high Al composition layer sequentially disposed on the substrate layer;

[0026] A p-GaN layer located on the high Al composition layer near one end of the device;

[0027] An AlF3 layer is located on the remaining high Al component layer;

[0028] A source electrode and a drain electrode, located in the source-drain electrode region at both ends of the device and penetrating the AlF3 layer to the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer;

[0029] The gate electrode is located on the p-GaN layer.

[0030] In one embodiment of the present invention, the high Al composition layer is an AlGaN material with an Al composition greater than 0.5 and a thickness of 1 nm to 2 nm.

[0031] In one embodiment of the present invention, the thickness of the AlF3 layer is 0.5 nm to 1 nm.

[0032] Beneficial effects of the present invention:

[0033] The self-termination etching method of the pGaN gate enhancement type device proposed in the present invention further improves the preparation method on the basis of improving the device structure to prepare a GaN-based enhancement device with high electron mobility, which combines the original high threshold voltage, high breakdown voltage, high current density, and excellent pinch-off characteristics of the GaN-based HEMT device, while reducing the required proportion of auxiliary gas in the etching process, thereby reducing the adverse effects caused by the auxiliary gas, effectively improving the surface roughness of the barrier layer after etching, avoiding the problem of over-etching the barrier layer, and effectively suppressing the gate leakage current of the device. Specifically: by adding a high Al component layer between the barrier layer and the p-GaN layer, the increase of the Al component makes it easier for the F ions in the etching gas and the Al in the high Al component layer to form an AlF3 layer in the process of etching the p-GaN layer in the non-gate region to improve the High etching selectivity reduces the etching damage to the barrier layer surface. After the p-GaN layer in the non-gate region is etched, the sample is placed in F plasma for surface treatment. On the one hand, the formation of the AlF3 layer is further promoted. The AlF3 layer acts as a passivation layer at this time, which can protect the barrier layer and suppress the gate leakage current of the device. On the other hand, a thin insulating layer is formed on the surface of the p-GaN layer after F plasma treatment, which can significantly reduce the leakage current of the Schottky gate. At the same time, it reduces the surface state and defects caused by etching the non-P-GaN gate region, and improves the working performance of the GaN-based HEMT device. The growth of the high Al component layer and the F plasma treatment after etching are compatible with the existing material growth process and p-GaN etching process, and no additional photolithography operation is required, which saves costs and effectively reduces the production cost on the basis of improving device performance.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic flow chart of a self-termination etching method for a pGaN gate enhancement type device provided by an embodiment of the present invention;

[0036] Figure 2a to Figure 2g It is a structural schematic diagram corresponding to the self-termination etching process of the pGaN gate enhancement mode device provided by an embodiment of the present invention;

[0037] Figure 3 The embodiment of the present invention provides Figure 1 Schematic diagram of transfer curve and gate electrode leakage current of pGaN gate enhancement mode device obtained by self-termination etching method;

[0038] Figure 4 It is original and has not been Figure 1 Schematic diagram of the roughness of the barrier layer processed by the self-termination etching method;

[0039] Figure 5 It is through Figure 1 Schematic diagram of the roughness of the barrier layer processed by the self-termination etching method;

[0040] Figure 6 It is a schematic structural diagram of a pGaN gate enhancement type device provided in an embodiment of the present invention.

[0041] Description of reference numerals:

[0042] 01-substrate layer; 02-nucleation layer; 03-buffer layer; 04-channel layer; 05-barrier layer; 06-high Al composition layer; 07-p-GaN layer; 08-AlF3 layer; 09-source electrode; 10-drain electrode; 11-gate electrode. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0044] See also Figure 1 The embodiment of the present invention provides a self-termination etching method based on a pGaN gate enhancement device, and the self-termination etching method includes:

[0045] S10 , a nucleation layer 02 , a buffer layer 03 , a channel layer 04 , a barrier layer 05 , a high Al composition layer 06 and a p-GaN layer 07 are sequentially grown on the substrate layer 01 .

[0046] In the embodiment of the present invention, the material of the substrate layer 01 is any one of silicon, sapphire, silicon carbide, gallium nitride, and a diamond self-supporting substrate.

[0047] The embodiment of the present invention adopts a metal organic chemical vapor deposition process to sequentially grow a nucleation layer 02, a buffer layer 03, a channel layer 04, a barrier layer 05, a high Al composition layer 06 and a p-GaN layer 07 on a substrate layer 01. Figure 2a As shown. Among them, the material of the nucleation layer 02 is AlN superlattice; the material of the buffer layer 03 is GaN or AlGaN, and the Al component in AlGaN here is a gradual process from 0.7 to 0.1 from bottom to top; the material of the channel layer 04 is GaN; the material of the barrier layer 05 is AlGaN, and the Al component in AlGaN here is 0.25; the material of the high Al component layer 06 is AlGaN, and the Al component in AlGaN here is greater than 0.5. Among them, the Al component in the high Al component layer 06 is greater than 0.5, which makes it easier to achieve self-termination etching. The higher the Al component, the greater the selective etching ratio of the p-GaN layer 07 and the barrier layer 05, and the smaller the interface damage after etching.

[0048] The embodiment of the present invention adopts a metal organic chemical vapor deposition process to sequentially grow a nucleation layer 02 with a thickness of 0.5nm to 2nm, a buffer layer 03 with a thickness of 0.2μm to 1μm, a channel layer 04 with a thickness of 100nm to 300nm, a barrier layer 05 with a thickness of 10nm to 30nm, a high Al component layer 06 with a thickness of 1nm to 2nm, and a p-GaN layer 07 with a thickness of 70nm to 120nm on a substrate layer 01.

[0049] In conventional pGaN gate enhancement devices, a certain proportion of SF6 is usually added to the etching gas to improve the etching selectivity of the p-GaN gate, but the proportion of auxiliary gas is usually 40% or higher. The higher the proportion of auxiliary gas, the more difficult volatile compounds such as GaF3 are formed during the etching process, which is not conducive to the formation of high-quality etching interfaces. By adding a high Al component layer 06 between the barrier layer 05 and the p-GaN layer 07, the proportion of auxiliary gas in the etching gas can be reduced, thereby reducing the formation of difficult volatile compounds such as GaF3 during the etching process. Among them, the thickness selection of the high Al component layer 06 is very critical. The appropriate thickness can achieve self-termination etching without causing too much impact on the device performance. The embodiment of the present invention preferably has a high Al component layer 06 of 1nm to 2nm, because the high Al component layer 06 less than 1nm has a poor effect of self-termination etching, and the high Al component layer 06 greater than 2nm causes the 2DEG concentration and mobility in the channel to change, thereby affecting the device performance.

[0050] S20 , etching away the p-GaN layer 07 except the gate electrode region to expose the high Al composition layer 06 .

[0051] The embodiment of the present invention obtains a patterned gate electrode region through a photolithography process; Figure 2b As shown, based on fluorine-based gas, the p-GaN layer 07 except the gate electrode region is etched away by ICP process, and only the p-GaN layer 07 below the gate electrode region is retained to expose the high Al composition layer 06, as shown in FIG. Figure 2c Here, the fluorine-based gas is selected in order to better achieve the effect of F plasma surface treatment on the high Al component layer 06 in the subsequent process.

[0052] S30 , performing F plasma surface treatment on the high Al composition layer 06 to form an AlF 3 layer 08 on the upper surface of the high Al composition layer 06 .

[0053] In the embodiment of the present invention, the high Al component layer 06 is subjected to F plasma surface treatment to form an AlF3 layer 08 on the upper surface of the high Al component layer 06, comprising: using an ICP device to place the sample obtained by S20 in F plasma to perform F plasma surface treatment on the high Al component layer 06 to form an AlF3 layer 08 on the upper surface of the high Al component layer 06, such as Figure 2d As shown, the AlF3 layer 08 is a thin layer structure with a thickness of 0.5nm to 1nm. The ICP process parameters used include: ICP power of 150W, RF power of 20W, CF4 gas flow of 30sccm, and processing time of 120s, to ensure that the device performance will not be damaged too much under these parameters, and the device gate leakage current can be effectively suppressed.

[0054] S40, etching the AlF3 layer 08 in the source and drain electrode regions at both ends of the device until the upper surface of the barrier layer 05, and forming a source electrode 09 and a drain electrode 10 on the upper surface of the barrier layer 05; wherein the source electrode 09 is close to the p-GaN layer 07; the remaining AlF3 layer 08 serves as a passivation layer to protect the barrier layer 05.

[0055] Before forming the source electrode 09 and the drain electrode 10, the embodiment of the present invention further includes: etching the AlF3 layer 08 at both ends of the device until the upper surface of the buffer layer 03 to form a mesa isolation, such as Figure 2e More specifically, the embodiment of the present invention etches the AlF3 layer 08 at both ends of the device until the upper surface of the buffer layer 03, including: etching the AlF3 layer 08 at both ends of the device until the upper surface of the buffer layer 03 using an ICP or RIE (Reactive Ion Etching) process based on at least one of chlorine-based, fluorine-based, Ar, N2 or O2 gases, that is, the etching depth is the sum of the thicknesses of the AlF3 layer 08, the high Al component layer 06, the barrier layer 05 and the channel layer 04.

[0056] Furthermore, in the embodiment of the present invention, a patterned source-drain electrode region is obtained by a photolithography process, and the AlF3 layer 08 of the source-drain electrode region at both ends of the device is etched by an ICP or RIE process based on at least one gas selected from the group consisting of chlorine-based, fluorine-based, Ar, N2, or O2 until the upper surface of the barrier layer 05, that is, the etching depth is the sum of the thicknesses of the AlF3 layer 08 and the high Al component layer 06, and an electron beam evaporation process is used to deposit an ohmic metal, such as a Ti / Al / Ni / Au or Ti / Al / Ti / Au stack, on the upper surface of the barrier layer 05 in the source-drain electrode region to form a source electrode 09 and a drain electrode 10, as shown in FIG. Figure 2f As shown, the ohmic contact is formed by thermal annealing at a high temperature of more than 800° C. in a nitrogen atmosphere for 15 seconds to 60 seconds.

[0057] S50 , forming a gate electrode 11 on the upper surface of the p-GaN layer 07 .

[0058] In the embodiment of the present invention, a patterned gate electrode region is obtained by photolithography, and a gate metal such as Ni / Au or Ni / TiN stack is deposited on the upper surface of the p-GaN layer 07 in the gate electrode region by electron beam evaporation to form a gate electrode 11. Figure 2gshown.

[0059] The gate leakage current of the p-GaN gate enhancement device under the conventional structure is about 10-4mA / mm, while the pGaN gate enhancement device prepared by the self-termination etching method proposed in the present invention, such as Figure 3 As shown, the gate leakage current is below 10-6mA / mm, which reduces the gate current by at least two orders of magnitude. The present invention effectively suppresses the gate leakage current of the device without reducing the output current of the device. Figure 3 The middle horizontal axis represents the gate voltage Vg, in V, the left vertical axis represents the device output current Id, in mA / mm, and the right vertical axis represents the gate leakage current Ig, in mA / mm.

[0060] Depend on Figure 4 It can be seen that the roughness Ra of the barrier layer that has not been processed by the self-termination etching method proposed by the present invention is 1.694nm; Figure 5 It can be seen that the roughness Ra of the barrier layer processed by the self-termination etching method proposed in the present invention is 0.231. By comparison, it can be seen that the self-termination etching method proposed in the present invention effectively improves the surface roughness of the barrier layer after etching. Figure 4 and Figure 5 The horizontal and vertical coordinate information determines the size of the measurement area.

[0061] In summary, the self-termination etching method of the pGaN gate enhancement device proposed in the embodiment of the present invention further improves the preparation method on the basis of improving the device structure, so as to prepare a GaN-based enhancement device with high electron mobility, which combines the original high threshold voltage, high breakdown voltage, high current density, and excellent pinch-off characteristics of the GaN-based HEMT device, while reducing the required proportion of auxiliary gas in the etching process, thereby reducing the adverse effects caused by the auxiliary gas, effectively improving the surface roughness of the barrier layer 05 after etching, avoiding the problem of over-etching the barrier layer 05, and effectively suppressing the gate leakage current of the device. Specifically: by adding a high Al component layer 06 between the barrier layer 05 and the p-GaN layer 07, the increase in the Al component makes it easier for the F ions in the etching gas and the Al in the high Al component layer 06 to form an AlF3 layer during the etching of the p-GaN layer 07 in the non-gate region. 08 is used to improve the etching selectivity and reduce the etching damage to the surface of the barrier layer 05; after the etching of the p-GaN layer 07 in the non-gate region is completed, the sample is placed in F plasma for surface treatment, which further promotes the formation of the AlF3 layer 08. The AlF3 layer 08 acts as a passivation layer at this time, which can protect the barrier layer 05 and suppress the gate leakage current of the device. On the other hand, a thin insulating layer is formed on the surface of the p-GaN layer 07 after the F plasma treatment, which can significantly reduce the leakage current of the Schottky gate and reduce the surface state and defects caused by etching the non-P-GaN gate region, thereby improving the working performance of the GaN-based HEMT device; the growth of the high Al composition layer 06 and the F plasma treatment after etching are compatible with the existing material growth process and p-GaN etching process, and no additional photolithography operation is required, which saves costs and effectively reduces the production cost on the basis of improving device performance.

[0062] Second, see Figure 6 The embodiment of the present invention provides a pGaN gate enhancement device, which is prepared by using any one of the self-termination etching methods of the pGaN gate enhancement device of the first aspect; the pGaN gate enhancement device comprises:

[0063] A substrate layer 01, and a nucleation layer 02, a buffer layer 03, a channel layer 04, a barrier layer 05, and a high Al composition layer 06 sequentially disposed on the substrate layer 01;

[0064] p-GaN layer 07, located on the high Al composition layer 06 near one end of the device;

[0065] AlF3 layer 08, located on the remaining high Al composition layer 06;

[0066] The source electrode 09 and the drain electrode are located in the source-drain electrode 10 region at both ends of the device and penetrate the AlF3 layer 08 to the upper surface of the barrier layer 05; wherein the source electrode 09 is close to the p-GaN layer 07;

[0067] The gate electrode 11 is located on the p-GaN layer 07 .

[0068] In the embodiment of the present invention, the high Al composition layer 06 is an AlGaN material with an Al composition greater than 0.5 and a thickness of 1 nm to 2 nm.

[0069] In the embodiment of the present invention, the thickness of the AlF3 layer 08 is 0.5 nm to 1 nm.

[0070] As for the device embodiment of the second aspect, since it is basically similar to the self-termination etching method embodiment of the first aspect, the description is relatively simple, and the relevant parts may refer to the partial description of the self-termination etching method embodiment of the first aspect.

[0071] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0072] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0073] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A self-termination etching method for a pGaN gate enhancement mode device, characterized in that: The self-termination etching method comprises: A nucleation layer, a buffer layer, a channel layer, a barrier layer, a high Al composition layer and a p-GaN layer are sequentially grown on the substrate layer; Etching away the p-GaN layer except for the gate electrode region to expose the high Al composition layer; Performing F plasma surface treatment on the high Al composition layer to form an AlF3 layer on the upper surface of the high Al composition layer; Etching the AlF3 layer in the source and drain electrode regions at both ends of the device until the upper surface of the barrier layer, and forming a source electrode and a drain electrode on the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; and the remaining AlF3 layer serves as a passivation layer to protect the barrier layer; A gate electrode is formed on the upper surface of the p-GaN layer.

2. The self-termination etching method of pGaN gate enhancement mode device according to claim 1, characterized in that: Growing a high Al composition layer on the barrier layer, comprising: An AlGaN material with an Al component greater than 0.5 and a thickness of 1 nm to 2 nm is grown on the barrier layer to obtain a high Al component layer.

3. The self-termination etching method for pGaN gate enhancement mode device according to claim 1, characterized in that: Etching away the p-GaN layer except for the gate electrode region to expose the high Al composition layer, comprising: Based on a fluorine-based gas, the p-GaN layer except for the gate electrode region is etched away to expose the high Al composition layer.

4. The self-termination etching method of pGaN gate enhancement mode device according to claim 1, characterized in that: The high Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high Al composition layer, comprising: The high Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high Al composition layer.

5. The self-termination etching method of pGaN gate enhancement mode device according to claim 1, characterized in that: The high Al composition layer is subjected to F plasma surface treatment to form an AlF3 layer on the upper surface of the high Al composition layer, comprising: The high Al component layer is subjected to F plasma surface treatment using ICP equipment to form an AlF3 layer with a thickness of 0.5 nm to 1 nm on the upper surface of the high Al component layer; the ICP process parameters used include: ICP power of 150 W, RF power of 20 W, CF4 gas flow rate of 30 sccm, and processing time of 120 s.

6. The self-termination etching method of pGaN gate enhancement mode device according to claim 1, characterized in that: Before forming the source electrode and the drain electrode, it also includes: The AlF3 layer at both ends of the device is etched to the upper surface of the buffer layer to form a mesa isolation.

7. The self-termination etching method of pGaN gate enhancement mode device according to claim 6, characterized in that: Etching the AlF3 layer at both ends of the device to the upper surface of the buffer layer, comprising: Based on at least one gas selected from the group consisting of chlorine-based, fluorine-based, Ar, N2, and O2, the AlF3 layer at both ends of the device is etched until the upper surface of the buffer layer.

8. A pGaN gate enhancement mode device, characterized in that: The pGaN gate enhancement mode device is prepared by the self-termination etching method of the pGaN gate enhancement mode device according to any one of claims 1 to 7; The pGaN gate enhancement mode device comprises: A substrate layer, and a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a high Al composition layer sequentially disposed on the substrate layer; A p-GaN layer located on the high Al composition layer near one end of the device; An AlF3 layer is located on the remaining high Al component layer; A source electrode and a drain electrode, located in the source-drain electrode region at both ends of the device and penetrating the AlF3 layer to the upper surface of the barrier layer; wherein the source electrode is close to the p-GaN layer; The gate electrode is located on the p-GaN layer.

9. The pGaN gate enhancement mode device according to claim 8, characterized in that: The high Al component layer is an AlGaN material with an Al component greater than 0.5 and a thickness of 1 nm to 2 nm.

10. The pGaN gate enhancement mode device according to claim 8, characterized in that: The thickness of the AlF3 layer is 0.5nm to 1nm.

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