Optimization method of silicon-on-insulator field effect transistor gate oxide and product thereof

Abstract

The invention discloses an optimization method of a silicon-on-insulator field effect transistor gate oxide and a product thereof, and belongs to the technical field of semiconductor manufacturing, and the method comprises the steps: forming an insulated gate dielectric layer at the top of an active region on a semiconductor substrate; forming a polycrystalline silicon gate on the insulating gate dielectric layer; removing a part of the insulating gate dielectric layer at the bottom of the polycrystalline silicon gate; covering an oxide liner on the periphery of the polycrystalline silicon grid electrode; an oxide liner is used as a mask, impurities are injected into the active region, and a lightly doped expansion region is generated; covering a silicon nitride layer on the periphery of the polycrystalline silicon gate covered with the oxide liner; etching the silicon nitride layer until the oxide liner is reached; the etched silicon nitride layer is used as a mask, impurities are injected into the lightly doped expansion region, and a source / drain region is generated; the dopant is activated, and the thickness of the active region silicon layer of the silicon-on-insulator device and the reliability of the silicon device are guaranteed by removing a part of the insulated gate dielectric layer in advance before re-oxidation.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for optimizing a gate oxide of a silicon-on-insulator field effect transistor and a silicon-on-insulator field effect transistor. Background Art

[0002] Since the adoption of RF silicon-on-insulator switches in the wireless communication field, RF silicon-on-insulator switches have occupied more than 90% of the market share. Breakdown voltage, device on-resistance, device off-capacitance and harmonics are key device characteristics of RF switches. The existing technology for reducing capacitance and increasing breakdown voltage is to apply a re-oxidation step after the polysilicon gate is formed. The re-oxidation step effectively erodes the edge of the polysilicon and increases the gate oxide thickness at the edge. Thicker gate oxide reduces the peak electric field, resulting in higher breakdown voltage. The increased thickness also reduces overlap capacitance, which helps device reliability and improves some RF switch performance. Reliability issues include hot carrier injection (HCI) that causes threshold voltage shift and gate-induced drain leakage (GIDL) current that causes early failures, where the drain leakage current deteriorates RF harmonic performance.

[0003] However, since the reoxidation step grows a thin layer of silicon oxide on the gate sidewalls and on top of the source and drain regions, in addition to the effect on the oxide thickness at the gate edge, it also erodes the silicon substrate, causing the substrate thickness to thin out on the outside of the gate region. The thickness of the substrate is not very important in ordinary bulk silicon processes, however, in RF silicon-on-insulator processes, the thickness of the active layer of silicon is much thinner. Subtracting the active silicon layer of silicon-on-insulator will introduce higher resistance, which is unacceptable for RF switches. Summary of the invention

[0004] The present invention aims to overcome the deficiencies in the prior art and provide a method for optimizing the gate oxide of a silicon-on-insulator field effect transistor and a product thereof, by partially removing the insulating gate dielectric layer at the bottom edge of the polysilicon gate before reoxidizing the periphery thereof, so that the amount of oxygen required for the reoxidation step can be consumed more quickly in the area outside the active area, so that the reoxidation step acts less on the active area or even does not act on the active area, thereby ensuring the thickness of the active silicon layer on the insulator.

[0005] To achieve the above object, the present invention is implemented by adopting the following technical solutions: In a first aspect, the present invention provides a method for optimizing a gate oxide of a silicon-on-insulator field effect transistor, comprising: forming an insulating gate dielectric layer on top of the active region on the semiconductor substrate; forming a polysilicon gate on the insulating gate dielectric layer; removing a portion of the insulating gate dielectric layer at the bottom of the polysilicon gate; Using the polysilicon gate as a mask, impurities are injected into the active region to generate a lightly doped extension region, thereby obtaining a first transistor semi-finished product; Covering the top of the first transistor semi-finished product with an oxide liner to obtain a second transistor semi-finished product; Covering the second transistor semi-finished product with a silicon nitride layer; etching the silicon nitride layer until the oxide liner is stopped; Using the etched polysilicon gate as a mask, dopants are injected into the lightly doped extension region to generate source / drain regions.

[0006] Optionally, forming an insulating gate dielectric layer on top of an active area on a semiconductor substrate comprises: forming an insulating gate dielectric layer by thermally growing silicon dioxide above the active area, wherein the active area is separated from the semiconductor substrate by a buried silicon oxide layer, and the active area is separated by an isolation layer.

[0007] Optionally, removing a portion of the insulating gate dielectric layer at the bottom of the polysilicon gate includes: removing the insulating gate dielectric layer by a wet etching cleaning process until edge regions on both sides of the bottom of the polysilicon gate are exposed.

[0008] Optionally, covering the top of the first transistor semi-finished product with an oxide liner includes: using a low-pressure chemical vapor deposition process to deposit an oxide liner on the top of the first transistor semi-finished product where the bottom edge of the polysilicon gate is exposed to the outside, so as to round the bottom edge of the polysilicon gate.

[0009] Optionally, covering the second transistor semi-finished product with a silicon nitride layer includes: depositing the silicon nitride layer on the second transistor semi-finished product using a low-pressure chemical vapor deposition process, wherein the deposition thickness of the silicon nitride layer is set according to process indicators of an ion etching process used for subsequently etching the silicon nitride layer.

[0010] Optionally, after using the etched polysilicon gate as a mask to inject dopants into the lightly doped extension area to generate source / drain areas, the method further includes: activating the dopants in the source area and the drain area by thermal annealing to drive the dopants in the lightly doped extension area to extend under the edges of both sides of the polysilicon gate, wherein the impurity concentration injected into the lightly doped extension area is lower than the dopant concentration injected into the source / drain area.

[0011] Optionally, after the impurities are injected into the semiconductor substrate from the top to produce a lightly doped extension area in the active area, the method further includes: diffusing the impurities injected in the lightly doped extension area so that the spacing distance between the impurities is reduced to a level capable of establishing a connection with the channel area at the bottom of the polysilicon gate.

[0012] In a second aspect, the present invention provides a silicon-on-insulator field effect transistor, which is prepared using the method for optimizing the gate oxide of the silicon-on-insulator field effect transistor as described in any step of the first aspect.

[0013] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: by partially removing the insulating gate dielectric layer at the bottom of the polysilicon gate before the reoxidation step, and the heavily doped polysilicon in the polysilicon gate oxidizes faster than the silicon layer on the surface of the active area, the subsequent reoxidation step can consume more and faster oxygen on the outer surface of the polysilicon gate, thereby reducing or even eliminating the oxidation effect on the silicon layer in the active area, and at the same time increasing the thickness of the edge of the polysilicon gate, ensuring the thickness of the silicon layer in the active area of ​​the silicon field effect transistor, while also ensuring the reliability of the silicon device; reoxidizing the polysilicon gate with the insulating gate dielectric layer at the bottom edge removed can make the bottom edge of the polysilicon gate rounded, which can significantly reduce the vertical electric field, reduce the gate-to-drain capacitance, thereby reducing the drain leakage current caused by the gate, and further benefiting the RF switch performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The figure is a flow chart of a method for optimizing gate oxide of a silicon-on-insulator field effect transistor in one embodiment of the present invention;

[0015] Figure 2 FIG. 1 is a schematic diagram of a semiconductor substrate structure in which an exposed area is generated at the bottom of a polysilicon gate in an embodiment of the present invention;

[0016] Figure 3 It is a schematic structural diagram of a field effect transistor for generating a lightly doped extension region in one embodiment of the present invention;

[0017] Figure 4 FIG. 1 is a schematic diagram showing the structure of a field effect transistor for generating source / drain regions in an embodiment of the present invention.

[0018] In the figure: 100, active area; 105, semiconductor substrate; 110, buried silicon oxide layer; 115, isolation layer; 120, polysilicon gate; 125, insulating gate dielectric layer; 130, exposed area; 135, thin layer of silicon oxide; 140, polysilicon gate edge; 145, lightly doped extension area; 150, spacer; 155, source / drain region. DETAILED DESCRIPTION

[0019] The following will discuss in detail the embodiments of the method for optimizing the gate oxide of low resistance and low capacitance and silicon field effect transistor on insulator in conjunction with the accompanying drawings. However, it should be understood that the embodiments provided below are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the scope of protection of the present invention.

[0020] Example 1

[0021] like Figure 1 As shown, this embodiment provides a method for optimizing gate oxide of a silicon-on-insulator field effect transistor, comprising: An insulating gate dielectric layer 125 is formed on top of the active region 100 on the semiconductor substrate 105; forming a polysilicon gate 120 on the insulating gate dielectric layer 125; removing a portion of the insulating gate dielectric layer 125 at the bottom of the polysilicon gate 120; Using the polysilicon gate 120 as a mask, impurities are injected into the active region 100 to generate a lightly doped extension region 145, thereby obtaining a first transistor semi-finished product; Covering the top of the first transistor semi-finished product with an oxide liner to obtain a second transistor semi-finished product; Covering the second transistor semi-finished product with a silicon nitride layer; etching the silicon nitride layer until the oxide liner is stopped; Using the etched polysilicon gate 120 as a mask, dopants are implanted into the lightly doped extension region 145 to generate source / drain regions 155 .

[0022] Before the conventional reoxidation step, the insulating gate dielectric layer 125 is cleared to expose a portion of the bottom area of ​​the polysilicon gate 120, so that the polysilicon gate 120 can consume more oxygen to form gate oxide in the subsequent reoxidation process, thereby reducing the oxidative effect of the reoxidation on the silicon layer of the active area 100 and minimizing the thickness of the silicon layer of the active area 100.

[0023] Example 2

[0024] Based on Example 1, this example also makes the following design.

[0025] like Figure 2 As shown, in the vertical direction, the active area 100 is separated from the semiconductor substrate 105 by the buried silicon oxide layer 110, and in the horizontal direction, the active area 100 is separated from other active areas by the isolation layer 115, and the isolation layer can be a PN junction, a shallow trench isolation STI or a local oxidation of silicon LOCOS. An insulating gate dielectric layer 125 is formed on the active area 100 by thermally growing silicon dioxide, and the polysilicon gate 120 forms a device gate on the insulating gate dielectric layer 125. After the polysilicon gate 120 is formed, the silicon dioxide of the insulating gate dielectric layer 125 will be removed by a wet etching cleaning process until a portion of the area below the two corners of the bottom of the polysilicon gate 120 is exposed to the subsequent polysilicon oxidation, and the exposed area 130 will be consumed by the subsequent re-oxidation step.

[0026] like Figure 3As shown, using the polysilicon gate 120 as a mask, impurities are implanted into the semiconductor substrate 105 from the top to generate a lightly doped extension region 145 in the active region 100, and a thin layer of silicon oxide 135 is grown on the periphery of the polysilicon gate 120 and on the top of the active region 100 where the lightly doped extension region 145 has been formed by applying a reoxidation step. The thin layer of silicon oxide 135 can provide an etching stop in the subsequent silicon nitride etching. According to performance requirements, a low-pressure chemical vapor deposition CVD process can be used to form a spacer thin oxide on the sidewall of the polysilicon gate 120 to provide an etching stop. Afterwards, using the polysilicon gate 120 covered with a thin layer of silicon oxide 135 as a self-aligned mask, impurities are implanted into the active region 100 from the top by an ion implantation process to generate a lightly doped extension region 145.

[0027] In the present embodiment, because the polysilicon gate edge 140 is exposed by the previous wet etching cleaning process, and because the heavily doped polysilicon used in the polysilicon gate 120 has a higher oxidation rate than the silicon layer of the active area 100, the technology of the present invention rounds the polysilicon gate edge 140 through a thin layer of silicon oxide 135, thereby increasing the oxide thickness of the polysilicon gate edge 140, while having little effect on the thickness of the silicon layer of the active area 100.

[0028] like Figure 4 As shown, a silicon nitride layer is deposited by a low-pressure chemical vapor deposition (CVD) process, with the goal of fine-tuning the electric field to achieve reliability. The deposition thickness of the silicon nitride layer can be pre-designed according to the process indicators of the subsequent spacer etching process. The silicon nitride layer is etched by a reactive ion etching (RIE) process to form a spacer 150. The etching step usually stops on a thin layer of silicon oxide 135 deposited before the silicon nitride layer, and in most cases a portion of the silicon oxide is etched. Afterwards, the polysilicon gate 120 covered with the spacer 150 is used as a self-aligned mask, and dopants are implanted into the lightly doped extension region 145 by an ion implantation process to form a source / drain region 155. The concentration of the dopant used to form the source / drain region 155 is higher than the impurity concentration used to form the lightly doped extension region 145, and the dopant implantation dose needs to be high enough to ensure that the back-end metal deposition and annealing process can form a reliable ohmic contact.

[0029] The scheme of removing the insulating gate dielectric layer 125 before the reoxidation step in this embodiment is particularly important for RF silicon-on-insulator processes customized for modern high-performance wireless applications. In one embodiment, the active silicon thickness of a fully depleted silicon-on-insulator MOS transistor can be as thin as 0.1 micron or thinner, so the lateral resistance of the silicon-on-insulator device is much higher than that of existing bulk silicon process devices. The existing technology will erode the top of the silicon layer of the active area 100. In the case that the silicon layer thickness of the silicon-on-insulator in modern sub-micron processes tends to be thinner, the existing technology of eroding the gate edge is not suitable for silicon-on-insulator, and the technology of the present invention makes the thinning of the source / drain silicon layer during the reoxidation process very limited.

[0030] Moreover, in this embodiment, rounding the edge of the polysilicon gate can significantly reduce the vertical electric field, thereby reducing the gate-induced drain leakage current. The gate-induced drain leakage current is the main source of harmful charges in RF switch applications. The technology of the present invention has almost no effect on the lightly doped drain diffusion, which will help control the lightly doped drain diffusion under the polysilicon gate. Lightly doped drain diffusion control can help alleviate the hot carrier injection HCI effect and reduce overlap capacitance. The increased thickness of the gate oxide at the edge of the polysilicon gate also helps to reduce overlap capacitance. The reduction in overlap capacitance caused by the present invention not only improves the RF switch performance, but also helps to improve f T and maximum oscillation frequency f m , thereby improving the overall RF performance.

[0031] Example 3

[0032] This embodiment provides a silicon-on-insulator field effect transistor, which is prepared by using the optimization method of the gate oxide of the silicon-on-insulator field effect transistor described in any step of Embodiment 2.

[0033] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A method for optimizing gate oxide of a silicon-on-insulator field effect transistor, characterized in that: include: forming an insulating gate dielectric layer on top of the active region on the semiconductor substrate; forming a polysilicon gate on the insulating gate dielectric layer; removing a portion of the insulating gate dielectric layer at the bottom of the polysilicon gate; Using the polysilicon gate as a mask, impurities are injected into the active region to generate a lightly doped extension region, thereby obtaining a first transistor semi-finished product; Covering the top of the first transistor semi-finished product with an oxide liner to obtain a second transistor semi-finished product; Covering the second transistor semi-finished product with a silicon nitride layer; etching the silicon nitride layer until the oxide liner is stopped; Using the etched polysilicon gate as a mask, dopants are injected into the lightly doped extension region to generate source / drain regions.

2. The method for optimizing gate oxide of silicon-on-insulator field effect transistor according to claim 1, characterized in that: The insulating gate dielectric layer is formed on the top of the active area on the semiconductor substrate, including: forming the insulating gate dielectric layer by thermally growing silicon dioxide above the active area, wherein the active area is separated from the semiconductor substrate by a buried silicon oxide layer, and the active area is separated by an isolation layer.

3. The method for optimizing gate oxide of silicon-on-insulator field effect transistor according to claim 1, characterized in that: The removing of part of the insulating gate dielectric layer at the bottom of the polysilicon gate comprises: removing the insulating gate dielectric layer by a wet etching cleaning process until the edge regions on both sides of the bottom of the polysilicon gate are exposed.

4. The method for optimizing gate oxide of silicon-on-insulator field effect transistor according to claim 3, characterized in that: The method of covering the top of the first transistor semi-finished product with an oxide liner includes: using a low-pressure chemical vapor deposition process to deposit an oxide liner on the top of the first transistor semi-finished product where the bottom edge of the polysilicon gate is exposed to the outside, so as to round the bottom edge of the polysilicon gate.

5. The method for optimizing gate oxide of silicon-on-insulator field effect transistor according to claim 1, characterized in that: The method of covering the second transistor semi-finished product with a silicon nitride layer includes: depositing the silicon nitride layer on the second transistor semi-finished product using a low-pressure chemical vapor deposition process, wherein the deposition thickness of the silicon nitride layer is set according to the process indicators of the ion etching process used for subsequently etching the silicon nitride layer.

6. The method for optimizing gate oxide of silicon-on-insulator field effect transistor according to claim 1, characterized in that: The method uses the etched polysilicon gate as a mask to inject dopants into the lightly doped extension area to generate source / drain areas, and further includes: activating the dopants in the source area and the drain area by thermal annealing to drive the dopants in the lightly doped extension area to extend under the edges of both sides of the polysilicon gate, wherein the impurity concentration injected into the lightly doped extension area is lower than the dopant concentration injected into the source / drain area.

7. The method for optimizing gate oxide of a silicon-on-insulator field effect transistor according to claim 1, characterized in that: After the impurities are injected into the semiconductor substrate from the top to produce a lightly doped extension area in the active area, the method further includes: diffusing the impurities injected in the lightly doped extension area to reduce the spacing between the impurities to a level capable of establishing a connection with the channel area at the bottom of the polysilicon gate.

8. A silicon-on-insulator field effect transistor, characterized in that: The method is used to prepare the gate oxide of a silicon-on-insulator field effect transistor according to any one of claims 1 to 7.

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