Field effect transistor including trench gate structure

Abstract

The disclosure relates to a field effect transistor (FET) comprising a trench gate structure, comprising: a transistor cell in a semiconductor substrate having a first surface; the source electrode region comprises a dopant of the first conductive type and is located on the first surface of the semiconductor substrate; a drain region including a dopant of the first conductivity type spaced apart from the source region in the first lateral direction; a trench gate structure between the source region and the drain region in a first lateral direction; a body region of the second conductivity type adjacent to the trench gate structure; and a body contact region including a dopant of the second conductivity type. The arrangement of the source region and the body contact region satisfies the following conditions: a distance from a bottom side of the body contact region to a vertical reference level at the first surface is greater than a distance from a bottom side of the source region to the vertical reference level; and / or a distance in a first lateral direction from a first edge of the body contact region to a lateral reference level at the drain region is less than a distance in the first lateral direction from a first edge of the source region to the lateral reference level.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and in particular to a field effect transistor (FET) including a trench gate structure. Background Art

[0002] Technology development of new generations of semiconductor devices, such as field effect transistors (FETs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. Although cost can be reduced by shrinking device geometries, various tradeoffs and challenges must be met when increasing device functionality per unit area. For example, the area ratio of the on-state resistance R on The trade-off between xA and reliability requirements influenced by, for example, avalanche breakdown behavior requires design optimization.

[0003] Therefore, there is a need for an improved field effect transistor. Summary of the invention

[0004] An example of the present disclosure relates to a field effect transistor (FET). The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes: a source region including a dopant of a first conductivity type, located on the first surface of the semiconductor substrate. The transistor cell also includes: a drain region including a dopant of the first conductivity type. The drain region is separated from the source region along a first lateral direction. The transistor cell also includes: a trench gate structure, arranged between the source region and the drain region along the first lateral direction. The transistor cell also includes: a body region of a second conductivity type, adjacent to the trench gate structure. The transistor cell also includes: a body contact region including a dopant of the second conductivity type. The arrangement of the source region and the body contact region satisfies at least one of the following conditions: i) a first vertical distance from a bottom side of the body contact region to a vertical reference level at a first surface is greater than a second vertical distance from a bottom side of the source region to the vertical reference level, or ii) a first lateral distance from a first edge of the body contact region to a lateral reference level at the drain region along a first lateral direction is less than a second lateral distance from a first edge of the source region to the lateral reference level along the first lateral direction.

[0005] Another example of the present disclosure relates to a method for manufacturing a field effect transistor FET, which includes a transistor cell in a semiconductor substrate having a first surface. Forming the transistor cell includes: forming a source region on the first surface of the semiconductor substrate, the source region including a dopant of the first conductivity type. Forming the transistor cell also includes: forming a drain region, the drain region including a dopant of the first conductivity type. The drain region is separated from the source region along a first lateral direction. Forming the transistor cell also includes: forming a trench gate structure, the trench gate structure is arranged between the source region and the drain region along the first lateral direction. Forming the transistor cell also includes: forming a body region of the second conductivity type, the body region is adjacent to the trench gate structure. Forming the transistor cell also includes: forming a body contact region, the body contact region includes a dopant of the second conductivity type. The arrangement of the source region and the body contact region satisfies at least one of the following conditions: i) a first vertical distance from a bottom side of the body contact region to a vertical reference level at a first surface is greater than a second vertical distance from a bottom side of the source region to the vertical reference level, or ii) a first lateral distance from a first edge of the body contact region to a lateral reference level at the drain region along a first lateral direction is less than a second lateral distance from a first edge of the source region to the lateral reference level along the first lateral direction.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate examples of semiconductor devices and together with the description serve to explain the principles of the examples. Additional examples are described in the following detailed description and claims.

[0008] Figures 1A to 1D are schematic top views and cross-sectional views for illustrating a configuration example of a FET including a trench gate structure.

[0009] Figure 2 and 3 are schematic top views and cross-sectional views for illustrating another configuration example of a FET including a trench gate structure.

[0010] Figure 4A and 4B Is used to illustrate the Figures 1A to 1D Also included are schematic top views and cross-sectional views of configuration examples of a trench field plate structured FET.

[0011] Figure 5A and 5B are schematic top views and cross-sectional views for illustrating another configuration example of a FET including a trench gate structure.

[0012] Fig. 6A and 6B is a schematic cross-sectional view for illustrating another configuration example of a FET including a trench gate structure. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific examples of FETs are illustrated as diagrams. It should be understood that other examples may be used and structural or logical changes may be implemented without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used in conjunction with other examples to produce another example. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale and are for illustration purposes only. If not otherwise indicated, corresponding elements are designated by the same reference numerals in different drawings.

[0014] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0015] The term "electrically connected" may describe a permanent low resistance connection between electrically connected elements, such as direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor materials. The term "electrically coupled" may include that one or more intervening elements suitable for signal and / or power transfer may be connected between the electrically coupled elements, such as elements that may be controlled to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.

[0016] Ranges given for physical dimensions may include boundary values. For example, a range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with one boundary value (e.g., "at most" and "at least").

[0017] The terms “on” and “over” should not be interpreted as meaning only “directly on” and “directly over.” Conversely, if an element is positioned “on” or “over another element” (for example, a layer is “on” or “over another layer” or “on” or “over a substrate”), another component (for example, another layer) may be positioned between the two elements (for example, if a layer is “on” or “over a substrate,” the other layer may be positioned between the layer and the substrate).

[0018] An example of the present disclosure relates to a field effect transistor (FET). The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes: a source region including a dopant of a first conductivity type, located on the first surface of the semiconductor substrate. The transistor cell also includes: a drain region including a dopant of the first conductivity type. The drain region is separated from the source region along a first lateral direction. The transistor cell also includes: a trench gate structure, arranged between the source region and the drain region along the first lateral direction. The transistor cell also includes: a body region of a second conductivity type, adjacent to the trench gate structure. The transistor cell also includes: a body contact region including a dopant of the second conductivity type. The arrangement of the source region and the body contact region may satisfy at least one of the following conditions: i) a first vertical distance from the bottom side of the body contact region to a vertical reference level at the first surface is greater than a second vertical distance from the bottom side of the source region to the vertical reference level, or ii) a first lateral distance from a first edge of the body contact region to a lateral reference level at the drain region along a first lateral direction is less than a second lateral distance from a first edge of the source region to the lateral reference level along the first lateral direction. For example, for condition i), the body contact region may be adjacent to the body region at the bottom side of the body contact region. For example, for condition ii), the first lateral distance may refer to the first surface.

[0019] The first conductivity type may be n-type, and the second conductivity type may be p-type. In this case, for example, the FET may be an n-channel FET. The first conductivity type may also be p-type, and the second conductivity type may be n-type. In this case, for example, the FET may be a p-channel FET.

[0020] For example, the FET may be a lateral FET. In a lateral FET, the load current flows in a lateral direction, such as a first lateral direction, and the source region and the drain region are separated from each other along the first lateral direction. For example, the lateral FET may be a lateral trench FET, such as a lateral trench metal oxide semiconductor field effect transistor (lateral trench MOSFET). In a trench gate structure, the trench gate dielectric may line the sidewalls and bottom side of the trench, and the trench gate electrode may be electrically isolated from the surrounding portion of the semiconductor substrate. In a lateral trench FET, for example, the channel current may flow along the first lateral direction at the opposite sidewall and along the bottom side of the trench gate structure.

[0021] For example, using hybrid technology, FETs can be implemented in a monolithic manner. This hybrid technology can be used, for example, to form analog circuit blocks in a chip by bipolar devices included in this technology to provide an interface for a digital system, and to form digital circuit blocks by complementary metal oxide semiconductor (CMOS) devices included in this technology to provide signal processing, and to form low, medium or high voltage or power blocks by field effect transistors included in this technology. This hybrid technology is, for example, called bipolar CMOS-DMOS (BCD) technology or smart power technology SPT, and is used in various application fields in the fields of, for example, lighting, motor control, automotive electronics, power management of mobile devices, audio amplifiers, power supplies, hard disks, printers. For example, in one of the above application fields, FETs can be part of a BCD or smart power chip.

[0022] The semiconductor substrate may be based on various semiconductor materials, such as silicon (Si), silicon on insulator (SOI), silicon-sapphire (SOS), silicon-germanium, germanium, gallium arsenide, silicon carbide, gallium nitride or other compound semiconductor materials. The semiconductor substrate may be based on a semiconductor base substrate (e.g., a semiconductor wafer) and may include one or more epitaxial layers deposited thereon, and / or may be backside thinned.

[0023] In order to achieve the desired current carrying capacity, the FET can be designed by connecting a plurality of transistor primitives in parallel. The transistor primitives connected in parallel can be, for example, transistor primitives formed in the shape of a strip or a strip segment. Of course, the transistor primitive can also have any other shape, such as a circle, an ellipse, a polygon (such as a hexagon or an octahedron). The transistor primitive can be arranged in a transistor primitive region of a semiconductor substrate. The transistor primitive region can be an active region, in which the source region of the FET and the drain region of the FET are arranged to be opposite to each other along a first lateral direction. In the active region, for example, through a contact plug on a first surface of the semiconductor substrate, the load current can enter or leave the semiconductor substrate of the FET.

[0024] For example, the first surface may be the front surface or top surface of the semiconductor substrate, and the second surface may be the back surface or rear surface of the semiconductor substrate. For example, the semiconductor substrate may be attached to a lead frame via the second surface. On top of the first surface of the semiconductor substrate, for example, a bonding pad may be arranged, and a bonding wire may be bonded on the bonding pad.

[0025] The source region and the body contact region may be electrically connected to the source electrode. For example, the source electrode may be a part of a wiring region on the first surface of the semiconductor substrate. The wiring region may include one or more than one (e.g., two, three, four or even more) wiring levels. Each wiring level may be formed by a single conductive layer or a stack of conductive layers (e.g., (one or more) metal layers). For example, the wiring levels may be patterned in a lithographic manner. Between the stacked wiring levels, an interlayer dielectric structure may be arranged. (One or more) contact plugs or (one or more) contact lines may be formed in an opening in the interlayer dielectric structure to electrically connect the parts of different wiring levels (e.g., metal lines or contact regions) to each other. The source electrode may be formed by one or more elements of the wiring region. Similarly, the FET may also include a drain electrode. In addition, the drain electrode may be formed by one or more elements of the wiring region on the first surface. For example, the source electrode and the drain electrode may include separate parts of the patterned first wiring level (e.g., the first metal layer). In some examples, a drain electrode may also be formed on the second surface of the semiconductor substrate. In this case, the drain region of the FET may be electrically connected to the drain electrode via a through contact or a trench contact extending at least partially through the semiconductor substrate.

[0026] The trench gate structure may include a trench gate dielectric and a trench gate electrode. For example, the trench gate dielectric electrically isolates the trench gate electrode from the surrounding portion of the semiconductor substrate. For example, the trench gate dielectric may be an insulating material, such as an oxide (e.g., SiO2), a nitride (e.g., Si3N4), a high-k dielectric or a low-k dielectric or any combination thereof. For example, the trench gate dielectric may be formed as a thermal oxide. The trench gate electrode may be formed of one or more conductive materials, such as metals, metal silicides, metal compounds, highly doped semiconductor materials (e.g., highly doped polysilicon). For example, the trench gate electrode may be a single layer (e.g., a highly doped polycrystalline layer) or a stack of layers. For example, the source region may be adjacent to the first sidewall of the trench gate structure. A drift region of the first conductivity type may be arranged between the trench gate structure and the drain region along a first lateral direction. The drift region may be adjacent to the second sidewall of the trench gate structure. Along the first lateral direction, the second sidewall may be opposite to the first sidewall.

[0027] For a lowermost position of the body contact region, e.g., a position of the body contact region disposed farthest from the first surface and closest to the second surface, a first vertical distance from a bottom side of the body contact region to a vertical reference level may be measured. Similarly, for a lowermost position of the source region, e.g., a position of the source region disposed farthest from the first surface and closest to the second surface, a second vertical distance from a bottom side of the source region to a vertical reference level may be measured. The vertical reference level may be any vertical reference level close to or coincident with the first surface.

[0028] A first lateral distance along a first lateral direction from a first edge of the body contact region to a lateral reference level at the drain region may refer to a position of the first edge, e.g., for vertical and horizontal locations, that is closest to the lateral reference level along the first lateral direction. Similarly, a second lateral distance along a first lateral direction from a first edge of the source region to a lateral reference level at the drain region may refer to a position of the first edge, e.g., for vertical and horizontal locations, that is closest to the lateral reference level along the first lateral direction. The lateral reference level may be any lateral reference level that is close to or coincides with an edge of the drain region.

[0029] By arranging the body contact region and the source region as defined in conditions i) and / or ii) above, in the case of an n-channel FET, holes generated by the electrical breakdown of the pn junction between the body region and the drift region can be discharged at a greater distance from the source region. As a result, the voltage drop between the body contact region and the source region can be reduced. This can allow the triggering of a parasitic bipolar transistor to be suppressed, or can allow the triggering current of a parasitic bipolar transistor having a source region as an emitter and a body contact region as a base to be increased. This can allow the reliability of the FET to be improved without adversely affecting R on xA.

[0030] For example, the first vertical distance may be 50 nm to 1000 nm, or 100 nm to 500 nm larger than the second vertical distance. This may allow the triggering of the parasitic bipolar transistor to be suppressed, or may allow the triggering current of the parasitic bipolar transistor to be increased.

[0031] For example, the first lateral distance may be 50 nm to 500 nm smaller, or 75 nm to 400 nm smaller than the second lateral distance. This may allow the triggering of the parasitic bipolar transistor to be suppressed, or may allow the triggering current of the parasitic bipolar transistor to be increased.

[0032] For example, the dopant of the second conductivity type of the body contact region may line at least a portion of the sidewalls of the body contact trench extending from the first surface into the semiconductor substrate. In some examples, the dopant of the second conductivity type may also line the bottom side of the body contact trench. For example, the dopant of the second conductivity type may be introduced into the body contact region via the sidewalls and / or bottom side of the body contact trench, for example by diffusion from a dopant source (such as a solid-state dopant source) and / or by ion implantation. For example, the body contact region may include additional conductive material(s), such as metal(s) and / or doped semiconductor material(s).

[0033] For example, the first vertical distance may be greater than a third vertical distance from the bottom side of the trench gate structure to the vertical reference level.

[0034] For example, the dopant of the first conductivity type of the source region may line at least a portion of the sidewalls of the source contact groove extending from the first surface into the semiconductor substrate. In some examples, the dopant of the first conductivity type may also line the bottom side of the source contact groove. For example, the dopant of the first conductivity type may be introduced into the source region through the sidewalls and / or bottom side of the source contact groove, for example by diffusion from a dopant source (such as a solid-state dopant source) and / or by ion implantation. For example, the source region may include additional (one or more) conductive materials, such as (one or more) metals and / or (one or more) doped semiconductor materials. For example, the depth of the source contact groove may be equal to, less than, or greater than the depth of the body contact groove. For example, the depth of the body contact groove may be greater than the depth of the source contact groove. According to another example, the depth of the body contact trench may be equal to the depth of the source contact trench, and the vertical extension of the second conductive type dopant of the body contact region from the bottom side of the body contact trench to the bottom side of the body contact region may be greater than the vertical extension of the first conductive type dopant of the source region from the bottom side of the source contact trench to the bottom side of the source region.

[0035] For example, the body contact region may include a buried body contact sub-region. The buried body contact sub-regions adjacent to the body contact region may overlap or abut each other along the second lateral direction. In some examples, the buried contact sub-region may also be formed below the source region and may abut the bottom side of the source region.

[0036] For example, the second vertical distance may be greater than a third vertical distance from the bottom side of the trench gate structure to the vertical reference level.

[0037] For example, the body region may be adjacent to the bottom side of the trench gate structure. For example, the body region may be adjacent to the bottom side of the trench gate structure and adjacent to the opposite sidewall of the trench gate structure. Thus, the channel region may be formed at the opposite sidewall and at the bottom side of the trench gate structure. Along the first lateral direction, the body region may be adjacent to more than 60% or more than 70% or more than 80% or more than 90% of the lateral extent of the bottom side along the first lateral direction.

[0038] For example, the source region may be adjacent to the body contact region along the second lateral direction. The second lateral direction may be perpendicular to the first lateral direction. In a transistor cell array comprising a plurality of transistor cells, for example, the source region and the body contact region may be arranged alternately along the second lateral direction.

[0039] For example, the dopant of the first conductivity type of the drain region may line at least a portion of the sidewalls of the drain contact trench extending from the first surface into the semiconductor substrate. In some examples, the dopant of the first conductivity type may also line the bottom side of the drain contact trench. For example, the dopant of the first conductivity type may be introduced into the drain region via the sidewalls and / or bottom side of the drain contact trench, for example by diffusion from a dopant source (such as a solid state dopant source) and / or by ion implantation. For example, the drain region may include additional conductive material(s), such as metal(s) and / or doped semiconductor material(s).

[0040] For example, the fourth vertical distance from the bottom side of the drain region to the vertical reference level may be greater than the second vertical distance.

[0041] For example, the FET may further include: a trench field plate structure arranged between the trench gate structure and the drain region along a first lateral direction. The trench gate structure may be separated from the trench field plate structure along the first lateral direction. For example, the width of the trench field plate structure (e.g., the width along the second lateral direction) may be greater than, for example, 20% and less than 100% compared to the width of the trench gate structure. For example, in the transistor cell region, the spacing of the arrangement of the trench field plate structure along the second lateral direction may be equal to the spacing of the arrangement of the trench gate structure along the second lateral direction. The trench field plate structure and the trench gate structure may be offset from each other along the second lateral direction, for example, by half of the offset spacing.

[0042] Similar to the trench gate structure, the trench field plate structure may include a trench field plate dielectric and a trench field plate electrode. For example, the trench field plate dielectric electrically isolates the trench field plate electrode from the surrounding portion of the semiconductor substrate. For example, the trench field plate dielectric may have a greater thickness than the trench gate dielectric. For example, the trench field plate dielectric may be an insulating material, such as an oxide (e.g., SiO2), a nitride (e.g., Si3N4), a high-k dielectric or a low-k dielectric, or any combination thereof. For example, the trench field plate dielectric may be formed as or include a thermal oxide and / or a deposited and annealed oxide. The trench field plate electrode may be formed of one or more conductive materials, such as metals, metal silicides, metal compounds, highly doped semiconductor materials (such as highly doped polysilicon). For example, the trench field plate electrode may be a single layer (e.g., a highly doped polycrystalline layer) or a stack of layers. For example, the trench gate electrode and the trench field plate electrode may be made of, for example, the same material or a combination of materials. The provision of the trench field plate structure may allow R on Further reduction of xA.

[0043] For example, the FET may further include a fifth vertical distance from the bottom side of the body region to the vertical reference level. A difference between the fifth vertical distance and the first vertical distance may be greater than a difference between the first vertical distance and the second vertical distance.

[0044] For example, the semiconductor substrate may include a base substrate of a first conductivity type and a semiconductor layer of the first conductivity type. The semiconductor layer may be arranged on the base substrate and may have a smaller concentration of a dopant of the first conductivity type than the base substrate. For example, the drift region of a FET may be a part of the semiconductor layer.

[0045] For example, the body region may be a well region in a semiconductor layer. The pn junction between the body region and the semiconductor layer may include a side region and a bottom region. A drift region as part of the semiconductor layer may be arranged between the side region and the drain region. A sub-region of the semiconductor layer may be arranged between the bottom region and the base substrate.

[0046] For example, the body region, the body contact region and the semiconductor substrate may be configured to provide an electrical breakdown site of the pn junction at or near the bottom region. For example, the electrical breakdown site may be located where the region of the pn junction has a minimum radius of curvature.

[0047] For example, the electrical breakdown site of the pn junction in the bottom region may be located directly below the bottom side of the body contact region.

[0048] Details of the structure or function or technical benefits of the features described above for semiconductor devices (such as FETs) are equally applicable to the exemplary methods described herein. Processing a semiconductor substrate may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0049] The description and drawings illustrate only the principles of the present disclosure. In addition, all examples described herein are primarily intended to be used for illustration purposes only to help readers understand the principles and concepts of the present disclosure contributed by (one or more) inventors to promote the art. All statements describing the principles, aspects and examples of the present disclosure and specific examples of the present disclosure herein are intended to include their equivalents.

[0050] It should be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims cannot be interpreted as falling within the specific order, unless, for example, it is explicitly or implicitly otherwise indicated by a statement such as "after" for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit these to a specific order unless such actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively, or may be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of this single action. Processing semiconductor substrate wafers for manufacturing FETs may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concepts or one or more examples described above or below.

[0051] An example of the present disclosure relates to a method for manufacturing a field effect transistor FET, which includes a transistor cell in a semiconductor substrate having a first surface. Forming the transistor cell may include: forming a source region on the first surface of the semiconductor substrate, the source region including a dopant of the first conductivity type. Forming the transistor cell may also include: forming a drain region, the drain region including a dopant of the first conductivity type. The drain region may be separated from the source region along a first lateral direction. Forming the transistor cell may also include: forming a trench gate structure, the trench gate structure is arranged between the source region and the drain region along the first lateral direction. Forming the transistor cell may also include: forming a body region of the second conductivity type, the body region being adjacent to the trench gate structure. Forming the transistor cell may also include: forming a body contact region, the body contact region including a dopant of the second conductivity type. The arrangement of the source region and the body contact region may satisfy at least one of the following conditions: i) a first vertical distance from the bottom side of the body contact region to a vertical reference level at the first surface is greater than a second vertical distance from the bottom side of the source region to the vertical reference level, or ii) a first lateral distance from a first edge of the body contact region to a lateral reference level at the drain region along a first lateral direction is less than a second lateral distance from the first edge of the source region to the lateral reference level along the first lateral direction.

[0052] The examples and features described above and below may be combined.

[0053] In the following, further examples of field effect transistors FET are explained in conjunction with the accompanying drawings. The functional and structural details described for the above examples will be equally applicable to the exemplary embodiments illustrated in the accompanying drawings and further described below. In the illustrated examples, for n-channel FETs, the first conductivity type is n-type, and the second conductivity type is p-type. However, for p-channel FETs, the first conductivity type may also be p-type, and the second conductivity type may be n-type.

[0054] Figure 1A A top view of a portion of a transistor cell TC of a FET 100 is schematically and exemplarily shown. Figure 1B Schematically and exemplarily shown along Figure 1A Cross-sectional view along line AA'. Figure 1C Schematically and exemplarily shown along Figure 1A Cross-sectional view along line BB'. Figure 1D Schematically and exemplarily shown along Figure 1A Cross-sectional view along line CC'.

[0055] Reference Figures 1A to 1DFET 100 includes a transistor cell TC in a semiconductor substrate 102. Semiconductor substrate 102 includes an n+ doped base substrate 1021 and an n-doped semiconductor layer 1022 (e.g., an epitaxial layer formed by a layer deposition process). Semiconductor layer 1022 is arranged on base substrate 1021 and has a smaller concentration of n-type dopant type than base substrate 1021.

[0056] The n+ doped source region 104 is formed at the first surface 108 of the semiconductor substrate 102 and adjoins the trench gate structure 112 along the first lateral direction x1. The n+ doped source region 104 is electrically connected to a source electrode S on the first surface 108 of the semiconductor substrate 102.

[0057] The n+ doped drain region 110 is separated from the source region 104 and from the trench gate structure 112 along a first lateral direction x1.

[0058] The p-doped body region 114 is adjacent to the trench gate structure 112. The p-doped body region 114 is adjacent to opposite sidewalls of the trench gate structure 112 and is adjacent to a bottom side 1121 of the trench gate structure 112. The p-doped body region 114 may be formed as a p-well in the semiconductor layer 1022. The pn junction 118 is located between the body region 114 and the semiconductor layer 1022 and includes a side region 1181 and a bottom region 1182. The n-doped drift region 120 is a portion of the semiconductor layer 1022 disposed between the side region 1181 and the drain region 110. A sub-region 122 of the semiconductor layer 1022 is disposed between the bottom region 1182 of the body region 108 and the base substrate 1021.

[0059] The p-doped body region 114 is electrically connected to the source electrode S via the p+ doped body contact region 116. Along a second lateral direction x2 perpendicular to the first lateral direction x1, the n+ doped source region 104 adjoins the p+ doped body contact region 116. For example, the p-type dopant of the body contact region 116 may line at least a portion of the sidewalls of the body contact trench extending from the first surface 108 into the semiconductor substrate 102. Likewise, the n-type dopant of the source region 104 may line at least a portion of the sidewalls of the source contact trench extending from the first surface 108 into the semiconductor substrate 102. For example, in the case where the dopant of the body contact region is introduced through the sidewalls and / or bottom side of the body contact trench by ion implantation and / or diffusion, the size of the body contact trench may be smaller than the size of the body contact region 116. Likewise, in the case where the dopant of the source region is introduced through the sidewalls and / or bottom side of the source contact trench by ion implantation and / or diffusion, the size of the source contact trench may be smaller than the size of the source region 104.

[0060] like Figure 1AAs shown in , a first lateral distance l1 from a first edge 1163 of the body contact region 116 to a lateral reference level lrL at the drain region 110 along a first lateral direction x1 is smaller than a second lateral distance l2 from a first edge 1043 of the source region 104 to the lateral reference level lrL along the first lateral direction x1. In some examples, the first lateral distance l1 is 50 nm to 500 nm smaller than the second lateral distance l2.

[0061] like Figure 1B As shown in , a first vertical distance v1 along the vertical direction y from the bottom side 1161 of the body contact region 116 to the vertical reference level vrL at the first surface 108 of the semiconductor substrate 102 is greater than a second vertical distance v2 from the bottom side 1041 of the source region 104 to the vertical reference level vrL. In some examples, the first vertical distance v1 is 50 nm to 1000 nm greater than the second vertical distance v2.

[0062] like Figure 1B Combination Figure 1D As shown, the first vertical distance v1 along the vertical direction y is greater than the third vertical distance v3 from the bottom side 1121 of the trench gate structure 112 to the vertical reference level vrL. Figure 1D As shown in , the second vertical distance v2 along the vertical direction y is greater than the third vertical distance v3. Figure 1D As shown in FIG. 1 , the fifth vertical distance v5 extends from the bottom side 1141 of the body region 114 to the vertical reference level vrL along the vertical direction y. A difference d1 between the fifth vertical distance v5 and the first vertical distance v1 is greater than a difference d2 between the first vertical distance v1 and the second vertical distance v2.

[0063] Another configuration example of FET 100 is illustrated in Figure 2 FET 100 can be based on Figure 1B , 1C and 1D cross-sectional views, and Figure 1A The version of is modified because l1 is equal to l2.

[0064] Another configuration example of FET 100 is illustrated in Figure 3 FET 100 can be based on Figure 1A , 1C and 1D top and cross-sectional views, and Figure 1B The version is modified because v1 is equal to v2.

[0065] Figure 4A and 4B The configuration example of the FET 100 illustrated in the top view and cross-sectional view is based on Figures 1A to 1D, and further comprising a trench field plate structure 117, the trench field plate structure 117 being arranged along the first lateral direction x1 between the trench gate structure 112 and the n+ doped drain region 110. For example, the n-type dopant of the drain region 110 may line at least a portion of a sidewall of a drain contact trench extending from the first surface 108 into the semiconductor substrate 102. A fourth vertical distance v4 along the vertical direction y from the bottom side 1101 of the drain region 110 to the vertical reference level vrL may be greater than Figure 1B , 1D , a second vertical distance v2 illustrated in any of the figures in 3.

[0066] Another configuration example of FET 100 is illustrated in Figure 5A and 5B FET 100 is based on Figure 1A , 1B The top view and the cross-sectional view of FIG. 1 further include a lateral distance between the source region 104 and the body contact region 116 along the second lateral direction x2. A portion of the body region 114 is arranged between the source region 104 and the body contact region 116.

[0067] Another configuration example of the FET 100 is illustrated in Fig. 6A and 6B FET 100 is based on Figure 3 The cross-sectional view of FIG. 1 further includes a lateral distance between the source region 104 and the body contact region 116 along a second lateral direction x2. A portion of the body region 114 is arranged between the source region 104 and the body contact region 116.

[0068] Reference Fig. 6A Each main contact area 116 also includes p + The doped buried body contact sub-region 1165. The p adjacent to the body contact region 116 + The doped buried body contact sub-regions 1165 overlap or abut each other along the second lateral direction x2. + The doped buried body contact sub-regions 1165 may have a lateral distance from each other along the second lateral direction x2. + Dopants that dope the buried body contact sub-region 1165 may be introduced into the semiconductor substrate 102 .

[0069] Reference Figure 6B , p + A doped buried body contact sub-region 1165 is also arranged below the source region 104 and adjoins the bottom side 1041 of the source region 104. +The doped buried body contact sub-regions 1165 are spaced apart from each other along the second lateral direction x2. + The doped buried body contact sub-regions 1165 may overlap or abut each other along the second lateral direction x2. + Dopants that dope the buried body contact sub-region 1165 may be introduced into the semiconductor substrate 102 .

[0070] The aspects and features mentioned and described in conjunction with one or more of the previously described examples and figures may also be combined with one or more of the other examples in order to replace similar features of the other examples, or to otherwise introduce the features into the other examples.

[0071] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A field effect transistor FET (100), comprising a transistor cell (TC) in a semiconductor substrate (102) having a first surface (108), wherein the transistor cell (TC) comprises: A source region (104), comprising a dopant of a first conductivity type, and located on a first surface (108) of the semiconductor substrate (102); A drain region (110), comprising a dopant of the first conductivity type, the drain region (110) being separated from the source region (104) along a first lateral direction (x1); A trench gate structure (112) is arranged between the source region (104) and the drain region (110) along the first lateral direction (x1); A body region (114) of the second conductivity type, adjacent to the trench gate structure (112); The main contact region (116) includes a dopant of the second conductivity type, wherein The arrangement of the source region (104) and the body contact region (116) satisfies at least one of the following conditions: i) a first vertical distance (v1) from a bottom side (1161) of the body contact region (116) to a vertical reference level (vrL) at the first surface (108) is greater than a second vertical distance (v2) from a bottom side (1041) of the source region (104) to the vertical reference level (vrL); ii) a first lateral distance (l1) from a first edge (1163) of the body contact region (116) to a lateral reference level (lrL) in the drain region (110) along the first lateral direction (x1) is smaller than a second lateral distance (l2) from a first edge (1043) of the source region (104) to the lateral reference level (lrL) along the first lateral direction (x1).

2. The FET (100) of the preceding claim, wherein the first vertical distance (v1) is 50 nm to 1000 nm larger than the second vertical distance (v2).

3. The FET (100) according to any one of the preceding claims, wherein the first lateral distance (l1) is 50 nm to 500 nm smaller than the second lateral distance (l2).

4. A FET (100) as described in any of the preceding claims, wherein the dopant lining of the second conductivity type of the body contact region (116) extends from the first surface (108) to at least a portion of a sidewall of a body contact trench in the semiconductor substrate (102).

5. The FET (100) as claimed in any one of the preceding claims, wherein the first vertical distance (v1) is greater than a third vertical distance (v3) from the bottom side (1121) of the trench gate structure (112) to the vertical reference level (vrL).

6. A FET (100) as claimed in any one of the preceding claims, wherein the dopant lining of the first conductivity type of the source region (104) extends from the first surface (108) to at least a portion of a sidewall of a source contact trench in the semiconductor substrate (102).

7. The FET (100) of any one of the preceding claims, wherein the second vertical distance (v2) is greater than a third vertical distance (v3) from the bottom side (1121) of the trench gate structure (112) to the vertical reference level (vrL).

8. The FET (100) as claimed in any one of the preceding claims, wherein the body region (114) adjoins a bottom side (1121) of the trench gate structure (112).

9. The FET (100) as claimed in any one of the preceding claims, wherein the source region (104) adjoins the body contact region (116) along a second lateral direction (x2), the second lateral direction (x2) being perpendicular to the first lateral direction (x1).

10. A FET (100) as claimed in any one of the preceding claims, wherein the dopant lining of the first conductivity type of the drain region (110) extends from the first surface (108) to at least a portion of a sidewall of a drain contact trench (1102) in the semiconductor substrate (102).

11. The FET (100) of the preceding claim, wherein a fourth vertical distance (v4) from a bottom side (1101) of the drain region (110) to the vertical reference level (vrL) is greater than the second vertical distance (v2).

12. The FET (100) as claimed in any one of the preceding claims, further comprising: A trench field plate structure (117) is arranged between the trench gate structure (112) and the drain region (110) along the first lateral direction (x1).

13. The FET (100) as claimed in any one of the preceding claims, further comprising: A fifth vertical distance (v5) from the bottom side (1141) of the main body area (114) to the vertical reference level (vrL), wherein a difference between the fifth vertical distance (v5) and the first vertical distance (v1) is greater than a difference between the first vertical distance (v1) and the second vertical distance (v2).

14. A FET (100) as claimed in any one of the preceding claims, wherein the semiconductor substrate (102) comprises a base substrate (1021) of the first conductivity type and a semiconductor layer (1022) of the first conductivity type, wherein the semiconductor layer (1022) is arranged on the base substrate (1021) and has a smaller concentration of dopants of the first conductivity type than the base substrate (1021).

15. The FET (100) of the preceding claim, wherein the body region (114) is a well region in the semiconductor layer (1022), and a pn junction (118) between the body region (114) and the semiconductor layer (1022) comprises a side region (1181) and a bottom region (1182), wherein a drift region (120) as part of the semiconductor layer (1022) is arranged between the side region (1181) and the drain region (110), and a sub-region (122) of the semiconductor layer (1022) is arranged between the bottom region (1182) and the base substrate (1021).

16. The FET (100) of the preceding claim, wherein the body region (114), the body contact region (116) and the semiconductor substrate (102) are configured to provide an electrical breakdown site for the pn junction (118) at or near the bottom region (1182).

17. The FET (100) of the preceding claim, wherein the electrical breakdown site of the pn junction (118) in the bottom region (1182) is located directly below the bottom side (1161) of the body contact region (116).

18. The FET (100) of any one of the preceding claims, wherein the body contact region (116) comprises p + doped buried body contact sub-region (1165), and wherein the p + The doped buried body contact sub-region (1165) overlaps or abuts another p+ doped buried body contact sub-region (1165) of another body contact region (116) of the FET (100).

19. A method of manufacturing a field effect transistor (FET) (100), the FET (100) comprising a transistor cell (TC) in a semiconductor substrate (102) having a first surface (101), wherein forming the transistor cell (TC) comprises: Forming a source region (104) on a first surface (108) of the semiconductor substrate (102), wherein the source region (104) includes a dopant of a first conductivity type; forming a drain region (110), the drain region (110) comprising dopants of the first conductivity type, the drain region (110) being separated from the source region (104) along a first lateral direction (x1); forming a trench gate structure (112), wherein the trench gate structure (112) is arranged between the source region (104) and the drain region (110) along the first lateral direction (x1); forming a body region (114) of the second conductivity type, wherein the body region (114) is adjacent to the trench gate structure (112); forming a body contact region (116), the body contact region (116) comprising a dopant of the second conductivity type, wherein The arrangement of the source region (104) and the body contact region (116) satisfies at least one of the following conditions: i) a first vertical distance (v1) from a bottom side (1161) of the body contact region (116) to a vertical reference level (vrL) at the first surface (108) is greater than a second vertical distance (v2) from a bottom side (1041) of the source region (104) to the vertical reference level (vrL); ii) a first lateral distance (l1) from a first edge (1163) of the body contact region (116) to a lateral reference level (lrL) in the drain region (110) along the first lateral direction (x1) is smaller than a second lateral distance (l2) from a first edge (1043) of the source region (104) to the lateral reference level (lrL) along the first lateral direction (x1).

20. The method of the preceding claim, wherein forming the source region (104) comprises: A source contact trench is formed extending from the first surface (108) into the semiconductor substrate (102), the dopant of the first conductivity type of the source region (104) is introduced into the semiconductor substrate (102) through the sidewall of the source contact trench, and the source contact trench is filled with a conductive material.

21. The method of any one of the two preceding claims, wherein forming the body contact region (116) comprises: A body contact groove is formed extending from the first surface (108) into the semiconductor substrate (102), the second conductive type dopant of the body contact region (116) is introduced into the semiconductor substrate (102) through the sidewall of the body contact groove, and the body contact groove is filled with a conductive material.

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