Semiconductor device, and memory device and electronic device including the same

Abstract

The invention provides a semiconductor device and a memory device and an electronic device including the same. The semiconductor device may include a gate electrode, a ferroelectric layer on the gate electrode, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the gate electrode and a remainder of the plurality of nanostructures may be adjacent to the channel layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and a storage device and an electronic device including the same. Background Art

[0002] As hard disks are replaced by solid-state drives (SSDs), NAND flash memory devices, a type of nonvolatile memory device, may be widely commercialized. Recently, with miniaturization and high integration, vertical NAND flash memory devices are being developed in which multiple memory cells are stacked in a direction perpendicular to a substrate.

[0003] Recently, research is being conducted to apply ferroelectric field effect transistors (FeFETs), which can have low operating voltage and fast programming speed, to vertical NAND flash memory devices. FeFET is a semiconductor device for realizing storage characteristics by using ferroelectric materials as gate insulating films. In FeFET, the threshold voltage can be adjusted according to the polarization direction of the ferroelectric material. Summary of the invention

[0004] A semiconductor device, and a memory device and an electronic device including the same are provided.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include a gate electrode, a ferroelectric layer on the gate electrode, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the gate electrode and the rest of the plurality of nanostructures may be adjacent to the channel layer.

[0007] In some embodiments, the plurality of nanostructures can be configured to store charge in response to a voltage being applied to the gate electrode and polarization being formed in the ferroelectric layer.

[0008] In some embodiments, the distance between the plurality of nanostructures and the interface of the ferroelectric layer may be 30% or less of the thickness of the ferroelectric layer.The interface of the ferroelectric layer may be adjacent to the gate electrode, the channel layer, or both the gate electrode and the channel layer.

[0009] In some embodiments, the band gap of the material of the plurality of nanostructures can be lower than the band gap of the material of the ferroelectric layer.

[0010] In some embodiments, the plurality of nanostructures may include an oxide of an element different from the material of the ferroelectric layer or a nitride of an element different from the material of the ferroelectric layer.

[0011] In some embodiments, the plurality of nanostructures may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN.

[0012] In some embodiments, the material of the plurality of nanostructures may have a thickness greater than 1×10 19 / cm 3 The trap density.

[0013] In some embodiments, the ferroelectric layer may include at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide. The ferroelectric layer may further include a dopant.

[0014] In some embodiments, the semiconductor device may further include a first insulating layer between the gate electrode and the ferroelectric layer, a second insulating layer between the channel layer and the ferroelectric layer, or both the first insulating layer between the gate electrode and the ferroelectric layer and the second insulating layer between the channel layer and the ferroelectric layer.

[0015] In some embodiments, the semiconductor device may further include a paraelectric layer in the ferroelectric layer.

[0016] According to one embodiment of the present disclosure, a storage device may include a substrate, a plurality of gate electrodes stacked in a direction perpendicular to the substrate, a ferroelectric layer on the plurality of gate electrodes, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the plurality of gate electrodes or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the plurality of gate electrodes and the rest of the plurality of nanostructures may be adjacent to the channel layer.

[0017] In some embodiments, the distance between the plurality of nanostructures and the interface of the ferroelectric layer may be 30% or less of the thickness of the ferroelectric layer.The interface of the ferroelectric layer may be adjacent to the plurality of gate electrodes, the channel layer, or both the plurality of gate electrodes and the channel layer.

[0018] In some embodiments, the material of the plurality of nanostructures may have a lower band gap than the material of the ferroelectric layer.

[0019] In some embodiments, the plurality of nanostructures may include an oxide of an element different from the material of the ferroelectric layer or a nitride of an element different from the material of the ferroelectric layer.

[0020] In some embodiments, the material of the plurality of nanostructures may have a thickness greater than 1×1019 / cm 3 The trap density.

[0021] In some embodiments, the ferroelectric layer may include at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0022] In some embodiments, the memory device may further include a first insulating layer between the multiple gate electrodes and the ferroelectric layer, a second insulating layer between the channel layer and the ferroelectric layer, or both the first insulating layer between the multiple gate electrodes and the ferroelectric layer and the second insulating layer between the channel layer and the ferroelectric layer.

[0023] In some embodiments, the memory device may further include a paraelectric layer in the ferroelectric layer.

[0024] According to an embodiment of the present disclosure, an electronic device may include the above storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment;

[0027] Figure 2 yes Figure 1 an enlarged view of part A;

[0028] Figure 3A shows negative (-) voltage applied to Figure 1 The state of the gate electrode of the semiconductor device shown;

[0029] Figure 3B shows a positive (+) voltage applied to Figure 1 The state of the gate electrode of the semiconductor device shown;

[0030] Figure 4 is a cross-sectional view of a semiconductor device according to a comparative example;

[0031] Figure 5 is a cross-sectional view of a semiconductor device according to another embodiment;

[0032] Figure 6 is a cross-sectional view of a semiconductor device according to another embodiment;

[0033] Figure 7 is a cross-sectional view of a semiconductor device according to another embodiment;

[0034] Figure 8is a perspective view schematically showing a storage device according to an embodiment;

[0035] Fig. 9 yes Figure 8 A cross-sectional view of a cell string of a memory device shown in FIG.

[0036] Fig.10 yes Fig. 9 an enlarged view of part B;

[0037] Fig.11 is a conceptual diagram schematically showing a device architecture that can be applied to an electronic device;

[0038] Fig.12 is a block diagram of a storage system according to an embodiment; and

[0039] Fig.13 is a block diagram showing a neuromorphic apparatus and external devices connected thereto according to an embodiment. DETAILED DESCRIPTION

[0040] Now will refer to the embodiment in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, by referring to the accompanying drawings, only the embodiment is described below to explain multiple aspects. When used in this article, the term "and / or" includes any combination and all combinations of one or more items in the relevant listed items. Statements such as "at least one of ..." modify the entire column of elements when located after a column of elements, without modifying the individual elements in the column. For example, "at least one of A, B and C" and similar language (such as "at least one selected from a group consisting of A, B and C", "at least one of A, B or C") can be interpreted as only A, only B, only C or any combination of two or more of A, B and C (such as, for example, ABC, AB, BC and AC).

[0041] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes the manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including the manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween (such as increments of 0.1%).

[0042] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same components, and the size of each component in the accompanying drawings may be exaggerated for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely illustrative, and various modifications are possible based on these embodiments.

[0043] It should also be understood that when an element is referred to as being "on" or "over" another element, the element may be in direct contact with the other element, or additional intervening elements may be present. Unless the context clearly indicates otherwise, the singular includes the plural. It should be understood that when a component "includes" or "comprises" an element in the specification, unless otherwise defined, additional elements are not excluded from the component, and the component may further include additional elements.

[0044] The use of the terms "a", "an", and "the" and similar referents in the context of describing the present disclosure should be construed to cover both the singular and the plural. Unless otherwise indicated herein or clearly contradicted by context, the operations of all methods described herein can be performed in any suitable order.

[0045] In addition, terms such as “unit”, “module” and the like refer to a unit that performs at least one function or operation, and the unit may be implemented as hardware or software, or as a combination of hardware and software.

[0046] The connecting lines or connectors shown in the various figures given are intended to represent example functional relationships and / or physical or logical connections between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may exist in a practical device.

[0047] The use of any and all examples, or exemplary language provided herein, is intended merely to better illuminate the present disclosure and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.

[0048] Figure 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment. Figure 1 The semiconductor device 100 shown in FIG. 1 may be, for example, a ferroelectric field effect transistor (FeFET). Figure 2 yes Figure 1 An enlarged view of part A of FIG.

[0049] refer to Figure 1 and Figure 2, the semiconductor device 100 may include a gate electrode 110, a channel layer 120, and a ferroelectric layer 130 disposed between the gate electrode 110 and the channel layer 120. For example, the gate electrode 110 may include a conductive material such as a metal, a metal nitride, a metal oxide, or polysilicon. For example, the gate electrode 110 may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and highly doped polysilicon. However, this is merely an example, and the gate electrode 110 may include various other conductive materials.

[0050] The channel layer 120 may include a semiconductor material. For example, the channel layer 120 may include a group IV semiconductor (such as Si, Ge, SiGe) or a group III-V semiconductor compound. The channel layer 120 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) semiconductor material, a quantum dot, or an organic semiconductor. Here, the oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include, for example, a transition metal dichalcogenide (TMD) or graphene, and the quantum dot may include a colloidal quantum dot (colloidal QD), a nanocrystal structure, etc. However, this is merely an example, and the present embodiment is not limited thereto.

[0051] The channel layer 120 may further include a dopant. Here, the dopant may include a p-type dopant or an n-type dopant. The p-type dopant may include, for example, a group III element such as B, Al, Ga, In, etc., and the n-type dopant may include a group V element such as P, As, Sb, etc. A source and a drain (not shown) may be disposed below and above the channel layer 120, respectively.

[0052] The ferroelectric layer 130 is disposed between the gate electrode 110 and the channel layer 120. Ferroelectrics have a spontaneous dipole (electric dipole), i.e., spontaneous polarization, because the charge distribution within the unit cell in the crystalline material structure is non-centrosymmetric. In addition, even in the absence of an external electric field, ferroelectrics have a residual polarization due to the dipole. In addition, in ferroelectrics, the direction of polarization can be switched on a domain-by-domain basis by an external electric field.

[0053] The ferroelectric layer 130 may include a fluorite-based material. For example, the ferroelectric layer 130 may include at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr. As an example, the ferroelectric layer 130 may include at least one of hafnium oxide (HfO), zirconium oxide (ZrO), and hafnium zirconium oxide (HfZrO). The ferroelectric layer 130 may further include a dopant. In this case, the dopant may include, for example, at least one of Si, Al, La, Y, Sr, and Gd. But this is only an example. The ferroelectric layer 130 may have a thickness (t) of, for example, about 4 nm to about 20 nm, but is not limited thereto.

[0054] A first insulating layer 141 may be provided between the gate electrode 110 and the ferroelectric layer 130. The first insulating layer 141 may act as a tunnel barrier. The first insulating layer 141 may include, for example, silicon oxide or silicon nitride, but is not limited thereto. In addition, a second insulating layer 142 may be further provided between the channel layer 120 and the ferroelectric layer 130. Like the first insulating layer 141, the second insulating layer 142 may include, for example, silicon oxide or silicon nitride, but is not limited thereto.

[0055] A plurality of nanostructures 150 are disposed inside the ferroelectric layer 130. Here, the plurality of nanostructures 150 are disposed separately from each other within the ferroelectric layer 130. The plurality of nanostructures 150 may be configured to store charges of a certain polarity, which move from the gate electrode 110 through the first insulating layer 141 by tunneling according to a voltage applied to the gate electrode 110. The plurality of nanostructures 150 may include a material having a lower band gap than the material of the ferroelectric layer 130. The plurality of nanostructures 150 may include an oxide or nitride containing an element different from the material of the ferroelectric layer 130. As an example, the plurality of nanostructures 150 may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN. However, the present disclosure is not limited thereto.

[0056] The plurality of nanostructures 150 may include a material having a relatively large trap density. For example, the plurality of nanostructures 150 may include a material having a trap density greater than about 1×10 19 / cm 3 The trap density of the material is as follows. However, this is only an example. Here, the trap density refers to the number of charges trapped in each nanostructure 150 per unit volume.

[0057] The plurality of nanostructures 150 may be disposed at a distance (d) close to an interface of the ferroelectric layer 130 adjacent to the gate electrode 110 (i.e., an interface between the first insulating layer 141 and the ferroelectric layer 130). For example, the distance (d) between the plurality of nanostructures 150 and the interface between the first insulating layer 141 and the ferroelectric layer 130 may be approximately 30% or less of the thickness (t) of the ferroelectric layer 130. As an example, when the thickness (t) of the ferroelectric layer 130 is 10 nm, the distance (d) between the plurality of nanostructures 150 and the interface between the first insulating layer 141 and the ferroelectric layer 130 may be approximately 3 nm or less (e.g., approximately 1 nm to approximately 2 nm).

[0058] Each of the plurality of nanostructures 150 may have various shapes. For example, each nanostructure 150 may have a spherical shape, an ellipsoidal shape, or a rod shape. However, the present disclosure is not limited thereto. Each of the plurality of nanostructures 150 may have a nanoscale size. In detail, the nanostructure 150 may have a size (S2) of 30% or less of the thickness (t) of the ferroelectric layer 130 in the thickness direction (x-axis direction) of the ferroelectric layer 130. In addition, each nanostructure 150 may have a size (S1) of about 10 nm or less in a direction (z-axis direction) parallel to the ferroelectric layer 130. The size of the nanostructure 150 described above is only an example, and the nanostructure 150 may have various sizes. The plurality of nanostructures 150 may be formed, for example, by spinodal decomposition or nucleation and growth.

[0059] According to the semiconductor device 100 (FeFET) described above, the memory characteristic can be realized by using a ferroelectric material as a gate insulating film and adjusting a threshold voltage according to the polarization direction of the ferroelectric material.

[0060] Figure 3A shows that a negative (-) voltage is applied to Figure 1 The state of the gate electrode 110 of the semiconductor device 100 is shown. Figure 3A , an example of a state in which a negative (−) voltage is applied to the gate electrode 110 for an erase operation of the semiconductor device 100 is shown.

[0061] refer to Figure 3A When a negative voltage is applied to the gate electrode 110, ferroelectric polarization may be formed in the −x-axis direction F1 inside the ferroelectric layer 130. To shield this ferroelectric polarization, negative charges from the gate electrode 110 may pass through the first insulating layer 141 by tunneling and be trapped in the plurality of nanostructures 150.

[0062] Figure 3B shows that a positive (+) voltage is applied to Figure 1 The state of the gate electrode 110 of the semiconductor device 100 is shown. Figure 3B , an example of a state in which a positive (+) voltage is applied to the gate electrode 110 for a program operation of the semiconductor device 100 is shown.

[0063] refer to Figure 3B When a positive voltage is applied to the gate electrode 110, ferroelectric polarization may be formed in the +x-axis direction F2 inside the ferroelectric layer 130. To shield this ferroelectric polarization, positive charges from the gate electrode 110 may pass through the first insulating layer 141 by tunneling and be trapped in the plurality of nanostructures 150.

[0064] In the semiconductor device 100 according to the embodiment described above, the nanostructure 150 for charge capture is arranged inside the ferroelectric layer 130, so the operating voltage does not increase. In addition, since the nanostructure 150 is located in the same space as the ferroelectric layer 130, the formation of the depolarization field can be limited and / or suppressed. As will be described later, when the semiconductor device 100 is applied to a vertical non-volatile memory device, since the nanostructures 150 are arranged separately from each other in the ferroelectric layer 130, it becomes difficult for the charges captured in the nanostructure 150 to move, and accordingly, the interference phenomenon or the degradation of the retention characteristics caused by the charge movement between the memory cells can be limited and / or suppressed.

[0065] Generally, in semiconductor devices having a metal-ferroelectric-insulator-semiconductor (MFIS) structure, the theoretical maximum value of the memory window (MW) is 2×E c ×t FE (E c is the coercive field, t FE is the thickness of the ferroelectric layer). In order to obtain a memory window larger than the maximum value of the memory window, a structure has been proposed in which a charge trapping layer 250 is inserted between the gate electrode 210 and the ferroelectric layer 230, such as Figure 4 shown.

[0066] Figure 4 is a cross-sectional view of a semiconductor device 200 according to a comparative example. Figure 4 The semiconductor device 200 shown is similar to Figure 1 The semiconductor device 100 shown in FIG. 1 is a semiconductor device 100, except that a charge trapping layer 250 is provided between the gate electrode 210 and the ferroelectric layer 230. In the following, the description will focus on Figure 1 The differences in the semiconductor device 100 are shown.

[0067] refer to Figure 4 , the ferroelectric layer 230 is disposed between the gate electrode 210 and the channel layer 220. Since the gate electrode 210, the channel layer 220 and the ferroelectric layer 230 have been described above, their description will be omitted. The first insulating layer 241 is disposed between the gate electrode 210 and the ferroelectric layer 230, and the second insulating layer 242 is disposed between the channel layer 220 and the ferroelectric layer 230.

[0068] The charge trap layer 250 is disposed between the first insulating layer 241 and the ferroelectric layer 230. The charge trap layer 250 may store charges of a certain polarity that move from the gate electrode 210 through the first insulating layer 241 by tunneling according to a voltage applied to the gate electrode 210.

[0069] exist Figure 4In the semiconductor device 200 shown, the storage window can increase as the amount of charge stored in the charge trap layer 250 increases. However, with the addition of the charge trap layer 250, the operating voltage of the semiconductor device 200 can increase. In addition, since the charge stored in the charge trap layer 250 is set separately from the ferroelectric layer 230, the depolarization field increases, and as a result, the amount of ferroelectric polarization decreases, thereby reducing the storage window and causing degradation of the retention characteristics. In addition, when the semiconductor device 200 is applied to a vertical non-volatile memory device, the charge stored in the charge trap layer 250 may move to adjacent memory cells, causing interference between memory cells and degradation of the retention characteristics.

[0070] However, as described above, in the semiconductor device 100 according to the embodiment, the nanostructure 150 is disposed inside the ferroelectric layer 130, so the increase in the operating voltage caused by the charge trapping layer disposed separately does not occur. In addition, since the nanostructure 150 is located in the same space as the ferroelectric layer 130, the formation of the depolarization field can be limited and / or suppressed. When the semiconductor device 100 is applied to a vertical non-volatile memory device, since the nanostructures 150 are arranged separately from each other in the ferroelectric layer 130, it becomes difficult for the charges trapped in the nanostructure 150 to move, and accordingly, the interference phenomenon or the degradation of the retention characteristics caused by the charge movement between the memory cells can be limited and / or suppressed.

[0071] Figure 5 is a cross-sectional view of a semiconductor device 300 according to an embodiment. Hereinafter, the description will focus on the differences from the above-described embodiment.

[0072] refer to Figure 5 , the semiconductor device 300 includes a gate electrode 110, a channel layer 120, and a ferroelectric layer 130. Since the gate electrode 110, the channel layer 120, and the ferroelectric layer 130 have been described above, their description will be omitted. A first insulating layer 141 may be provided between the gate electrode 110 and the ferroelectric layer 130. In addition, a second insulating layer 142 may be further provided between the channel layer 120 and the ferroelectric layer 130. The second insulating layer 142 may act as a tunnel barrier.

[0073] Inside the ferroelectric layer 130, a plurality of nanostructures 350 are disposed separately from each other. The plurality of nanostructures 350 may include a material having a lower band gap than the material of the ferroelectric layer 130. The plurality of nanostructures 350 may include an oxide or nitride containing an element different from the material of the ferroelectric layer 130. As an example, the plurality of nanostructures 350 may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN. However, the present disclosure is not limited thereto. The plurality of nanostructures 350 may include a material having a relatively large trap density. For example, the plurality of nanostructures 350 may include a material having a trap density greater than about 1×10 19 / cm 3 This is just an example.

[0074] The plurality of nanostructures 350 may be disposed at a distance close to an interface of the ferroelectric layer 130 adjacent to the channel layer 120 (i.e., an interface between the second insulating layer 142 and the ferroelectric layer 130). For example, the distance between the plurality of nanostructures 350 and the interface between the second insulating layer 142 and the ferroelectric layer 130 may be about 30% or less of the thickness of the ferroelectric layer 130. Each of the plurality of nanostructures 350 may have a spherical shape, an ellipsoidal spherical shape, or a rod shape. However, the present disclosure is not limited thereto.

[0075] In the semiconductor device 300 according to the present embodiment, the plurality of nanostructures 350 may store charges of a certain polarity that move from the channel layer 120 through the second insulating layer 142 by tunneling according to a voltage applied to the gate electrode 110 .

[0076] Figure 6 is a cross-sectional view of a semiconductor device 400 according to another embodiment. Hereinafter, the description will focus on the differences from the above-described embodiment.

[0077] refer to Figure 6 , the semiconductor device 400 includes a gate electrode 110, a channel layer 120, and a ferroelectric layer 130. A first insulating layer 141 may be disposed between the gate electrode 110 and the ferroelectric layer 130, and a second insulating layer 142 may be further disposed between the channel layer 120 and the ferroelectric layer 130. Each of the first insulating layer 141 and the second insulating layer 142 may function as a tunnel barrier.

[0078] Inside the ferroelectric layer 130, a plurality of first nanostructures 451 and a plurality of second nanostructures 452 are provided. The first nanostructure 451 may be disposed at a distance close to an interface of the ferroelectric layer 130 adjacent to the gate electrode 110 (i.e., an interface between the first insulating layer 141 and the ferroelectric layer 130). Here, the distance between the plurality of first nanostructures 451 and the interface between the first insulating layer 141 and the ferroelectric layer 130 may be about 30% or less of the thickness of the ferroelectric layer 130. The second nanostructure 452 may be disposed at a distance close to an interface of the ferroelectric layer 130 adjacent to the channel layer 120 (i.e., an interface between the second insulating layer 142 and the ferroelectric layer 130). Here, the distance between the plurality of second nanostructures 452 and the interface between the second insulating layer 142 and the ferroelectric layer 130 may be about 30% or less of the thickness of the ferroelectric layer 130.

[0079] The first nanostructure 451 and the second nanostructure 452 may each include an oxide or a nitride containing an element different from the material of the ferroelectric layer 130. As an example, the first nanostructure 451 and the second nanostructure 452 may each include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN. However, the present disclosure is not limited thereto. The first nanostructure 451 and the second nanostructure 452 may each include a material having a relatively large trap density. For example, the first nanostructure 451 and the second nanostructure 452 may each include a material having a trap density greater than about 1×10 19 / cm 3 The first nanostructure 451 and the second nanostructure 452 may each have, for example, a spherical shape, an ellipsoidal spherical shape, or a rod shape. The first nanostructure 451 and the second nanostructure 452 may include the same material or materials different from each other. Figure 6 An example is shown in which the first nanostructure 451 and the second nanostructure 452 are both spherical, but example embodiments are not limited thereto, and the first nanostructure 451 and the second nanostructure 452 in some embodiments may have different shapes from each other.

[0080] In the semiconductor device 400 according to the present embodiment, the first nanostructure 451 can store charges of a first polarity that move from the gate electrode 110 through the first insulating layer 141 by tunneling according to a voltage applied to the gate electrode 110, and the second nanostructure 452 can store charges of a second polarity opposite to the first polarity, and the charges of the second polarity move from the channel layer 120 through the second insulating layer 142 by tunneling.

[0081] Figure 7is a cross-sectional view of a semiconductor device 500 according to another embodiment. Hereinafter, the description will focus on the differences from the above-described embodiment.

[0082] refer to Figure 7 , the first ferroelectric layer 531, the paraelectric layer 570, and the second ferroelectric layer 532 are disposed between the gate electrode 110 and the channel layer 120. Since the first ferroelectric layer 531 and the second ferroelectric layer 532 are the same as the ferroelectric layers described above, the description thereof is omitted. The paraelectric layer 570 may be provided between the first ferroelectric layer 531 and the second ferroelectric layer 532 to adjust the ferroelectric properties of the first ferroelectric layer 531 and the second ferroelectric layer 532. For example, the paraelectric layer 570 may include SiO 2 、Al 2 O 3 ,La 2 O 3 and Y 2 O 3 However, this is merely an example, and the paraelectric layer 570 may include various other dielectric materials.

[0083] The first insulating layer 141 may be disposed between the gate electrode 110 and the first ferroelectric layer 531, and the second insulating layer 142 may be disposed between the channel layer 120 and the second ferroelectric layer 532. Inside the first ferroelectric layer 531, a plurality of nanostructures 550 are disposed separately from each other. The plurality of nanostructures 550 may include a material having a lower band gap than the material of the first ferroelectric layer 531. The plurality of nanostructures 550 may include an oxide or nitride containing an element different from the material of the first ferroelectric layer 531. As an example, the plurality of nanostructures 550 may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN. However, the present disclosure is not limited thereto. The plurality of nanostructures 550 may include a material having a relatively large trap density, for example, a material having a trap density greater than about 1×10 19 / cm 3 This is just an example.

[0084] The plurality of nanostructures 550 may be disposed at a distance close to an interface of the first ferroelectric layer 531 adjacent to the gate electrode 110 (i.e., an interface between the first insulating layer 141 and the first ferroelectric layer 531). For example, the distance between the plurality of nanostructures 550 and the interface between the first insulating layer 141 and the first ferroelectric layer 531 may be about 30% or less of the thickness of the first ferroelectric layer 531. Each of the plurality of nanostructures 550 may have, for example, a spherical shape, an ellipsoidal spherical shape, or a rod shape, but is not limited thereto.

[0085] The case where the plurality of nanostructures 550 are disposed adjacent to the interface between the first insulating layer 141 and the first ferroelectric layer 531 has been described above. However, the present disclosure is not limited thereto, and the plurality of nanostructures 550 may be disposed adjacent to the interface between the second insulating layer 142 and the second ferroelectric layer 532. In addition, the plurality of nanostructures 550 may be disposed adjacent to the interface between the first insulating layer 141 and the first ferroelectric layer 531 and the interface between the second insulating layer 142 and the second ferroelectric layer 532.

[0086] Figure 8 is a perspective view schematically showing a storage device 700 according to an embodiment. Figure 8 The memory device 700 shown in FIG. 7 may be a vertical non-volatile memory device. Fig. 9 yes Figure 8 700 is a cross-sectional view of a cell string CS of a memory device 700, Fig.10 yes Fig. 9 An enlarged view of part B.

[0087] refer to Figures 8 to 10 , the memory device 700 includes a plurality of cell strings CS disposed on a substrate 701. Here, each cell string CS may be disposed to extend in a direction (z-axis direction) perpendicular to the substrate 701. The plurality of cell strings CS may be arranged in various shapes on the substrate 701.

[0088] Each cell string CS includes a plurality of memory cells MC stacked in a direction (z-axis direction) perpendicular to the substrate 701. Here, each memory cell MC may include the semiconductor device (FeFET) according to the above-described embodiment.

[0089] The substrate 701 may include various materials. For example, the substrate 701 may include, but is not limited to, a single crystal silicon substrate, a compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate. In addition, the substrate 701 may further include, for example, an impurity region by doping, a peripheral circuit for selecting and controlling an electronic device such as a transistor, or a memory cell for storing data.

[0090] A plurality of gate electrodes 710 are stacked and spaced apart from each other in a direction perpendicular to the substrate 701. Each gate electrode 710 extends in a direction parallel to the substrate 701. The gate electrode 710 controls a corresponding channel layer 720, and a word line may be electrically connected to the gate electrode 710. A voltage that turns on / off the corresponding channel layer 720 may be selectively applied to the gate electrode 710.

[0091] For example, the gate electrode 710 may include a conductive material such as a metal, a metal nitride, a metal oxide, or polysilicon. For example, the gate electrode 710 may include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and highly doped polysilicon. However, this is merely an example, and the gate electrode 710 may include various other conductive materials.

[0092] A plurality of interlayer insulating layers 715 are stacked between the gate electrodes 710 in a direction perpendicular to the substrate 701. The interlayer insulating layer 715 may serve as a spacer for insulation between the gate electrodes 710. The interlayer insulating layer 715 may include, for example, silicon oxide, silicon nitride, but is not limited thereto.

[0093] Inside the gate electrode 710, a ferroelectric layer 730 and a channel layer 720 are sequentially provided. The ferroelectric layer 730 and the channel layer 720 are each provided to extend vertically to the substrate 701 and can be shared by a plurality of memory cells MC. A source and a drain may be provided at the lower end and the upper end of the channel layer 710, and the source and the drain may be connected to a common source line and a bit line.

[0094] A through hole penetrating the gate electrode 710 and the interlayer insulating layer 715 is formed in a direction perpendicular to the substrate 701, and this through hole can be formed to have, for example, a circular cross section. The ferroelectric layer 730 and the channel layer 720 are sequentially arranged on the inner wall of the through hole in a direction parallel to the substrate 701. Each of the ferroelectric layer 730 and the channel layer 720 can be formed to have a cylindrical shape extending in a direction perpendicular to the substrate 701.

[0095] The channel layer 720 may include a semiconductor material. For example, the channel layer 720 may include a Group IV semiconductor such as Si, Ge, SiGe, or a Group III-V semiconductor compound. The channel layer 720 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D semiconductor material, a quantum dot, or an organic semiconductor. Here, the oxide semiconductor may include, for example, InGaZnO, the 2D semiconductor material may include, for example, TMD or graphene, and the quantum dot may include a colloidal quantum dot, a nanocrystal structure, etc. However, this is merely an example, and the present embodiment is not limited thereto.

[0096] The channel layer 720 may further include a dopant. Here, the dopant may include a p-type dopant or an n-type dopant. The p-type dopant may include, for example, a group III element such as B, Al, Ga, In, and the n-type dopant may include a group V element such as P, As, Sb.

[0097] Inside the channel layer 720, a filling insulating layer 760 may be provided to fill the via hole. The filling insulating layer 760 may include, for example, silicon oxide or air, but is not limited thereto.

[0098] The ferroelectric layer 730 is disposed between the gate electrode 710 and the channel layer 720. The ferroelectric layer 730 may include a fluorite-based material. For example, the ferroelectric layer 730 may include at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr. As an example, the ferroelectric layer 730 may include at least one of hafnium oxide (HfO), zirconium oxide (ZrO), and hafnium zirconium oxide (HfZrO). The ferroelectric layer 730 may further include a dopant. The dopant may include, for example, at least one of Si, Al, La, Y, Sr, and Gd. But this is only an example. The ferroelectric layer 730 may have a thickness of, for example, about 4 nm to about 20 nm, but is not limited thereto.

[0099] A first insulating layer 741 may be provided between the gate electrode 710 and the ferroelectric layer 730. The first insulating layer 741 may act as a tunnel barrier. The first insulating layer 741 may include, for example, silicon oxide or silicon nitride, but is not limited thereto. In addition, a second insulating layer 742 may be further provided between the channel layer 720 and the ferroelectric layer 730.

[0100] Inside the ferroelectric layer 730, a plurality of nanostructures 750 are disposed separately from each other. The plurality of nanostructures 750 may be configured to store charges of a certain polarity, which move from the gate electrode 710 through the first insulating layer 741 by tunneling according to a voltage applied to the gate electrode 710. The plurality of nanostructures 750 may include a material having a lower band gap than the material of the ferroelectric layer 730. The plurality of nanostructures 750 may include an oxide or nitride containing an element different from the material of the ferroelectric layer 730. As an example, the plurality of nanostructures 750 may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN. However, the present disclosure is not limited thereto. The plurality of nanostructures 750 may include a material having a relatively large trap density. For example, the plurality of nanostructures 750 may include a material having a band gap greater than about 1×10 19 / cm 3 This is just an example.

[0101] The plurality of nanostructures 750 may be disposed at a distance close to an interface of the ferroelectric layer 730 adjacent to the gate electrode 710 (i.e., an interface between the first insulating layer 741 and the ferroelectric layer 730). For example, the distance between the plurality of nanostructures 750 and the interface between the first insulating layer 741 and the ferroelectric layer 730 may be about 30% or less of the thickness of the ferroelectric layer 730.

[0102] Each of the plurality of nanostructures 750 may have various shapes such as a sphere, an ellipsoidal sphere, or a rod. Each of the plurality of nanostructures 750 may have a nanoscale size. In detail, each nanostructure 750 may have a size of 30% or less of the thickness of the ferroelectric layer 730 in the thickness direction of the ferroelectric layer 730. In addition, each nanostructure 750 may have a size of about 10 nm or less in a direction parallel to the ferroelectric layer 730. However, this is only an example.

[0103] In the memory device 700 according to the embodiment described above, the nanostructure 750 for charge trapping is provided inside the ferroelectric layer 730, so the operating voltage does not increase. Since the nanostructure 750 is located in the same space as the ferroelectric layer 730, the formation of the depolarization field can be limited and / or suppressed. In addition, since the nanostructures 750 are arranged separately from each other inside the ferroelectric layer 730, it becomes difficult for the charges trapped in the nanostructures 750 to move, so the interference phenomenon and the degradation of the retention characteristics caused by the charge movement between the memory cells MC can be limited and / or suppressed.

[0104] The case where the nanostructure 750 is disposed adjacent to the gate electrode 710 has been described above, but the present disclosure is not limited thereto, and the nanostructure 750 may also be disposed adjacent to the channel layer 720. In addition, the nanostructure 750 may be disposed adjacent to the gate electrode 710 and the channel layer 720. A paraelectric layer may be inserted into the ferroelectric layer 730.

[0105] The storage device 700 according to the above-described embodiment may be used to store data in various electronic devices. Fig.11 is a conceptual diagram schematically illustrating a device architecture that may be applied to an electronic device according to an embodiment.

[0106] refer to Fig.11 , the cache memory 1510, the arithmetic logic unit (ALU) 1520 and the control unit 1530 may form a central processing unit (CPU) 1500, and the cache memory 1510 may be a static random access memory (SRAM). In addition to the CPU 1500, a main memory 1800 and an auxiliary storage 1900 may be provided. An input / output device 2500 (e.g., a keyboard, a display) may be provided. The main memory 1800 may include a dynamic random access memory (DRAM) device, and the auxiliary storage 1900 may include the storage device 700 (vertical non-volatile storage device) described above. In some cases, the device architecture may be implemented in the form of a computing unit device and a storage unit device adjacent to each other on a single chip without distinction of sub-units.

[0107] The memory device 700 according to the above-described embodiment may be implemented as a memory block in the form of a chip and used as a neuromorphic computing platform, or may be used to configure a neural network.

[0108] Fig.12 is a block diagram of a storage system 1600 according to one embodiment.

[0109] refer to Fig.12 , the storage system 1600 may include a storage controller 1601 and a storage device 1602. The storage controller 1601 performs a control operation on the storage device 1602, for example, the storage controller 1601 provides an address ADD and provides a command CMD to the storage device 1602 to perform a programming (or recording), reading and / or erasing operation on the storage device 1602. In addition, data for a programming operation and read data may be transmitted between the storage controller 1601 and the storage device 1602.

[0110] The memory device 1602 may include a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 may include a plurality of memory cells, and may include the memory device 700 (vertical nonvolatile memory device) according to the above-described embodiment.

[0111] The memory controller 1601 may include a processing circuit, such as hardware including a logic circuit; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuit is more specifically a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc., but is not limited thereto. The memory controller 1601 may operate in response to a request from a host (not shown), and may be configured to access the memory device 1602 and control the above-mentioned control operations (e.g., write / read operations) to convert the memory controller 1601 into a dedicated controller. The memory controller 1601 may generate an address ADD and a command CMD to perform a program / read / erase operation on the memory cell array 1610. In addition, in response to a command from the memory controller 1601, the voltage generator 1620 (e.g., a power supply circuit) may generate a voltage control signal for controlling the voltage level of a word line for programming data on the memory cell array 1610 or reading data from the memory cell array 1610.

[0112] In addition, the memory controller 1601 may perform a decision operation on the data read from the memory device 1602. For example, the number of on cells and / or the number of off cells may be determined by the data read from the memory cells. The memory device 1602 may provide a pass / fail signal P / F to the memory controller 1601 according to the read result of the read data. The memory controller 1601 may control the write and read operations of the memory cell array 1610 by referring to the pass / fail signal P / F.

[0113] Fig.13 is a block diagram illustrating a neuromorphic device 1700 and external devices connected thereto according to an embodiment.

[0114] refer to Fig.13 , the neuromorphic device 1700 may include a processing circuit 1710 and / or an on-chip memory 1720. The neuromorphic device 1700 may include the memory device 700 (vertical non-volatile memory device) according to the embodiments described above.

[0115] In some embodiments, the processing circuit 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the on-chip memory 1720. In some embodiments, the processing circuit may include hardware such as a logic circuit, a hardware / software combination such as a processor that executes software, or a combination thereof. For example, the processor may include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, an ASIC, but is not limited thereto. In some embodiments, the processing circuit 1710 is configured to read / write various data to the external device 1730 and / or to execute the neuromorphic device 1700 by using the read / written data. In some embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (e.g., a complementary metal oxide semiconductor (CMOS) image sensor circuit).

[0116] In some embodiments, Fig.13The neuromorphic device 1700 can be applied to a machine learning system. As a machine learning system, various artificial neural network systems and processing models can be used, such as a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) (optionally including a long short-term memory (LSTM) unit and / or a gated recurrent unit (GRU)), a stacked neural network (SNN), a state space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN) and / or a restricted Boltzmann machine (RBM).

[0117] Alternatively or additionally, these machine learning systems may be implemented with other forms of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or ensemble methods such as random forests, or combinations thereof. These machine learning models may be used to provide various services and / or applications, such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., which may be performed by electronic devices.

[0118] In the semiconductor device according to the above-mentioned embodiment, the nanostructure for charge trapping is arranged inside the ferroelectric layer, so that the operating voltage does not increase, and since the nanostructure is located in the same space as the ferroelectric layer, the increase of the depolarization field can be limited and / or suppressed. When the semiconductor device is applied to a vertical non-volatile memory device, since the nanostructures are arranged separately from each other inside the ferroelectric layer, it becomes difficult for the charges trapped in the nanostructures to move to adjacent memory cells, and accordingly, the interference phenomenon caused by the charge movement between the memory cells and the degradation of the retention characteristics can be limited and / or suppressed.

[0119] The above has been described with reference to the embodiments shown in the accompanying drawings, but these are merely examples, and various modifications and other equivalent embodiments may be derived therefrom. Figure 1 , 2 , 3A, 3B, and 5-9, the nanostructures 150, 350, 451, 452, 550, and 750 described may include two or more different types of nanostructures (e.g., a first nanostructure and a second nanostructure having different materials and / or shapes). Figure 1 Some embodiments illustrate a single column of nanostructures 150, but example embodiments are not limited thereto, and the nanostructures 150 may be spaced apart from each other in more than one column and / or spaced apart from each other at different distances from each other.

[0120] One or more of the elements disclosed above may include or be implemented in a processing circuit (such as hardware including logic circuits; a hardware / software combination such as a processor that executes software; or a combination thereof). For example, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0121] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined in the appended claims.

[0122] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137033 filed in the Korean Intellectual Property Office on October 13, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a gate electrode; a ferroelectric layer on the gate electrode; a channel layer on the ferroelectric layer; as well as A plurality of nanostructures spaced apart from each other in the ferroelectric layer, wherein The plurality of nanostructures are adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures are adjacent to the gate electrode and the remaining portion of the plurality of nanostructures are adjacent to the channel layer.

2. The semiconductor device according to claim 1, wherein The plurality of nanostructures are configured to store charge in response to a voltage being applied to the gate electrode and polarization being formed in the ferroelectric layer.

3. The semiconductor device according to claim 1, wherein A distance between the plurality of nanostructures and an interface of the ferroelectric layer is 30% or less of a thickness of the ferroelectric layer, and The interface of the ferroelectric layer is adjacent to the gate electrode, the channel layer, or both the gate electrode and the channel layer. 4 . The semiconductor device according to claim 1 , wherein a band gap of a material of the plurality of nanostructures is lower than a band gap of a material of the ferroelectric layer.

5. The semiconductor device according to claim 4, wherein The plurality of nanostructures include an oxide of an element different from the material of the ferroelectric layer or a nitride of an element different from the material of the ferroelectric layer. 6 . The semiconductor device of claim 4 , wherein the plurality of nanostructures include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, and ZrN.

7. The semiconductor device according to claim 1, wherein the material of the plurality of nanostructures has a thickness greater than 1×10 19 / cm 3 The trap density. 8 . The semiconductor device according to claim 1 , wherein the ferroelectric layer comprises at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

9. The semiconductor device according to claim 8, wherein the ferroelectric layer further comprises a dopant.

10. The semiconductor device according to claim 1, further comprising: a first insulating layer between the gate electrode and the ferroelectric layer, a second insulating layer between the channel layer and the ferroelectric layer, or Both the first insulating layer between the gate electrode and the ferroelectric layer and the second insulating layer between the channel layer and the ferroelectric layer.

11. The semiconductor device according to claim 1, further comprising: A paraelectric layer in the ferroelectric layer.

12. A storage device comprising: substrate; a plurality of gate electrodes stacked in a direction perpendicular to the substrate; a ferroelectric layer on the plurality of gate electrodes; a channel layer on the ferroelectric layer; as well as a plurality of nanostructures spaced apart from each other and in the ferroelectric layer, wherein The plurality of nanostructures are adjacent to the plurality of gate electrodes or the channel layer, or a portion of the plurality of nanostructures are adjacent to the plurality of gate electrodes and the remaining portion of the plurality of nanostructures are adjacent to the channel layer.

13. The storage device according to claim 12, wherein A distance between the plurality of nanostructures and an interface of the ferroelectric layer is 30% or less of a thickness of the ferroelectric layer, and The interface of the ferroelectric layer is adjacent to the plurality of gate electrodes, the channel layer, or both the plurality of gate electrodes and the channel layer.

14. The memory device of claim 12, wherein a band gap of a material of the plurality of nanostructures is lower than a band gap of a material of the ferroelectric layer. 15 . The memory device of claim 12 , wherein the plurality of nanostructures include an oxide of an element different from a material of the ferroelectric layer or a nitride of an element different from the material of the ferroelectric layer.

16. The memory device according to claim 12, wherein the material of the plurality of nanostructures has a thickness greater than 1×10 19 / cm 3 The trap density.

17. The memory device of claim 12, wherein the ferroelectric layer comprises at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

18. The storage device according to claim 12, further comprising: a first insulating layer between the plurality of gate electrodes and the ferroelectric layer, a second insulating layer between the channel layer and the ferroelectric layer, or Both the first insulating layer between the plurality of gate electrodes and the ferroelectric layer and the second insulating layer between the channel layer and the ferroelectric layer.

19. The storage device according to claim 12, further comprising: A paraelectric layer in the ferroelectric layer.

20. An electronic device, comprising: The storage device according to claim 12.

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