Semiconductor structure and preparation method thereof, memory and electronic equipment

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, a memory and electronic equipment. The semiconductor structure comprises a substrate, a laminated structure and a gate structure, the laminated structure is located on the substrate and comprises a first end structure, a channel layer and a second end structure which are sequentially laminated from bottom to top; the first end structure comprises a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure comprises a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer; the gate structure surrounds the channel layer. According to the semiconductor structure, lattice damage can be avoided, the short-channel effect is effectively inhibited, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure and a preparation method thereof, a memory and an electronic device. Background Art

[0002] In the field of integrated circuit design and manufacturing technology, in order to form more devices in the same area, the integration of semiconductor devices continues to increase, and the technical nodes of the devices continue to decrease. In order to further improve the storage density of memory, one of the research directions of R&D personnel is to design a tighter structure to achieve a larger storage capacity and reduce device costs.

[0003] However, the current method of achieving source-drain doping through ion implantation usually has problems such as uneven dopant distribution, inability to accurately control the doping area, and lattice damage caused by excessive implantation energy. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a method for preparing the same, a memory and an electronic device, which can at least avoid lattice damage and improve device performance.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a semiconductor structure, which includes a substrate, a stacked structure and a gate structure; the stacked structure is located on the substrate, including a first end structure, a channel layer and a second end structure stacked in sequence from bottom to top; the first end structure includes a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure includes a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer; the gate structure surrounds the channel layer.

[0006] In some embodiments, the first end structure includes a drain, and the second end structure includes a source; or the first end structure includes a source, and the second end structure includes a drain.

[0007] In some embodiments, the first end epitaxial layer and the second end epitaxial layer both include phosphorus-doped silicon layers; and the first end barrier layer and the second end barrier layer both include arsenic-doped silicon layers.

[0008] In some embodiments, a protective layer is further included, and the protective layer is located on the upper surface of the stacked structure.

[0009] In some embodiments, the channel layer includes an intrinsic silicon layer; the width of the first end structure, the width of the second end structure and the width of the channel layer are all the same, and the sidewalls of the first end structure, the sidewalls of the second end structure and the sidewalls of the channel layer are all flush.

[0010] In some embodiments, the channel layer includes a germanium silicon layer; the sidewalls of the first end structure, the sidewalls of the second end structure, and the sidewalls of the gate structure away from the channel layer are all flush.

[0011] In some embodiments, a cap layer is further included, and the cap layer surrounds the surface of the channel layer; and the gate structure surrounds the surface of the cap layer.

[0012] According to some embodiments, another aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0013] providing a substrate;

[0014] A stacked structure is formed on a substrate, the stacked structure comprising a first end structure, a channel layer and a second end structure stacked in sequence from bottom to top; the first end structure comprises a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure comprises a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer;

[0015] A gate structure is formed, wherein the gate structure surrounds the channel layer.

[0016] In some embodiments, a stacked structure is formed on a substrate, comprising:

[0017] Forming an epitaxial material stack on the substrate, the epitaxial material stack comprising a first end epitaxial material layer, a first end barrier material layer, a channel material layer, a second end barrier material layer and a second end epitaxial material layer stacked in sequence from bottom to top;

[0018] The epitaxial material stack is etched to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top.

[0019] In some embodiments, the channel layer includes an intrinsic silicon layer; the epitaxial material stack is etched to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked sequentially from bottom to top, including:

[0020] forming a protective layer on the upper surface of the epitaxial material stack, the protective layer defining the shape and position of the stack structure;

[0021] The epitaxial material stack is etched based on the protective layer to obtain a stacked structure; the width of the first end structure, the width of the second end structure and the width of the channel layer are all the same, and the sidewalls of the first end structure, the sidewalls of the second end structure and the sidewalls of the channel layer are all flush.

[0022] In some embodiments, the channel layer includes a germanium silicon layer; the epitaxial material stack is etched to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked sequentially from bottom to top, including:

[0023] forming a protective layer on the upper surface of the epitaxial material stack, the protective layer defining the shape and position of the stack structure;

[0024] Etching the epitaxial material stack based on the protective layer to obtain a first end epitaxial layer, a first end barrier layer, an initial channel layer, a second end barrier layer and a second end epitaxial layer;

[0025] The initial channel layer is selectively etched to obtain a channel layer, and a groove is formed at the periphery of the channel layer; and a gate structure is formed in the groove.

[0026] In some embodiments, after forming the stacked structure on the substrate and before forming the gate structure, the method further includes: forming a cap layer in the groove, the cap layer surrounding the surface of the channel layer; and the gate structure surrounding the surface of the cap layer.

[0027] According to some embodiments, another aspect of the present disclosure provides a memory including the above-mentioned semiconductor structure.

[0028] According to some embodiments, another aspect of the present disclosure provides an electronic device including the above-mentioned memory.

[0029] The embodiments of the present disclosure may or at least have the following advantages:

[0030] In the embodiment of the present disclosure, the first end structure and the second end structure of the stacked structure can be used as the source and drain of the device. Compared with the method of realizing source and drain doping by ion implantation process in the related art, the first end structure and the second end structure adopt epitaxial layer, which can accurately control the area of ​​the source and drain, and have the advantage of uniform doping concentration, while avoiding lattice damage caused by injection energy, and there is no need to consider factors such as energy, angle, total dose and number of injections of impurities, thereby reducing the difficulty of preparing the semiconductor structure. In addition, the first end structure includes a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure includes a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer, that is, the first end structure and the second end structure both adopt double-layer structure, which can effectively suppress the short channel effect and improve the performance of the device. Among them, the first end barrier layer and the second end barrier layer can reduce the diffusion of dopants, so that the first end structure and the second end structure obtain a clearer interface. In addition, the gate structure surrounding the channel layer can form a surrounding gate (Gate-All-Around, referred to as GAA) structure, which can increase the contact area between the gate structure and the channel layer, improve the gate control capability, and further improve the performance of the device. The GAA structure is also conducive to saving structural size and process stacking, so as to further improve the distribution density of the semiconductor structure, thereby further improving the storage density of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of a structure obtained by forming a source and a drain by an ion implantation process;

[0033] Figure 2 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment;

[0034] Figure 3 is a schematic cross-sectional view of a semiconductor structure provided in another embodiment;

[0035] Figure 4 This is a schematic diagram comparing the lattice constants of phosphorus and other elements;

[0036] Figure 5 is a schematic diagram of a curve showing that the doping concentration of arsenic element varies with depth;

[0037] Figure 6 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0038] Figure 7 It is a schematic cross-sectional view of a structure obtained in step 31 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0039] Figure 8 It is a schematic cross-sectional view of a structure obtained in step 32 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0040] Fig. 9 It is a schematic cross-sectional view of a structure obtained in step 41 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0041] Fig.10 It is a schematic cross-sectional view of a structure obtained in step 42 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0042] Fig.11 It is a schematic cross-sectional view of a structure obtained in step 51 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0043] Fig.12 It is a schematic cross-sectional view of a structure obtained in step 52 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0044] Fig.13 It is a schematic cross-sectional view of a structure obtained in step 53 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0045] Fig.14 It is a cross-sectional schematic diagram of a structure obtained in step 60 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0046] Fig.15 It is a cross-sectional schematic diagram of a structure obtained in step 31 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0047] Fig.16 It is a cross-sectional schematic diagram of a structure obtained in step 323 and step 324 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0048] Fig.17 It is a cross-sectional schematic diagram of a structure obtained in step 325 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0049] Fig.18It is a schematic cross-sectional view of a structure obtained in step 40 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0050] Fig.19 It is a schematic cross-sectional view of a structure obtained in step 51 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0051] Fig. 20 It is a schematic cross-sectional view of a structure obtained in step 52 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0052] Fig.21 It is a schematic cross-sectional view of a structure obtained in step 53 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0053] Fig. 22 It is a schematic cross-sectional view of a structure obtained in step 54 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0054] Fig.23 It is a schematic cross-sectional view of a structure obtained in step 60 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.

[0055] Description of reference numerals:

[0056] 1. Substrate; 2. Stacked structure; 2a. Epitaxial material stack; 21. First end structure; 211. First end epitaxial layer; 211a. First end epitaxial material layer; 212. First end barrier layer; 212a. First end barrier material layer; 22. Channel layer; 22a. Channel material layer; 221. Initial channel layer; 222. Groove; 23. Second end structure; 231. Second end epitaxial layer; 231a. Second end barrier material layer; 232. Second end barrier layer; 232a. Second end epitaxial material layer; 3. Gate structure; 31. Gate dielectric layer; 31a. Gate dielectric material layer; 32. Gate conductive layer; 32a. Gate conductive material layer; 4. Protective layer; 5. Cap layer; 6. Isolation layer; 61. Initial isolation layer; 7. Oxide layer. DETAILED DESCRIPTION

[0057] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0059] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and is not to be understood as having one number.

[0060] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0061] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0062] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0063] As the semiconductor industry's technology process nodes gradually shrink, the semiconductor industry further pursues higher device density, higher performance and lower cost. The challenges from manufacturing and design issues have led to the design and development of three-dimensional structures such as fin field effect transistors (Fin-FET) or vertical-gate-all-around (GAA). Please refer to Figure 1, usually in Fin-FET devices, there is a thin and vertical "fin" structure extending from the substrate, and in VGAA devices, there is a columnar structure extending perpendicular to the substrate. The source and drain doping is achieved through ion implantation, which usually has the problem of uneven dopant distribution and inability to accurately control the doping area. Since the deeper the ion implantation, the higher the required implantation energy, the fin structure in the Fin-FET device and the active column structure in the VGAA device both have a large aspect ratio. When ion implantation is performed on a morphology with a large aspect ratio, the problem of lattice damage caused by excessive implantation energy will occur.

[0064] In view of the above-mentioned deficiencies in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, a memory and an electronic device, the details of which will be described in subsequent embodiments.

[0065] According to some embodiments, the present disclosure provides a semiconductor structure.

[0066] As an example, the semiconductor structure can be used to form a semiconductor device, such as a memory, and the memory can include a transistor structure and a capacitor connected to the transistor structure, the capacitor is used to store data, and the transistor structure is used to read data in the capacitor or write data into the capacitor. It can be understood that the semiconductor structure provided in the embodiment of the present application can be directly used as a transistor structure in the memory, or as a component of a transistor structure, for example, it can be a transistor in a 1T1C structure, or a transistor in a 2T0C structure, but it is not limited to this. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0067] Please refer to Figure 2 The semiconductor structure includes a substrate 1, a stacked structure 2 and a gate structure 3; the stacked structure 2 is located on the substrate 1, and includes a first end structure 21, a channel layer 22 and a second end structure 23 stacked in sequence from bottom to top; the first end structure 21 includes a first end epitaxial layer 211 and a first end barrier layer 212, the first end epitaxial layer 211 is located between the channel layer 22 and the substrate 1, and the first end barrier layer 212 is located between the first end epitaxial layer 211 and the channel layer 22; the second end structure 23 includes a second end epitaxial layer 231 and a second end barrier layer 232, the second end epitaxial layer 231 is located on the channel layer 22, and the second end barrier layer 232 is located between the second end epitaxial layer 231 and the channel layer 22; the gate structure 3 surrounds the channel layer 22.

[0068] In the semiconductor structure of the above embodiment, the first end structure 21 and the second end structure 23 of the stacked structure 2 can be used as the source and drain of the device. Compared with the method of realizing source and drain doping through ion implantation process in the related art, the first end structure 21 and the second end structure 23 use epitaxial layers, which can accurately control the source and drain areas and have the advantage of uniform doping concentration. At the same time, it avoids lattice damage caused by injection energy, and there is no need to consider factors such as the energy, angle, total dose and number of injections of impurities, thereby reducing the difficulty of preparing the semiconductor structure.

[0069] In addition, the first end structure 21 includes a first end epitaxial layer 211 and a first end barrier layer 212, wherein the first end epitaxial layer 211 is located between the channel layer 22 and the substrate 1, and the first end barrier layer 212 is located between the first end epitaxial layer 211 and the channel layer 22; the second end structure 23 includes a second end epitaxial layer 231 and a second end barrier layer 232, wherein the second end epitaxial layer 231 is located on the channel layer 22, and the second end barrier layer 232 is located between the second end epitaxial layer 231 and the channel layer 22, that is, both the first end structure 21 and the second end structure 23 adopt a double-layer structure, which can effectively suppress the short channel effect and improve the performance of the device. Among them, the first end barrier layer 212 and the second end barrier layer 232 can reduce the diffusion of dopants, so that the first end structure 21 and the second end structure 23 obtain a clearer interface.

[0070] In addition, the gate structure 3 surrounding the channel layer 22 can form a surrounding gate (Gate-All-Around, GAA for short) structure, which can increase the contact area between the gate structure 3 and the channel layer 22, improve the gate control capability, and further enhance the performance of the device. The GAA structure is also beneficial for saving structural size and process stacking, so as to further improve the distribution density of the semiconductor structure, thereby further improving the storage density of the device.

[0071] In some embodiments, the first terminal structure 21 includes a drain, and the second terminal structure 23 includes a source; or the first terminal structure 21 includes a source, and the second terminal structure 23 includes a drain.

[0072] In some embodiments, the semiconductor structure further includes a protective layer 4 , which is located on the upper surface of the stacked structure 2 and can provide electrical protection for the stacked structure 2 to prevent contamination by external air or water vapor.

[0073] In some embodiments, the channel layer 22 includes an intrinsic silicon layer; the width of the first end structure 21, the width of the second end structure 23 and the width of the channel layer 22 are all the same, and the sidewalls of the first end structure 21, the sidewalls of the second end structure 23 and the sidewalls of the channel layer 22 are all flush. In this way, the semiconductor structure in this embodiment can be used to form a junctionless field effect transistor (JLT). In the JLT, the impurity doping type of the source, channel and drain is the same, there is no PN junction, and it is a majority carrier conductive device. The gate bias voltage is used to change the electric field strength perpendicular to the conductive channel, so that the majority carriers in the channel are accumulated or depleted, thereby modulating the channel conductance to control the channel current, which can alleviate the technical challenges faced by traditional transistors due to feature size miniaturization.

[0074] In some embodiments, the semiconductor structure further includes an isolation layer 6, which surrounds the first end structure 21, and the top surface of the isolation layer 6 is parallel to the top surface of the first end barrier layer 212 away from the substrate 1, and is used to isolate adjacent first end structures 21 when forming multiple stacked structures 2.

[0075] In some embodiments, the semiconductor structure further includes an oxide layer 7 which at least surrounds the second terminal structure 23 and the gate structure 3 , and a top surface of the oxide layer 7 is parallel to a top surface of the protection layer 4 .

[0076] For example, Figure 2 As shown, the oxide layer 7 is located on the surface of the isolation layer 6 .

[0077] In some embodiments, the gate structure 3 includes a gate dielectric layer 31 and a gate conductive layer 32 . The gate dielectric layer 31 surrounds the channel layer 22 , and the gate conductive layer 32 surrounds the gate dielectric layer 31 .

[0078] Please refer to Figure 3 In some embodiments, the channel layer 22 includes a germanium silicon layer; the sidewalls of the first end structure 21 , the sidewalls of the second end structure 23 , and the sidewalls of the gate structure 3 away from the channel layer 22 are all flush.

[0079] For example, in the channel layer 22 using a germanium silicon layer, the content of germanium element ranges from 10% to 30%. For example, the content of germanium element may be 10%, 15%, 20%, 25% or 30%.

[0080] In some embodiments, a cap layer 5 is further included, and the cap layer 5 surrounds the surface of the channel layer 22; the gate structure 3 surrounds the surface of the cap layer 5. The cap layer 5 can use the quantum confinement effect to confine electrons in the cap layer 5 to increase the mobility of electrons, increase the on-state current, and improve the interface. In this way, the semiconductor structure in this embodiment can be used to form a transistor with an inversion mode.

[0081] It can be understood that the generation or disappearance of the inversion layer can be controlled by the gate voltage. The gate voltage when the inversion layer is generated or disappears is the threshold voltage of the device; for enhancement-type devices, this threshold voltage is called the turn-on voltage; for depletion-type devices, this threshold voltage is called the pinch-off voltage. Since the minority carrier concentration in the channel follows an exponential function relationship with the depth of the surface potential well (proportional to the gate voltage), when the gate voltage causes a channel to appear on the semiconductor surface, the minority carrier concentration in the channel will be very large (equal to or even greater than the majority carrier concentration in the body). Therefore, the surface inversion layer has a shielding effect on the gate voltage, that is, after the channel appears, the gate voltage will increase, and it will not affect the state of the semiconductor under the inversion layer, thereby improving the device performance.

[0082] In some embodiments, the gate dielectric layer 31 surrounds the cap layer 5 and covers the sidewall of the first end structure 21 close to the channel layer 22 and covers the sidewall of the second end structure 23 close to the channel layer 22 . The gate conductive layer 32 covers the gate dielectric layer 31 .

[0083] For example, Figure 3 As shown, the oxide layer 7 is located on the surface of the substrate 1 and surrounds the first end structure 21 .

[0084] Please refer to Figures 2 to 5 In some embodiments, both the first end epitaxial layer 211 and the second end epitaxial layer 231 include phosphorus-doped silicon layers.

[0085] Combination Figure 4 It can be understood that the lattice constant refers to the length of the lattice parameter in the crystal structure. The lattice constant is an important physical quantity in crystallography, which characterizes the periodicity of the arrangement of atoms or molecules in the crystal. The value of the lattice constant can be obtained by experimental measurement or by theoretical calculation. For the crystal structure, the lattice constant usually refers to the lattice parameter in the basic repeating unit of the lattice. In the above embodiment, since the lattice constant of phosphorus is smaller than that of silicon, tensile strain can be generated, thereby obtaining a smaller contact resistance and improving the mobility of carriers.

[0086] In some embodiments, both the first end barrier layer 212 and the second end barrier layer 232 include arsenic-doped silicon layers.

[0087] Combination Figure 5 It can be understood that the doping concentration of the arsenic-doped silicon layer decreases with increasing depth, that is, the arsenic-doped silicon layer is not easy to diffuse, which can reduce the diffusion of dopants. The first end barrier layer 212 and the second end barrier layer 232 of the arsenic-doped silicon layer can obtain a clear interface.

[0088] In some embodiments, the thickness of the first end epitaxial layer 211 is the same as the thickness of the second end epitaxial layer 231. For example, the thickness of the first end epitaxial layer 211 and the thickness of the second end epitaxial layer 231 both range from 40 nm to 60 nm, for example, the thickness of the first end epitaxial layer 211 and the thickness of the second end epitaxial layer 231 can both be 40 nm, 45 nm, 50 nm, 55 nm or 60 nm.

[0089] In some embodiments, the thickness of the first end barrier layer 212 is the same as the thickness of the second end barrier layer 232. For example, the thickness of the first end barrier layer 212 and the thickness of the second end barrier layer 232 both range from 8 nm to 12 nm, for example, the thickness of the first end barrier layer 212 and the thickness of the second end barrier layer 232 can both be 8 nm, 9 nm, 10 nm, 11 nm, or 12 nm.

[0090] For example, the first-end epitaxial layer 211 and the second-end epitaxial layer 231 are both phosphorus-doped silicon layers with a thickness of 50 nm, and the first-end blocking layer 212 and the second-end blocking layer 232 are both arsenic-doped silicon layers with a thickness of 10 nm. At this time, the resistivity of the first-end structure 21 formed by the first-end epitaxial layer 211 and the first-end blocking layer 212 is the same as that of a single-layer phosphorus-doped silicon layer with a thickness of 50 nm, and has the same electron mobility, thereby reducing the diffusion of dopants, suppressing the short channel effect, and improving device performance while ensuring the resistivity and electron mobility.

[0091] According to some embodiments, the present application also provides a method for preparing a memory cell, which is used to prepare the semiconductor structure provided by some of the above embodiments. Therefore, the technical effects possessed by the above semiconductor structure are also possessed by the method for preparing the semiconductor structure.

[0092] Please refer to Figure 6 In some embodiments, the method for preparing a semiconductor structure may include the following steps:

[0093] S10: providing a substrate;

[0094] S30: forming a stacked structure on the substrate, the stacked structure comprising a first end structure, a channel layer and a second end structure stacked in sequence from bottom to top; the first end structure comprising a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure comprising a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer;

[0095] S50: forming a gate structure, wherein the gate structure surrounds the channel layer.

[0096] In some embodiments, step S30, forming a stacked structure on a substrate, includes:

[0097] S31: forming an epitaxial material stack on a substrate, wherein the epitaxial material stack includes a first end epitaxial material layer, a first end barrier material layer, a channel material layer, a second end barrier material layer and a second end epitaxial material layer stacked in sequence from bottom to top;

[0098] S32: etching the epitaxial material stack to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top.

[0099] In some embodiments, the channel layer includes an intrinsic silicon layer; step S32, etching the epitaxial material stack to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top, including:

[0100] S321: forming a protective layer on the upper surface of the epitaxial material stack, wherein the protective layer defines the shape and position of the stack structure;

[0101] S322: etching the epitaxial material stack based on the protective layer to obtain a stacked structure; the width of the first end structure, the width of the second end structure and the width of the channel layer are all the same, and the sidewalls of the first end structure, the sidewalls of the second end structure and the sidewalls of the channel layer are all flush.

[0102] In some embodiments, the channel layer includes a germanium silicon layer; step S32, etching the epitaxial material stack to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top, including:

[0103] S323: forming a protective layer on the upper surface of the epitaxial material stack, wherein the protective layer defines the shape and position of the stack structure;

[0104] S324: etching the epitaxial material stack based on the protective layer to obtain a first end epitaxial layer, a first end barrier layer, an initial channel layer, a second end barrier layer and a second end epitaxial layer;

[0105] S325: selectively etching the initial channel layer to obtain a channel layer, wherein a groove is formed at the periphery of the channel layer; and a gate structure is formed in the groove.

[0106] In some embodiments, after forming the stacked structure on the substrate in step S32 and before forming the gate structure in step S50, the process further includes:

[0107] S40: forming a cap layer in the groove, wherein the cap layer surrounds the surface of the channel layer; and a gate structure surrounds the surface of the cap layer.

[0108] It should be understood that although Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0109] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiments, Figures 7 to 14 Understand some embodiments of the present application.

[0110] The present embodiment does not specifically limit the constituent material of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate 1, a silicon germanium carbon (SiGeC) substrate 1, a silicon carbide (SiC) substrate 1, a gallium arsenide (GaAs) substrate 1, an indium arsenide (InAs) substrate 1, an indium phosphide (InP) substrate 1 or other III / V semiconductor substrates 1 or II / VI semiconductor substrates 1. Alternatively, for example, the substrate 1 can be a layered substrate 1 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator, etc.

[0111] Please refer to Figures 7 and 8 In step S30, a stacked structure 2 is formed on the substrate 1, the stacked structure 2 comprising a first end structure 21, a channel layer 22 and a second end structure 23 stacked in sequence from bottom to top; the first end structure 21 comprises a first end epitaxial layer 211 and a first end barrier layer 212, the first end epitaxial layer 211 is located between the channel layer 22 and the substrate 1, and the first end barrier layer 212 is located between the first end epitaxial layer 211 and the channel layer 22; the second end structure 23 comprises a second end epitaxial layer 231 and a second end barrier layer 232, the second end epitaxial layer 231 is located on the channel layer 22, and the second end barrier layer 232 is located between the second end epitaxial layer 231 and the channel layer 22;

[0112] In some embodiments, step S30, forming a stacked structure 2 on a substrate 1, includes:

[0113] S31: Figure 7As shown, an epitaxial material stack 2a is formed on a substrate 1, and the epitaxial material stack 2a includes a first end epitaxial material layer 211a, a first end barrier material layer 212a, a channel material layer 22a, a second end barrier material layer 231a and a second end epitaxial material layer 232a stacked in sequence from bottom to top;

[0114] S32: Figure 8 As shown, the epitaxial material stack 2a is etched to obtain a stacked structure 2 including a first end epitaxial layer 211, a first end barrier layer 212, a channel layer 22, a second end barrier layer 232 and a second end epitaxial layer 231 stacked in sequence from bottom to top.

[0115] In some embodiments, the channel layer 22 includes an intrinsic silicon layer;

[0116] like Figures 7 and 8 As shown, in an embodiment where the channel layer 22 includes an intrinsic silicon layer, in step S32, the epitaxial material stack 2a is etched to obtain a stacked structure 2 including a first end epitaxial layer 211, a first end barrier layer 212, a channel layer 22, a second end barrier layer 232 and a second end epitaxial layer 231 stacked sequentially from bottom to top, including:

[0117] S321: forming a protective layer 4 on the upper surface of the epitaxial material stack 2a, wherein the protective layer 4 defines the shape and position of the stack structure 2;

[0118] S322: Etching the epitaxial material stack 2a based on the protective layer 4 to obtain the stack structure 2; the width of the first end structure 21, the width of the second end structure 23 and the width of the channel layer 22 are all the same, and the side walls of the first end structure 21, the side walls of the second end structure 23 and the side walls of the channel layer 22 are all flush.

[0119] Please refer to Fig. 9 and Fig.10 In some embodiments, after step S32, the method further includes:

[0120] S41: Fig. 9 As shown, an initial isolation layer 61 is formed on the substrate 1, and the initial isolation layer 61 surrounds the stacked structure 2;

[0121] S42: Fig.10 As shown, the initial isolation layer 61 is etched back to obtain the isolation layer 6 , and the top surface of the isolation layer 6 is flush with the top surface of the first end structure 21 .

[0122] Illustratively, the isolation layer 6 includes a silicon nitride layer.

[0123] Please refer to Figures 11 to 13 In some embodiments, step S50, forming a gate structure 3, wherein the gate structure 3 surrounds the channel layer 22, includes:

[0124] S51: Fig.11 As shown, a gate dielectric material layer 31a is formed, and the gate dielectric material layer 31a conformally covers the exposed surface of the substrate 1, the sidewalls of the stacked structure 2, and the outer surface of the protective layer 4;

[0125] S52: Fig.12 As shown, the gate dielectric material layer 31a located on the surface of the substrate 1 is removed, and a gate conductive material layer 32a is formed, wherein the gate conductive material layer 32a conformally covers the exposed surface of the substrate 1 and the outer surface of the retained gate dielectric material layer 31a;

[0126] S53: Fig.13 As shown, the gate conductive material layer 32a located on the surface of the substrate 1 is etched, and the gate dielectric material layer 31a and the gate conductive material layer 32a located on the sidewall of the stacked structure 2 and the outer surface of the protective layer 4 are etched to obtain the gate dielectric layer 31 and the gate conductive layer 32.

[0127] By way of example, the material of the gate dielectric layer 31 may be a high-K dielectric material. It will be understood that the high-K dielectric material is a dielectric material having a dielectric constant greater than 3.9. For example, the material of the gate dielectric layer 31 includes at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0128] By way of example, the material of the gate conductive layer 32 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. By way of example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0129] Please refer to Fig.14 In some embodiments, after step S53, the method further includes:

[0130] S60 : forming an oxide layer 7 on the surface of the isolation layer 6 , the oxide layer 7 surrounds the second terminal structure 23 and the gate structure 3 , and the top surface of the oxide layer 7 is parallel to the top surface of the protection layer 4 .

[0131] Illustratively, the oxide layer 7 includes a silicon oxide layer.

[0132] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiments, Figures 15 to 23 Understand other embodiments of the present application.

[0133] Please refer to Fig.15 In step S31, an epitaxial material stack 2a is formed on the substrate 1, which is similar to the implementation in the aforementioned embodiment and will not be described again here.

[0134] In some embodiments, the channel layer includes a silicon germanium layer;

[0135] Please refer to Figure 16 to Figure 17 In an embodiment where the channel layer includes a germanium silicon layer, step S32, etching the epitaxial material stack 2a to obtain a stacked structure 2 including a first end epitaxial layer 211, a first end barrier layer 212, a channel layer 22, a second end barrier layer 232 and a second end epitaxial layer 231 stacked sequentially from bottom to top, including:

[0136] S323: Fig.16 As shown, a protective layer 4 is formed on the upper surface of the epitaxial material stack 2a, and the protective layer 4 defines the shape and position of the stack structure 2;

[0137] S324: Fig.16 As shown, the epitaxial material stack 2a is etched based on the protective layer 4 to obtain a first end epitaxial layer 211, a first end barrier layer 212, an initial channel layer 221, a second end barrier layer 232 and a second end epitaxial layer 231;

[0138] S325: Fig.17 As shown, the initial channel layer 221 is selectively etched to obtain the channel layer 22 , and a groove 222 is formed at the periphery of the channel layer 22 ; the gate structure 3 is formed in the groove 222 .

[0139] Please refer to Fig.18 In some embodiments, after forming the stacked structure 2 on the substrate 1, step S32 further includes:

[0140] S40 : forming a cap layer 5 in the groove 222 , wherein the cap layer 5 surrounds the surface of the channel layer 22 .

[0141] Please refer to Figures 19 to 22 In some embodiments, step S50, forming a gate structure 3, the gate structure 3 surrounds the channel layer 22 and surrounds the surface of the cap layer 5, including:

[0142] S51: Fig.19 As shown, a gate dielectric material layer 31a is formed, and the gate dielectric material layer 31a conformally covers the groove 222, the exposed surface of the substrate 1, the sidewall of the stacked structure 2, and the outer surface of the protective layer 4;

[0143] S52: Fig. 20 As shown, the gate dielectric material layer 31a outside the groove 222 is removed to form a gate dielectric layer 31, and the gate dielectric layer 31 surrounds the cap layer 5;

[0144] S53: Fig.21 As shown, a gate conductive material layer 32a is formed on the surface of the substrate 1, and the gate conductive material layer 32a fills the groove 222 and surrounds the stacked structure 2;

[0145] S54: Fig. 22 As shown, the gate conductive material layer 32 a outside the groove 222 is removed to obtain the gate conductive layer 32 .

[0146] Please refer to Fig.23 In some embodiments, after step S54, the method further includes:

[0147] S60 : forming an oxide layer 7 on the surface of the substrate 1 , wherein the oxide layer 7 surrounds the stacked structure 2 and the gate structure 3 , and a top surface of the oxide layer 7 is parallel to a top surface of the protection layer 4 .

[0148] In some embodiments, a memory is provided, comprising the above-mentioned semiconductor structure.

[0149] In some embodiments, an electronic device is provided, including the above-mentioned memory. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device, or a smart mobile terminal. Since a memory with better performance and reliability is used, the electronic device of this embodiment has more beneficial performance and higher reliability.

[0150] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0151] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0152] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A stacked structure, located on the substrate, comprising a first end structure, a channel layer and a second end structure stacked in sequence from bottom to top; the first end structure comprises a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure comprises a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer; The gate structure surrounds the channel layer.

2. The semiconductor structure according to claim 1, characterized in that: The first terminal structure includes a drain, and the second terminal structure includes a source; or the first terminal structure includes a source, and the second terminal structure includes a drain.

3. The semiconductor structure according to claim 1, characterized in that: The first-end epitaxial layer and the second-end epitaxial layer both include phosphorus-doped silicon layers; the first-end barrier layer and the second-end barrier layer both include arsenic-doped silicon layers.

4. The semiconductor structure according to claim 1, characterized in that: Also includes: A protective layer is located on the upper surface of the stacked structure.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The channel layer includes an intrinsic silicon layer; the width of the first end structure, the width of the second end structure and the width of the channel layer are all the same, and the sidewall of the first end structure, the sidewall of the second end structure and the sidewall of the channel layer are all flush.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The channel layer includes a germanium silicon layer; the sidewall of the first end structure, the sidewall of the second end structure, and the sidewall of the gate structure away from the channel layer are all flush.

7. The semiconductor structure according to claim 6, characterized in that: Also includes: A cap layer surrounds the surface of the channel layer; and the gate structure surrounds the surface of the cap layer.

8. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A stacked structure is formed on the substrate, the stacked structure comprising a first end structure, a channel layer and a second end structure stacked in sequence from bottom to top; the first end structure comprises a first end epitaxial layer and a first end barrier layer, the first end epitaxial layer is located between the channel layer and the substrate, and the first end barrier layer is located between the first end epitaxial layer and the channel layer; the second end structure comprises a second end epitaxial layer and a second end barrier layer, the second end epitaxial layer is located on the channel layer, and the second end barrier layer is located between the second end epitaxial layer and the channel layer; A gate structure is formed, wherein the gate structure surrounds the channel layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: A stacked structure is formed on the substrate, comprising: Forming an epitaxial material stack on the substrate, wherein the epitaxial material stack includes a first end epitaxial material layer, a first end barrier material layer, a channel material layer, a second end barrier material layer and a second end epitaxial material layer stacked in sequence from bottom to top; The epitaxial material stack is etched to obtain the stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The channel layer includes an intrinsic silicon layer; the epitaxial material stack is etched to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top, including: forming a protective layer on the upper surface of the epitaxial material stack, wherein the protective layer defines the shape and position of the stack structure; The epitaxial material stack is etched based on the protective layer to obtain the stacked structure; the width of the first end structure, the width of the second end structure and the width of the channel layer are all the same, and the side walls of the first end structure, the side walls of the second end structure and the side walls of the channel layer are all flush.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that: The channel layer includes a germanium silicon layer; the epitaxial material stack is etched to obtain a stacked structure including a first end epitaxial layer, a first end barrier layer, a channel layer, a second end barrier layer and a second end epitaxial layer stacked in sequence from bottom to top, including: forming a protective layer on the upper surface of the epitaxial material stack, wherein the protective layer defines the shape and position of the stack structure; Etching the epitaxial material stack based on the protective layer to obtain the first end epitaxial layer, the first end barrier layer, the initial channel layer, the second end barrier layer and the second end epitaxial layer; The initial channel layer is selectively etched to obtain the channel layer, and a groove is formed at the periphery of the channel layer; the gate structure is formed in the groove.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: After forming the stacked structure on the substrate and before forming the gate structure, the method further includes: A cap layer is formed in the groove, and the cap layer surrounds the surface of the channel layer; and the gate structure surrounds the surface of the cap layer.

13. A memory, characterized in that: include: A semiconductor structure as claimed in any one of claims 1 to 6.

14. An electronic device, characterized in that: include: The memory as claimed in claim 13.

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