Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for improving the yield and the working performance of a ring gate transistor. The semiconductor device includes a semiconductor substrate, and a first transistor disposed on the semiconductor substrate. A channel region of the first transistor comprises a first nano structure and a second nano structure which are made of different materials, the first nano structure and the second nano structure are alternately distributed in the thickness direction of the semiconductor substrate, and the structure, located on the bottom layer, in the channel region of the first transistor is the first nano structure. Along the length direction of the gate stack structure of the first transistor, the width of the first nano-structure is smaller than that of the second nano-structure, and the second nano-structure is at least arranged between two adjacent layers of first nano-structures. A first nano-structure located at the bottom layer in a channel region of the first transistor and the semiconductor substrate are arranged at an interval; alternatively, the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when all transistors in a semiconductor device are GMT-A, it is beneficial to improve the operating performance of the semiconductor device.

[0003] However, the yield of gate-around transistors manufactured using existing methods is low, and the performance of gate-around transistors is poor. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the yield and performance of gate-around transistors.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor device comprising: a semiconductor substrate, and a first transistor disposed on the semiconductor substrate. The channel region of the first transistor includes first nanostructures and second nanostructures made of different materials, the first nanostructures and second nanostructures being alternately distributed along the thickness direction of the semiconductor substrate, and the structure located at the bottom layer in the channel region of the first transistor is the first nanostructure. Each layer of first nanostructure and each layer of second nanostructure in the first transistor are in contact with a source region and a drain region, respectively. Along the length direction of the gate stack structure of the first transistor, the width of the first nanostructure is smaller than the width of the second nanostructure, and the second nanostructure is disposed at least between two adjacent layers of first nanostructure. Wherein, the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, and the gate stack structure of the first transistor surrounds the outer periphery of the channel region; or, the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, and the gate stack structure of the first transistor covers the outer periphery of the channel region.

[0006] In the above-described technical solution, the channel region of the first transistor disposed on the semiconductor substrate not only has a first nanostructure with a relatively large width, but also has a second nanostructure with a smaller width between at least two adjacent first nanostructures. In this case, during actual manufacturing, even if the length of the gate stack structure included in the first transistor is large, resulting in a large aspect ratio of the first nanostructure, the presence of the second nanostructure can provide support after releasing part of the width of the first nanostructure, preventing the first nanostructure from bending or breaking due to insufficient support, thus improving the yield of the semiconductor device. Furthermore, because the second nanostructure is smaller, the gate stack structure included in the first transistor can cover the outer periphery of the portion of the first nanostructure that is wider than the second nanostructure. Therefore, compared to conventional fin field-effect transistors, the first transistor in the semiconductor device provided by this invention has a relatively higher gate control capability. Secondly, compared to conventional gate-to-ring transistors, because both the first and second nanostructures in the channel region of the semiconductor device provided by this invention can contact the source and drain regions, the conduction area of ​​the channel region can be increased. Therefore, the first transistor has a relatively large driving performance, which is beneficial for improving the operating performance of the semiconductor device.

[0007] In one example, when the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, the distance between the first nanostructure located at the bottom layer and the semiconductor substrate is greater than or equal to the thickness of the second nanostructure.

[0008] In one example, where the first nanostructure at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, the material of the first nanostructure at the bottom layer is different from the material of the rest of the first nanostructure.

[0009] In one example, where the first nanostructure at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, the thickness of the first nanostructure at the bottom layer is greater than or equal to the thickness of the other first nanostructures.

[0010] In one example, the width of at least one second nanostructure is greater than the width of the second nanostructure located on top of itself along the thickness direction of the semiconductor substrate, and the width direction of the second nanostructure is parallel to the length direction of the gate stack structure included in the first transistor.

[0011] In one example, the material of at least one layer of the second nanostructure is different from the material of the second nanostructure located on top of itself along the thickness direction of the semiconductor substrate.

[0012] In one example, the material of the first nanostructure includes Si. 1-x Ge x The materials for the second nanostructure include Si.1- y Ge y Where 0≤x≤1, 0≤y≤1, and |xy|≥0.1.

[0013] In one example, the aspect ratio of the first nanostructure is greater than or equal to 3 and less than or equal to 10.

[0014] In one example, the aspect ratio of the second nanostructure is greater than or equal to 6 and less than or equal to 30.

[0015] In one example, the ratio of the width of the first nanostructure to the width of the second nanostructure is greater than or equal to 2 and less than or equal to 5.

[0016] In one example, the longitudinal cross-sectional shape of the first nanostructure and / or the second nanostructure is quasi-square, quasi-circular, or quasi-triangular.

[0017] In one example, the semiconductor device further includes a second transistor disposed on a semiconductor substrate. The first and second transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate. The second transistor is a gate-ring transistor.

[0018] In one example, the first transistor is of P-type conductivity.

[0019] In one example, the length of the gate stack structure of the first transistor is greater than the length of the gate stack structure of the second transistor.

[0020] Secondly, the present invention provides a method for manufacturing a semiconductor device, the method comprising: first, providing a semiconductor substrate; next, forming a first transistor on the semiconductor substrate. The channel region of the first transistor includes a first nanostructure and a second nanostructure made of different materials, the first nanostructure and the second nanostructure being alternately distributed along the thickness direction of the semiconductor substrate, and the structure located at the bottom layer in the channel region of the first transistor being the first nanostructure. Each layer of the first nanostructure and each layer of the second nanostructure in the first transistor are in contact with the source region and the drain region, respectively. Along the length direction of the gate stack structure of the first transistor, the width of the first nanostructure is smaller than the width of the second nanostructure, and the second nanostructure is disposed at least between two adjacent layers of the first nanostructure. Wherein, the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, and the gate stack structure of the first transistor surrounds the outer periphery of the channel region. Alternatively, the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, and the gate stack structure of the first transistor covers the outer periphery of the channel region.

[0021] In one example, forming a first transistor on a semiconductor substrate includes: forming a first fin structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the first fin structure includes a first semiconductor layer and second and third semiconductor layers alternately disposed on the first semiconductor layer. Of the alternately disposed second and third semiconductor layers, the underlying film layer is the second semiconductor layer. Next, a mask structure is formed across the first fin structure. Next, the portion of the first fin structure exposed outside the mask structure is processed to form the source and drain regions included in the first transistor. Next, at least a portion of the mask structure is removed. Next, the remaining first semiconductor layer is removed, and along the length direction of the gate stack structure included in the first transistor, the side edge portions of the remaining third semiconductor layer are removed, so that the remaining third semiconductor layer forms a second nanostructure, and the remaining second semiconductor layer forms a first nanostructure; or, along the length direction of the gate stack structure included in the first transistor, the side edge portions of the remaining second semiconductor layer are removed, so that the remaining second semiconductor layer forms a second nanostructure, and the remaining first and third semiconductor layers form a first nanostructure.

[0022] In one example, when the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, the material of the first semiconductor layer and the material of the third semiconductor layer are the same, and the thickness of the first semiconductor layer is greater than the thickness of the third semiconductor layer; or, the material of the first semiconductor layer and the material of the third semiconductor layer are different, and the thickness of the first semiconductor layer is greater than or equal to the thickness of the third semiconductor layer.

[0023] In one example, after providing a semiconductor substrate, the method of manufacturing a semiconductor device further includes: forming a second transistor disposed on the semiconductor substrate. The first transistor and the second transistor are spaced apart along a direction parallel to the surface of the semiconductor substrate. The second transistor is a gate-ring transistor.

[0024] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0026] Figure 1 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 1 ;

[0027] Figure 2A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ;

[0028] Figure 3 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 3 ;

[0029] Figure 4 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 4 ;

[0030] Figure 5 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 5 ;

[0031] Figure 6 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 6 ;

[0032] Figure 7 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 7 ;

[0033] Figure 8 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 8 ;

[0034] Figure 9 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 9 ;

[0035] Figure 10 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 ;

[0036] Figure 11 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 one;

[0037] Figure 12 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 two;

[0038] Figure 13 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 three;

[0039] Figure 14 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Four;

[0040] Figure 15 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 five;

[0041] Figure 16 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 six;

[0042] Figure 17 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 seven;

[0043] Figure 18 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 eight;

[0044] Figure 19 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Nine;

[0045] Figure 20 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ten;

[0046] Figure 21 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 eleven;

[0047] Figure 22 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 twelve.

[0048] Reference numerals: 11 is a semiconductor substrate, 12 is a first transistor, 13 is a channel region, 14 is a first nanostructure, 15 is a second nanostructure, 16 is a gate stack structure, 17 is a source region, 18 is a drain region, 19 is a second transistor, 20 is a shallow trench isolation structure, 21 is a gate sidewall, 22 is an interlayer dielectric layer, 23 is a first fin structure, 24 is a first semiconductor layer, 25 is a second semiconductor layer, 26 is a third semiconductor layer, 27 is a mask structure, and 28 is a second fin structure. Detailed Implementation

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0050] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0051] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0053] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when all transistors in a semiconductor device are GMT-A, it is beneficial to improve the operating performance of the semiconductor device.

[0055] However, the crystal orientation of the channel in existing gate-around transistors is typically

[100] . Furthermore, when the gate length of a gate-around transistor is large, the aspect ratio of each nanostructure layer within the channel is also large. In this case, during actual manufacturing, when removing the sacrificial gate and releasing the channel region by removing the sacrificial layer, the large aspect ratio and suspended nanostructures are prone to collapse, leading to problems such as nanostructure breakage or adhesion between adjacent nanostructure layers. In other words, the yield of gate-around transistors formed using existing manufacturing methods is low, and the operating performance of gate-around transistors is poor.

[0056] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, a narrower second nanostructure is disposed between at least two adjacent first nanostructure layers to improve the yield and performance of the semiconductor device.

[0057] Specifically, in a first aspect, embodiments of the present invention provide a semiconductor device. For example... Figures 18 to 21 As shown, the semiconductor device provided in this embodiment of the invention includes: a semiconductor substrate 11, and a first transistor 12 disposed on the semiconductor substrate 11. The channel region 13 of the first transistor 12 includes a first nanostructure 14 and a second nanostructure 15 made of different materials. The first nanostructure 14 and the second nanostructure 15 are alternately distributed along the thickness direction of the semiconductor substrate 11, and the structure located at the bottom layer of the channel region 13 of the first transistor 12 is the first nanostructure 14. Each layer of the first nanostructure 14 and each layer of the second nanostructure 15 in the first transistor 12 are in contact with the source region 17 and the drain region 18, respectively. Along the length direction of the gate stack structure 16 of the first transistor 12, the width of the first nanostructure 14 is smaller than the width of the second nanostructure 15, and the second nanostructure 15 is disposed at least between two adjacent layers of the first nanostructure 14. In this configuration, the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is spaced apart from the semiconductor substrate 11, and the gate stack structure 16 of the first transistor 12 surrounds the outer periphery of the channel region 13; or, the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is in direct contact with the semiconductor substrate 11, and the gate stack structure 16 of the first transistor 12 covers the outer periphery of the channel region 13.

[0058] When the above technical solution is adopted, such as Figures 18 to 21As shown, the channel region 13 of the first transistor 12 disposed on the semiconductor substrate 11 not only has a first nanostructure 14 with a relatively large width, but also has a second nanostructure 15 with a smaller width between at least two adjacent layers of the first nanostructure 14. In this case, during the actual manufacturing process, even if the length of the gate stack structure 16 included in the first transistor 12 is large, resulting in a large aspect ratio of the first nanostructure 14, the presence of the second nanostructure 15 can provide support after releasing part of the width of the first nanostructure 14, preventing the first nanostructure 14 from bending or breaking due to insufficient support, thereby improving the yield of the semiconductor device. In addition, because the width of the second nanostructure 15 is small, the gate stack structure 16 included in the first transistor 12 can cover the outer periphery of the portion of the first nanostructure 14 that is wider than the second nanostructure 15. Therefore, compared with conventional fin field-effect transistors, the first transistor 12 in the semiconductor device provided by the embodiment of the present invention has a relatively high gate control capability. Secondly, compared with conventional gate-around transistors, in the semiconductor device provided by the embodiments of the present invention, the first nanostructure 14 and the second nanostructure 15 in the channel region 13 can both contact the source region 17 and the drain region 18, which can increase the conduction area of ​​the channel region 13. Therefore, the first transistor 12 has relatively large driving performance, which is beneficial to improving the working performance of the semiconductor device.

[0059] In practical applications, the specific structure of the aforementioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in this embodiment of the invention can be a silicon, germanium-silicon, germanium, or other semiconductor substrate without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate with some structure formed. For example, when the first transistor in this embodiment of the invention is a transistor in the second or higher layer of a semiconductor device, the semiconductor substrate includes a semiconductor structure located below the first transistor, etc.

[0060] In terms of conductivity type, the first transistor can be either N-type or P-type. However, the channel orientation of existing gate-ring transistors is typically

[100] . In this case, the channel of the gate-ring transistor is advantageous for electron transport but disadvantageous for hole transport. Furthermore, the channel carriers of an N-type transistor are electrons, while those of a P-type transistor are holes. Therefore, when a gate ring transistor including a

[100] crystal orientation channel is applied to the aforementioned N-type transistor, the gate ring transistor is beneficial for improving the electron mobility of the N-type transistor, which can significantly improve the working performance of the N-type transistor. However, when a gate ring transistor including a

[100] crystal orientation channel is applied to the aforementioned P-type transistor, the gate ring transistor is not beneficial for improving the hole mobility of the P-type transistor. Therefore, the improvement in the working performance of the P-type transistor is not ideal. Thus, when the conductivity type of the first transistor in the semiconductor device provided in this embodiment of the invention is P-type, it can not only prevent the first nanostructure in the P-type transistor from bending or breaking due to insufficient support, but also increase the conduction area of ​​the channel region of the P-type transistor, thereby improving the driving performance of the P-type transistor.

[0061] From a structural perspective, such as Figures 12 to 21 As shown, in the first transistor 12, the channel region 13 is located between the source region 17 and the drain region 18, and both ends of the channel region 13 along its own length direction (the length direction of the channel region 13 is parallel to the length direction of the gate stack structure 16) are in contact with the source region 17 and the drain region 18, respectively. Specifically, each layer of the first nanostructure 14 and each layer of the second nanostructure 15 in the first transistor 12 are in contact with the source region 17 and the drain region 18, respectively.

[0062] The placement of the narrower second nanostructure can be determined based on the actual manufacturing process; no specific limitation is made here, as long as the first and second nanostructures are alternately distributed along the thickness direction of the semiconductor substrate, and the first nanostructure is located at the bottom layer of the channel region of the first transistor. For example... Figure 18 and Figure 21 As shown, in the channel region 13 included in the first transistor 12, the second nanostructure 15 may be located only between two adjacent layers of the first nanostructure 14. Alternatively, as... Figure 19 and Figure 20 As shown, the second nanostructure 15 is not only located between two adjacent layers of the first nanostructure 14, but also disposed on the first nanostructure 14 located on the top layer.

[0063] As for the first nanostructure with a larger width, such as Figure 18 and Figure 20As shown, in the channel region 13 of the first transistor 12, the first nanostructure 14 located at the bottom layer is spaced apart from the semiconductor substrate 11. In this case, the gate stack structure 16 of the first transistor 12 can surround the outer periphery of the channel region 13 through the gap between the first nanostructure 14 located at the bottom layer and the semiconductor substrate 11. Alternatively, as... Figure 19 and Figure 21 As shown, the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 can also be in direct contact with the semiconductor substrate 11. At this time, the gate stack structure 16 of the first transistor 12 can only cover the outer periphery of the channel region 13.

[0064] It is understandable that, such as Figure 18 and Figure 20 As shown, when the gate stack structure 16 surrounds the outer periphery of the channel region 13, the gate stack structure 16 has a strong control over the channel region 13, which is beneficial for suppressing the short-channel effect of the first transistor 12. Based on this, the positional relationship between the first nanostructure 14 located at the bottom layer in the channel region 13 and the semiconductor substrate 11 can be determined according to the requirements of the gate control capability of the first transistor 12 in the actual application scenario.

[0065] In terms of materials, the source and drain regions of the first transistor can be made of any semiconductor material such as silicon, silicon germanium, or germanium. The first and second nanostructures of the channel region can be made of any two different semiconductor materials.

[0066] For example, the material of the first nanostructure includes Si. 1-x Ge x The materials for the second nanostructure include Si. 1-y Ge y Where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and |xy| ≥ 0.1. In this case, the germanium content in the material of the first nanostructure can be higher or lower. The germanium content in the first and second nanostructures can be determined based on the channel structure and the conductivity type of the first transistor, and is not specifically limited here. Optionally, when the conductivity type of the first transistor is P-type, the germanium content in the first nanostructure material can be higher than that in the second nanostructure material (e.g., the material of the first nanostructure may include Ge, Si). 0.1 Ge 0.9 Si 0.2 Ge 0.8 Si 0.3 Ge 0.7 or Si 0.4 Ge 0.6 Materials for the second nanostructure may include: Si, Si 0.9 Ge 0.1 Si0.8 Ge 0.2 Si 0.7 Ge 0.3 or Si 0.6 Ge 0.4 (etc.). Optionally, when the first transistor is of N-type conductivity, the germanium content in the second nanostructure material may be higher than the germanium content in the first nanostructure material (e.g., the material of the first nanostructure may include: Si, Si...). 0.9 Ge 0.1 Si 0.8 Ge 0.2 Si 0.7 Ge 0.3 or Si 0.6 Ge 0.4 Materials for the second nanostructure may include: Ge, Si 0.1 Ge 0.9 Si 0.2 Ge 0.8 Si 0.3 Ge 0.7 or Si 0.4 Ge 0.6 (etc.). As for the difference in germanium content between the first and second nanostructures, it can be determined according to the actual application scenario, and no specific limitation is made here.

[0067] Specifically, the materials of the different layers of the first nanostructure can be the same or different. When the materials of the different layers of the first nanostructure are the same, it reduces the types of different semiconductor materials used in the channel region, lowers the limitation on critical epitaxial thickness, and reduces the difficulty of the manufacturing process. When the materials of the different layers of the first nanostructure are different, at least one layer of the first nanostructure can have a higher carrier mobility than the layer above it, along the direction closest to the semiconductor substrate. In this case, the lower layer of the first nanostructure also has higher conductivity, improving the conductivity uniformity between the different layers of the first nanostructure.

[0068] For example, when the first transistor includes three layers of first nanostructures, the carrier mobility of the material in the bottom first nanostructure can be greater than that of the material in the second first nanostructure.

[0069] For example: Figure 19 and Figure 21 As shown, when the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is in direct contact with the semiconductor substrate 11, the material of the first nanostructure 14 located at the bottom layer is different from the material of the other first nanostructures 14.

[0070] Secondly, the materials of the different layers of the second nanostructure can be the same or different. When the materials of the different layers of the second nanostructure are the same, it reduces the variety of semiconductor materials used in the channel region, lowers the limitation on critical epitaxial thickness, and reduces the difficulty of the manufacturing process. When the materials of the different layers of the first nanostructure are different, at least one layer of the second nanostructure can be made of a different material than the second nanostructure located above it along the thickness direction of the semiconductor substrate. This allows the conductivity of at least one layer of the second nanostructure to be greater than that of the second nanostructure located above it along the direction close to the semiconductor substrate. (This can be achieved by changing the material type to give the lower layer of the second nanostructure a higher carrier mobility, thereby improving its conductivity. Alternatively, it can be achieved by changing the material type to give the lower layer of the second nanostructure higher etch resistance, thus making the width of the lower layer of the second nanostructure greater than that of the upper layer, thereby increasing the conduction area of ​​the lower layer of the second nanostructure and improving its conductivity.)

[0071] When the materials of the first nanostructure and the second nanostructure in different layers are different, the materials of the first nanostructure and the second nanostructure in each layer can be determined according to the actual application scenario, and no specific limitation is made here.

[0072] Regarding the materials of the gate stack structure, the gate stack structure may include a gate dielectric layer and a gate. The gate dielectric layer is formed on the outer periphery of the channel region and covers the corresponding gate formation region of the semiconductor substrate. The gate is located on the gate dielectric layer. The material of the gate dielectric layer may be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate may be a conductive material such as TiN, TaN, or TiSiN.

[0073] In terms of size, along the length of the gate stack structure of the first transistor, the width of the first nanostructure is smaller than the width of the second nanostructure. The specific specifications of the first and second nanostructures, as well as the width difference between them, can be determined based on the size requirements of the first transistor in the actual application scenario, and the manufacturing requirements of the channel region in the first transistor; no specific limitations are made here.

[0074] For example, the aspect ratio of the first nanostructure can be greater than or equal to 3 and less than or equal to 10.

[0075] For example, the aspect ratio of the second nanostructure can be greater than or equal to 6 and less than or equal to 30.

[0076] For example, the ratio of the width of the first nanostructure to the width of the second nanostructure can be greater than or equal to 2 and less than or equal to 5.

[0077] Among them, such as Figures 18 to 22 As shown, the widths of the second nanostructures 15 located in different layers can be the same or different. When the widths of the second nanostructures 15 in different layers are different, at least one layer of the second nanostructure 15 may have a width greater than the width of the second nanostructure 15 located on top of it along the thickness direction of the semiconductor substrate 11, and the width direction of the second nanostructure 15 is parallel to the length direction of the gate stack structure 16 included in the first transistor 12. In this case, which specific layer of the second nanostructure 15 has a width greater than the width of the second nanostructure 15 located on top of it can be set according to actual needs and is not specifically limited here. For example, only the width of the second nanostructure 15 located at the bottom layer may be greater than the width of the second nanostructure 15 located on top of it. Or, as... Figure 22 As shown, the width of each second nanostructure 15 can also be greater than the width of the second nanostructure 15 located on top of itself.

[0078] In one example, such as Figure 18 and Figure 20 As shown, when the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is spaced apart from the semiconductor substrate 11, the distance between the first nanostructure 14 located at the bottom layer and the semiconductor substrate 11 can be greater than or equal to the thickness of the second nanostructure 15. The relationship between the distance between the first nanostructure 14 located at the bottom layer and the semiconductor substrate 11, and the thickness of the second nanostructure 15, can be determined based on the relationship between the material used to release the first semiconductor layer 24 forming the aforementioned distance and the material used to manufacture the third semiconductor layer 26 of the second nanostructure 15 during the actual manufacturing process. For example: Figures 1 to 17 As shown, when the material of the first semiconductor layer 24 is the same as that of the third semiconductor layer 26, the distance between the first nanostructure 14 located at the bottom layer and the semiconductor substrate 11 can be greater than the thickness of the second nanostructure 15, to ensure that the first semiconductor layer 24 can be completely removed during the etching process of the third semiconductor layer 26. Alternatively, when the material of the first semiconductor layer 24 is different from that of the third semiconductor layer 26, the distance between the first nanostructure 14 located at the bottom layer and the semiconductor substrate 11 can be greater than or equal to the thickness of the second nanostructure 15, so that at least through the difference in their materials, a difference in their etching rates is achieved, ensuring that the first nanostructure 14 located at the bottom layer is suspended above the semiconductor substrate 11.

[0079] In one example, such as Figures 19 to 21As shown, when the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is in direct contact with the semiconductor substrate 11, the thickness of the first nanostructure 14 located at the bottom layer is greater than or equal to the thickness of the other first nanostructures 14. The relationship between the thickness of the first nanostructure 14 located at the bottom layer and the thickness of the second nanostructure 15 can be set according to actual needs and is not specifically limited here.

[0080] In terms of morphology, the longitudinal cross-sectional shape of the first nanostructure and / or the second nanostructure is square, circular or triangular.

[0081] In one example, such as Figures 18 to 21 As shown, the semiconductor device may further include a second transistor 19 disposed on the semiconductor substrate 11. The first transistor 12 and the second transistor 19 are spaced apart along a direction parallel to the surface of the semiconductor substrate 11. The second transistor 19 is a gate-around transistor. In this case, the semiconductor device provided by the embodiments of the present invention can integrate a conventional gate-around transistor and the first transistor 12, improving the applicability of the semiconductor device provided by the embodiments of the present invention in different application scenarios.

[0082] The second transistor may include a source region, a drain region, a channel region, and a gate stack structure. The channel region is located between the source and drain regions and is adjacent to both the source and drain regions. The gate stack structure surrounds the outer periphery of each nanostructure layer included in the channel region. The materials of the source, drain, channel, and gate stack structures in the second transistor can be referenced to the materials of the source, drain, channel, and gate stack structures described above in the first transistor, and will not be repeated here.

[0083] Furthermore, the first and second transistors can have the same or different conductivity types. Secondly, the length of the gate stack structure of the first transistor can be greater than the length of the gate stack structure of the second transistor.

[0084] In one example, such as Figure 12 ,as well as Figures 18 to 21 As shown, the semiconductor device may further include gate sidewalls 21 located on both sides of the gate stack structure 16 along its length. Along the length of the gate stack structure 16, the gate sidewalls 21 span the two edge regions of the channel region 13 to isolate the gate stack structure 16 of the first transistor 12 (or the first transistor 12 and the second transistor 19) from other conductive structures, ensuring that the first transistor 12 has stable electrical characteristics.

[0085] In some cases, such as Figure 12 ,as well as Figures 18 to 21As shown, the semiconductor device provided in this embodiment of the invention may further include a shallow trench isolation structure 20 and / or an interlayer dielectric layer 22. The shallow trench isolation structure 20 is located on the semiconductor substrate 11 and is used to isolate different active regions of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 20 can be set according to actual conditions. The interlayer dielectric layer 22 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 16 included in the first transistor 12 (or the first transistor 12 and the second transistor 19), and is used to protect the source region 17 and drain region 18 included in the first transistor 12 (or the first transistor 12 and the second transistor 19) from the effects of etching and cleaning operations when removing the sacrificial gate.

[0086] The material of at least one of the above-mentioned gate sidewall, shallow trench isolation structure and interlayer dielectric layer can be insulating materials such as SiN, Si3N4, SiO2 or SiCO.

[0087] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 21 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0088] First, a semiconductor substrate is provided.

[0089] Next, as Figures 18 to 22 As shown, a first transistor 12 is formed on a semiconductor substrate 11. The channel region 13 of the first transistor 12 includes a first nanostructure 14 and a second nanostructure 15 made of different materials. The first nanostructure 14 and the second nanostructure 15 are alternately distributed along the thickness direction of the semiconductor substrate 11, and the structure located at the bottom layer in the channel region 13 of the first transistor 12 is the first nanostructure 14. Each layer of the first nanostructure 14 and each layer of the second nanostructure 15 in the first transistor 12 are in contact with the source region 17 and the drain region 18, respectively. Along the length direction of the gate stack structure 16 of the first transistor 12, the width of the first nanostructure 14 is smaller than the width of the second nanostructure 15, and the second nanostructure 15 is disposed at least between two adjacent layers of the first nanostructure 14. The first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is spaced apart from the semiconductor substrate 11, and the gate stack structure 16 of the first transistor 12 surrounds the outer periphery of the channel region 13. Alternatively, the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor 12 is in direct contact with the semiconductor substrate 11, and the gate stack structure 16 of the first transistor 12 covers the outer periphery of the channel region 13.

[0090] The structure and materials of the semiconductor substrate, as well as the structure, materials, and specifications of the first transistor, can be referred to in the preceding text and will not be repeated here.

[0091] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0092] In an actual manufacturing process, for example, forming a first transistor on a semiconductor substrate may include the following steps:

[0093] like Figures 1 to 5 As shown, a first fin structure 23 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the first fin structure 23 includes a first semiconductor layer 24, and a second semiconductor layer 25 and a third semiconductor layer 26 alternately disposed on the first semiconductor layer 24. Among the alternately disposed second semiconductor layer 25 and third semiconductor layer 26, the film layer located at the bottom is the second semiconductor layer 25.

[0094] The materials and number of layers of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer included in the above-mentioned fin structure can be determined according to the specific structure of the first transistor manufactured based on the first fin structure, and are not specifically limited here.

[0095] When the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, the second semiconductor layer is used to fabricate the first nanostructure. Therefore, the material and thickness of the second semiconductor layer, as well as the number of first nanostructure layers included in the channel region, can be determined based on the material and thickness of the first nanostructure and the number of second semiconductor layers included in the first fin structure. The third semiconductor layer is used to fabricate the second nanostructure. Therefore, the material and thickness of the third semiconductor layer, as well as the number of second nanostructure layers included in the channel region, can be determined based on the material and thickness of the second nanostructure and the number of third semiconductor layers included in the first fin structure. Furthermore, the first semiconductor layer is used to release the gap between the first nanostructure located at the bottom layer and the semiconductor substrate. Therefore, the thickness of the first semiconductor layer can be determined based on the height requirement of this gap in the actual application scenario. Additionally, the material of the first semiconductor layer can be the same as or different from the material of the third semiconductor layer. Specifically, when the materials of the first and third semiconductor layers are the same, the thickness of the first semiconductor layer is greater than the thickness of the third semiconductor layer to ensure that the first semiconductor layer is completely removed while a portion of the width of the third semiconductor layer is removed to form the second nanostructure. Alternatively, when the materials of the first semiconductor layer and the third semiconductor layer are different, the thickness of the first semiconductor layer can be greater than or equal to the thickness of the third semiconductor layer.

[0096] The difference in thickness between the first and third semiconductor layers can be determined based on the actual application scenario, as long as it allows the first nanostructure located at the bottom layer to be suspended on the semiconductor substrate.

[0097] When the first nanostructure at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, the second semiconductor layer is used to fabricate the second nanostructure. Therefore, the material and thickness of the second semiconductor layer, and the number of second semiconductor layers included in the first fin structure, can be determined based on the material and thickness of the second nanostructure, the number of second nanostructure layers in the channel region, and the number of third semiconductor layers included in the first fin structure. The first and third semiconductor layers are used to fabricate the first nanostructure, and thus, the material and thickness of the first and third semiconductor layers, and the number of third semiconductor layers included in the first fin structure, can be determined based on the material and thickness of the first nanostructure, the number of first nanostructure layers in the channel region, and the number of third semiconductor layers included in the first fin structure. Specifically, the first semiconductor layer is used to fabricate the first nanostructure at the bottom layer, and the third semiconductor layer is used to fabricate the remaining layers of the first nanostructure. Furthermore, the material of the first semiconductor layer can be the same as or different from the material of the third semiconductor layer. The thickness of the first semiconductor layer can be the same as or different from the thickness of the third semiconductor layer.

[0098] In the actual manufacturing process, such as Figure 1 and Figure 2 As shown, a first semiconductor layer 24, a second semiconductor layer 25, and a third semiconductor layer 26 can be formed on the semiconductor substrate 11 using processes such as epitaxy. Then, as... Figure 3 and Figure 4 As shown, photolithography and etching processes can be used to etch at least the first semiconductor layer 24, the second semiconductor layer 25, and the third semiconductor layer 26. If the manufactured semiconductor device also includes a shallow trench isolation structure 20, additional etching is required to further etch down the semiconductor substrate 11 to form the fins. Next, as... Figure 5 As shown, a shallow trench isolation structure 20 is formed on a semiconductor substrate 11 using processes such as deposition and etching. The material of this shallow trench isolation structure 20 can be found previously. Furthermore, the top height of the shallow trench isolation structure 20 is less than or equal to the bottom height of the first semiconductor layer 24, and the portion of the fin exposed outside the shallow trench isolation structure 20 constitutes the first fin structure 23. Alternatively, if the manufactured semiconductor device does not include the aforementioned shallow trench isolation structure, the first fin structure can be obtained simply by etching the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

[0099] It should be noted that if the manufactured semiconductor device also includes a second transistor, the same manufacturing process can be used simultaneously with the manufacturing of the first fin structure, and a second fin structure can be additionally formed based on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. This second fin structure has the same specific structure as the first fin structure. Alternatively, the second fin structure can be additionally manufactured using processes such as deposition and etching before or after the manufacturing of the first fin structure.

[0100] Next, as Figures 6 to 8 As shown, a mask structure 27 is formed across the first fin structure 23.

[0101] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, photolithography and etching processes are used to selectively etch the mask material to form the aforementioned mask structure. The material of the mask structure can be selected according to actual needs, as long as it can provide subsequent mask protection.

[0102] For example, the mask structure described above may include a sacrificial gate. The material of the sacrificial gate may include an easily removable material such as polysilicon. Secondly, the mask structure may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include a material such as silicon oxide. Additionally, the mask structure may also include a sacrificial gate and gate sidewalls located at least on both sides of the sacrificial gate along its length.

[0103] Secondly, such as Figure 7 As shown, if the length of the gate stack structure of the second transistor in the manufactured semiconductor device is less than the length of the gate stack structure of the first transistor, then the length of the mask structure 27 spanning the first fin structure 23 is greater than the length of the mask structure 27 spanning the second fin structure 28. Figure 6 As shown, if the length of the gate stack structure of the second transistor in the manufactured semiconductor device is equal to the length of the gate stack structure of the first transistor, then the length of the mask structure 27 spanning the first fin structure 23 is also equal to the length of the mask structure 27 spanning the second fin structure 28.

[0104] Next, as Figure 9 and Figure 10 As shown, the portion of the first fin structure exposed outside the mask structure 27 is processed to form the source region 17 and drain region 18 included in the first transistor 12.

[0105] In the actual manufacturing process, processes such as ion implantation can be used to directly dope the portion of the first fin structure exposed outside the mask structure to form the source and drain regions of the first transistor. Alternatively, processes such as wet etching or dry etching can be used to selectively remove the portion of the first fin structure exposed outside the mask structure; then, epitaxial growth processes can be used to form the source and drain regions of the first transistor on both sides of the remaining first fin structure.

[0106] It should be noted that if the manufactured semiconductor device also includes a second transistor, the formation process of the source and drain regions of the second transistor can refer to the formation process of the source and drain regions of the first transistor described above, and will not be repeated here. Furthermore, the formation order of the source and drain regions of the second transistor and the first transistor can be determined based on the conductivity type of the first and second transistors, the materials of their source and drain regions, and actual requirements; no specific limitations are made here. Specifically, when the conductivity type of the first and second transistors and the materials of their source and drain regions are the same, the same process can be used to simultaneously form the source and drain regions of both transistors to improve the manufacturing efficiency of the semiconductor device; alternatively, the source and drain regions of the first and second transistors can be formed separately. However, when the conductivity type of the first and second transistors is different, and / or the materials of their source and drain regions are different, under the protection of a corresponding mask, the source and drain regions of one of the first and second transistors must be formed first, followed by the source and drain regions of the other.

[0107] Next, as Figure 11 As shown, an interlayer dielectric layer 22 can be formed on the semiconductor substrate 11 using processes such as deposition and chemical mechanical polishing. The top of this interlayer dielectric layer 22 is flush with the top of the mask structure 27. The material of the interlayer dielectric layer 22 can be referred to the previous text and will not be repeated here.

[0108] Next, as Figure 12 As shown, dry etching or wet etching processes can be used to remove at least part of the mask structure.

[0109] Specifically, whether to remove the entire mask structure depends on its specific structure. For example, if the mask structure only includes the gate oxide layer and the sacrificial gate, then the entire mask structure needs to be removed. As another example, if the mask structure includes the sacrificial gate and the gate sidewall, then only the sacrificial gate needs to be removed, meaning only a portion of the mask structure needs to be removed.

[0110] Next, dry etching or wet etching processes can be used, such as... Figures 13 to 17 As shown, the remaining first semiconductor layer is removed, and along the length direction of the gate stack structure included in the first transistor, the two side edge portions of the remaining third semiconductor layer are removed, so that the remaining third semiconductor layer forms a second nanostructure 15, and the remaining second semiconductor layer forms a first nanostructure 14; or, along the length direction of the gate stack structure included in the first transistor, the two side edge portions of the remaining second semiconductor layer are removed, so that the remaining second semiconductor layer forms a second nanostructure 15, and the remaining first semiconductor layer and the remaining third semiconductor layer form a first nanostructure 14.

[0111] In the actual manufacturing process, after exposing the remaining first fin structure, the specific etching target can be determined based on the structure of the channel region included in the manufactured first transistor. Specifically, for example... Figure 14 and Figure 16 As shown, when the channel region 13 of the first transistor is suspended on the semiconductor substrate 11, the remaining first semiconductor layer needs to be removed, and the two side edge portions of the remaining third semiconductor layer are removed along the length direction of the gate stack structure of the first transistor, so that the remaining third semiconductor layer forms the second nanostructure 15, and the remaining second semiconductor layer forms the first nanostructure 14.

[0112] like Figure 15 and Figure 17 As shown, when the first nanostructure 14 located at the bottom layer in the channel region 13 of the first transistor is in direct contact with the semiconductor substrate 11, it is necessary to remove the two side edge portions of the remaining second semiconductor layer along the length direction of the gate stack structure included in the first transistor, so that the remaining second semiconductor layer forms the second nanostructure 15, and the remaining first semiconductor layer and the remaining third semiconductor layer form the first nanostructure 14.

[0113] It should be noted that if the manufactured semiconductor device also includes a second transistor, then during the formation of the channel region included in the first transistor, a mask needs to be used to cover the remaining second fin structure to prevent the etchant from affecting the second fin structure. Similarly, during the formation of the channel region included in the second transistor, a mask also needs to be used to cover the outer periphery of the channel region included in the first transistor to prevent the etchant from affecting the outer periphery of the channel region included in the first transistor. Alternatively, the same method can be used, forming the channel region included in the second transistor first, and then forming the channel region included in the first transistor.

[0114] Next, as Figures 18 to 22 As shown, the gate stack structure 16 of the first transistor 12 can be formed using processes such as atomic layer deposition. The specific structure and materials of the gate stack structure 16 can be referred to the previous text, and will not be repeated here.

[0115] It should be noted that if the manufactured semiconductor device also includes a second transistor, the same manufacturing process can be used to simultaneously form the gate stack structure included in the first transistor and the second transistor. When the materials or thicknesses of the gate stack structures of the first transistor and the second transistor are different, the gate stack structures included in the first transistor and the second transistor can be formed respectively under the protection of the corresponding masks.

[0116] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0117] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, and a first transistor disposed on the semiconductor substrate; The channel region of the first transistor includes a first nanostructure and a second nanostructure made of different materials, the first nanostructure and the second nanostructure are alternately distributed along the thickness direction of the semiconductor substrate, and the structure at the bottom layer in the channel region of the first transistor is the first nanostructure; each layer of the first nanostructure and each layer of the second nanostructure in the first transistor are in contact with the source region and the drain region respectively; Along the length direction of the gate stack structure of the first transistor, the width of the first nanostructure is smaller than the width of the second nanostructure, and the second nanostructure is at least arranged between two adjacent layers of the first nanostructure; Among them, the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, and the gate stack structure of the first transistor surrounds the periphery of the channel region; or, the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, and the gate stack structure of the first transistor covers the periphery of the channel region.

2. The semiconductor device according to claim 1, wherein: When the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, the distance between the first nanostructure located at the bottom layer and the semiconductor substrate is greater than or equal to the thickness of the second nanostructure.

3. The semiconductor device according to claim 1, wherein: In the case where the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, the material of the first nanostructure located at the bottom layer is different from the material of the remaining first nanostructures; And / or, when the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, the thickness of the first nanostructure located at the bottom layer is greater than or equal to the thickness of the remaining first nanostructures.

4. The semiconductor device according to claim 1, wherein: The width of at least one layer of the second nanostructure is greater than the width of the second nanostructure located on the upper layer thereof along the thickness direction of the semiconductor substrate, and the width direction of the second nanostructure is parallel to the length direction of the gate stack structure included in the first transistor; And / or, the material of at least one layer of the second nanostructure is different from the material of the second nanostructure located on the semiconductor substrate along the thickness direction of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein: The material of the first nanostructure includes Si 1- x Ge x , the material of the second nanostructure includes Si 1-y Ge y ; Among them, 0≤x≤1, 0≤y≤1, and |xy|≥0.

1.

6. The semiconductor device according to claim 1, wherein: The aspect ratio of the first nanostructure is greater than or equal to 3 and less than or equal to 10; And / or, the aspect ratio of the second nanostructure is greater than or equal to 6 and less than or equal to 30; And / or, a ratio of a width of the first nanostructure to a width of the second nanostructure is greater than or equal to 2 and less than or equal to 5; And / or, the longitudinal cross-section shape of the first nanostructure and / or the second nanostructure is square-like, circular-like or triangular-like.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a second transistor disposed on the semiconductor substrate; the first transistor and the second transistor are spaced apart and distributed in a direction parallel to the surface of the semiconductor substrate; The second transistor is a gate-all-around transistor.

8. The semiconductor device according to claim 7, characterized in that The conductivity type of the first transistor is P type; And / or, the length of the gate stack structure of the first transistor is greater than the length of the gate stack structure of the second transistor.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate; forming a first transistor on the semiconductor substrate; The channel region of the first transistor includes a first nanostructure and a second nanostructure made of different materials, the first nanostructure and the second nanostructure are alternately distributed along the thickness direction of the semiconductor substrate, and the structure at the bottom layer in the channel region of the first transistor is the first nanostructure; each layer of the first nanostructure and each layer of the second nanostructure in the first transistor are in contact with the source region and the drain region respectively; Along the length direction of the gate stack structure of the first transistor, the width of the first nanostructure is smaller than the width of the second nanostructure, and the second nanostructure is at least arranged between two adjacent layers of the first nanostructure; Among them, the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, and the gate stack structure of the first transistor surrounds the periphery of the channel region; or, the first nanostructure located at the bottom layer in the channel region of the first transistor is in direct contact with the semiconductor substrate, and the gate stack structure of the first transistor covers the periphery of the channel region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming the first transistor on the semiconductor substrate includes: A first fin-shaped structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the first fin-shaped structure includes a first semiconductor layer, and a second semiconductor layer and a third semiconductor layer alternately arranged on the first semiconductor layer; among the alternately arranged second semiconductor layers and the third semiconductor layers, the film layer located at the bottom is the second semiconductor layer; forming a mask structure spanning over the first fin-shaped structure; Processing a portion of the first fin structure exposed outside the mask structure to form a source region and a drain region included in the first transistor; removing at least a portion of the mask structure; The remaining first semiconductor layer is removed, and the side edge portions of the remaining third semiconductor layer are removed along the length direction of the gate stack structure included in the first transistor, so that the remaining third semiconductor layer forms the second nanostructure, and the remaining second semiconductor layer forms the first nanostructure; or, the side edge portions of the remaining second semiconductor layer are removed along the length direction of the gate stack structure included in the first transistor, so that the remaining second semiconductor layer forms the second nanostructure, and the remaining first semiconductor layer and the remaining third semiconductor layer form the first nanostructure.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: In the case where the first nanostructure located at the bottom layer in the channel region of the first transistor is spaced apart from the semiconductor substrate, The material of the first semiconductor layer is the same as that of the third semiconductor layer, and the thickness of the first semiconductor layer is greater than the thickness of the third semiconductor layer; Alternatively, a material of the first semiconductor layer is different from a material of the third semiconductor layer, and a thickness of the first semiconductor layer is greater than or equal to a thickness of the third semiconductor layer.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: After providing the semiconductor substrate, the method for manufacturing the semiconductor device further includes: A second transistor is formed and arranged on the semiconductor substrate; the first transistor and the second transistor are spaced apart and distributed along a direction parallel to the surface of the semiconductor substrate; and the second transistor is a ring-gate transistor.

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