Ring gate transistor and manufacturing method thereof

Abstract

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for enhancing the gate control capability of the gate-all-around transistor, reducing the electric leakage risk and improving the working performance of the gate-all-around transistor. The gate-all-around transistor comprises a semiconductor substrate, an active structure and a gate stack structure. The active structure is disposed on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region located between the source region and the drain region. The channel region includes at least one layer of nanostructure. Each layer of nano structure comprises at least two layers of semiconductor parts which are arranged at intervals along the thickness direction of the semiconductor substrate, and a medium part which is arranged between two adjacent layers of semiconductor parts. And the gate stack structure surrounds the periphery of each layer of nano structure. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gate-all-around transistor and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the ring-gate transistor has emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect.

[0003] However, as the gate length continues to shrink, the gate control capability of existing ring-gate transistors also tends to decline, resulting in an increased leakage risk of the ring-gate transistors, which is not conducive to improving the working performance of the ring-gate transistors. Summary of the invention

[0004] The object of the present invention is to provide a ring-gate transistor and a manufacturing method thereof, which are used to enhance the gate control capability of the ring-gate transistor, reduce the leakage risk, and improve the working performance of the ring-gate transistor.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a ring-gate transistor, which includes: a semiconductor substrate, an active structure and a gate stack structure. The active structure is arranged on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least one layer of nanostructure. Each layer of nanostructure includes at least two layers of semiconductor parts arranged at intervals along the thickness direction of the semiconductor substrate, and a dielectric part arranged between two adjacent layers of semiconductor parts. The gate stack structure surrounds the periphery of each layer of nanostructure.

[0006] In the case of adopting the above technical solution, in the ring-gate transistor provided by the present invention, the gate stack structure surrounds the periphery of each layer of the nanostructure. In addition, each layer of the nanostructure includes a dielectric portion arranged between two adjacent layers of semiconductor portions, and the dielectric portion is an insulating layer formed by manufacturing an insulating dielectric material. At this time, each layer of the nanostructure can form a structure similar to a "fully depleted silicon on insulator" type, so that the depletion layer fills the entire channel region, improves the gate control capability, increases the carriers, and improves the driving performance of the ring-gate transistor. In addition, the presence of the dielectric portion can also effectively inhibit the flow of electrons from the source to the drain, greatly reducing the leakage current that causes performance degradation, and meeting the need for further miniaturization of the gate length. In addition, when the thickness of the nanostructure is fixed, compared with the ring-gate transistor in which the nanostructure is manufactured by semiconductor materials in each region, the ring-gate transistor provided by the present invention can also improve the carriers in the nanostructure and improve the driving performance. Under the premise of not increasing the number of nanostructure stacking layers and the total stacking height, it is beneficial to reduce the process difficulty of manufacturing the ring-gate transistor, improve the yield of the semiconductor device, and the presence of the dielectric layer can also have greater immunity to process fluctuations, and improve the working performance of the ring-gate transistor.

[0007] In one example, the material of the dielectric portion is a low dielectric constant material.

[0008] In one example, the thickness of the dielectric portion is less than or equal to 5 nm.

[0009] In one example, along the length direction of the gate stack structure, in the same nanostructure, the width of the dielectric portion is less than or equal to the width of the semiconductor portion.

[0010] In one example, in the same nanostructure, a material of at least one semiconductor portion is different from materials of other semiconductor portions.

[0011] In an example, when the material of the semiconductor portion includes silicon, silicon germanium or germanium, in the same nanostructure, the difference in germanium content in the materials of different semiconductor portions is less than 10%.

[0012] In one example, in the channel region, different semiconductor parts included in different layers of nanostructures have different materials.

[0013] In an example, when the material of the semiconductor portion includes silicon, silicon germanium or germanium, the difference in germanium content in the materials of different semiconductor portions included in different layers of the nanostructure is less than 10%.

[0014] In one example, the thickness of the at least one semiconductor layer is greater than or equal to 2 nm and less than or equal to 10 nm.

[0015] In one example, in the same nanostructure, different semiconductor parts have the same thickness.

[0016] In a second aspect, the present invention provides a method for manufacturing a ring-gate transistor, the method for manufacturing a ring-gate transistor comprising: first, providing a semiconductor substrate. Next, forming an active structure on the semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least one layer of nanostructure. Each layer of nanostructure includes at least two layers of semiconductor portions spaced apart in a thickness direction of the semiconductor substrate, and a dielectric portion disposed between two adjacent layers of semiconductor portions. Next, forming a gate stack structure surrounding the periphery of each layer of nanostructure.

[0017] In one example, an active structure is formed on a semiconductor substrate, including: forming a fin structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes alternately arranged first sacrificial layers and semiconductor stacks. Among the alternately arranged first sacrificial layers and semiconductor stacks, the film layer located at the bottom is the first sacrificial layer. The semiconductor stack includes multiple semiconductor layers arranged at intervals, and a second sacrificial layer located between two adjacent semiconductor layers. Next, a mask structure is formed across the fin structure. Next, the portion of the fin structure exposed outside the mask structure is processed to form a source region and a drain region. Next, at least a portion of the mask structure is removed. Next, the remaining first sacrificial layer and the second sacrificial layer are removed so that the remaining semiconductor layer forms a semiconductor portion. Next, a dielectric portion is formed between two adjacent semiconductor portions.

[0018] In one example, forming a dielectric portion between two adjacent semiconductor portions includes: using a thermal oxidation process or an atomic layer deposition process to form a dielectric material that fills between the two adjacent semiconductor portions and covers the periphery of the semiconductor portion. Next, under the protection of the semiconductor portion, the portion of the dielectric material covering the periphery of the semiconductor portion is selectively removed to obtain the dielectric portion.

[0019] In one example, the thickness of the second sacrificial layer is less than the thickness of the first sacrificial layer.

[0020] In one example, when the material of one of the first sacrificial layer and the second sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content between the materials of the first sacrificial layer and the second sacrificial layer is greater than or equal to 10%.

[0021] In one example, when the material of one of the first sacrificial layer and the semiconductor layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content between the materials of the first sacrificial layer and the semiconductor layer is greater than or equal to 20%.

[0022] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0025] Figure 2 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0026] Figure 3 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0027] Figure 4 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 4 ;

[0028] Figure 5 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0029] Figure 6 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 6 ;

[0030] Figure 7 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 7 ;

[0031] Figure 8 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 8 ;

[0032] Fig. 9 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 9 ;

[0033] Fig.10 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 ;

[0034] Fig.11 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 one;

[0035] Fig.12 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 two;

[0036] Fig.13 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 three;

[0037] Fig.14 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Four;

[0038] Fig.15 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 five.

[0039] Figure numerals: 11 is a semiconductor substrate, 12 is a source region, 13 is a drain region, 14 is a nanostructure, 15 is a semiconductor part, 16 is a dielectric part, 17 is a gate stack structure, 18 is a shallow trench isolation structure, 19 is a gate sidewall, 20 is an interlayer dielectric layer, 21 is a fin structure, 22 is a first sacrificial layer, 23 is a semiconductor layer, 24 is a second sacrificial layer, 25 is a mask structure, and 26 is a dielectric material. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0041] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0042] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] With the development of semiconductor technology, the ring-gate transistor has emerged. Because the gate stack structure of the ring-gate transistor is not only formed on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has a stronger gate control capability, which is conducive to suppressing the short channel effect.

[0046] However, with the further miniaturization of the gate length, the gate control capability of the existing ring-gate transistor also has a downward trend, resulting in an increase in the leakage risk of the ring-gate transistor, which is not conducive to improving the working performance of the ring-gate transistor. In response to this technical problem, technicians in this field have improved the control ability of the gate stack structure over the channel region by simply increasing the number of stacked layers of nanostructures in the channel region or increasing the width of the nanostructure. However, the increase in the number of nanostructure layers will also cause the parasitic capacitance to increase, affecting the driving performance of the ring-gate transistor; and it will also cause the aspect ratio of the ring-gate transistor to increase, increasing the difficulty of the manufacturing process. The increase in the width of the nanostructure will also increase the difficulty of the release process of the nanostructure and reduce the yield of the ring-gate transistor.

[0047] In order to solve the above technical problems, the embodiment of the present invention provides a ring-gate transistor and a manufacturing method thereof. In the ring-gate transistor provided by the embodiment of the present invention, each layer of nanostructure includes a dielectric portion arranged between two adjacent layers of semiconductor portions, so that each layer of nanostructure can form a structure similar to a "fully depleted silicon-on-insulator" type, improve the gate control capability, increase the carriers, and enhance the driving performance of the ring-gate transistor.

[0048] Specifically, in a first aspect, an embodiment of the present invention provides a gate-all-around transistor. Figures 13 to 15 As shown, the ring-gate transistor includes: a semiconductor substrate 11, an active structure and a gate stack structure 17. The active structure is arranged on the semiconductor substrate 11. The active structure includes a source region 12, a drain region 13, and a channel region located between the source region 12 and the drain region 13. The channel region includes at least one layer of nanostructure 14. Each layer of nanostructure 14 includes at least two layers of semiconductor portions 15 spaced apart along the thickness direction of the semiconductor substrate 11, and a dielectric portion 16 arranged between two adjacent layers of semiconductor portions 15. The gate stack structure 17 surrounds the periphery of each layer of nanostructure 14.

[0049] When the above technical solution is adopted, Figures 13 to 15As shown, in the ring-gate transistor provided by the embodiment of the present invention, the gate stack structure 17 surrounds the periphery of each layer of nanostructure 14. In addition, each layer of nanostructure 14 includes a dielectric portion 16 disposed between two adjacent layers of semiconductor portions 15, and the dielectric portion 16 is an insulating layer formed by manufacturing an insulating dielectric material. At this time, each layer of nanostructure 14 can form a structure similar to a "fully depleted silicon on insulator" type, so that the depletion layer fills the entire channel region, improves the gate control capability, increases the carriers, and enhances the driving performance of the ring-gate transistor. In addition, the presence of the dielectric portion 16 can also effectively inhibit the flow of electrons from the source to the drain, greatly reducing the leakage current that causes performance degradation, and meeting the need for further miniaturization of the gate length. Moreover, when the thickness of the nanostructure 14 is fixed, compared with the ring-gate transistor in which each region of the nanostructure 14 is made of semiconductor materials, the ring-gate transistor provided by the embodiment of the present invention can also increase the carriers in the nanostructure 14 and improve the driving performance without increasing the number of stacking layers and the total stacking height of the nanostructure 14, which is beneficial to reducing the process difficulty of manufacturing the ring-gate transistor and improving the yield of the semiconductor device. In addition, the presence of the dielectric layer can also have greater immunity to process fluctuations and improve the working performance of the ring-gate transistor.

[0050] In the actual application process, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. For example, the semiconductor substrate provided in the embodiment of the present invention can be a semiconductor substrate such as silicon, silicon germanium, germanium, etc. without any structure formed. Alternatively, the semiconductor substrate can also be a semiconductor substrate formed with some structures. For example: when the ring-gate transistor provided in the embodiment of the present invention is a transistor of the second layer or higher layer in the semiconductor device, the semiconductor substrate includes a semiconductor structure located below the ring-gate transistor, etc.

[0051] For the above active structure, from the structural aspect, the source region and the drain region included in the active structure are spaced apart in a direction parallel to the surface of the semiconductor substrate. The channel region is located between the source region and the drain region. Secondly, the channel region may only include a layer of nanostructures, or, as Fig.14 and Fig.15 As shown, the channel region may also include multiple layers of nanostructures 14 spaced apart along the thickness direction of the semiconductor substrate 11. The nanostructures 14 at the bottom of the channel region are spaced apart from the semiconductor substrate 11. The number of layers of the nanostructures 14 included in the channel region, the interval between the nanostructures 14 and the semiconductor substrate 11, and the interval between different layers of nanostructures 14 may be set according to actual needs and are not specifically limited here.

[0052] like Fig.14 and Fig.15As shown, each layer of nanostructure 14 may include only two layers of semiconductor parts 15 spaced apart in the thickness direction of the semiconductor substrate 11, and in this case, each layer of nanostructure 14 includes only one layer of dielectric part 16. Alternatively, each layer of nanostructure may also include at least three layers of semiconductor parts. The number of layers of semiconductor parts included in the nanostructure may be determined according to the thickness requirements of a single-layer nanostructure, a single-layer semiconductor part, and a single-layer dielectric part in actual application scenarios, and is not specifically limited here.

[0053] As for the thickness of the semiconductor part and the dielectric part, it can be determined based on the driving performance and gate control capability of the ring-gate transistor in the actual application scenario, as well as the actual manufacturing process accuracy, and no specific limitation is made here.

[0054] Exemplarily, the thickness of the dielectric portion may be less than or equal to 5 nm. For example, the thickness of the dielectric portion may be 1 nm, 2 nm, 3 nm, 4 nm or 5 nm, etc. In this case, the thickness of the dielectric portion is relatively small, which is conducive to further improving the driving performance and gate control capability of the ring-gate transistor. Specifically, in the case where the ring-gate transistor includes multiple layers of dielectric portions, the thicknesses of different dielectric portions may be the same or different. When the thicknesses of different dielectric portions are the same, the difficulty of releasing the space for filling the dielectric portion can be reduced, as well as the difficulty of simultaneously filling different spaces with dielectric materials, thereby improving the yield of the ring-gate transistor.

[0055] Exemplarily, the thickness of at least one semiconductor layer may be greater than or equal to 2 nm and less than or equal to 10 nm. For example, the thickness of at least one semiconductor layer may be 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm. Specifically, in the same nanostructure, the thicknesses of different semiconductor layers may be the same or different. When the gate-all-around transistor includes a multilayer nanostructure, the thicknesses of different semiconductor layers included in the nanostructure may be the same or different.

[0056] In addition, if Fig.14 and Fig.15 As shown, along the length direction of the gate stack structure 17, in the same nanostructure 14, the width of the dielectric portion 16 can be smaller than the width of the semiconductor portion 15, or can be equal to the width of the semiconductor portion 15, so as to reduce the difficulty of manufacturing the ring-gate transistor. Among them, when the width of the dielectric portion 16 is smaller than the width of the semiconductor portion 15, the difference between the widths can be determined according to the actual manufacturing process, and is not specifically limited here.

[0057] From the material aspect, the source region, drain region and semiconductor part included in the active structure can include any semiconductor material such as silicon, silicon germanium or germanium, as long as it can be applied to the ring-gate transistor provided in the embodiment of the present invention. Secondly, in the same nanostructure, the materials of the semiconductor parts of different layers can be the same or different.

[0058] For example, the materials of semiconductor parts in different layers can all be silicon, silicon germanium or germanium.

[0059] For another example: in the same nanostructure, when the material of at least one semiconductor part is different from the material of the remaining semiconductor parts, when the material of the semiconductor part includes silicon, silicon germanium or germanium, in the same nanostructure, the difference in the germanium content in the materials of different semiconductor parts is less than 10%, so as to reduce the limitation of the critical thickness of the epitaxy, and is conducive to improving the formation quality of the semiconductor part, reducing the process difficulty of releasing the semiconductor part, and improving the yield of the ring-gate transistor. Specifically, when the same nanostructure includes at least three layers of semiconductor parts, only one layer of semiconductor parts can be different from the material of the remaining semiconductor parts, or the materials of every two layers of semiconductor parts can be different.

[0060] As for the materials of the different semiconductor parts included in different layers of nanostructures, they can be the same or different. When the materials of the different semiconductor parts included in different layers of nanostructures are different, only some of the semiconductor parts can be different from the materials of the different semiconductor parts in the remaining nanostructures, or the materials of the semiconductor parts included in every two layers of nanostructures can be different.

[0061] When the materials of different semiconductor parts included in different layers of nanostructures are different, the material differences of different semiconductor parts in different layers of nanostructures can be set according to actual needs, and are not specifically limited here.

[0062] For example, when the material of the semiconductor part includes silicon, silicon germanium or germanium, the difference in the germanium content in the materials of different semiconductor parts included in different layers of nanostructures can be less than 10%. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the difference in the germanium content in the materials of different semiconductor parts in the same nanostructure being less than 10% when the material of the semiconductor part includes silicon, silicon germanium or germanium, which will not be repeated here.

[0063] Among them, when the materials of different semiconductor parts included in different layers of nanostructures are different, the carrier mobility of the semiconductor part material in at least one layer of nanostructure can be greater than the carrier mobility of the semiconductor part material in the nanostructure located on the upper layer, so as to improve the conduction uniformity between different layers of nanostructures, further improve the conduction performance of the channel region, and improve the driving performance of the ring-gate transistor.

[0064] As for the material of the dielectric part, the material of the dielectric part may include low dielectric constant materials such as silicon oxide, silicon nitride or silicon oxynitride; or, it may also include high dielectric constant materials such as hafnium oxide. The material of the dielectric part can be determined according to the thickness of the dielectric part and the requirements for the driving performance and gate control capability of the ring-gate transistor in the actual application scenario, and is not specifically limited here.

[0065] For the above-mentioned gate stack structure, the gate stack structure may include a gate dielectric layer and a gate. The gate dielectric layer surrounds the periphery of each layer of nanostructures and covers the portion of the semiconductor substrate corresponding to the gate formation region. The gate is located on the gate dielectric layer. The material of the above-mentioned gate dielectric layer may be an insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the above-mentioned gate may be a conductive material such as TiN, TaN or TiSiN.

[0066] In one example, if Fig.13 As shown, the above-mentioned ring-gate transistor may also include gate sidewalls 19 located on both sides of the gate stack structure 17 along its own length direction. Along the length direction of the gate stack structure 17, the gate sidewalls 19 span the edge areas on both sides of the channel region to isolate the gate stack structure 17 from other conductive structures, ensuring that the ring-gate transistor has stable electrical characteristics.

[0067] In some cases, such as Fig.13 As shown, the ring-gate transistor provided by the embodiment of the present invention may also include a shallow trench isolation structure 18 and / or an interlayer dielectric layer 20. The above-mentioned shallow trench isolation structure 18 is located on the semiconductor substrate 11, and is used to isolate different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 18 can be set according to actual conditions. The above-mentioned interlayer dielectric layer 20 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 17, which is used to protect the source area 12 and the drain area from being affected by operations such as etching and cleaning when removing the sacrificial gate.

[0068] The material of at least one of the gate sidewall, the shallow trench isolation structure and the interlayer dielectric layer may be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0069] In a second aspect, an embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. Figures 1 to 15 The manufacturing process is described by a stereoscopic or cross-sectional view of the operation shown. Specifically, the manufacturing method of the ring-gate transistor includes the steps of:

[0070] First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can be referred to above and will not be described in detail here.

[0071] Next, if Figures 7 to 12 As shown, an active structure is formed on a semiconductor substrate 11. The active structure includes a source region 12, a drain region 13, and a channel region between the source region 12 and the drain region 13. The channel region includes at least one layer of nanostructure 14. Each layer of nanostructure 14 includes at least two layers of semiconductor portions 15 spaced apart in the thickness direction of the semiconductor substrate 11, and a dielectric portion 16 disposed between two adjacent layers of semiconductor portions 15.

[0072] Among them, the structure, materials and specifications of the active structure can be referred to in the previous text and will not be repeated here.

[0073] In an actual manufacturing process, illustratively, forming an active structure on a semiconductor substrate may include the following steps:

[0074] like Figures 1 to 3 As shown, a fin structure 21 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 21 includes a first sacrificial layer 22 and a semiconductor stack arranged alternately. Among the first sacrificial layers 22 and the semiconductor stack arranged alternately, the film layer located at the bottom is the first sacrificial layer 22. The semiconductor stack includes multiple semiconductor layers 23 arranged at intervals, and a second sacrificial layer 24 located between two adjacent semiconductor layers 23.

[0075] Among them, the semiconductor layer in each semiconductor stack is used to manufacture the semiconductor part of the corresponding layer of nanostructure included in the channel region of the ring-gate transistor, so the number of layers of semiconductor stacks included in the fin structure can be determined according to the number of layers of nanostructures included in the channel region, the number of layers of semiconductor layers included in each semiconductor stack can be determined according to the number of layers of semiconductor parts included in the nanostructure, and the material and thickness of the semiconductor layers included in each semiconductor stack can be determined according to the material and thickness of the semiconductor parts included in the nanostructure. In addition, the second sacrificial layer in the semiconductor stack is used to release the space to fill the dielectric part in the subsequent release, so the thickness of the second sacrificial layer can refer to the thickness of the dielectric part described above. Secondly, the material of the second sacrificial layer is different from the material of the semiconductor layer.

[0076] As for the first sacrificial layer, it is used to form a gap for filling the gate stack structure in the subsequent release, so the thickness of the first sacrificial layer can be determined according to the thickness of the gate stack structure, and is not specifically limited here. Secondly, the material of the first sacrificial layer is different from the material of the semiconductor layer.

[0077] In addition, the materials of the first sacrificial layer and the second sacrificial layer may be the same or different. For example: when the material of one of the first sacrificial layer and the second sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in the germanium content in the materials of the first sacrificial layer and the second sacrificial layer is greater than or equal to 10%, so as to ensure that the second sacrificial layer can be completely removed while the first sacrificial layer is subsequently removed. As for which of the first sacrificial layer and the second sacrificial layer has a higher germanium content, it can be determined according to the actual application scenario, and no specific limitation is made here. For example: when the material of the semiconductor layer is silicon or silicon germanium with a lower germanium content, the germanium content in the material of the second sacrificial layer may be greater than the germanium content in the material of the first sacrificial layer. For another example: when the material of the semiconductor layer is germanium or silicon germanium with a higher germanium content, the germanium content in the material of the second sacrificial layer may be less than the germanium content in the material of the first sacrificial layer.

[0078] Exemplarily, when the material of one of the first sacrificial layer and the semiconductor layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in the germanium content in the materials of the first sacrificial layer and the semiconductor layer may be greater than or equal to 20%, so as to further improve the formation quality of the semiconductor portion and improve the working performance of the ring-gate transistor. As for which of the first sacrificial layer and the semiconductor layer has a higher germanium content, it can be determined according to the conductivity type of the ring-gate transistor and the actual application scenario, and is not specifically limited here. For example: in the case where the conductivity type of the ring-gate transistor is P-type, the germanium content in the semiconductor layer material may be greater than the germanium content in the first sacrificial layer material. For another example: in the case where the conductivity type of the ring-gate transistor is N-type, the germanium content in the semiconductor layer material may be less than the germanium content in the first sacrificial layer material.

[0079] Secondly, if Figure 3 As shown, the thickness of the second sacrificial layer 24 can be less than that of the first sacrificial layer 22 to ensure that the gate stack structure can be filled normally, so that the dielectric portion has a smaller thickness and the driving performance and gate control capability of the ring-gate transistor are improved.

[0080] In the actual manufacturing process, Figure 1 As shown, epitaxy or other processes can be used to form a first sacrificial layer 22, a second sacrificial layer 24 and a semiconductor layer 23 on the semiconductor substrate 11 according to the relative position relationship of each film layer in the fin structure. Then, as shown in FIG. Figure 2 As shown, photolithography and etching processes can be used to etch at least the first sacrificial layer 22, the second sacrificial layer 24 and the semiconductor layer 23. If the manufactured semiconductor device also includes a shallow trench isolation structure, it is necessary to further etch a portion of the semiconductor substrate 11 downward to form a fin. Next, as Figure 3 As shown, a shallow trench isolation structure 18 is formed on a semiconductor substrate 11 by using processes such as deposition and etching. The material of the shallow trench isolation structure 18 can refer to the above. Secondly, the top height of the shallow trench isolation structure 18 is less than or equal to the bottom height of the first sacrificial layer 22, and the part of the fin exposed outside the shallow trench isolation structure 18 is a fin-shaped structure 21. Alternatively, if the manufactured semiconductor device does not include the above-mentioned shallow trench isolation structure, it is only necessary to etch the first sacrificial layer, the second sacrificial layer and the semiconductor layer to obtain the fin-shaped structure.

[0081] Next, if Figure 4 As shown, a mask structure 25 is formed across the fin structure 21 .

[0082] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure. As for the material of the mask structure, it can be set according to actual needs, as long as it can play a protective role in the subsequent mask.

[0083] Exemplarily, the mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the mask structure may also include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include materials such as silicon oxide. In addition, the mask structure may also include a sacrificial gate, and gate sidewalls located at least on both sides of the sacrificial gate along the length direction. The material of the gate sidewall can be referred to in the above text and will not be repeated here.

[0084] Next, if Figure 5 and Figure 6 As shown, the portion of the fin structure exposed outside the mask structure 25 is processed to form a source region 12 and a drain region 13 .

[0085] In the actual manufacturing process, ion implantation and other processes can be used to directly dope the portion of the fin structure exposed outside the mask structure to form the source region and drain region included in the ring-gate transistor. Alternatively, wet etching or dry etching and other processes can be used to selectively remove the portion of the fin structure exposed outside the mask structure; then, epitaxy and other processes are used to form the source region and drain region included in the ring-gate transistor on both sides of the remaining fin structure.

[0086] Next, if Figure 7 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 20 on the semiconductor substrate 11. The top of the interlayer dielectric layer 20 is flush with the top of the mask structure 25. The material of the interlayer dielectric layer 20 can be referred to above and will not be repeated here.

[0087] Next, if Figure 8 As shown, at least a portion of the mask structure may be removed by using a dry etching process or a wet etching process.

[0088] Specifically, whether to completely remove the mask structure can be determined according to the specific structure of the mask structure. For example, when the mask structure only includes a gate oxide layer and a sacrificial gate, the mask structure needs to be completely removed. For another example, when the mask structure includes a sacrificial gate and a gate sidewall, only the sacrificial gate needs to be removed, that is, only part of the mask structure needs to be removed.

[0089] Next, if Fig. 9 As shown, a dry etching process or a wet etching process may be used to remove the remaining first sacrificial layer and the second sacrificial layer, so that the remaining semiconductor layer forms the semiconductor portion 15 .

[0090] Next, if Figures 10 to 12 As shown, a dielectric portion 16 is formed between two adjacent semiconductor portions 15 .

[0091] In the actual manufacturing process, the forming process and forming process of the dielectric part can be determined according to the material of the dielectric part and the actual needs. Fig.10 As shown, a thermal oxidation process or an atomic layer deposition process can be used to form a dielectric material 26 that fills between two adjacent semiconductor portions 15 and covers the periphery of the semiconductor portion 15. Next, as Fig.11 and Fig.12 As shown, dry etching or wet etching or other processes may be used to selectively remove the portion of the dielectric material covering the periphery of the semiconductor portion 15 under the protection of the semiconductor portion 15 to obtain the dielectric portion 16 .

[0092] Next, if Figures 13 to 15 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 17 surrounding the periphery of each layer of nanostructure 14. The specific structure and material of the gate stack structure 17 can be referred to above and will not be repeated here.

[0093] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0094] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0095] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A gate-all-around transistor, characterized in that: include: Semiconductor substrate, An active structure is arranged on the semiconductor substrate; the active structure comprises a source region, a drain region, and a channel region located between the source region and the drain region; the channel region comprises at least one layer of nanostructure; each layer of the nanostructure comprises at least two layers of semiconductor portions arranged at intervals along the thickness direction of the semiconductor substrate, and a dielectric portion arranged between two adjacent layers of the semiconductor portions; The gate stack structure surrounds the periphery of each layer of the nanostructure.

2. The gate-all-around transistor according to claim 1, characterized in that: The material of the dielectric part is a low dielectric constant material; And / or, the thickness of the dielectric portion is less than or equal to 5 nm.

3. The gate-all-around transistor according to claim 1, wherein: Along the length direction of the gate stack structure, in the same nanostructure, the width of the dielectric portion is less than or equal to the width of the semiconductor portion.

4. The gate-all-around transistor according to claim 1, wherein: In the same nanostructure, the material of at least one semiconductor portion is different from the materials of the other semiconductor portions; And / or, when the material of the semiconductor part includes silicon, silicon germanium or germanium, in the same nanostructure, the difference in germanium content in the materials of different semiconductor parts is less than 10%.

5. The gate-all-around transistor according to claim 1, wherein: In the channel region, different semiconductor parts of different layers of the nanostructures are made of different materials; And / or, in the case where the material of the semiconductor portion includes silicon, silicon germanium or germanium, the difference in germanium content in the materials of different semiconductor portions included in different layers of the nanostructure is less than 10%.

6. The gate-all-around transistor according to claim 1, wherein: The thickness of at least one semiconductor layer is greater than or equal to 2 nm and less than or equal to 10 nm; And / or, in the same nanostructure, different semiconductor parts have the same thickness.

7. A method for manufacturing a gate-all-around transistor, characterized in that: include: Providing a semiconductor substrate; An active structure is formed on the semiconductor substrate; the active structure comprises a source region, a drain region, and a channel region between the source region and the drain region; the channel region comprises at least one layer of nanostructure; each layer of the nanostructure comprises at least two layers of semiconductor portions spaced apart in a thickness direction of the semiconductor substrate, and a dielectric portion disposed between two adjacent layers of the semiconductor portions; A gate stack structure is formed around the periphery of each layer of the nanostructure.

8. The method for manufacturing a gate-all-around transistor according to claim 7, characterized in that: The active structure is formed on the semiconductor substrate, comprising: A fin-shaped structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the fin-shaped structure includes alternately arranged first sacrificial layers and semiconductor stacks; wherein, among the alternately arranged first sacrificial layers and semiconductor stacks, the film layer located at the bottom is the first sacrificial layer; the semiconductor stack includes multiple semiconductor layers arranged at intervals, and a second sacrificial layer located between two adjacent semiconductor layers; forming a mask structure spanning over the fin-shaped structure; Processing the portion of the fin structure exposed outside the mask structure to form the source region and the drain region; removing at least a portion of the mask structure; removing the remaining first sacrificial layer and the second sacrificial layer so that the remaining semiconductor layer forms the semiconductor portion; The dielectric portion is formed between two adjacent semiconductor portions.

9. The method for manufacturing a gate-all-around transistor according to claim 8, characterized in that: The dielectric portion is formed between two adjacent layers of the semiconductor portions, comprising: Using a thermal oxidation process or an atomic layer deposition process, a dielectric material is formed to fill between two adjacent layers of the semiconductor parts and cover the periphery of the semiconductor parts; Under the protection of the semiconductor part, the portion of the dielectric material covering the periphery of the semiconductor part is selectively removed to obtain the dielectric part.

10. The method for manufacturing a gate-all-around transistor according to claim 8, wherein: The thickness of the second sacrificial layer is less than the thickness of the first sacrificial layer; And / or, when the material of one of the first sacrificial layer and the second sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content in the materials of the first sacrificial layer and the second sacrificial layer is greater than or equal to 10%.

11. The method for manufacturing a gate-all-around transistor according to claim 8, wherein: When the material of one of the first sacrificial layer and the semiconductor layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content between the materials of the first sacrificial layer and the semiconductor layer is greater than or equal to 20%.

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