High electron mobility transistor

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to high electron mobility transistors and methods of manufacture. The structure comprises a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connected to the gate structure; and a field plate connected to the source region of the gate structure. The gate metal and the field plate comprise the same material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to high electron mobility transistors and methods of fabrication. Background Art

[0002] A high electron mobility transistor (HEMT) is a field effect transistor that includes a junction between two materials with different band gaps (i.e., a heterojunction) as the channel, rather than a doped region (as is usually the case with MOSFETs). Commonly used material families are GaN or GaAs, although other materials may be used depending on the application of the device.

[0003] Due to the higher critical field and switching quality factor (figures of merit) of the GaN material system, GaN HEMT devices generally have higher electric field strength than silicon MOSFETs, thereby providing substantial performance improvements in terms of on-resistance and breakdown voltage, while providing fast switching speeds and other important parameters. Since these characteristics fundamentally lead to higher system efficiency, HEMTs can be used in various power management applications, such as AC-DC and DC-DC conversion in consumer or automotive fields. In RF applications, they can be used for high-frequency power amplifiers, low-noise amplifiers or switches in applications such as mobile phones, satellites or receivers or radar equipment. Summary of the invention

[0004] In one aspect of the disclosure, a structure includes: a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connected to the gate structure; and a field plate connected to a source region of the gate structure, wherein the gate metal and the field plate include the same material.

[0005] In one aspect of the present disclosure, a structure includes: a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connected to the gate structure; and a field plate adjacent to and coplanar with the gate metal.

[0006] In one aspect of the present disclosure, a method includes: forming a gate structure on a semiconductor substrate; forming a gate metal connected to the gate structure; and forming a field plate connected to a source region of the gate structure, wherein the gate metal and the field plate include the same material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure, with reference to the several figures mentioned.

[0008] Figure 1 Devices according to some aspects of the present disclosure are shown.

[0009] Figures 2A-2H A method for manufacturing a Figure 1 The manufacturing process of the device. DETAILED DESCRIPTION

[0010] The present disclosure relates to semiconductor structures, and more particularly, to high electron mobility transistors and methods of manufacturing. More particularly, the present disclosure relates to a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT) including an air gap between a gate metal and a field plate metal. In an embodiment, the HEMT may be an AlGaN / GaN HEMT with the same material for the gate metal and the field plate metal. Advantageously, the HEMT has a reduced gate-to-source capacitance and does not require etching through a separate field plate metal.

[0011] In a more specific embodiment, the HEMT may include a field plate and a gate metal formed of the same material during the same deposition process. An air gap (e.g., a cavity) may be formed between the field plate and the gate metal. The field plate and the gate metal have the same thickness / height and material composition (e.g., TiN, Al, etc.). An interlayer dielectric material may be disposed over the field plate, the gate metal, and the air gap. The interlayer dielectric material may surround or encapsulate the air gap. Furthermore, in an embodiment, the air gap may be self-aligned with the field plate and the gate metal.

[0012] The devices of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the devices of the present disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithography process. Specifically, the manufacture of the device uses three basic building blocks: (i) depositing a material film on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0013] Figure 1 A device according to some aspects of the present disclosure is shown. In an embodiment, the device 10 includes a semiconductor substrate 12, wherein a buffer layer 14 is above the semiconductor substrate 12, and barrier layers 16, 18 are above the buffer layer 14. A gate structure 20 can be formed on the buffer layer 14, wherein the barrier layers 16, 18 are partially above the gate structure 20.

[0014] In an embodiment, the semiconductor substrate 12 may be a bulk semiconductor material or a semiconductor on insulator (SOI) technology. The semiconductor substrate may be, for example, silicon having a single crystal orientation. For example, in a preferred embodiment, the semiconductor substrate 12 comprises a p-type silicon material having a suitable crystal orientation (e.g., (111)). In alternative embodiments, the semiconductor substrate 12 may be any suitable material, including but not limited to SiC, SiGe, SiGeC, GaAs, InAs, InP, sapphire, and other III / V or II / VI compound semiconductors.

[0015] As is known in the art, the buffer layer 14 can be any semiconductor material used as a buffer material in a HEMT. For example, the buffer layer 24 can include a GaN stack, such as AlGaN / GaN. In a more specific embodiment and as an illustrative, non-limiting example, the GaN stack can be, for example, a graded AlGaN / GaN superlattice (to reduce stress mismatch between the semiconductor substrate 12), followed by a GaN layer and an AlGaN layer.

[0016] The barrier layer 16 may be an insulator material. For example, the insulator material may be Al y O x The barrier layer 18 may be SiN, an oxide, or other dielectric material. In an embodiment, the barrier layers 16, 18 may be partially formed over the gate structure 20, wherein the gate structure 20 includes P-doped GaN. The gate electrode 22 may be disposed over the gate structure 20. In an embodiment, as an example, the gate electrode 22 may be TiN.

[0017] Figure 1 A common metal material 24 is also shown that serves as a gate metal 24a and a field plate 24b. In an embodiment, the common metal material 24 may be a combination of TiN / Al / TiN or other metals or alloys formed or deposited in the same deposition process (thereby eliminating an additional masking process). By using a single deposition process, the common metal material 24 will have the same height or thickness for the gate metal 24a and the field plate 24b; that is, the gate metal 24a and the field plate 24b will have the same thickness. The gate metal 24a contacts the gate electrode 22 of the gate structure 20, and the field plate 24b may be a field plate for a source connection.

[0018] Still refer to Figure 1, an air gap 26 may be provided between the gate metal 24a and the field plate 24b. In an embodiment, the air gap 26 is self-aligned with the gate metal 24a and the field plate 24b. For example, the air gap is located at the same level of the structure as the gate metal 24a and the field plate 24b. The self-alignment is generated by a pinch-off process during the deposition of the interlayer dielectric material 28 over the gate metal 24a and the field plate 24b. In an embodiment, the air gap 26 may be surrounded (e.g., encapsulated) by the interlayer dielectric material 28 and may electrically isolate the gate metal 24a from the field plate 24b.

[0019] Furthermore, by using a combination of gate metal 24a and field plate 24b having the same metal material and an air gap 26 between gate metal 24a and field plate 24b, gate metal 24a and field plate 24b can now be brought very close to each other, thereby reducing gate-to-source capacitance. This would not be possible in the case of using separate metal deposition processes and / or materials for the gate metal and field plate due to processing parameters, such as minimum critical dimensions in the deposition process and / or the superposition of two separate masks. Although not shown, it will be appreciated by those skilled in the art that contacts may be provided to gate metal 24a and field plate 24b as is known in the art.

[0020] Figures 2A-2H The manufacturing method according to some aspects of the present disclosure is shown. Figure 1 2 shows a semiconductor substrate 12, wherein a buffer layer 14 is above the semiconductor substrate 12, and a gate material 20a that can be formed on the buffer layer 14. The buffer layer 14 can be formed by an epitaxial growth process known in the art so that the present disclosure can be fully understood without further explanation herein. A gate electrode 22 is formed above the gate material 20a, and a masking material 26 is formed above the gate electrode 22. The masking material 26 can be a SiN material deposited by a conventional deposition method such as a chemical vapor deposition (CVD) process. A hard mask 30 can be formed and patterned on the masking material 26 to define a gate structure.

[0021] exist Figure 2B In the embodiment, the gate structure 20 is patterned using a conventional etching process. For example, the etching process can be a reactive etching (RIE) process. The masking material can be removed from the top surface of the gate structure 20 (e.g., the gate electrode 22). A pull-back process, such as a wet etching process, can be used to pull back the gate electrode 22, such as the TiN material.

[0022] exist Figure 2C, a barrier layer 16 (e.g., an insulator material) may be deposited over the structure. The barrier layer material 16 may be deposited by a conventional deposition process, such as CVD. A resist 32 is formed over the barrier layer 16 and patterned to form an opening over and aligned with the gate structure 20. The exposed insulator material 16 may be removed, such as etched, to expose the gate electrode 22. The resist 32 may be removed by a conventional oxygen ashing process or other stripping agents known in the art.

[0023] exist Figure 2D , a barrier layer 18 is formed over barrier layer 16 and exposed gate electrode 22. In an embodiment, barrier layer 18 may be an insulator material such as SiN deposited by conventional deposition methods (e.g., CVD). Resist 34 may be formed over barrier layer 18. Resist 34 may be patterned, for example, by conventional photolithography processes, to expose barrier layer 18 over, for example, gate structure 20 and a source region of the device.

[0024] exist Figure 2E In the embodiment, the exposed barrier layer 18 above the gate structure 20 and the source region of the device is removed by a conventional etching process (e.g., RIE) having a chemistry that is selective to the barrier layer. In an embodiment, the etching process will expose, for example, the gate electrode 22 of the gate structure 20 and the underlying barrier layer 16 in the source region. The resist can be removed by a conventional oxygen ashing process or other stripping agents known in the art.

[0025] exist Figure 2F In the embodiment, a blanket deposition of the metal material 24 may be provided over the entire structure. In an embodiment, the metal material 24 may be deposited over, for example, the gate electrode 22 of the gate structure 20 and the underlying barrier layer 16 in the source region. In this way, the metal material 24 may be in direct contact with, for example, the gate electrode 22 of the gate structure 20 and the underlying barrier layer 16 in the source region. The metal material 24 will have the same thickness over the structure. The metal material 24 may be deposited by a conventional deposition process such as PVD.

[0026] exist Figure 2G In the embodiment, a resist 36 is formed and patterned over the metal material 24. In an embodiment, the patterning of the resist will define the Figure 2H The gate metal 24a and the field plate 24b are shown in FIG.

[0027] exist Figure 2HIn the embodiment, after patterning of the resist 36, the metal material 24 will undergo an etching process, such as RIE, to form the gate metal 24a and the field plate 24b, and form an opening 24c therebetween. In an embodiment, the opening 24c electrically isolates the gate metal 24a from the field plate 24b. And, by using a single deposition process of the metal material 24 and a subsequent etching process, the alignment problem of the gate metal 24a and the field plate 24b can now be eliminated. The gate metal 24a and the field plate 24b will also have the same thickness and the same material.

[0028] return Figure 1 , an interlayer dielectric material 28 may be deposited over the patterned metal material 24 (e.g., gate metal 24a and field plate 24b). The interlayer dielectric material 28 may be deposited by a conventional deposition process (e.g., CVD). During the deposition process, an air gap 26 will be formed within the opening 24c due to a pinch-off phenomenon known in the art. The interlayer dielectric material 28 will surround or encapsulate the air gap 26, which will also isolate the gate metal 24a and the field plate 24b.

[0029] HEMTs can be used as single devices in discrete applications, combined with several other devices of the same or different types in a single package through co-packaging or multi-chip 3D integration technology, or combined with several other devices in system-on-chip (SoC) technology. SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, SoCs consume much less power and occupy much less area than multi-chip designs with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (for example, in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things. In addition, GaN devices are increasingly being adopted in SoC designs, in which multiple GaN HEMTs are formed on a single substrate.

[0030] The above method is used for the manufacture of discrete devices or integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including discrete or integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0031] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: Semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connected to the gate structure; as well as a field plate connected to the source region of the gate structure, Wherein, the gate structure and the field plate include the same material.

2. The structure according to claim 1, wherein: The same material includes TiN.

3. The structure according to claim 2, wherein: The same material includes TiN / Al / TiN.

4. The structure of claim 1 further comprising an air gap between the field plate and the gate metal.

5. The structure according to claim 4, wherein: The air gap is encapsulated by an interlayer dielectric material.

6. The structure according to claim 5, wherein: The interlayer dielectric material is over the field plate and the gate metal.

7. The structure according to claim 1, wherein: The gate structure includes p-doped GaN.

8. The structure according to claim 7, wherein: The semiconductor substrate includes a GaN stack.

9. The structure according to claim 1, wherein: The field plate and the gate metal comprise the same thickness.

10. The structure according to claim 1, wherein: The field plate and the gate metal are coplanar.

11. The structure according to claim 1, wherein: The air gap is self-aligned with the field plate and the gate metal.

12. A structure comprising: Semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connected to the gate structure; A field plate is adjacent to and coplanar with the gate metal.

13. The structure according to claim 12, wherein: The gate metal and the field plate include the same metal material.

14. The structure of claim 12, further comprising an air gap encapsulated by an interlayer dielectric material.

15. The structure according to claim 14, wherein: The interlayer dielectric material is over the field plate and the gate metal.

16. The structure of claim 12, wherein: The gate structure includes p-doped GaN.

17. The structure of claim 12, wherein: The field plate and the gate metal comprise the same thickness.

18. The structure of claim 12, wherein: The air gap is self-aligned with the field plate and the gate metal.

19. The structure of claim 12, wherein: The field plate is connected to a source region of the gate structure.

20. A method comprising: forming a gate structure on a semiconductor substrate; forming a gate metal connected to the gate structure; as well as A field plate is formed connected to the source region of the gate structure, wherein the gate metal and the field plate comprise the same material.

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