Integrated circuit device and method of forming integrated circuit device

Abstract

Integrated circuit devices and methods of forming integrated circuit devices are disclosed. The integrated circuit device includes a p-type field effect transistor including a strained channel, the strained channel including a silicon channel and a silicon germanium cladding layer on opposite surfaces of the silicon channel, the silicon germanium cladding layer abutting the silicon channel without growing from the silicon channel.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 589,113, filed on October 10, 2023, entitled INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices including stacked transistors. Background Art

[0003] The size of transistors has continued to decrease to allow for continued scaling down of logic elements. As planar transistors have evolved into gate-all-around structures such as fin field effect transistors (FinFETs) and multi-bridge channel field effect transistors (MBCFETs), the technology of concentrating more transistors in the same area has continued to develop. Three-dimensional device structures can allow for a higher concentration of transistors in the same area. However, because three-dimensional devices can have a high aspect ratio due to the vertical positioning of n-channel FET (nFET) transistors and p-channel FET (pFET) transistors, the gate metal process can be complex. Summary of the invention

[0004] An integrated circuit device according to some embodiments includes a p-type field effect transistor including a strained channel, the strained channel including a silicon channel and a silicon germanium cladding layer on opposing surfaces of the silicon channel, the silicon germanium cladding layer abutting the silicon channel without growing therefrom.

[0005] A method according to some embodiments includes: forming a p-type field effect transistor stack, the p-type field effect transistor stack including a pair of silicon germanium layers having a silicon channel therebetween, the silicon channel being spaced apart from the pair of silicon germanium layers; and epitaxially growing silicon germanium on a respective surface of each of the silicon germanium layers adjacent to the silicon channel such that each of the silicon germanium layers is adjacent to the silicon channel on an opposite surface of the silicon germanium layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1H is a cross-sectional view illustrating a method of forming an integrated circuit according to some disclosed embodiments.

[0007] Figure 2 is a diagram showing some embodiments according to the disclosure Figures 1A to 1G A flow chart of operations related to a cross-sectional view.

[0008] Figures 3A to 3Gis a cross-sectional view illustrating a method of forming an integrated circuit device according to some disclosed embodiments.

[0009] Figure 4 is a diagram showing some embodiments according to the disclosure Figures 3A to 3G A flow chart of operations related to a cross-sectional view.

[0010] Figure 5 is a perspective view of a gate-all-around finFET structure including a plurality of field effect transistors each having a strained channel according to some disclosed embodiments. DETAILED DESCRIPTION

[0011] Some embodiments stem from the recognition that as complementary metal oxide semiconductor (CMOS) devices have been scaled smaller, new materials have been considered as alternatives to silicon. Silicon germanium has been considered as a new material for p-channel metal oxide semiconductor (PMOS) devices. Germanium provides the highest hole mobility (1900 cm2 / Vs) among all group IV or III-V materials. Because it is generally difficult to use germanium to make a good insulator, silicon germanium can be used as an alternative option. Germanium has a larger lattice constant than silicon (~4.2% mismatch), which causes silicon germanium to be compressively strained when on silicon. Strained silicon germanium channels (e.g., silicon germanium on silicon) can increase hole mobility in PMOS devices. Some embodiments of the inventive concept can provide an integrated circuit device including one or more p-type field effect transistors, wherein each transistor includes a strained channel, the strained channel including a silicon channel and a silicon germanium cladding layer on its opposite surface. The silicon germanium cladding layer is adjacent to the silicon channel without growing from the silicon channel. According to some embodiments, the silicon germanium cladding layer can be epitaxially grown from a sacrificial silicon germanium layer adjacent to the silicon channel. As a result, three-dimensional integrated circuit devices can be manufactured without increasing the complexity of the manufacturing process.

[0012] Figures 1A to 1H and Figure 2 An integrated circuit device including a p-type field effect transistor (PFET) having a silicon germanium clad channel and a method of forming the integrated circuit device are shown according to some disclosed embodiments. Figure 1A and Figure 2 Operations begin at block 205 where a stack is formed including alternating silicon germanium layers 105 and silicon channels 110, wherein sacrificial silicon germanium layers 115 separate adjacent silicon germanium layers 105 from silicon channels 110. In some embodiments, the percentage composition of germanium in each silicon germanium layer 105 is greater than about 20%. In other embodiments, the percentage composition of germanium in each silicon germanium layer 105 is about 25%. The sacrificial silicon germanium layer 115 may have a percentage composition of germanium of about 55%. One of the sacrificial silicon germanium layers 115a may be between two of the silicon germanium layers 105.

[0013] Reference Figure 1Band Figure 2 At block 210, the sacrificial silicon germanium layer 115 and the sacrificial silicon germanium layer 115a are selectively removed. The sacrificial silicon germanium layer 115 may be selectively removed using an etchant that has an etching selectivity for the sacrificial silicon germanium layer 115 relative to the other silicon channels 110 and the silicon germanium layer 105. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0014] Reference Figure 1C and Figure 2 At block 215, an intermediate dielectric isolation spacer 120 is formed on opposite ends of each of the opposite surfaces of each silicon channel 110. In addition, in the region vacated by the sacrificial silicon germanium layer 115a (refer to, Figure 1B ) to form an intermediate dielectric isolation layer 125. According to various disclosed embodiments, the intermediate dielectric isolation spacer 120 and the intermediate dielectric isolation layer 125 may include nanoporous silicon dioxide, hydrogen silsesquioxane (HSQ), teflon-AF (polytetrafluoroethylene or PTFE), silicon oxyfluoride (FSG), silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride. The intermediate dielectric isolation layer 125 may be formed in the region vacated by the sacrificial silicon germanium layer 115 (refer to, Figure 1B ), and then selectively etching to remove the central portion of the intermediate dielectric isolation spacer 120 so that the intermediate dielectric isolation spacer 120 remains on the opposite ends of each of the opposite surfaces of each silicon channel 110. The etchant used may have an etching selectivity for the intermediate dielectric isolation spacer 120 relative to the silicon channel 110 and the silicon germanium layer 105. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0015] In some embodiments, the stack including the alternating silicon channels 110 and the silicon germanium layers 105 can be considered as an upper stack for forming a p-type transistor, which can be on a similarly constructed lower stack for forming an n-type transistor, where both the upper stack and the lower stack are formed on a substrate. The substrate may include one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP) and / or may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Therefore, in some embodiments, an intermediate dielectric isolation layer 125 can be used to separate the upper stack from the lower stack and / or the substrate.

[0016] Reference Figure 1D, the end of the silicon germanium layer 105 may be etched so that the end of the silicon germanium layer 105 is recessed from the end of the silicon channel 110 adjacent to the silicon germanium layer 105. The etchant used may have an etching selectivity to the silicon germanium layer 105 relative to the silicon channel 110 and the intermediate dielectric isolation spacer 120. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0017] Reference Figure 1E and Figure 2 At block 220, an inner spacer 130 is formed between adjacent silicon trenches 110 in the stack. The inner spacer 130 may include one or more insulating materials (such as silicon oxide, silicon oxynitride, silicon nitride, and / or silicon carbonitride). Figure 1E As shown in FIG. 1 , one of the silicon channels 110 and the adjacent silicon germanium layer 105 are shown grouped into a combination 140 for forming a p-type field effect transistor.

[0018] Reference Figure 1F and Figure 2 , in box 225, silicon germanium is epitaxially grown on the corresponding surface of each silicon germanium layer 105 adjacent to each silicon channel 110. According to some embodiments, the silicon germanium layer 105 is used as a seed layer, and the epitaxial growth body 145 and the seed layer are the continuation of the same silicon germanium compound. Therefore, this epitaxial growth process can be called a homoepitaxial process. The epitaxial growth body 145 of the silicon germanium layer 105 can have the same crystallographic orientation as the silicon germanium layer 105. According to some embodiments, the silicon germanium cladding layer can be epitaxially grown from a sacrificial silicon germanium layer adjacent to the silicon channel. For example, the epitaxial growth body 145 can be formed by epitaxially growing from the silicon germanium layer 105 in the area vacated by the sacrificial silicon germanium layer 115. The epitaxial growth body 145 can form the silicon germanium cladding layer 150 in a subsequent process. As Figure 1F As shown in , epitaxial growth 145 may abut the surface of the corresponding silicon channel 110 without growing from the surface.

[0019] Reference Figure 1G and Figure 2 At block 230, a portion of each silicon germanium layer 105 adjacent to the silicon channel 110 is selectively removed to leave a silicon germanium cladding layer 150 on the opposite surface of the corresponding silicon channel 110 between the intermediate dielectric isolation spacers 120. The silicon germanium layer 105 may be selectively etched to remove a central portion of the etched silicon germanium layer 105 so that the silicon germanium cladding layer 150 remains on the opposite surface of each silicon channel 110. The etchant used may have an etch selectivity to the silicon germanium layer 105 relative to the silicon channel 110, the intermediate dielectric isolation spacers 120, and the inner spacers 130. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0020] Therefore, if Figure 1GAs shown in , a p-type integrated circuit device (such as a p-type field effect transistor) including a strained channel can be formed. The strained channel includes a silicon channel 110 and a silicon germanium cladding layer 150 on opposite surfaces of the silicon channel 110, wherein the silicon germanium cladding layer 150 is adjacent to the silicon channel 110 but not grown from the silicon channel 110. Instead, a homoepitaxial process is used to grow from a silicon germanium layer 105 (see, Figure 1F ) grow a silicon germanium cladding layer 150.

[0021] Figure 1H 1 is a perspective view of a silicon channel 110 having a silicon germanium cladding layer 150 formed thereon. According to various embodiments, the silicon germanium cladding layer 150 may be formed on only a single pair of opposite sides of the silicon channel 110 (eg, the upper opposite surface and the lower opposite surface of the silicon channel 110). In other embodiments, such as Figure 1H As shown in , the silicon germanium cladding layer 150 may be formed on multiple pairs of opposing surfaces (such as top opposing surfaces and bottom opposing surfaces, and front opposing surfaces and back opposing surfaces) of the silicon channel 110. In such an embodiment, the silicon germanium cladding layer 150 may form a package around the silicon channel 110.

[0022] Figures 3A to 3G and Figure 4 An integrated circuit device including a p-type field effect transistor (PFET) having a silicon germanium clad channel and a method of forming the integrated circuit device are shown according to some disclosed embodiments. Figure 3A and Figure 4 , operation begins at frame 405, in which a stack including alternating silicon germanium layers 305 and silicon channels 310 is formed, wherein a sacrificial silicon germanium layer 315 separates adjacent silicon germanium layers 305 from silicon channels 310. Each silicon channel 310 includes a silicon germanium layer 312 therein. As described above, silicon germanium is compressively strained when on silicon. Strained silicon germanium channels can be used to increase hole mobility in PMOS devices. Therefore, the silicon germanium layer 312 in the silicon channel 310 further improves the carrier mobility in the silicon channel 310. In some embodiments, the percentage composition of germanium in each of the silicon germanium layer 305 and the silicon germanium layer 312 is greater than about 20%. In other embodiments, the percentage composition of germanium in each of the silicon germanium layer 305 and the silicon germanium layer 312 is about 25%. The sacrificial silicon germanium layer 315 may have a percentage composition of germanium of about 55%. One of the sacrificial silicon germanium layers 315a may be between two of the silicon germanium layers 305.

[0023] Reference Figure 3B and Figure 4, at block 410, the sacrificial silicon germanium layer 315 and the sacrificial silicon germanium layer 315a are selectively removed. The sacrificial silicon germanium layer 315 may be selectively removed using an etchant that has an etching selectivity for the sacrificial silicon germanium layer 315 relative to the other silicon channels 310 and the silicon germanium layer 305. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0024] Reference Figure 3C and Figure 4 At block 415, an intermediate dielectric isolation spacer 320 is formed on opposite ends of each of the opposite surfaces of each silicon channel 310. In addition, in the region vacated by the sacrificial silicon germanium layer 315a (refer to, Figure 3B ) to form an intermediate dielectric isolation layer 325. According to various disclosed embodiments, the intermediate dielectric isolation spacer 320 and the intermediate dielectric isolation layer 325 may include nanoporous silicon dioxide, hydrogen silsesquioxane (HSQ), teflon-AF (polytetrafluoroethylene or PTFE), silicon oxyfluoride (FSG), silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride. The intermediate dielectric isolation layer 325 may be formed in the region vacated by the sacrificial silicon germanium layer 315 (see, Figure 3B ), and then selectively etching to remove the central portion of the intermediate dielectric isolation spacer 320 so that the intermediate dielectric isolation spacer 320 remains on the opposite ends of each of the opposite surfaces of each silicon channel 310. The etchant used may have an etching selectivity for the intermediate dielectric isolation spacer 320 relative to the silicon channel 310 and the silicon germanium layer 305. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0025] In some embodiments, the stack including alternating silicon channels 310 and silicon germanium layers 305 can be considered as an upper stack for forming a p-type transistor, which can be on a similarly constructed lower stack for forming an n-type transistor, where both the upper stack and the lower stack are formed on a substrate. The substrate may include one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP) and / or may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Therefore, in some embodiments, an intermediate dielectric isolation layer 325 can be used to separate the upper stack from the lower stack and / or the substrate.

[0026] Reference Figure 3D, the end of the silicon germanium layer 305 may be etched so that the end of the silicon germanium layer 305 is recessed from the end of the silicon channel 310 adjacent to the silicon germanium layer 305. The etchant used may have an etching selectivity to the silicon germanium layer 305 relative to the silicon channel 310 and the intermediate dielectric isolation spacer 320. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0027] Reference Figure 3E and Figure 4 At block 420, an inner spacer 330 is formed between adjacent silicon trenches 310 in the stack. The inner spacer 330 may include one or more insulating materials (such as silicon oxide, silicon oxynitride, silicon nitride, and / or silicon carbonitride). Figure 3E As shown in FIG. 3 , one of the silicon channels 310 and the adjacent silicon germanium layer 305 are shown grouped into a combination 340 for forming a p-type field effect transistor.

[0028] Reference Figure 3F and Figure 4 , in box 425, silicon germanium is epitaxially grown on the corresponding surface of each silicon germanium layer 305 adjacent to each silicon channel 310. According to some embodiments, the silicon germanium layer 305 is used as a seed layer, and the epitaxial growth body 345 and the seed layer are the continuation of the same silicon germanium compound. Therefore, this epitaxial growth process can be called a homoepitaxial process. The epitaxial growth body of the silicon germanium layer can have the same crystallographic orientation as the silicon germanium layer 305. According to some embodiments, the silicon germanium cladding layer can be epitaxially grown from a sacrificial silicon germanium layer adjacent to the silicon channel. For example, the epitaxial growth body 345 can be formed by epitaxially growing from the silicon germanium layer 305 in the area vacated by the sacrificial silicon germanium layer 315. The epitaxial growth body 345 can form the silicon germanium cladding layer 350 in a subsequent process. As Figure 3F As shown in , the epitaxial growth 345 may abut the surface of the corresponding silicon channel 310 without growing from the surface.

[0029] Reference Figure 3G and Figure 4 At block 430, a portion of each silicon germanium layer 305 adjacent to the silicon channel 310 is selectively removed to leave a silicon germanium cladding layer 350 on the opposite surface of the corresponding silicon channel 310 between the intermediate dielectric isolation spacers 320. The silicon germanium layer 305 may be selectively etched to remove a central portion of the etched silicon germanium layer 305 so that the silicon germanium cladding layer 350 remains on the opposite surface of each silicon channel 310. The etchant used may have an etch selectivity to the silicon germanium layer 305 relative to the silicon channel 310, the intermediate dielectric isolation spacers 320, and the inner spacers 330. According to various disclosed embodiments, the etching may be performed using a wet etching and / or dry etching process.

[0030] Therefore, if Figure 3GAs shown in , a p-type integrated circuit device (such as a p-type field effect transistor) including a strained channel can be formed. The strained channel includes a silicon channel and a silicon germanium cladding layer 350 on opposite surfaces of the silicon channel, wherein the silicon germanium cladding layer 350 is adjacent to the silicon channel 310 but not grown from the silicon channel 310. Instead, the silicon germanium cladding layer 350 is grown from the silicon germanium cladding layer 350 adjacent to the silicon channel 310 using a homoepitaxial process.

[0031] Similar to the above Figure 1H In the described embodiment, the silicon germanium cladding layer 350 may be formed on only a single pair of opposing sides of the silicon channel 310 (e.g., the upper opposing surface and the lower opposing surface of the silicon channel 310). In other embodiments, the silicon germanium cladding layer 350 may be formed on multiple pairs of opposing surfaces of the silicon channel 310 (such as, the top opposing surface and the bottom opposing surface, and the front opposing surface and the back opposing surface). In such an embodiment, the silicon germanium cladding layer 350 may form a wrap around the silicon channel 310.

[0032] Figure 5 is a perspective view of a gate-all-around finFET structure including multiple field effect transistors each having a strained channel according to some disclosed embodiments. The finFET structure 500 is constructed as a gate-all-around structure in which the gate interfaces with the channel on the top, bottom, and sides of the channel. Multiple transistors (such as p-type field effect transistors) can be formed on a substrate 575 in the vertical finFET structure 500, where the transistors share a common gate 580, and each transistor includes a source layer 585 and a drain layer 590. The source layer 585 and the drain layer 590 can be electrically coupled using a strained channel therebetween, which is controlled using a voltage applied to the gate 580. The strained channel can be controlled according to the above description of Figures 1A to 1H , Figure 2 , Figures 3A to 3G and Figure 4 Any of the embodiments described may be implemented.

[0033] Example embodiments are described herein with reference to the accompanying drawings. Without departing from the teachings of the present disclosure, many different forms and embodiments are feasible, and therefore the disclosure should not be interpreted as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Throughout the specification, the same reference numerals identify the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Note that, although there is no specific description that can be incorporated into different embodiments with respect to the aspects described with respect to one embodiment, the aspects described with respect to one embodiment may be incorporated into different embodiments. That is, all embodiments and / or the features of any embodiment may be combined in any manner and / or combination.

[0034] Example embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are contemplated. Thus, the embodiments herein should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0035] It should also be noted that in some alternative implementations, the function / action shown in the flow chart frame here may not occur in the order shown in the flow chart. For example, depending on the function / action involved, the two frames shown in succession may actually be performed substantially simultaneously, or the frame may sometimes be performed in reverse order. In addition, the function of a given frame of a flow chart and / or block diagram may be divided into a plurality of frames and / or the function of two or more frames of a flow chart and / or block diagram may be integrated at least in part. Finally, without departing from the scope of the present invention, other frames may be added / inserted between the frames shown, and / or frames / operations may be omitted.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0037] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. It will be further understood that when the terms "comprise" and / or "comprising" are used in this specification, the stated features, steps, operations, elements and / or components are specified, but the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof are not excluded.

[0038] It will be understood that when an element is referred to as being "connected to" another element or "on" another element, the element may be directly connected to or on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element or "directly on" another element, there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or".

[0039] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and obscure. Therefore, this specification including the accompanying drawings should be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0040] The subject matter disclosed above is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the inventive concept. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. An integrated circuit device, comprising: A p-type field effect transistor includes a strained channel, the strained channel including a silicon channel and a silicon germanium cladding layer on opposing surfaces of the silicon channel, the silicon germanium cladding layer adjacent to the silicon channel without growing from the silicon channel.

2. The integrated circuit device of claim 1, further comprising: an intermediate dielectric isolation spacer on opposite ends of each of the opposing surfaces of the silicon trench; Wherein, the silicon germanium cladding layer is respectively between the intermediate dielectric isolation spacers on the opposite surfaces of the silicon channel.

3. The integrated circuit device according to claim 2, wherein: The intermediate dielectric isolation spacer includes: nanoporous silicon dioxide, hydrogen silsesquioxane, polytetrafluoroethylene, silicon oxyfluoride, silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride.

4. The integrated circuit device according to claim 1, wherein: The silicon channel includes a silicon germanium layer therein.

5. The integrated circuit device of claim 4, wherein: The percentage of germanium in the silicon germanium layer in the silicon channel is greater than 20%.

6. The integrated circuit device according to claim 1, wherein: The p-type field effect transistor is one of a plurality of p-type field effect transistors arranged in a stack, each of the plurality of p-type field effect transistors including a strained channel.

7. The integrated circuit device of claim 6, further comprising: an intermediate dielectric isolation spacer on opposite ends of each of the opposing surfaces of each of the silicon trenches in the stack; Wherein, the silicon germanium cladding layer is respectively between intermediate dielectric isolation spacers on opposite surfaces of each of the silicon channels in the stack.

8. The integrated circuit device of claim 7, further comprising: An inner spacer is between adjacent ones of the silicon channels in the stack and contacts an intermediate dielectric isolation spacer on a corresponding one of the silicon channels in the stack.

9. The integrated circuit device of claim 6, further comprising: An intermediate dielectric isolation layer is between the substrate and the stack.

10. The integrated circuit device of claim 9, wherein: The intermediate dielectric isolation layer includes: Nanoporous silica, hydrogenated silsesquioxane, polytetrafluoroethylene, silicon oxyfluoride, silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride.

11. The integrated circuit device of claim 1, wherein: A silicon germanium cladding layer wraps around the silicon channel.

12. A method of forming an integrated circuit device, comprising: forming a p-type field effect transistor stack including a pair of silicon germanium layers having a silicon channel therebetween, the silicon channel being spaced apart from the pair of silicon germanium layers; as well as Silicon germanium is epitaxially grown on a corresponding surface of each of the pair of silicon germanium layers adjacent to the silicon channel, so that each of the pair of silicon germanium layers adjoins the silicon channel on the corresponding surface of the silicon germanium layer.

13. The method of claim 12, further comprising: Portions of each of the pair of silicon germanium layers are removed to leave silicon germanium cladding layers on opposite surfaces of the silicon channel, respectively.

14. The method of claim 12, wherein: The steps of forming a p-type field effect transistor stack include: forming a stack including alternating silicon germanium layers and silicon channels, wherein a sacrificial silicon germanium layer separates adjacent ones of the silicon germanium layers and silicon channels, the alternating silicon germanium layers and silicon channels including the pair of silicon germanium layers and the silicon channel; and removing the sacrificial silicon germanium layer; Each of the sacrificial silicon germanium layers has a germanium composition percentage of at least 55%.

15. The method of claim 14, further comprising: forming an intervening dielectric isolation spacer on opposite ends of each of the opposite surfaces of each of the silicon channels in the stack; The intermediate dielectric isolation spacer includes: nanoporous silicon dioxide, hydrogen silsesquioxane, polytetrafluoroethylene, silicon oxyfluoride, silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride.

16. The method of claim 15, further comprising: forming interspacers between adjacent ones of the silicon channels in the stack, the interspacers contacting intervening dielectric isolation spacers on corresponding ones of the silicon channels in the stack; Wherein, the inner spacer comprises silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride.

17. The method of claim 16, wherein: The step of epitaxially growing silicon germanium on a corresponding surface of each of the silicon germanium layers in the stack comprises: epitaxially growing silicon germanium on a respective surface of each of the silicon germanium layers adjacent to each of the silicon channels in the stack such that each of the silicon germanium layers abuts an adjacent one of the silicon channels in the stack; and removing portions of each of the silicon germanium layers to leave silicon germanium cladding layers on opposing surfaces of each of the silicon channels in the stack, respectively; Wherein, the silicon germanium cladding layer is respectively between intermediate dielectric isolation spacers on opposite surfaces of each of the silicon channels in the stack.

18. The method of claim 14, wherein: The step of forming a stack including alternating silicon germanium layers and silicon channels, wherein a sacrificial silicon germanium layer separates adjacent ones of the silicon germanium layers and silicon channels, further comprises: One of the sacrificial silicon germanium layers is formed between the stack and the substrate.

19. The method of claim 18, further comprising: After removing the sacrificial silicon germanium layer, forming an intermediate dielectric isolation layer between the stack and the substrate; Wherein, the intermediate dielectric isolation layer comprises: nanoporous silicon dioxide, hydrogen silsesquioxane, polytetrafluoroethylene, silicon oxyfluoride, silicon oxide, silicon oxynitride, silicon nitride and / or silicon carbonitride.

20. The method of claim 12, wherein: The silicon channel includes a silicon germanium layer therein.

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