Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate provided with a diode region, a first IGBT region, and a second IGBT region between a first main surface and a second main surface opposite to the first main surface; in a plan view of the semiconductor substrate, the diode region is annular and surrounds the first IGBT region, and the second IGBT region surrounds the diode region. By arranging the annular diode area, the IGBT areas are distributed on the inner side and the outer side of the annular diode area, and when the diode works, heat generated by the diode can be uniformly diffused and dissipated to the first IGBT area located on the inner side of the diode area and the second IGBT area located on the outer side of the diode area. The heat dissipation uniformity of the diode is improved, the damage of partial region in the diode due to heat concentration is avoided, and the failure rate of the semiconductor device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In recent years, from the viewpoint of energy saving, semiconductor devices with low energy loss have been required in the fields of electric railways, vehicles, industrial machinery, and consumer equipment.

[0003] For example, a semiconductor device that arranges an insulated gate bipolar transistor (IGBT) and a diode on one semiconductor substrate, namely an RC IGBT (reverse conducting power semiconductor device), has emerged. The IGBT chip and the diode chip are integrated into one chip, which reduces the number of chips, reduces the complexity of wire connections, reduces the thermal resistance of the chip, and thus reduces energy loss.

[0004] However, the heat dissipation uniformity of the diode of the RC IGBT in the related art is poor, resulting in a high failure rate of the semiconductor device. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] The present application aims to address the deficiencies in the prior art, and its main purpose is to provide a semiconductor device to improve the heat dissipation uniformity of the diode and reduce the failure rate of the semiconductor device.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In response to the current problems, an embodiment of the present invention provides a semiconductor device, which includes: a semiconductor substrate, wherein a diode region, a first IGBT region, and a second IGBT region are arranged between a first main surface and a second main surface opposite to the first main surface; when looking down at the semiconductor substrate, the diode region is annular in shape and surrounds the first IGBT region, and the second IGBT region surrounds the diode region.

[0009] The above-mentioned embodiment has the following beneficial effects: by setting an annular diode area, IGBT areas are distributed both inside and outside the annular diode area. When the diode is working, the heat generated by the diode can be evenly diffused and dissipated to the first IGBT area located inside the diode area and the second IGBT area located outside the diode area, thereby improving the heat dissipation uniformity of the diode, avoiding damage to some areas of the diode due to heat concentration, and reducing the failure rate of the semiconductor device.

[0010] In some embodiments, the number of diode regions and first IGBT regions is multiple, and the multiple diode regions are arranged in an array spaced apart along a first direction and a second direction to form a diode array; wherein the first direction and the second direction are cross-arranged; when looking down at the semiconductor substrate, each diode region corresponds to a first IGBT region and surrounds the corresponding first IGBT region.

[0011] The above embodiment has the following beneficial effects: by arranging a plurality of diode regions in an array spaced apart along the first direction and the second direction, any two adjacent diode regions are separated by a second IGBT region, so that when the diode is working, part of the heat generated by each diode can not only be diffused and dissipated to the first IGBT region located inside the diode region, but can also be diffused and dissipated evenly outward from the second IGBT region outside the diode region, thereby avoiding damage to individual diode regions due to heat concentration, improving the uniformity of heat dissipation between different diodes, and thereby reducing the failure rate of the semiconductor device.

[0012] In some embodiments, the diode array has a first symmetry line parallel to the second direction; and the area of ​​the first IGBT region gradually decreases as the first IGBT region closest to the first symmetry line moves toward the first IGBT region closest to the edge of the diode array in the first direction.

[0013] The above embodiment has the following beneficial effects: by virtue of the characteristic that the heat dissipation performance is worse at the position closer to the first symmetry line on the semiconductor substrate, and the heat dissipation performance is better at the edge regions closer to the two sides of the first direction, that is, by virtue of the characteristic that the heat dissipation performance gradually increases from the middle of the semiconductor substrate to the two sides of the semiconductor substrate, the area of ​​the first IGBT region closer to the edge of the diode array in the first direction is smaller, so that the heat generated by the diode at this position is more uniformly dissipated outward through the second IGBT region outside it; the area of ​​the first IGBT region closer to the first symmetry line of the diode array in the first direction is larger, and the heat generated by the diode at this position is more uniformly dissipated outward through the first IGBT region inside it. The area of ​​the first IGBT region at different positions matches the heat dissipation performance of the semiconductor substrate at the position, and the heat dissipation uniformity of the diode regions at different positions is improved.

[0014] In some embodiments, the first direction is a row direction, the second direction is a column direction, and the areas of all diode regions in the same row are equal; or,

[0015] As the diode region closest to the first symmetry line moves toward the diode region closest to the edge of the diode array in the first direction, the area of ​​the diode region gradually increases.

[0016] The above embodiments have the following beneficial effects: the area of ​​the diode region is positively correlated with the heat generated when it is working, that is, the larger the area of ​​the diode region, the more heat it generates when it is working, and the smaller the area of ​​the diode region, the less heat it generates when it is working. In some embodiments, on the basis of the equal area of ​​all diode regions in the same row, the inner side of the diode region closer to the side of the semiconductor substrate is provided with a first IGBT region with a smaller area, and the inner side of the diode region farther from the side of the semiconductor substrate is provided with a first IGBT region with a larger area, so that the area of ​​the diode region at different positions matches the area of ​​the first IGBT region, and the heat dissipation uniformity of the diode regions at different positions is improved. In other embodiments, considering that the heat dissipation performance of the middle of the semiconductor substrate is worse than the heat dissipation performance of the two sides of the semiconductor substrate, the area of ​​the diode region closer to the first symmetry line is smaller, so as to reduce the heat generated by the diode at this position when it is working; and the area of ​​the diode region farther away from the first symmetry line is larger, so as to increase the heat generated by the diode at this position when it is working. Matching the area of ​​the diode region at different positions with the heat dissipation performance of the semiconductor substrate at this position is conducive to improving the heat dissipation uniformity of the diode regions at different positions.

[0017] In some embodiments, the diode array has a second symmetry line parallel to the first direction; and the area of ​​the first IGBT region gradually decreases as the first IGBT region closest to the second symmetry line moves toward the first IGBT region closest to the edge of the diode array in the second direction.

[0018] The above embodiment has the following beneficial effects: by virtue of the fact that the heat dissipation performance is worse at the position closer to the second symmetry line on the semiconductor substrate, and the heat dissipation performance is better at the edge regions on both sides closer to the second direction, that is, by virtue of the fact that the heat dissipation performance gradually increases from the middle of the semiconductor substrate to the two sides of the semiconductor substrate, the area of ​​the first IGBT region inside the diode region closer to the side of the semiconductor substrate is smaller, and the heat generated by the diode at this position is more evenly dissipated outward through the second IGBT region outside it; the area of ​​the first IGBT region inside the diode region closer to the second symmetry line is larger, and the heat generated by the diode at this position is more evenly dissipated outward through the first IGBT region inside it. Therefore, the areas of the first IGBT regions at different positions in the first direction and the second direction are matched with the heat dissipation performance of the semiconductor substrate at the position, and the heat dissipation uniformity of the diode regions at different positions is improved.

[0019] In some embodiments, the first direction is a row direction, the second direction is a column direction, and the areas of all diode regions in the same column are equal; or,

[0020] As the diode region closest to the second symmetry line moves toward the diode region closest to the edge of the diode array in the second direction, the area of ​​the diode region gradually increases.

[0021] The above embodiments have the following beneficial effects: the area of ​​the diode region is positively correlated with the heat generated during operation, that is, the larger the area of ​​the diode region, the more heat it generates during operation, and the smaller the area of ​​the diode region, the less heat it generates during operation. In some embodiments, on the basis that the areas of all diode regions in the same arrangement direction parallel to the second direction are equal, the area of ​​the first IGBT region on the inner side of the diode region closer to the side of the semiconductor substrate in the second direction is smaller, and the area of ​​the first IGBT region on the inner side of the diode region closer to the second symmetry line is larger, so that the areas of the diode region and the first IGBT region located at different positions in the first direction and the second direction are matched with the heat dissipation performance of the semiconductor substrate at the position, thereby improving the heat dissipation uniformity of the diode regions at different positions. In other embodiments, considering that the heat dissipation performance of the middle of the semiconductor substrate is worse than the heat dissipation performance of the two sides of the semiconductor substrate, the area of ​​the diode region closer to the second symmetry line is smaller, so as to reduce the heat generated by the diode at the position when it is working; and the area of ​​the diode region closer to the side of the semiconductor substrate in the second direction is larger, so as to increase the heat generated by the diode at the position when it is working. Matching the areas of the diode regions at different positions in the first direction and the second direction with the heat dissipation performance of the semiconductor substrate at the positions is beneficial to improving the heat dissipation uniformity of the diode regions at different positions.

[0022] In some embodiments, the first direction is a row direction, and the second direction is a column direction; areas of all first IGBT regions located in the same column are equal; areas of all diode regions located in the same column are equal.

[0023] The above-mentioned embodiment has the following beneficial effects: the area of ​​the first IGBT region at different positions in the first direction is matched with the heat dissipation performance of the semiconductor substrate at that position, so as to improve the heat dissipation uniformity of the diode region at different positions, and at the same time, the area of ​​the first IGBT region and the diode region at different positions in the second direction are equal, thereby simplifying the topological structure of the array-arranged diode region and the first IGBT region for easy manufacturing.

[0024] In some embodiments, the diode array has a first symmetry line parallel to the second direction; the spacing between two adjacent diode regions in the first direction gradually decreases from close to the first symmetry line to away from the first symmetry line.

[0025] The above embodiment has the following beneficial effects: considering that the heat dissipation performance of the middle of the semiconductor substrate is worse than the heat dissipation performance of the two sides of the semiconductor substrate, the spacing between two adjacent diode regions in the first direction gradually decreases from close to the first symmetry line to away from the first symmetry line, so that the arrangement spacing of the diode regions closer to the first symmetry line in the first direction is sparser, and the arrangement spacing of the diode regions farther away from the first symmetry line in the first direction is denser, so that the arrangement spacing of the diode regions at different positions in the first direction matches the heat dissipation performance of the semiconductor substrate at that position, thereby improving the heat dissipation uniformity of the diode regions at different positions.

[0026] In some embodiments, the first direction is a row direction, and the second direction is a column direction; in all diode regions located in the same column, the spacing between any two adjacent diode regions is equal; or,

[0027] The semiconductor substrate has a second symmetry line parallel to the first direction; the distance between two adjacent diode regions in the second direction gradually decreases from close to the second symmetry line to far away from the second symmetry line.

[0028] The above embodiments have the following beneficial effects: In some embodiments, the spacing between any two adjacent diode regions in all diode regions in the same column is equal, so that the diode regions are arranged at equal intervals along the second direction, simplifying the topological structure of the diode array and facilitating manufacturing. In other embodiments, considering that the heat dissipation performance of the middle of the semiconductor substrate is worse than the heat dissipation performance of the two sides of the semiconductor substrate, the spacing between two adjacent diode regions in the second direction gradually decreases from close to the second symmetry line to away from the second symmetry line, so that the arrangement spacing of the diode regions closer to the second symmetry line in the second direction is sparser, and the arrangement spacing of the diode regions farther away from the second symmetry line in the second direction is denser, so that the arrangement spacing between the diode regions at different positions in the first direction and the second direction matches the heat dissipation performance of the semiconductor substrate at that position, thereby improving the heat dissipation uniformity of the diode regions at different positions.

[0029] In some embodiments, a spacing between two adjacent diode regions in the first direction or the second direction is greater than half of the sum of the ring widths of the two diode regions and less than the sum of the ring widths of the two diode regions; and / or,

[0030] The width of each first IGBT region in the first direction or the second direction is greater than the ring width of the diode region surrounding it, and less than twice the ring width of the diode region surrounding it.

[0031] The above embodiments have the following beneficial effects: In some embodiments, by making the spacing between two adjacent diode regions greater than half of the sum of the ring widths of the two diode regions, the second IGBT region between the two diode regions is wide enough, so that the heat diffused from the two diode regions when working can be promptly diffused to the semiconductor substrate, thereby improving the heat dissipation effect. In addition, the spacing between the two adjacent diode regions is controlled to be less than the sum of the ring widths of the two diode regions, thereby ensuring the heat dissipation effect while avoiding the diode regions from being too sparsely arranged, thereby balancing the arrangement density and heat dissipation performance of the diode regions, ensuring the heat dissipation effect while also improving the arrangement density of the diode regions. In other embodiments, the width of each first IGBT region in the first direction or the second direction is greater than the ring width of the diode region surrounding it, so that the first IGBT region is wide enough, so that the heat diffused from the diode region surrounding it when working can be promptly diffused to the semiconductor substrate, thereby improving the heat dissipation effect. The width of each first IGBT region is also controlled to be less than twice the ring width of the diode region surrounding it, so as to avoid the mismatch between the heat dissipation capacity and the heat dissipation demand due to the width of the first IGBT region being too large and the ring width of the diode region being too narrow while ensuring the heat dissipation effect, so that the heat dissipation capacity provided by the first IGBT region and the heat dissipation demand required by the diode region are matched, avoiding insufficient heat dissipation capacity or excessive heat dissipation capacity of the first IGBT region. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0033] In the attached figure:

[0034] Figure 1 A schematic top view of a semiconductor device according to a specific embodiment of the present invention is shown;

[0035] Figure 2 A schematic block diagram showing a top view of a first main surface of a semiconductor substrate in a semiconductor device according to a specific embodiment of the present invention;

[0036] Figure 3 A schematic top view of a plug in a first interlayer dielectric layer in a semiconductor device according to a specific embodiment of the present invention is shown;

[0037] Figure 4 A schematic top view of a gate flow channel of a semiconductor device according to a specific embodiment of the present invention is shown;

[0038] Figure 5A schematic top view block diagram showing the spacing arrangement of gate flow channels and emitter flow channels of a semiconductor device according to a specific embodiment of the present invention;

[0039] Figure 6 A schematic top view of a plug in a second interlayer dielectric layer in a semiconductor device according to a specific embodiment of the present invention is shown;

[0040] Figure 7 A schematic top view block diagram showing the spacing arrangement of the gate pad and the emitter pad of a semiconductor device according to a specific embodiment of the present invention;

[0041] Figure 8 A schematic structural diagram of the AA cross section of a semiconductor device according to a specific embodiment of the present invention is shown;

[0042] Fig. 9 A schematic structural diagram of a semiconductor device taken along a BB cross section according to a specific embodiment of the present invention is shown;

[0043] Figures 10 to 13 A schematic diagram showing the top view distribution of the area and spacing of the diode region and the first IGBT region in different specific embodiments of the present invention is shown;

[0044] Fig.14 A schematic top view of the distribution of a diode array arranged in a staggered array in a specific embodiment of the present invention is shown.

[0045] Reference numerals:

[0046] 10-semiconductor substrate 11-first symmetry line 12-second symmetry line

[0047] 20-active area 30-diode area 31-anode area

[0048] 32- cathode region 33- virtual gate 40- drift region

[0049] 41 - first IGBT region 42 - second IGBT region 43 - first active gate

[0050] 44- second active gate 45- emitter region 46- contact region

[0051] 47-base region 48-P+ type well region 51-first interlayer dielectric layer

[0052] 52-second interlayer dielectric layer 61-first plug 62-second plug

[0053] 63 - third plug 62 - fourth plug 65 - fifth plug

[0054] 66 - sixth plug 71 - first gate wiring portion 72 - second gate wiring portion

[0055] 73 - Gate wiring converging portion 74 - Gate pad portion 75 - Gate pad

[0056] 80 - emitter wiring bus 81 - emitter wiring 82 - emitter pad

[0057] 91-field stop region 92-collector region 93-collector metal layer DETAILED DESCRIPTION

[0058] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0059] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0060] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0061] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated or otherwise) and the spatial descriptors used herein are interpreted accordingly.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is N type and the second conductivity type is P type. In addition, N- represents a concentration lower than N in impurity concentration, and N+ represents a concentration higher than N in impurity concentration. Similarly, P- represents a concentration lower than P in impurity concentration, and P+ represents a concentration higher than P in impurity concentration.

[0064] Figure 1 A top view of a semiconductor device according to the present application is shown, showing a semiconductor device as an RC-IGBT (Reverse Conducting IGBT). In addition, the RC-IGBT is a semiconductor device in which an IGBT region functioning as an IGBT and a diode region 30 functioning as a diode are provided on a single semiconductor substrate 10. The semiconductor device can be applied to electronic products such as, but not limited to, laptop computers, desktop computers, tablet computers, mobile phone terminals, smart wearable devices, inverters, power factor correction circuits, and voltage converters.

[0065] In some embodiments, reference Figure 1, a semiconductor device is proposed, which mainly includes: a semiconductor substrate 10, wherein the semiconductor substrate 10 is provided with a diode region 30, a first IGBT region 41 and a second IGBT region 42 between a first main surface and a second main surface opposite to the first main surface; when looking down at the semiconductor substrate 10, the diode region 30 is in a ring shape and surrounds the first IGBT region 41, and the second IGBT region 42 surrounds the diode region 30.

[0066] The above embodiment has the following beneficial effects: by setting the annular diode area 30, IGBT areas are distributed both inside and outside the annular diode area 30. When the diode is working, the heat generated by the diode can be evenly diffused and dissipated to the first IGBT area 41 located inside the diode area 30 and the second IGBT area 42 located outside the diode area 30, thereby improving the heat dissipation uniformity of the diode, avoiding damage to some areas of the diode due to heat concentration, and reducing the failure rate of the semiconductor device.

[0067] The above structures are described in detail below in conjunction with the accompanying drawings.

[0068] Regarding the semiconductor substrate 10 described above, it is used to set an IGBT region that functions as an IGBT and a diode region 30 that functions as a diode. The top view shape of the diode region 30 in the present application is annular, and a first IGBT region 41 is set inside the annular diode region 30, and a second IGBT region 42 is set outside the annular diode region 30. Specifically, when viewed from above, the diode region 30 has an inner circle and an outer circle, and the outer circle surrounds the inner circle and has a certain width area between the inner circle to serve as the body area of ​​the diode region 30. The first IGBT region 41 is located on the inner circle of the diode region 30 toward the center of the ring, and the second IGBT region 42 is located on the outer circle of the diode region 30 away from the center of the ring, so that when viewed from above, the diode region 30 surrounds the first IGBT region 41, and the second IGBT region 42 surrounds the diode region 30, and the diode region 30 completely separates the first IGBT region 41 and the second IGBT region 42 in the semiconductor substrate 10.

[0069] For example, the diode may be a freewheeling diode, and the diode region 30 may be a region where the freewheeling diode is disposed. The diode region 30 may be disposed in any manner. Figure 8The diode region 30 may be provided with regions formed by N-type or P-type doping, such as but not limited to the anode region 31, the cathode region 32, the drift region 40, the field stop region 91, etc. Of course, the diode region 30 may also be provided with a virtual gate 33. Correspondingly, the first IGBT region 41 and the second IGBT region 42 may be provided in any manner. For example, referring to Figure 8 Each of the first IGBT region 41 and the second IGBT region 42 may include regions formed by N-type or P-type doping, such as but not limited to an emitter region 45, a contact region 46, a collector region 92, a field stop region 91, a drift region 40, a base region 47, etc. Of course, an active gate may also be provided in the first IGBT region 41 and the second IGBT region 42.

[0070] Exemplary, reference Figure 8 The semiconductor substrate 10 is common between the IGBT region and the diode region 30. In this example, one main surface of the semiconductor substrate 10 is referred to as a first main surface, and the other main surface of the semiconductor substrate 10 is referred to as a second main surface. Figure 8 For example, the first main surface is the upper surface of the semiconductor substrate 10, and the second main surface is the lower surface of the semiconductor substrate 10. Exemplarily, the semiconductor substrate 10 is a silicon substrate. However, in other examples, the semiconductor substrate 10 may also be a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium oxide (GaO) substrate.

[0071] It should be noted that the first main surface and the second main surface are only used to distinguish the two main surfaces of the semiconductor substrate 10, and are not intended to be substantial limitations. Figure 8 , the cathode region 32 in the diode region 30 and the collector region 92 in the IGBT region are located on the second main surface side of the semiconductor substrate 10, and the anode region 31 and the dummy gate 33 in the diode region 30 are located on the first main surface side of the semiconductor substrate 10. Referring to the figure, the emitter region 45, the contact region 46 and the active gate in the IGBT region are located on the first main surface side of the semiconductor substrate 10.

[0072] Exemplary, reference Figure 8The semiconductor substrate 10 has a P-type base region 47 from the first main surface to a predetermined depth position. The base region 47 in this example is provided in the IGBT region and the diode region 30. It should be noted that the base region 47 of the diode region 30 is also the anode region 31 of the diode region 30. In addition, the semiconductor substrate 10 has an N-type drift region 40 in the IGBT region and the diode region 30, from the base region 47 and the anode region 31 to a predetermined depth position. The anode region 31 of the diode region 30 is also connected to the emitter wiring portion 81, and the emitter wiring portion 81 located above the diode region 30 functions as an anode electrode. The diode region 30 has a diode formed by a PN junction of the P-type anode region 31 and the N-type drift region 40. The diode of the diode region 30 is connected in reverse parallel to the IGBT in the IGBT region, so that the return current flows when the IGBT is turned off.

[0073] Exemplary, reference Figure 8 , the emitter region 45 can be an N+ type semiconductor layer, and the contact region 46 can be a P+ type semiconductor layer. The N+ type emitter region 45 and the P+ type contact region 46 are arranged in a manner of being exposed on the first main surface. The emitter region 45 and the contact region 46 are arranged on both sides of the first direction of the active gate. The emitter region 45 is arranged in direct contact with both sides of the active gate. In contrast, the contact region 46 is separated from the active gate. Among the base region 47, the area in contact with the active gate acts as a channel formation area. It should be noted that the arrangement of the emitter region 45 and the contact region 46 is not limited to the arrangement shown above. In addition, other arrangements can also be adopted.

[0074] refer to Figure 2 , various methods can be used to form the first active gate 43 and the second active gate 44. In some embodiments, a gate trench can be formed by etching from the first main surface of the semiconductor substrate 10 to the drift region 40, and then a gate insulating film and an active gate are provided in the gate trench. The gate insulating film is arranged in direct contact with the inner wall of the gate trench. The inner wall may include a bottom surface and a side surface. The active gate is arranged in direct contact with the gate insulating film. That is, the interior of the gate trench is filled with a gate insulating film and an active gate. The material of the active gate may include polysilicon. The arrangement of the virtual gate 33 is basically the same as the arrangement of the active gate, and will not be repeated.

[0075] Exemplary, reference Fig. 9A P+ well region 48 deeper than the first active gate 43 may be formed around the end position of the first active gate 43. For the P+ well region 48, the bottom of the gate trench of the first active gate 43 is covered by the P+ well region 48. Thus, no depletion layer is formed at the end of the first active gate 43, thereby preventing electric field concentration. Of course, it should be noted that the setting method of the doping region at the end position of the first active gate 43 is not limited to the method shown above, and other setting methods can also be used.

[0076] Exemplary, reference Figure 8 The semiconductor substrate 10 has a field stop region 91 (FieldStop, FS for short) below the drift region 40. The field stop region 91 may be an N-type semiconductor layer. The field stop region 91 may be commonly provided in the first IGBT region 41, the diode region 30, and the second IGBT region 42.

[0077] Exemplary, reference Figure 8 The semiconductor substrate 10 may have a collector region 92 and a cathode layer below the field stop region 91. In this example, the collector region 92 is disposed in the first IGBT region 41 and the second IGBT region 42, and the cathode region 32 is disposed in the diode region 30. The collector region 92 may be a P+ type semiconductor layer. In contrast, the cathode region 32 may be an N+ type semiconductor layer.

[0078] Exemplary, reference Figure 8 , a collector metal layer 93 is provided on the second main surface side of the semiconductor substrate 10. It should be noted that the collector metal layer 93 is provided on the second main surface side of the semiconductor substrate 10, but is not located between the first main surface and the second main surface, that is, it does not belong to the structure of the semiconductor substrate 10. For example, refer to Figure 8 The collector metal layer 93 is commonly provided in the first IGBT region 41, the diode region 30, and the second IGBT region 42. It should be noted that the collector metal layer 93 functions as a cathode electrode in the diode region 30. The collector pad in the semiconductor device can be electrically connected to the collector metal layer 93.

[0079] Exemplary, reference Figure 1 The IGBT region and the diode region 30 provided between the first main surface and the second main surface of the semiconductor substrate 10 may both be located in the active region 20 of the semiconductor substrate 10. An edge termination portion may be provided outside the active region 20, and the edge termination portion may be provided in a ring shape surrounding the entire outer side of the second IGBT region 42. The edge termination portion is located from the outermost side of the second IGBT region 42 to the end of the semiconductor substrate 10. The edge termination portion may have a voltage-resistant structure such as a guard ring structure and a channel stopper.

[0080] Exemplary, reference Figure 4 The semiconductor device may further include a gate flow channel, the gate flow channel includes a gate wiring portion and a gate pad portion 74, and the gate wiring portion and the gate pad portion 74 may be arranged in a variety of ways. Exemplarily, the gate wiring portion and the gate pad portion 74 may be a double-layer structure of a polysilicon film and an aluminum-silicon alloy film on top thereof. Alternatively, the gate wiring portion and the gate pad portion 74 may also be a single-layer structure of an aluminum-silicon alloy film.

[0081] In some embodiments, another semiconductor device is provided, referring to Figure 1 , the number of the diode regions 30 and the first IGBT regions 41 are both multiple, and the two adjacent diode regions 30 are spaced apart. When looking down at the semiconductor substrate 10, each diode region 30 corresponds to a first IGBT region 41 and surrounds the corresponding first IGBT region 41. The two adjacent diode regions 30 can be separated by the second IGBT region 42, that is, the second IGBT region 42 is at least distributed between the outer circles of the two adjacent annular diode regions 30. In some embodiments, the second IGBT region 42 can also extend and be distributed over the entire periphery of all the diode regions 30. When viewed from above, the second IGBT region 42 has a closed periphery and surrounds all the diode regions 30.

[0082] The above embodiment has the following beneficial effects: by setting a plurality of annular diode regions 30 arranged at intervals, each first IGBT region 41 corresponds to a diode region 30 and is located on the inner side of the corresponding diode region 30, and the second IGBT region 42 is located between adjacent diode regions 30 or on the outer side of all diode regions 30, so that the large-area diode region 30 is dispersed into a plurality of small-area diode regions 30 arranged at intervals, so that the outer side and the outer side of the annular diode region 30 are both IGBT regions. When the diode is working, the heat generated by the diode can be evenly dissipated from the inside and the outside of the diode region 30 to the outside, thereby improving the heat dissipation uniformity of the diode, avoiding damage to some areas of the diode due to heat concentration, and reducing the failure rate of the semiconductor device.

[0083] The number of diode regions 30 may be as follows: Figure 1 , Figure 10-Figure 14 The 4, 10, 12, 15, and 25 shown in the figure may also be any value not less than 2. Correspondingly, the number of the first IGBT regions 41 is equal to the number of the diode regions 30. When viewed from above, each first IGBT region 41 is located inside a corresponding diode region 30.

[0084] Regarding the number of the second IGBT regions 42, refer to Figure 1, the number of the second IGBT regions 42 may be 1, and the second IGBT region 42 surrounds the outer rings of all the diode regions 30 and is connected as a whole when viewed from above. In other embodiments, the number of the second IGBT regions 42 may be 2 or more, which may be equal to the number of the diode regions 30 at most, and each second IGBT region 42 surrounds the outer ring of at least one diode region 30 when viewed from above, and different second IGBT regions 42 may not be connected. For example, the number of the second IGBT regions 42 may be equal to the number of the diode regions 30, and the number of the second IGBT regions 42 is also ring-shaped, and each second IGBT region 42 corresponds to a diode region 30 and only surrounds the outer ring of a corresponding diode region 30 when viewed from above, and different second IGBT regions 42 are not connected together, thereby being distinguished as different IGBT regions.

[0085] There are many ways to arrange the multiple diode regions 30 , and one of them is described below as an example.

[0086] In some embodiments, another semiconductor device is provided, referring to Figure 1 The number of diode regions 30 and the number of first IGBT regions 41 are both multiple, and the multiple diode regions 30 are arranged in an array spaced apart along the first direction and the second direction to form a diode array; wherein the first direction and the second direction are cross-arranged; when looking down at the semiconductor substrate 10, each diode region 30 corresponds to a first IGBT region 41 and surrounds the corresponding first IGBT region 41.

[0087] The above embodiment has the following beneficial effects: by arranging a plurality of diode regions 30 in an array spaced apart along the first direction and the second direction, any two adjacent diode regions 30 are separated by a second IGBT region 42, so that when the diode is working, part of the heat generated by each diode can not only be diffused and dissipated to the first IGBT region 41 located inside the diode region 30, but can also be diffused and dissipated evenly outward from the second IGBT region 42 outside the diode region 30, thereby avoiding damage to individual diode regions 30 due to heat concentration, improving the heat dissipation uniformity between different diodes, and thereby reducing the failure rate of the semiconductor device.

[0088] It should be noted that the array arrangement of the plurality of diode regions 30 may be in a variety of array arrangements. Figure 1 , the plurality of diode regions 30 may be arranged in an aligned array. In other embodiments, referring to Fig.14 , the multiple diode regions 30 may also be arranged in a staggered array.

[0089] Exemplary, reference Figure 1, the first direction can be perpendicular or substantially perpendicular to the second direction. It should be noted that the first direction is not limited to the lateral direction as shown in the figure, and the second direction is not limited to the vertical direction as shown in the figure. In other embodiments, the first direction can also be a lateral direction, and the second direction can also be a vertical direction.

[0090] Exemplarily, one of the first direction and the second direction is a row direction, and the other direction is a column direction. Exemplarily, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, exemplary, the second direction may be a column direction, and the first direction may be a row direction. In some of the following embodiments, the first direction is a row direction, and the second direction is a column direction.

[0091] In some embodiments, another semiconductor device is provided, referring to Figure 1 The shape of the diode region 30 may be a rectangular ring, and the shape of the first IGBT region 41 may be a rectangle.

[0092] The above embodiment has the following beneficial effects: by setting a rectangular ring-shaped diode area 30 and a rectangular first IGBT area 41, it is convenient to set a strip-shaped virtual gate 33 in the diode area 30 and a strip-shaped active gate in the IGBT area, thereby simplifying the difficulty of setting the virtual gate 33 and the active gate.

[0093] It should be noted that, when viewed from above, the inner and outer circles of the rectangular ring can be regular rectangles or irregular rectangles connected by rounded corners at right angles. Correspondingly, the outer periphery of the first IGBT region 41 can be regular rectangles or irregular rectangles.

[0094] Of course, the shape of the diode region 30 may be other rings besides a rectangular ring, for example, an elliptical ring, a circular ring, etc. The shape of the first IGBT region 41 is the same as the shape of the inner side of the ring of the diode region 30, and may change according to the change of the shape of the inner side of the ring of the diode region 30.

[0095] In some embodiments, another semiconductor device is provided, referring to Fig.10 The diode array has a first symmetry line 11 parallel to the second direction; as the first IGBT region 41 closest to the first symmetry line 11 moves toward the first IGBT region 41 closest to the edge of the diode array in the first direction, the area of ​​the first IGBT region 41 gradually decreases.

[0096] The above embodiment has the following beneficial effects: by virtue of the fact that the heat dissipation performance of the semiconductor substrate 10 is worse at the position closer to the first symmetry line 11 and better at the edge regions on both sides of the first direction, that is, by virtue of the fact that the heat dissipation performance gradually increases from the middle of the semiconductor substrate 10 to the two sides of the semiconductor substrate 10, the area of ​​the first IGBT region 41 closer to the edge of the diode array in the first direction is smaller, so that the heat generated by the diode at this position is more uniformly dissipated outward through the second IGBT region 42 outside it; the area of ​​the first IGBT region 41 closer to the first symmetry line 11 of the diode array in the first direction is larger, and the heat generated by the diode at this position is more uniformly dissipated outward through the first IGBT region 41 inside it. The area of ​​the first IGBT region 41 at different positions matches the heat dissipation performance of the semiconductor substrate 10 at the positions, and the heat dissipation uniformity of the diode regions 30 at different positions is improved.

[0097] Exemplarily, the first direction may be a row direction, the second direction may be a column direction, and the number of diode regions 30 located in the same row is at least three. Specifically, the number of diode regions 30 located in the same row may be any value not less than 3, such as 3, 4, 10, 20, etc.

[0098] Exemplary, reference Fig.10 The semiconductor substrate 10 has two first sides opposite to each other in the first direction, both of which extend along the second direction, and the symmetry line of the two first sides is also the first symmetry line 11, and the first symmetry line 11 is equidistant from the two first sides. That is, the diode array is arranged in the middle area of ​​the semiconductor substrate 10 in the first direction.

[0099] Exemplary, reference Fig.10 , as the first IGBT region 41 closest to the first symmetry line 11 moves toward the first IGBT region 41 closest to the edge of the diode array in the first direction, the area of ​​the first IGBT region 41 gradually decreases. Specifically, between two adjacent first IGBT regions 41 in the first direction, the closer to the first symmetry line 11, the larger the area of ​​the first IGBT region 41; the farther from the first symmetry line 11, the smaller the area of ​​the first IGBT region 41.

[0100] Exemplary, reference Fig.10 When the first symmetry line 11 is also the symmetry line of the two first sides, between two adjacent first IGBT regions 41 in the first direction, the smaller the distance from the nearest first side of the two first sides, the smaller the area of ​​the first IGBT region 41; the larger the distance from the nearest first side of the two first sides, the larger the area of ​​the first IGBT region 41.

[0101] Exemplary, reference Fig.10 , the area of ​​the first IGBT region 41b may be set to be larger than the area of ​​the first IGBT region 41a, and the area of ​​the first IGBT region 41c may be set to be larger than the area of ​​the first IGBT region 41d.

[0102] In some embodiments, another semiconductor device is provided, referring to Fig.10 The first direction is the row direction, the second direction is the column direction, and the areas of all diode regions 30 located in the same row are equal.

[0103] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the heat generated when it is working, that is, the larger the area of ​​the diode region 30, the more heat it generates when it is working, and the smaller the area of ​​the diode region 30, the less heat it generates when it is working. On the basis that the areas of all the diode regions 30 located in the same row are equal, the first IGBT region 41 with a smaller area is arranged inside the diode region 30 closer to the side of the semiconductor substrate 10, and the first IGBT region 41 with a larger area is arranged inside the diode region 30 farther from the side of the semiconductor substrate 10, so that the areas of the diode regions 30 and the first IGBT regions 41 at different positions are matched, thereby improving the heat dissipation uniformity of the diode regions 30 at different positions.

[0104] For example, refer to Fig.10 , the areas of the diode region 30a, the diode region 30b, the diode region 30c and the diode region 30d can be set to be equal.

[0105] In some other embodiments, another semiconductor device is provided, referring to Fig.10 As the diode region 30 closest to the first symmetry line 11 moves toward the diode region 30 closest to the edge of the diode array in the first direction, the area of ​​the diode region 30 gradually increases.

[0106] Specifically, refer to Fig.10 , between two diode regions 30 adjacent in the first direction, the area of ​​the diode region 30 closer to the first symmetry line 11 is smaller than the area of ​​the diode region 30 farther from the first symmetry line 11. That is, between two diode regions 30 adjacent in the first direction, the area of ​​the diode region 30 closer to the first symmetry line 11 is smaller, and the area of ​​the diode region 30 farther from the first symmetry line 11 is larger.

[0107] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the heat generated when it is working, that is, the larger the area of ​​the diode region 30, the more heat it generates when it is working, and the smaller the area of ​​the diode region 30, the less heat it generates when it is working. Considering that the heat dissipation performance of the middle of the semiconductor substrate 10 is worse than the heat dissipation performance of the two sides of the semiconductor substrate 10, the area of ​​the diode region 30 closer to the first symmetry line 11 is smaller to reduce the heat generated by the diode at this position when it is working; and the area of ​​the diode region 30 farther away from the first symmetry line 11 is larger to increase the heat generated by the diode at this position when it is working. Matching the area of ​​the diode region 30 at different positions with the heat dissipation performance of the semiconductor substrate 10 at this position is conducive to improving the heat dissipation uniformity of the diode region 30 at different positions.

[0108] For example, refer to Fig.10 , the area of ​​the diode region 30a can be made larger than the area of ​​the diode region 30b, and the area of ​​the diode region 30d can be made larger than the area of ​​the diode region 30c.

[0109] In some embodiments, another semiconductor device is provided, referring to Fig.11 The diode array has a second symmetry line 12 parallel to the first direction; as the first IGBT region 41 closest to the second symmetry line 12 moves toward the first IGBT region 41 closest to the edge of the diode array in the second direction, the area of ​​the first IGBT region 41 gradually decreases.

[0110] The above embodiment has the following beneficial effects: by virtue of the fact that the heat dissipation performance at the position closer to the second symmetry line 12 on the semiconductor substrate 10 is worse, and the heat dissipation performance at the edge regions closer to the two sides of the second direction is better, that is, by virtue of the fact that the heat dissipation performance gradually increases from the middle of the semiconductor substrate 10 to the two sides of the semiconductor substrate 10, the area of ​​the first IGBT region 41 on the inner side of the diode region 30 closer to the side of the semiconductor substrate 10 is smaller, and the heat generated by the diode at this position is more uniformly dissipated outward through the second IGBT region 42 outside it; the area of ​​the first IGBT region 41 on the inner side of the diode region 30 closer to the second symmetry line 12 is larger, and the heat generated by the diode at this position is more uniformly dissipated outward through the first IGBT region 41 inside it. Therefore, the areas of the first IGBT regions 41 at different positions in the first direction and the second direction are matched with the heat dissipation performance of the semiconductor substrate 10 at the position, and the heat dissipation uniformity of the diode regions 30 at different positions is improved.

[0111] Exemplary, reference Fig.11, the semiconductor substrate 10 has a second symmetry line 12 parallel to the first direction. For example, the first direction is the row direction and the second direction is the column direction. The number of diode regions 30 located in the same column is at least three; wherein, between two adjacent second IGBT regions 42 in the second direction, the area of ​​the first IGBT region 41 closer to the second symmetry line 12 is greater than the area of ​​the first IGBT region 41 farther from the second symmetry line 12.

[0112] Specifically, the number of diode regions 30 in the same column is at least three. Specifically, the number of diode regions 30 in the same column can be any value not less than three, such as 3, 4, 10, 20, etc.

[0113] Exemplary, reference Fig.11 The semiconductor substrate 10 has two opposite second sides in the second direction, both of which extend along the first direction, and the symmetry line of the two second sides is also the second symmetry line 12, and the distance between the second symmetry line 12 and the two second sides is equal. That is, the diode array is arranged in the middle area of ​​the semiconductor substrate 10 in the second direction.

[0114] refer to Fig.11 , as the first IGBT region 41 closest to the second symmetry line 12 moves toward the first IGBT region 41 closest to the edge of the diode array in the second direction, the area of ​​the first IGBT region 41 gradually decreases. Specifically, between two adjacent first IGBT regions 41 in the second direction, the closer to the second symmetry line 12, the larger the area of ​​the first IGBT region 41; the farther from the second symmetry line 12, the smaller the area of ​​the first IGBT region 41.

[0115] In other words, reference Fig.11 When the second symmetry line 12 is still the symmetry line of the two second sides, between two adjacent first IGBT regions 41 in the second direction, the smaller the distance from the nearest second side of the two second sides, the smaller the area of ​​the first IGBT region 41; the larger the distance from the nearest second side of the two second sides, the larger the area of ​​the first IGBT region 41.

[0116] For example, refer to Fig.11 , the area of ​​the first IGBT region 41e may be set to be larger than the area of ​​the first IGBT region 41a and the area of ​​the first IGBT region 41f.

[0117] In some embodiments, another semiconductor device is provided, referring to Fig.10 and Fig.11 The first direction is the row direction, the second direction is the column direction, and the areas of all diode regions 30 located in the same column are equal.

[0118] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the heat generated when it is working, that is, the larger the area of ​​the diode region 30, the more heat it generates when it is working, and the smaller the area of ​​the diode region 30, the less heat it generates when it is working. On the basis that the areas of all the diode regions 30 located in the same column are equal, the area of ​​the first IGBT region 41 on the inner side of the diode region 30 closer to the side of the semiconductor substrate 10 in the second direction is smaller, and the area of ​​the first IGBT region 41 on the inner side of the diode region 30 closer to the second symmetry line 12 is larger, so that the areas of the diode region 30 and the first IGBT region 41 located at different positions in the first direction and the second direction are matched with the heat dissipation performance of the semiconductor substrate 10 at the position, and the heat dissipation uniformity of the diode regions 30 at different positions is improved.

[0119] For example, refer to Fig.10 and Fig.11 , the areas of the diode region 30a, the diode region 30e, and the diode region 30f can be set to be equal.

[0120] In some other embodiments, another semiconductor device is provided, referring to Fig.11 As the diode region 30 closest to the second symmetry line 12 moves toward the diode region 30 closest to the edge of the diode array in the second direction, the area of ​​the diode region 30 gradually increases.

[0121] Specifically, refer to Fig.11 , between two diode regions 30 adjacent in the second direction, the area of ​​the diode region 30 closer to the second symmetry line 12 is smaller than the area of ​​the diode region 30 farther from the second symmetry line 12. That is, between two diode regions 30 adjacent in the second direction, the area of ​​the diode region 30 closer to the second symmetry line 12 is smaller, and the area of ​​the diode region 30 farther from the second symmetry line 12 is larger.

[0122] The above embodiment has the following beneficial effects: the area of ​​the diode region 30 is positively correlated with the heat generated when it is working, that is, the larger the area of ​​the diode region 30, the more heat it generates when it is working, and the smaller the area of ​​the diode region 30, the less heat it generates when it is working. Considering that the heat dissipation performance of the middle of the semiconductor substrate 10 is worse than the heat dissipation performance of the two sides of the semiconductor substrate 10, the area of ​​the diode region 30 closer to the second symmetry line 12 is smaller to reduce the heat generated by the diode at this position when it is working; and the area of ​​the diode region 30 closer to the side of the semiconductor substrate 10 in the second direction is larger to increase the heat generated by the diode at this position when it is working. Matching the area of ​​the diode region 30 at different positions in the first direction and the second direction with the heat dissipation performance of the semiconductor substrate 10 at this position is conducive to improving the heat dissipation uniformity of the diode region 30 at different positions.

[0123] For example, refer to Fig.11 , the area of ​​the diode region 30e can be set to be smaller than the area of ​​the diode region 30a and the area of ​​the diode region 30f.

[0124] In some embodiments, another semiconductor device is provided, referring to Fig.11 The first direction is the row direction, the second direction is the column direction, and the areas of all the first IGBT regions 41 located in the same column are equal; the areas of all the diode regions 30 located in the same column are equal.

[0125] The above-mentioned embodiment has the following beneficial effects: the area of ​​the first IGBT region 41 at different positions in the first direction is matched with the heat dissipation performance of the semiconductor substrate 10 at the position, so as to improve the heat dissipation uniformity of the diode region 30 at different positions, and at the same time, the area of ​​the first IGBT region 41 and the diode region 30 at different positions in the second direction are equal, thereby simplifying the topological structure of the array-arranged diode region 30 and the first IGBT region 41 for easy manufacturing.

[0126] For example, refer to Fig.11 , the areas of the first IGBT region 41a, the first IGBT region 41e, and the first IGBT region 41f can be set to be equal, and the areas of the diode region 30a, the diode region 30e, and the diode region 30f can be set to be equal.

[0127] In some embodiments, another semiconductor device is provided, referring to Fig.12 The diode array has a first symmetry line 11 parallel to the second direction; the spacing between two adjacent diode regions 30 in the first direction gradually decreases from close to the first symmetry line 11 to away from the first symmetry line 11.

[0128] The above embodiment has the following beneficial effects: considering that the heat dissipation performance of the middle of the semiconductor substrate 10 is worse than that of the two sides of the semiconductor substrate 10, the spacing between two adjacent diode regions 30 in the first direction gradually decreases from close to the first symmetry line 11 to away from the first symmetry line 11, so that the arrangement spacing of the diode regions 30 closer to the first symmetry line 11 in the first direction is sparser, and the arrangement spacing of the diode regions 30 farther away from the first symmetry line 11 in the first direction is denser, so that the arrangement spacing of the diode regions 30 at different positions in the first direction matches the heat dissipation performance of the semiconductor substrate 10 at that position, thereby improving the heat dissipation uniformity of the diode regions 30 at different positions.

[0129] It should be noted that the spacing between two adjacent diode regions 30 in the first direction refers to: the minimum spacing between the outer circles of two adjacent diode regions 30 in the first direction. Correspondingly, the spacing between two adjacent diode regions 30 in the second direction refers to: the minimum spacing between the outer circles of two adjacent diode regions 30 in the second direction.

[0130] Specifically, refer to Fig.12 , taking the first direction as the row direction and the second direction as the column direction as an example, the number of diode regions 30 located in the same row is at least four. The spacing between any two adjacent diode regions 30 in the first direction is defined as a first spacing. Among them, the closer the first spacing is to the first symmetry line 11, the larger it is, and the farther the first spacing is from the first symmetry line 11, the smaller it is. That is, in two adjacent first spacings in the first direction, the first spacing closer to the first symmetry line 11 is greater than the first spacing farther from the first symmetry line 11.

[0131] Exemplarily, taking the first direction as the row direction and the second direction as the column direction as an example, the number of diode regions 30 located in the same row can be 4, 10, 20, or any other value not less than 3, so that there can be at least three first spacings in the first direction.

[0132] For example, refer to Fig.12 The number of first intervals between two adjacent diode regions 30 in the first direction is 4, namely d1, d2, d3, and d4, and d2>d1 and d3>d4 can be set.

[0133] Of course, in other embodiments, any two adjacent first spacings in the first direction may be made equal to each other to simplify the setting difficulty. Fig.12 The number of first intervals between two adjacent first IGBT regions 41 in the first direction is four, namely d1, d2, d3, and d4, and d1=d2=d3=d4 can be set.

[0134] In some embodiments, another semiconductor device is provided, referring to Fig.13 The semiconductor substrate 10 has a second symmetry line 12 parallel to the first direction; the distance between two adjacent diode regions 30 in the second direction gradually decreases from close to the second symmetry line 12 to away from the second symmetry line 12.

[0135] The above embodiment has the following beneficial effects: considering that the heat dissipation performance of the middle of the semiconductor substrate 10 is worse than that of the two sides of the semiconductor substrate 10, the spacing between two adjacent diode regions 30 in the second direction gradually decreases from close to the second symmetry line 12 to away from the second symmetry line 12, so that the arrangement spacing of the diode regions 30 closer to the second symmetry line 12 in the second direction is sparser, and the arrangement spacing of the diode regions 30 farther away from the second symmetry line 12 in the second direction is denser, so that the arrangement spacing between the diode regions 30 at different positions in the first direction and the second direction matches the heat dissipation performance of the semiconductor substrate 10 at that position, thereby improving the heat dissipation uniformity of the diode regions 30 at different positions.

[0136] Specifically, refer to Fig.12 , taking the first direction as the row direction and the second direction as the column direction as an example, the number of diode regions 30 located in the same column is at least four. The spacing between any two adjacent diode regions 30 in the second direction is defined as the second spacing. Among them, the closer the second spacing is to the second symmetry line 12, the larger it is, and the farther the second spacing is from the second symmetry line 12, the smaller it is. That is, in two adjacent second spacings in the second direction, the second spacing closer to the second symmetry line 12 is greater than the second spacing farther from the second symmetry line 12.

[0137] Exemplary, reference Fig.12 Taking the first direction as the row direction and the second direction as the column direction as an example, the number of diode regions 30 located in the same column can be 4, 10, 20 or any other value not less than 3, so that there can be at least three second spacings in the second direction.

[0138] For example, refer to Fig.12 The number of second intervals between two adjacent diode regions 30 in the second direction is 4, namely d5, d6, d7, and d8, and d6>d5 and d7>d8 ​​can be set.

[0139] Exemplarily, another semiconductor device is provided, referring to Fig.12 The first direction is the row direction, and the second direction is the column direction; in all the diode regions 30 located in the same column, the spacing between any two adjacent diode regions 30 is equal.

[0140] The above embodiment has the following beneficial effects: the spacing between any two adjacent diode regions 30 in all diode regions 30 in the same column is equal, the diode regions 30 are arranged at equal intervals along the second direction, the topological structure of the diode array is simplified, and the manufacturing is facilitated.

[0141] For example, any two adjacent second spacings in the second direction can be made equal to each other to simplify the setting difficulty. Fig.12 The number of second intervals between two adjacent diode regions 30 in the second direction is 4, namely d5, d6, d7, and d8, and d5=d6=d7=d8 can be set.

[0142] Exemplarily, another semiconductor device is provided, referring to Fig.10 , a spacing between two adjacent diode regions 30 in the first direction or the second direction is greater than half of the sum of the ring widths of the two diode regions 30 , and less than the sum of the ring widths of the two diode regions 30 .

[0143] The above embodiment has the following beneficial effects: by making the spacing between two adjacent diode regions 30 greater than half of the sum of the ring widths of the two diode regions 30, the second IGBT region 42 between the two diode regions 30 is wide enough, so that the heat diffused from the two diode regions 30 during operation can be promptly diffused to the semiconductor substrate 10, thereby improving the heat dissipation effect. In addition, the spacing between two adjacent diode regions 30 is controlled to be less than the sum of the ring widths of the two diode regions 30, thereby ensuring the heat dissipation effect while avoiding the diode regions 30 from being too sparsely arranged, thereby balancing the arrangement density and heat dissipation performance of the diode regions 30, ensuring the heat dissipation effect while also improving the arrangement density of the diode regions 30.

[0144] It should be noted that the ring width of the diode region 30 refers to: the minimum distance between the inner circle and the outer circle of the diode region 30 .

[0145] by Fig.10 For example, the spacing between two adjacent diode regions 30 in the first direction is m1, the ring width of the diode region 30 on the left of the two diode regions 30 is m2, and the ring width of the diode region 30 on the right is m3. Then the relationship between m1, m2 and m3 satisfies: (m2+m3) / 2<m1<m2+m3. Therefore, the heat dissipation capacity of the width m1 of the second IGBT region 42 between the two diode regions 30 in the first direction is sufficient to match the heat dissipation requirements of the half-ring width region of the two diode regions 30 close to it during operation, thereby improving the heat dissipation effect and avoiding the diode regions 30 from being too sparsely arranged in the first direction.

[0146] Continue with Fig.10 For example, the spacing between two adjacent diode regions 30 in the second direction is m6, the ring width of the lower diode region 30 of the two diode regions 30 is m2, and the ring width of the upper diode region 30 is m7. Then the relationship between m2, m6 and m7 satisfies: (m2+m7) / 2<m6<m2+m7. Therefore, the heat dissipation capacity of the width m6 of the second IGBT region 42 between the two diode regions 30 in the second direction is sufficient to match the heat dissipation requirements of the half-ring width region of the two diode regions 30 close to it during operation, thereby improving the heat dissipation effect and avoiding the diode regions 30 from being too sparsely arranged in the second direction.

[0147] Exemplarily, another semiconductor device is provided, referring to Fig.10 The width of each first IGBT region 41 in the first direction or the second direction is greater than the ring width of the diode region 30 surrounding it, and less than twice the ring width of the diode region 30 surrounding it.

[0148] The above embodiment has the following beneficial effects: the width of each first IGBT region 41 in the first direction or the second direction is greater than the ring width of the diode region 30 surrounding it, so that the first IGBT region 41 is wide enough, so that the heat diffused from the diode region 30 surrounding it during operation can be diffused to the semiconductor substrate 10 in a timely manner, thereby improving the heat dissipation effect. In addition, the width of each first IGBT region 41 is controlled to be less than twice the ring width of the diode region 30 surrounding it, so as to avoid the mismatch between the heat dissipation capacity and the heat dissipation demand between the excessive width of the first IGBT region 41 and the excessively narrow ring width of the diode region 30 while ensuring the heat dissipation effect, so that the heat dissipation capacity provided by the first IGBT region 41 and the heat dissipation demand required by the diode region 30 are matched, and the insufficient or excessive heat dissipation capacity of the first IGBT region 41 is avoided.

[0149] It should be noted that when the first IGBT region 41 is an irregular shape such as a circle or an ellipse, the width of the first IGBT region 41 in the first direction refers to: the maximum width of the first IGBT region 41 along the first direction. Correspondingly, the width of the first IGBT region 41 in the second direction refers to: the maximum width of the first IGBT region 41 along the second direction.

[0150] by Fig.10For example, the width of the first IGBT region 41 in the first direction is m4, and the ring width of the diode region 30 surrounding it is m3, then m3 and m4 satisfy: m3<m4<2*m3. Therefore, the heat dissipation capacity of the width m4 of the first IGBT region 41 in the first direction matches the heat dissipation requirement of the half-ring width region close to it in the diode region 30 surrounding it during operation, so that the heat diffused to it is promptly diffused to the semiconductor substrate 10, improving the heat dissipation effect. At the same time, it is prevented that the width of the first IGBT region 41 in the first direction is too large to cause excessive heat dissipation capacity.

[0151] by Fig.10 For example, the width of the first IGBT region 41 in the second direction is m5, and the ring width of the diode region 30 surrounding it is m3, then m3 and m5 satisfy: m3<m5<2*m3. Therefore, the heat dissipation capacity of the width m5 of the first IGBT region 41 in the second direction matches the heat dissipation demand of the half-ring width region close to it in the diode region 30 surrounding it during operation, so that the heat diffused to it is promptly diffused to the semiconductor substrate 10, improving the heat dissipation effect. At the same time, it is prevented that the width of the first IGBT region 41 in the second direction is too large to cause excessive heat dissipation capacity.

[0152] In some embodiments, another semiconductor device is provided, referring to Figure 1 When looking down at the semiconductor substrate 10 , the second IGBT regions 42 are distributed between adjacent diode regions 30 and outside the diode array to form a grid-shaped second IGBT region 42 .

[0153] Specifically, refer to Figure 1 The grids in the grid-shaped second IGBT region 42 are the locations where the diode region 30 and the first IGBT region 41 are set. The locations of the longitude and latitude lines of the grid are the locations of the body region of the second IGBT region 42. Of course, it should be noted that, referring to Figure 1 , the grid-shaped longitude and latitude may be vertical or substantially vertical, and the diode array in this case adopts an aligned array mode. In other embodiments, the grid-shaped longitude and latitude may not be vertically arranged, that is, the grid-shaped longitude and latitude may be arranged at an acute angle or an obtuse angle, and the diode array in this case may adopt a cross array mode. Of course, in other embodiments, an irregular grid shape may also be adopted as the top view shape of the second IGBT region 42.

[0154] The above embodiment has the following beneficial effects: by adopting the grid-shaped second IGBT region 42, any two adjacent diode regions 30 are completely separated by the second IGBT region 42, which is not only beneficial to increase the area of ​​the second IGBT region 42, but also beneficial to diffuse the heat generated by the diode region 30 to the edge position of the semiconductor substrate 10 along the extension direction of the longitude and latitude of the grid-shaped second IGBT region 42 after diffusing to the second IGBT region 42, thereby improving the heat dissipation efficiency.

[0155] In some embodiments, reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 7 , Figure 8 and Fig. 9 , a semiconductor device is proposed, the semiconductor device mainly comprising:

[0156] A semiconductor substrate 10, wherein the semiconductor substrate 10 is provided with a diode region 30, a first IGBT region 41, and a second IGBT region 42 between a first main surface and a second main surface opposite to the first main surface; when the semiconductor substrate 10 is viewed from above, the diode region 30 is annular in shape and surrounds the first IGBT region 41, and the second IGBT region 42 surrounds the diode region 30; the first IGBT region 41 is provided with a first active gate 43 on the first main surface side, and the second IGBT region 42 is provided with a second active gate 44 on the first main surface side;

[0157] A first interlayer dielectric layer 51 is disposed on the first main surface, a first plug 61 and a second plug 62 are disposed through the first interlayer dielectric layer 51, a first end of the first plug 61 is electrically connected to the first active gate 43, and a first end of the second plug 62 is electrically connected to the second active gate 44;

[0158] A gate runner includes a gate wiring portion and a gate pad portion 74 disposed on the first interlayer dielectric layer 51, the gate wiring portion electrically connecting the first plug 61 and the second end of the second plug 62, and the gate pad portion 74 electrically connecting the gate wiring portion;

[0159] A second interlayer dielectric layer 52 covers the gate runner, a fourth plug 64 is provided through the second interlayer dielectric layer 52, and a first end of the fourth plug 64 is electrically connected to the gate pad portion 74; and,

[0160] The gate pad 75 is disposed on the second interlayer dielectric layer 52 , and the gate pad 75 is electrically connected to the second end of the fourth plug 64 .

[0161] The above embodiment has the following beneficial effects: by setting the annular diode region 30, the IGBT region is distributed both inside and outside the annular diode region 30. When the diode is working, the heat generated by the diode can be evenly diffused to the first IGBT region 41 located inside the diode region 30 and the second IGBT region 42 located outside the diode region 30, thereby improving the heat dissipation uniformity of the diode, avoiding damage to some regions in the diode due to heat concentration, and reducing the failure rate of the semiconductor device. Since the diode region 30 completely separates the first active gate 43 in the first IGBT region 41 and the second active gate 44 in the second IGBT region 42, when the active gates of the IGBT regions are led out, the above embodiment sets a first interlayer dielectric layer 51, sets a first plug 61 and a second plug 62 electrically connecting the first active gate 43 and the second active gate 44 respectively in the first interlayer dielectric layer 51, and sets a gate wiring electrically connecting the first plug 61 and the second plug 62 on the first interlayer dielectric layer 51. A gate pad portion 74 electrically connected to the gate wiring portion is provided on the first interlayer dielectric layer 51, so that the gate pad 75 is electrically connected to the gate pad portion, thereby solving the problem of how to lead the active gate in the IGBT region to the gate pad 75 when the diode region 30 completely separates the first active gate 43 in the first IGBT region 41 and the second active gate 44 in the second IGBT region 42, so as to facilitate the reliable and stable application of gate voltage to the active gate in the IGBT region through the gate pad 75 and simplify the structure.

[0162] refer to Figure 1 and Figure 2 Since the diode region 30 completely separates the first IGBT region 41 from the second IGBT region 42, when the gate channel is directly disposed on the first main surface of the semiconductor substrate 10, a short circuit defect may occur, resulting in the gate channel being unable to be directly disposed on the first main surface of the semiconductor substrate 10. Figure 8 and Fig. 9 In the present application, the gate channel is separated from the first main surface of the semiconductor substrate 10 by a first interlayer dielectric layer 51 to avoid the defect of short circuit between the gate channel and the structure on the first main surface. The active gate in the IGBT region is led out through a plug provided in the first interlayer dielectric layer 51.

[0163] refer to Figure 3 and Figure 4 When there are multiple first IGBT regions 41, the arrangement and distribution of the multiple first IGBT regions 41 determine the extension position of the gate channel to a certain extent. It is necessary to ensure that at least part of the gate channel extends above each first IGBT region 41 so as to be able to electrically connect the first active gate 43 in the first IGBT region 41 through the first plug 61 in the first interlayer dielectric layer 51. Figure 3 , Figure 4 and Fig. 9 Specifically, the first end of the first plug 61 contacts the first active gate 43 to achieve electrical connection between the two, and the second end of the first plug 61 contacts the gate channel to achieve electrical connection. The first plug 61 can be formed by etching an opening in the first interlayer dielectric layer 51 to connect the first active gate 43, and then filling the opening with a material such as but not limited to a metal material to form the first plug 61. Exemplarily, the material of the first plug 61 can be metal tungsten.

[0164] Corresponding, reference Figure 3 and Figure 4 The number and distribution position of the second IGBT region 42 also determine the extension position of the gate flow channel, and it is also necessary to ensure that at least part of the gate flow channel extends above the second IGBT region 42 to electrically connect the active gate in the second IGBT region 42. The active gate in the second IGBT region 42 is electrically connected to the gate flow channel through the second plug 62 in the first interlayer dielectric layer 51. Figure 3 and Figure 4 Specifically, the first end of the second plug 62 contacts the second active gate 44 to achieve electrical connection between the two, and the second end of the second plug 62 contacts the gate channel to achieve electrical connection. The second plug 62 can be formed by etching an opening in the first interlayer dielectric layer 51 to connect the second active gate 44, and then filling the opening with a material such as but not limited to a metal material to form the second plug 62. Exemplarily, the material of the second plug 62 can be metal tungsten.

[0165] Of course, the number and arrangement of active gates in different IGBT regions also determine the extension of the gate channel to a certain extent, and it is necessary to ensure that each active gate can be electrically connected to the gate channel through the plug structure. The following is an exemplary introduction to some gate channel arrangement methods.

[0166] In some embodiments, another semiconductor device is provided, referring to Figure 3 and Figure 4, the number of the first plugs 61 and the number of the second plugs 62 are both multiple, the multiple first plugs 61 are arranged in at least two rows along the second direction, and the multiple second plugs 62 are arranged in at least two rows along the second direction. The gate wiring portion includes: a plurality of first gate wiring portions 71, a plurality of second gate wiring portions 72, and a gate wiring confluence portion 73; wherein the first gate wiring portions 71 all extend along the second direction and are arranged at intervals along the first direction, and the first gate wiring portions 71 are electrically connected to the second ends of the first plugs 61 in the same row; the second gate wiring portions 72 all extend along the second direction and are arranged at intervals along the first direction, and the second gate wiring portions 72 are electrically connected to the second ends of the second plugs 62 in the same row; the gate wiring confluence portion 73 is electrically connected to the gate pad portion 74, the gate wiring confluence portion 73 extends along the first direction and is located on the first side outside the diode array; the gate wiring confluence portion 73 electrically connects the first ends of the first gate wiring portions 71 and the second gate wiring portions 72 to form a first comb structure.

[0167] The above-mentioned embodiment has the following beneficial effects: by adopting the gate wiring portion constituting the first comb-tooth structure, the first gate wiring portion 71 extends above all the first IGBT regions 41 in the same arrangement direction parallel to the second direction to electrically connect the second end of the first plug 61 located in the same arrangement direction; the second gate wiring portion 72 extends above the second IGBT region 42 between two adjacent diode regions 30 to electrically connect the second end of the second plug 62 located in the same arrangement direction, and then the first gate wiring portion 71 and the second gate wiring portion 72 as the comb teeth can be indirectly electrically connected to the gate pad portion 74 through the gate wiring confluence portion 73 as the comb handle, thereby realizing the electrical connection between the first plug 61 and the second plug 62 at different positions and the gate pad portion 74, thereby simplifying the structure of the gate wiring portion.

[0168] Specifically, refer to Figure 3 and Figure 4 When the diode array adopts an aligned array or a staggered array, taking the first direction as the row direction and the second direction as the column direction as an example, if there are at least two first IGBT regions 41 in the same column, a first gate wiring portion 71 can be extended to the top of these first IGBT regions 41 to achieve electrical connection with the active gates in these first IGBT regions 41 through the first plugs 61 in the first interlayer dielectric layer 51. Exemplarily, the first plugs 61 corresponding to the first IGBT regions 41 in the same column can be arranged in the same column.

[0169] Correspondingly, the second IGBT region 42 is distributed between the two columns of diode regions 30, and a second gate wiring portion 72 can be extended to the upper part of the second IGBT region 42 located between the two columns of diode regions 30, so as to realize electrical connection with the active gates in the second IGBT region 42 at these positions through the second plugs 62 in the first interlayer dielectric layer 51. Exemplarily, the second plugs 62 corresponding to the second IGBT region 42 between the two columns of diode regions 30 can be arranged in the same column.

[0170] The first ends of the first gate wiring section 71 and the second gate wiring section 72 are both located on the first side outside the diode array (for example, Figure 3 and Figure 4 The first side shown is the upper side outside the diode array), so that at least part of the first gate wiring portion 71 and the second gate wiring portion 72 are directly contacted and electrically connected to the same gate wiring bus portion 73, forming a first comb tooth structure that is comb-tooth-shaped when viewed from above, thereby realizing mutual electrical connection between all active gates, so as to facilitate the application of gate voltage to all active gates at the same time.

[0171] In some embodiments, another semiconductor device is provided, referring to Figure 4 The gate pad portion 74 is located at the intersection of the gate wiring converging portion 73 and the outermost second gate wiring portion 72 among the plurality of second gate wiring portions 72, and is also electrically connected to the first end of the outermost second gate wiring portion 72. When the gate pad portion 74 and the second active gate 44 are viewed from above, the first portion of the gate pad portion 74 overlaps with the second portion of the second active gate 44, and the first end and the second end of some of the second plugs 62 among the plurality of second plugs 62 are electrically connected to the second portion and the first portion, respectively.

[0172] The above embodiment has the following beneficial effects: by arranging the gate pad portion 74 at the intersection of the gate wiring confluence portion 73 and the outermost second gate wiring portion 72, it is convenient to realize the electrical connection between the gate pad portion 74 and the gate wiring portion, and the gate pad 75 portion can also be correspondingly arranged above the gate pad portion 74, so that the gate pad 75 is located at a corner above the diode array, and a larger whole area can be reserved for the emitter pad 82. By arranging the first part of the gate pad portion 74 and the second part of the second active gate 44 to overlap, a larger area of ​​the gate pad portion 74 and the gate pad 75 can be arranged, thereby improving the current carrying capacity. At this time, the second part of the second active gate 44 can be directly electrically connected to the first part of the gate pad portion 74 through the second plug 62, without the need to rely on the second gate wiring portion 72 and the gate wiring confluence portion 73, thereby shortening the current path length when the second active gate 44 connected with the second part is energized.

[0173] Exemplary, reference Figure 4 The gate pad portion 74 is located at the intersection of the gate wiring converging portion 73 and the second gate wiring portion 72 on the far left. It should be noted that the gate pad portion 74 is not limited to this position. For example, the gate pad portion 74 can also be located at the intersection of the gate wiring converging portion 73 and the second gate wiring portion 72 on the far right.

[0174] It should also be noted that the gate pad portion 74 is not limited to being located at the intersection of the gate wiring confluence portion 73 and the outermost second gate wiring portion 72 among the plurality of second gate wiring portions 72, and can be located at any position of the first comb-tooth structure, for example, it can be located at the intersection of the gate wiring confluence portion 73 and any first gate wiring portion 71, or at the intersection of the third wiring portion and any second gate wiring portion 72. In some embodiments, the gate pad portion 74 can even be located at the end of one of the first gate wiring portions 71 or the second gate wiring portion 72. That is, as long as the electrical connection between the first comb-tooth structure and the gate pad portion 74 can be achieved, it is within the protection scope of the present application.

[0175] Exemplary, reference Figure 3 and Figure 4 The gate pad portion 74 has a larger area and covers part of the second active gate 44 in a plan view. The portion of the gate pad portion 74 overlapping with the second active gate 44 can be defined as the first portion of the gate pad portion 74, and the portion of the second active gate 44 overlapping with the gate pad portion 74 can be defined as the second portion of the second active gate 44. Figure 3 and Figure 4 , the second active gate 44 with the second portion is the two second active gates 44 located at the uppermost side. Since the first portion and the second portion overlap each other, part of the second plug 62 can be directly disposed between the first portion and the second portion, thereby electrically connecting the gate pad portion 74 and part of the second active gate 44, so as to shorten the current path length when power is supplied between the gate pad portion 74 and the second active gate 44 with the second portion. And the gate pad portion 74 can be disposed in a larger area.

[0176] In some embodiments, another semiconductor device is provided, referring to Figure 4 , a plurality of first gate wiring portions 71 and a plurality of second gate wiring portions 72 are staggered along the first direction. Specifically, at least two columns of first plugs 61 and at least two columns of second plugs 62 are also staggered along the first direction, so that the staggered plurality of first gate wiring portions 71 and a plurality of second gate wiring portions 72 are electrically connected to the second ends of a corresponding column of first plugs 61 and the second ends of a corresponding column of second plugs 62, respectively.

[0177] The above embodiment has the following beneficial effects: by staggering the first gate wiring portion 71 and the second gate wiring portion 72 along the first direction, it is convenient to realize electrical connection between the first active gate 43 and the second active gate 44 at different positions and the gate wiring confluence portion 73 serving as a comb handle, thereby facilitating the extraction of the active gate and simplifying the structure.

[0178] Specifically, refer to Figure 3 and Figure 4 , since the diode regions 30 in different columns (taking the second direction as the column direction as an example) are separated by the second IGBT region 42, and the second IGBT region 42 between two diode regions 30 in the arrangement direction parallel to the first direction is also separated by the diode region 30. The first IGBT region 41 is arranged inside each column of diode regions 30. Therefore, when the first gate wiring portion 71 and the plurality of second gate wiring portions 72 are arranged alternately along the first direction, the second gate wiring portion 72 can be extended to the top of the second IGBT region 42 between the diode regions 30 of different types, so as to facilitate the electrical connection of the active gates at these positions, simplify the lead-out method of the active gates, and can be applicable to various types of extended arrangement methods of the active gates.

[0179] Regarding the manner of setting the active gate in the first IGBT region 41 and the second IGBT region 42 , various manners may be adopted, and some manners are exemplarily introduced as follows.

[0180] In some embodiments, another semiconductor device is provided, referring to Figure 3 , Figure 4 and Fig. 9 The first IGBT region 41 is provided with a plurality of first active gates 43 extending along the first direction and arranged at intervals along the second direction, each first active gate 43 corresponds to a first plug 61 and is electrically connected to the first end of the corresponding first plug 61; the second IGBT region 42 is provided with a plurality of second active gates 44 extending along the first direction and arranged at intervals along the second direction, each second active gate 44 corresponds to a second plug 62 and is electrically connected to the first end of the corresponding second plug 62.

[0181] The above embodiment has the following beneficial effects: by making all the first active gates 43 extend along the first direction and be arranged at intervals along the second direction, it is convenient for the first gate wiring portion 71 extending along the second direction to be electrically connected to all the first active gates 43 in the same arrangement direction parallel to the second direction through the first plug 61; by making all the second active gates 44 extend along the first direction and be arranged at intervals along the second direction, it is convenient for the second gate wiring portion 72 extending along the second direction to be electrically connected to all the second active gates 44 in the same arrangement direction parallel to the second direction through the second plug 62. The difficulty of electrical connection between the gate wiring portion and all the active gates is simplified.

[0182] Exemplary, reference Figure 2 , Figure 8 and Fig. 9 , four first active gates 43 may be provided in the first IGBT region 41. Of course, it should be noted that the number of first active gates 43 provided in each first IGBT region 41 is not limited to four, and can also be any value not less than one.

[0183] It should be noted that the arrangement of the active gate in the IGBT region is not limited to the above-mentioned arrangement. In addition, other arrangements may be adopted. For example, in some embodiments, the active gate in the first IGBT region 41 may be arranged in a circular manner, and the number of the circular active gates may be one or more. When the number of the circular active gates is multiple, the multiple circular active gates may be arranged at intervals along the second direction, or an arrangement similar to a "concentric circle" arrangement may be adopted, which is arranged concentrically and at intervals from the center of the first IGBT region 41 to the outside. As long as each active gate is electrically connected to the gate wiring portion through the first plug 61, it is within the protection scope of the present application. Correspondingly, the active gate in the second IGBT region 42 may also be extended in a manner such as, but not limited to, a circular manner, and it may be distributed at intervals in the second IGBT region 42 in any manner, and as long as each active gate is electrically connected to the gate wiring portion through the second plug 62, it is within the protection scope of the present application.

[0184] As mentioned above, reference Figure 7 and Figure 8 , the first main surface side of the semiconductor substrate 10 is not limited to the active gate. The first main surface side of the semiconductor substrate 10 can also be provided with an emitter region 45, a contact region 46, an anode region 31, a virtual gate 33, etc. These structures all need to be electrically connected to the emitter pad 82 of the semiconductor device to apply an emitter voltage to these structures. When realizing the electrical connection between these structures and the emitter pad 82, it is also necessary to electrically connect the structures distributed at different positions on the first main surface side to each other first, so as to facilitate the electrical connection of the emitter pad 82. Specifically, the emitter region 45, the contact region 46, the anode region 31, the virtual gate 33 and other structures at different positions on the first main surface side can be electrically connected to each other through the emitter flow channel. There are many ways to set up the emitter flow channel, and some of the methods are introduced as examples below.

[0185] In some embodiments, another semiconductor device is provided, referring to Figure 4 , Figure 5 and Figure 8The semiconductor device further includes: an emitter flow channel, including an emitter wiring bus 80 and a plurality of emitter wiring parts 81 arranged on the first interlayer dielectric layer 51, the plurality of emitter wiring parts 81 all extend along the second direction and are arranged at intervals along the first direction, the emitter wiring bus 80 extends along the first direction and is located on the second side of the diode array; the emitter wiring bus 80 is electrically connected to the first ends of the plurality of emitter wiring parts 81 to form a second comb tooth structure; wherein the second side is opposite to the first side, and the first comb tooth structure and the second comb tooth structure are relatively staggered and arranged at intervals.

[0186] The above embodiment has the following beneficial effects: by setting the emitter flow channel constituting the second comb-tooth structure, it is convenient to electrically connect the contact area 46 and the emitter area 45 located in the first IGBT region 41 and the second IGBT region 42 to the emitter flow channel, and it is also convenient to electrically connect the anode area 31 located in the diode region 30 to the emitter flow channel.

[0187] Specifically, the number of emitter wiring sections 81 can be 5, 8, 10, etc., which is specifically related to the number of similar comb teeth in the first comb tooth structure. It is necessary to ensure that an emitter wiring section 81 is provided between any two comb teeth in the first comb tooth structure to electrically connect structures such as but not limited to the emitter region 45, the contact region 46, the anode region 31, the virtual gate 33, etc. located below these positions. The emitter wiring sections 81 all extend along the second direction, and the first ends of several emitter wiring sections 81 are all connected to the emitter wiring bus 80 extending along the first direction and located on the second side of the diode array, thereby forming an integral second comb tooth structure.

[0188] It should be noted that the second side of the diode array is not limited to the second side outside the diode array, it can be a position directly above the diode array close to the second side, or it can be the second side outside the diode array, and the connection width between different emitter wiring parts 81 in the second direction can be as wide as possible, so as to improve the current carrying capacity. Figure 5 , the first side of the diode array is the upper side, and the second side of the diode region 30 is the lower side opposite to the upper side.

[0189] Of course, the width of the emitter wiring portion 81 in the first direction may also be as wide as possible to improve the current carrying capacity of the entire emitter wiring portion 81.

[0190] In some embodiments, another semiconductor device is provided, referring to Figure 5When looking down at the first comb tooth structure and the second comb tooth structure, the first comb tooth structure is a narrow comb tooth structure relative to the second comb tooth structure, and the second comb tooth structure is a wide comb tooth structure relative to the first comb tooth structure. Specifically, the width of the emitter wiring portion 81 in the first direction is greater than the width of the first gate wiring portion 71 and the second gate wiring portion 72 in the first direction. For example, refer to Figure 5 , the width of the emitter wiring section 81 in the first direction is d9, the width of the first gate wiring section 71 and the second gate wiring section 72 in the first direction are both d10, and d9 is greater than d10. And the width of the emitter wiring bus section 80 in the second direction is greater than the width of the gate wiring bus section 73 in the second direction, so as to improve the current flow capacity of the emitter wiring bus section 80.

[0191] The above embodiment has the following beneficial effects: the first comb tooth structure is set as a narrow comb tooth structure, and the second comb tooth structure is set as a wide comb tooth structure, so that the area of ​​the emitter flow channel can be increased, thereby improving the current flow capacity of the emitter flow channel.

[0192] refer to Figure 4 , Figure 5 and Figure 8 To prevent the emitter flow channel from short-circuiting with the active gate, the emitter flow channel is disposed above the first interlayer dielectric layer 51, and the emitter flow channel can be electrically connected to structures such as but not limited to the emitter region, the contact region 46, and the anode region 31 disposed on the first main surface side through a plug in the first interlayer dielectric layer 51. Some exemplary methods are introduced as follows.

[0193] In some embodiments, another semiconductor device is provided, referring to Figure 4 , Figure 5 and Figure 8 A third plug 63 is also provided in the first interlayer dielectric layer 51, and a first end of the third plug 63 is electrically connected to the first conductive type emitter region 45 provided on the first main surface side, and the second conductive type contact region 46 and the anode region 31, and a second end of the third plug 63 is electrically connected to the emitter channel; when looking down at the third plug 63, the third plug 63 extends along the first direction, and the third plug 63 is disconnected at a position below the gate wiring portion.

[0194] Specifically, refer to Figure 4 , Figure 5 and Figure 8The first end of the third plug 63 faces the first main surface side and is in direct contact with the emitter region 45, the contact region 46 and the anode region 31 on the first main surface side to be electrically connected, and the second end of the third plug 63 faces the emitter flow channel and is in direct contact with the emitter flow channel to be electrically connected. The top view shape of the third plug 63 is a strip extending along the first direction, and the third plug 63 is disconnected at a position below the gate wiring part, so that when the first direction is the row direction, the third plugs 63 in the same row have multiple sections of third plugs 63 that are disconnected from each other.

[0195] The above embodiment has the following beneficial effects: by providing a strip-shaped structure extending along the first direction as the third plug 63, the cross-sectional area of ​​the third plug 63 can be increased, which facilitates the electrical connection between the third plug 63 and the emitter region 45, the contact region 46 and the anode region 31, and can also improve the current flow capacity; and the third plug 63 is disconnected at a position below the gate wiring portion, thereby preventing a short circuit defect between the third plug 63 and the gate wiring portion.

[0196] When the third plug 63 is provided, an etching process may be used to form a strip-shaped opening extending along the first direction in the first interlayer dielectric layer 51, and the opening is connected to the anode region 31, the contact region 46 and the emitter region 45 on the first main surface side. Then, the third plug 63 is formed by filling the opening with a material such as but not limited to a metal material. Exemplarily, the material of the third plug 63 may be metal tungsten.

[0197] In some embodiments, reference Figure 8 The diode region 30 may only have an anode region 31 on the first main surface. In other embodiments, a contact region may be provided in the anode region 31 of the diode region 30 and the contact region is also exposed on the first main surface to be electrically connected to the first end of the third plug 63 .

[0198] Exemplarily, a P+ type contact region is provided on the first main surface side of the P-type anode region 31. The concentration of the P-type impurity in the P+ type contact region can be set to the same concentration as the P-type impurity in the P+ type contact region of the IGBT region, or can be set to a different concentration. When it is necessary to distinguish the P+ type contact region and the P-type anode region 31, each can be referred to separately, or the P+ type contact region and the P-type anode region 31 can be collectively referred to as the anode region 31.

[0199] In some embodiments, reference Figure 8 The first IGBT region 41 and the second IGBT region 42 may be provided with an emitter region 45 and a contact region 46 on the first main surface side. Any arrangement method may be adopted for the emitter region 45 and the contact region 46, as long as both the emitter region 45 and the contact region 46 have exposed areas on the first main surface side and are electrically connected to the first end of the third plug 63.

[0200] Exemplary, reference Figure 8 The portion of the first active gate 43 exposed on the first main surface side is separated from the third plug 63 and the emitter wiring portion 81 by the first interlayer dielectric layer 51, thereby achieving insulation isolation between them.

[0201] In some embodiments, another semiconductor device is provided, referring to Figure 2 , Figure 3 and Figure 5 A virtual gate 33 exposed on the first main surface side is provided in the diode region 30, and a sixth plug 66 is also provided in the first interlayer dielectric layer 51. The first end of the sixth plug 66 is electrically connected to the virtual gate 33 provided on the first main surface side, and the second end of the sixth plug 66 is electrically connected to the emitter flow channel. Specifically, the first end of the sixth plug 66 is in contact and electrically connected with the virtual gate 33, and the second end of the sixth plug 66 is in contact and electrically connected with the emitter flow channel, so as to realize the electrical connection between the virtual gate 33 provided in the diode region 30 and the emitter flow channel.

[0202] Regarding the setting method of the virtual gate 33, various methods can be adopted, and some methods are introduced as follows. Figure 2 , there are a plurality of virtual gates 33, each of which extends along the first direction, and all of the virtual gates 33 are arranged at intervals along the second direction. Figure 2 , Figure 3 and Figure 5 , each virtual gate 33 is electrically connected to the emitter flow channel through a sixth plug 66. Of course, in other embodiments, the extension direction of the virtual gate 33 can also extend along the first direction and be arranged at intervals along the second direction. Even in some embodiments, the top view shape of the virtual gate 33 can also be annular, and the number of virtual gates 33 is multiple, and the multiple virtual gates 33 are concentrically arranged from the inner circle to the outer circle of the annular diode region 30.

[0203] In some embodiments, another semiconductor device is provided, referring to Figure 5-Figure 9 The semiconductor device further includes: an emitter pad 82, which is disposed on the second interlayer dielectric layer 52 and spaced apart from the gate pad 75; the second interlayer dielectric layer 52 also covers the emitter flow channel, and a fifth plug 65 is also penetrated in the second interlayer dielectric layer 52; when looking down at the fifth plug 65 and the second comb-tooth structure, the shape of the fifth plug 65 is comb-tooth-shaped, and the outline of the second comb-tooth structure surrounds the outline of the fifth plug 65; the first end of the fifth plug 65 is electrically connected to the emitter flow channel, and the second end of the fifth plug 65 is electrically connected to the emitter pad 82.

[0204] The above embodiment has the following beneficial effects: by providing the comb-tooth-shaped fifth plug 65 , the contour of the second comb-tooth structure surrounds the contour of the fifth plug 65 , thereby increasing the cross-sectional area of ​​the fifth plug 65 and thus improving the current carrying capacity of the fifth plug 65 .

[0205] Exemplary, reference Figure 5-Figure 9 The gap between the emitter flow channel and the gate flow channel is filled with a dielectric material, that is, the gap between the first comb-tooth structure and the second comb-tooth structure is filled with a dielectric material, thereby achieving insulation isolation between each other.

[0206] When setting the fifth plug 65, refer to Figure 6 First, an opening for setting the fifth plug 65 is formed in the second interlayer dielectric layer 52, and the surface of the emitter flow channel is exposed in the opening. Then, the fifth plug 65 is formed by filling the opening with a conductive material such as but not limited to a metal material, so that the first end of the fifth plug 65 is in contact with and electrically connected to the emitter flow channel. Exemplarily, the material of the fifth plug 65 is metal tungsten. Figure 6 Since the top view shape of the fifth plug 65 is comb-tooth shaped, the top view shape of the opening for setting the fifth plug 65 is also comb-tooth shaped, and the outline of the second comb-tooth structure surrounds the outline of the opening for setting the fifth plug 65, so that the top view shape of the fifth plug 65 formed subsequently is also comb-tooth shaped. After the fifth plug 65 is formed in the second interlayer dielectric layer 52, an emitter pad 82 in contact with the fifth plug 65 can be formed on the second interlayer dielectric layer 52.

[0207] refer to Figure 6, the shape and size of the fourth plug 64 are specifically related to the shape and size of the gate pad portion 74. When setting the fourth plug 64, it is necessary to first form an opening in the second interlayer dielectric layer 52 above the gate pad portion 74 by etching to ensure that the surface of the gate pad portion 74 is exposed to the opening, and then the fourth plug 64 is formed by filling the opening with a conductive material such as but not limited to a metal material, so that the first end of the fourth plug 64 is in contact with and electrically connected to the gate pad portion 74. Exemplarily, the material of the fourth plug 64 is metal tungsten. The gate pad portion 74 is wider than the width of the gate wiring portion, so as to provide support for the setting of the fourth plug 64. And because the fourth plug 64 does not need to be in contact with and electrically connected to the gate wiring portion, the difficulty of aligning the opening in the second interlayer dielectric layer 52 when setting the fourth plug 64 is also reduced. In a more preferred embodiment, it is necessary to ensure that when the fourth plug 64 and the gate pad 74 are viewed from above, the outline of the gate pad 74 surrounds the outline of the fourth plug 64, and the size of the fourth plug 64 is set as large as possible to improve the current flow capacity. After the fourth plug 64 is formed in the second interlayer dielectric layer 52, a gate pad 75 that is in contact with the fourth plug 64 can be formed on the second interlayer dielectric layer 52.

[0208] For example, when the emitter pad 82 and the gate wiring portion are viewed from above, the emitter pad 82 and the gate wiring portion are at least partially overlapped.

[0209] The above embodiment has the following beneficial effect: by making the emitter pad 82 overlap at least part of the gate wiring portion, a larger emitter pad 82 can be provided to improve the current flow capacity of the emitter pad 82 .

[0210] Exemplary, reference Figure 7 The shape of the emitter pad 82 is a quasi-rectangular shape with a missing corner, and a gate pad 75 is provided at the missing corner, and the gate pad 75 is spaced apart from the emitter pad 82 to increase the area of ​​the emitter pad 82 and improve its current carrying capacity.

[0211] Exemplarily, the gap between the emitter pad 82 and the gate pad 75 may be filled with an insulating material to achieve insulation isolation.

[0212] It should be noted that the above only exemplifies the arrangement of the first plug 61 to the sixth plug 66. In addition, other arrangements may be used. For example, after forming an opening for arranging the plug in the interlayer dielectric layer, before filling the conductive material, a barrier metal may be formed at the bottom of the opening, and then the conductive material may be filled to form the plug. This process is particularly suitable for the first plug 61, the second plug 62, the third plug 63, and the sixth plug 66, which are plugs that are directly in contact with the first main surface side, so that there is a barrier metal on the side of these plugs that is in contact with the semiconductor substrate 10. The type of conductive material is not limited to a single material layer. In some embodiments, a plug structure formed by stacking multiple conductive material layers may be used. For example, tungsten may be buried in a manner that is in contact with the barrier metal, and a plug structure may be formed on the tungsten by a conductive material such as aluminum.

[0213] Exemplarily, the material of the first interlayer dielectric layer 51 and the second interlayer dielectric layer 52 may be a silicon dioxide film, or an interlayer insulating film including other materials (eg, a BPSG film) may be further provided on the silicon dioxide.

[0214] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein a diode region, a first IGBT region, and a second IGBT region are provided between a first main surface and a second main surface opposite to the first main surface; When the semiconductor substrate is viewed in a plan view, the diode region has a ring shape and surrounds the first IGBT region, and the second IGBT region surrounds the diode region.

2. The semiconductor device according to claim 1, wherein The number of the diode regions and the number of the first IGBT regions are both multiple, and the multiple diode regions are arranged in an array spaced apart along the first direction and the second direction to form a diode array; wherein the first direction and the second direction are arranged crosswise; When the semiconductor substrate is viewed from above, each of the diode regions corresponds to one of the first IGBT regions and surrounds the corresponding first IGBT region.

3. The semiconductor device according to claim 2, wherein: The diode array has a first symmetry line parallel to the second direction; As the first IGBT region closest to the first symmetry line moves toward the first IGBT region closest to the edge of the diode array in the first direction, the area of ​​the first IGBT region gradually decreases.

4. The semiconductor device according to claim 3, wherein: The first direction is a row direction, the second direction is a column direction, and the areas of all the diode regions in the same row are equal; or, As the diode region closest to the first symmetry line moves toward the diode region closest to the edge of the diode array in the first direction, the area of ​​the diode region gradually increases.

5. The semiconductor device according to any one of claims 2 to 4, wherein: The diode array has a second symmetry line parallel to the first direction; As the first IGBT region closest to the second symmetry line moves toward the first IGBT region closest to the edge of the diode array in the second direction, the area of ​​the first IGBT region gradually decreases.

6. The semiconductor device according to claim 5, wherein: The first direction is a row direction, the second direction is a column direction, and the areas of all the diode regions in the same column are equal; or, As the diode region closest to the second symmetry line moves toward the diode region closest to the edge of the diode array in the second direction, the area of ​​the diode region gradually increases.

7. The semiconductor device according to any one of claims 2 to 4, wherein: The first direction is a row direction, and the second direction is a column direction; The areas of all the first IGBT regions in the same column are equal; All the diode regions in the same column have the same area.

8. The semiconductor device according to any one of claims 2 to 7, wherein: The diode array has a first symmetry line parallel to the second direction; The distance between two adjacent diode regions in the first direction gradually decreases from being close to the first symmetry line to being far away from the first symmetry line.

9. The semiconductor device according to claim 8, wherein: The first direction is the row direction, and the second direction is the column direction; in all the diode regions located in the same column, the spacing between any two adjacent diode regions is equal; or, The semiconductor substrate has a second symmetry line parallel to the first direction; the distance between two adjacent diode regions in the second direction gradually decreases from close to the second symmetry line to far away from the second symmetry line.

10. The semiconductor device according to any one of claims 2 to 9, wherein: The spacing between two adjacent diode regions in the first direction or the second direction is greater than half of the sum of the ring widths of the two diode regions and less than the sum of the ring widths of the two diode regions; and / or, The width of each of the first IGBT regions in the first direction or the second direction is greater than the ring width of the diode region surrounding it, and less than twice the ring width of the diode region surrounding it.

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