Heterojunction battery and preparation method thereof

Abstract

The invention discloses a heterojunction battery and a preparation method thereof. The preparation method of the heterojunction battery comprises the following steps: providing a semiconductor substrate layer; forming a tunneling dielectric film on at least one side surface of the semiconductor substrate layer, wherein a plurality of micropores are formed in the tunneling dielectric film; and forming a doped semiconductor layer on the surface of one side, deviating from the semiconductor substrate layer, of the tunneling dielectric film. According to the preparation method of the heterojunction cell, the parasitic light absorption of the heterojunction cell can be reduced, the conductivity is improved, and the conversion efficiency of the heterojunction cell is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a heterojunction cell and a preparation method thereof. Background Art

[0002] Heterojunction cells combine the advantages of crystalline silicon cells and thin-film cells, and have the advantages of simple structure, low process temperature, good passivation effect, high open circuit voltage, good temperature characteristics, and double-sided power generation. They are one of the hot spots for high conversion efficiency silicon-based solar cells. However, although amorphous silicon in existing heterojunction cells has a good passivation effect, it has parasitic light absorption and poor conductivity, which have become factors restricting the improvement of heterojunction cell conversion efficiency.

[0003] Therefore, the existing preparation method of heterojunction batteries needs to be improved. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the problem in the prior art that it is difficult to improve the conversion efficiency of heterojunction cells due to parasitic light absorption and poor conductivity.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a heterojunction battery, comprising: providing a semiconductor substrate layer; forming a tunneling dielectric film on at least one side surface of the semiconductor substrate layer, wherein the tunneling dielectric film has a plurality of micropores; and forming a doped semiconductor layer on the side surface of the tunneling dielectric film away from the semiconductor substrate layer.

[0006] Optionally, the step of forming the tunneling dielectric film includes: forming an initial dielectric film on at least one side surface of the semiconductor substrate layer; and annealing the initial dielectric film to form the tunneling dielectric film from the initial dielectric film.

[0007] Optionally, the process of forming the initial dielectric film includes an oxidation process, and the oxidation process is performed in a thermal oxygen furnace.

[0008] Optionally, the parameters of the oxidation process include: the gas used includes oxygen, the concentration of oxygen is 1slm-1000slm, the temperature is 650°C-970°C, and the oxidation time is 5 minutes-180 minutes.

[0009] Optionally, in the oxidation process, the temperature used is 800° C. and the oxidation time is 35 minutes.

[0010] Optionally, the parameters of the annealing treatment include: a temperature of 600° C.-950° C. and a time of 1 minute-80 minutes.

[0011] Optionally, in the annealing treatment, the temperature used is 750° C. and the annealing time is 40 minutes.

[0012] Optionally, the thickness of the tunnel dielectric film is 1 nm-10 nm.

[0013] Optionally, the material of the tunnel dielectric film includes silicon oxide.

[0014] Optionally, the diameter of the micropore is 1nm-500nm.

[0015] Optionally, the micropores are evenly distributed.

[0016] Optionally, the ratio of the surface area of ​​the micropores to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is 1%-30%. Optionally, the step of forming a tunneling dielectric film on at least one side surface of the semiconductor substrate layer includes: forming a first tunneling dielectric film on one side surface of the semiconductor substrate layer; forming a second tunneling dielectric film on the other side surface of the semiconductor substrate layer; the step of doping a semiconductor layer on the side surface of the tunneling dielectric film away from the semiconductor substrate layer includes: forming a first doped semiconductor layer on the side surface of the first tunneling dielectric film away from the semiconductor substrate layer; forming a second doped semiconductor layer on the side surface of the second tunneling dielectric film away from the semiconductor substrate layer.

[0017] Optionally, the thickness of the first doped semiconductor layer is 5nm-15nm; the thickness of the second doped semiconductor layer is 5nm-15nm.

[0018] Optionally, the conductivity type of the first doped semiconductor layer is P type, and the process for forming the first doped semiconductor layer is a plasma chemical vapor deposition process. The parameters for forming the first doped semiconductor layer include: the gases used include silane, hydrogen and diborane, the flow rate of silane is 1sccm-10000sccm, the flow rate of hydrogen is 0.1slm-50slm, the flow rate of diborane is 1sccm-8000sccm, the chamber pressure is 1mbar-1000mbar, and the temperature is 50℃-300℃.

[0019] Optionally, the conductivity type of the second doped semiconductor layer is N-type, and the process for forming the second doped semiconductor layer is a plasma chemical vapor deposition process. The parameters for forming the second doped semiconductor layer include: the gases used include silane, hydrogen and phosphine, the flow rate of silane is 1sccm-10000sccm, the flow rate of hydrogen is 0.1slm-50slm, the flow rate of phosphine is 1sccm-8000sccm, the chamber pressure is 1mbar-1000mbar, and the temperature is 50℃-300℃.

[0020] Optionally, it also includes: forming a gate line on the side of the doped semiconductor layer away from the semiconductor substrate layer; after forming the gate line, performing a light injection annealing treatment, the light injection annealing treatment includes a first temperature zone light injection annealing treatment to an Nth temperature zone light injection annealing treatment performed in sequence, N is an integer greater than or equal to 1; the temperature of the first temperature zone light injection annealing treatment to the Nth temperature zone light injection annealing treatment is 100°C-250°C.

[0021] Optionally, N is an integer equal to or greater than 8, the temperature of the first temperature zone annealing treatment to the third temperature zone annealing treatment is 138℃-142℃, the temperature of the fourth temperature zone annealing treatment to the sixth temperature zone annealing treatment is 155℃-175℃, and the temperature of the sixth temperature zone annealing treatment to the Nth temperature zone annealing treatment is 145℃-155℃.

[0022] The present invention also provides a heterojunction battery, comprising a semiconductor substrate layer; a tunneling dielectric film located on at least one side surface of the semiconductor substrate layer, wherein the tunneling dielectric film has a plurality of micropores; and a doped semiconductor layer located on one side surface of the tunneling dielectric film away from the semiconductor substrate layer.

[0023] Optionally, the thickness of the tunnel dielectric film is 1 nm-10 nm.

[0024] Optionally, the material of the tunnel dielectric film includes silicon oxide.

[0025] Optionally, the diameter of the micropore is 1nm-500nm.

[0026] Optionally, the ratio of the surface area of ​​the micropores to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is 1%-30%.

[0027] Optionally, the tunneling dielectric film includes: a first tunneling dielectric film located on one side surface of the semiconductor substrate layer; a second tunneling dielectric film located on the other side surface of the semiconductor substrate layer; the doped semiconductor layer includes: a first doped semiconductor layer located on a side surface of the first tunneling dielectric film away from the semiconductor substrate layer; and a second doped semiconductor layer located on a side surface of the second tunneling dielectric film away from the semiconductor substrate layer.

[0028] Optionally, the thickness of the first doped semiconductor layer is 5nm-15nm; the thickness of the second doped semiconductor layer is 5nm-15nm.

[0029] The technical solution of the present invention has the following advantages: The preparation method of the heterojunction battery provided by the present invention forms a tunnel dielectric film on at least one side surface of the semiconductor substrate layer, and the tunnel dielectric film can passivate the semiconductor substrate layer, thereby increasing the open circuit voltage; the tunnel dielectric film has a plurality of micropores, and the tunnel dielectric film has a tunneling characteristic, which can enable carriers to tunnel through the tunnel dielectric film. Secondly, the micropores in the tunnel dielectric film can provide a channel for carrier migration, thereby improving the carrier transportation capacity, thereby increasing the short-circuit current and improving the conductivity of the heterojunction battery; the tunnel dielectric film replaces the amorphous silicon intrinsic layer of the heterojunction battery in the prior art. Compared with intrinsic amorphous silicon, the tunnel dielectric film has very little parasitic light absorption, which will promote more light to enter the substrate, which is beneficial to increasing the short-circuit current, thereby improving the conversion efficiency of the heterojunction battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A flow chart of a method for preparing a heterojunction battery provided by one embodiment of the present invention; Figures 2 to 5 A schematic structural diagram of a heterojunction battery preparation process provided in one embodiment of the present invention.

[0032] In the accompanying drawings: 1-semiconductor substrate layer, 2-micropore, 201-first tunnel dielectric film, 202-second tunnel dielectric film, 301-first doped semiconductor layer, 302-second doped semiconductor layer, 401-first transparent conductive film, 402-second transparent conductive film. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0035] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] This embodiment provides a method for preparing a heterojunction battery. Figure 1 , including the following steps: S1: providing a semiconductor substrate layer; S2: forming a tunnel dielectric film on at least one side surface of the semiconductor substrate layer, wherein the tunnel dielectric film has a plurality of micropores; S3: forming a doped semiconductor layer on a surface of the tunnel dielectric film facing away from the semiconductor substrate layer.

[0037] Reference below Figures 2 to 5 The preparation method of the heterojunction battery is introduced in detail.

[0038] refer to Figure 2 , providing a semiconductor substrate layer 1.

[0039] In this embodiment, the semiconductor substrate layer 1 is taken as an example of a silicon substrate, specifically a single crystal silicon substrate. In other embodiments, the semiconductor substrate layer may also be made of other semiconductor materials.

[0040] The preparation method also includes forming a velvet surface on both side surfaces of the semiconductor substrate layer 1, wherein the velvet surface is a pyramid velvet surface with low reflectivity, and performing a cleaning treatment after the velvet surface is formed. The cleaning liquid used in the cleaning treatment includes a KOH solution, the concentration of the KOH solution is 1%-10%, the cleaning time ranges from 1min to 60min, and the cleaning temperature ranges from 5°C to 80°C.

[0041] refer to Figure 3 A tunnel dielectric film is formed on at least one side surface of the semiconductor substrate layer 1, wherein the tunnel dielectric film has a plurality of micropores 2.

[0042] Specifically, after the suede surface is cleaned, a tunnel dielectric film is formed.

[0043] The tunneling is the tunneling from the perspective of quantum mechanics, that is, when the thickness of the tunneling dielectric film is less than a certain thickness, the carriers can pass through the tunneling dielectric film between the micropores 2, and the potential energy of the tunneling dielectric film is greater than the total energy of the particles. The step of forming the tunneling dielectric film includes: forming an initial dielectric film on at least one side surface of the semiconductor substrate layer 1; annealing the initial dielectric film so that the initial dielectric film forms the tunneling dielectric film.

[0044] The process of forming the tunnel dielectric film includes an oxidation process, and the oxidation process is performed in a thermal oxygen furnace.

[0045] In one embodiment, the parameters of the oxidation process include: the gas used includes oxygen, the concentration of oxygen is 1slm-1000slm, for example, 500slm; the temperature is 650°C-970°C, for example, 700°C; the oxidation time is 5 minutes-180 minutes, for example, 30 minutes.

[0046] In the oxidation process, if the concentration of oxygen is lower than 1 slm, the oxidation rate of the semiconductor substrate layer is too slow; if the concentration of oxygen is higher than 1000 slm, the oxidation rate is too fast, making it difficult to control the oxidation rate of the semiconductor substrate layer.

[0047] In the oxidation process, if the temperature is lower than 650° C., the oxidation rate of the semiconductor substrate layer is too slow; if the temperature is higher than 970° C., the oxidation rate is too fast, making it difficult to control the oxidation rate of the semiconductor substrate layer.

[0048] In the oxidation process, if the oxidation time is less than 5 minutes, the semiconductor substrate layer is not fully oxidized and the thickness uniformity of the initial dielectric film is poor; if the oxidation time is more than 180 minutes, the semiconductor substrate layer will be over-oxidized, resulting in an initial dielectric film that is too thick, which is not conducive to the formation of micropores in the subsequent annealing process.

[0049] In one embodiment, in the oxidation process, the temperature used is 800° C. and the oxidation time is 35 minutes.

[0050] In this embodiment, the oxidation process forms an initial dielectric film on at least one side of the semiconductor substrate layer. Specifically, the initial dielectric film is an oxide film. When the material of the semiconductor substrate layer is silicon, the material of the initial dielectric film is silicon oxide. In other embodiments, the material of the initial dielectric film may also be other oxide materials that can provide a certain passivation effect.

[0051] After the oxidation process is performed, the method further includes: performing an annealing process on the initial dielectric film to transform the initial dielectric film into the tunnel dielectric film. The purpose of the annealing process is to transform the initial dielectric film into a tunnel dielectric film having micropores 2 .

[0052] In one embodiment, the annealing process is performed in a hot oxygen furnace. Furthermore, the annealing process and the oxidation process are performed in the same hot oxygen furnace, which can simplify the process. Of course, the annealing process and the oxidation process can also be performed separately in different hot oxygen furnaces.

[0053] In another embodiment, the annealing process is performed in a high temperature furnace.

[0054] In one embodiment, the parameters of the annealing treatment include: a temperature of 600° C.-950° C., for example, 800° C.; and a time of 1 minute-80 minutes, for example, 50 minutes.

[0055] In the annealing treatment, if the temperature is lower than 600°C, the diameter of the formed micropores is smaller, resulting in an insignificant effect of carrier tunneling through the tunneling dielectric film; if the temperature is higher than 950°C, the diameter of the formed micropores is too large, resulting in an insignificant effect of the tunneling dielectric film passivating the semiconductor substrate layer, and thus an insignificant effect of increasing the open circuit voltage.

[0056] In the annealing treatment, if the time is less than 1 minute, the diameter of the formed micropores is small, resulting in an insignificant effect of carrier tunneling through the tunneling dielectric film; if the time exceeds 80 minutes, the diameter of the formed micropores is too large, resulting in an insignificant effect of the tunneling dielectric film passivating the semiconductor substrate layer, and further an insignificant effect of increasing the open circuit voltage.

[0057] In a specific embodiment, in the annealing process, the temperature used is 750° C. and the annealing time is 40 minutes.

[0058] The tunnel dielectric film is used to passivate the surface of the semiconductor substrate layer to reduce defects on the surface of the semiconductor substrate layer. The tunnel dielectric film replaces the amorphous silicon intrinsic layer of the heterojunction cell in the prior art. Compared with intrinsic amorphous silicon, the parasitic light absorption of the tunnel dielectric film is reduced by 1%-30%, which promotes more light to enter the substrate and increases the short-circuit current by 1%-10%.

[0059] In one embodiment, the thickness of the tunneling dielectric film is 1nm-10nm, for example, 5nm; if the thickness of the tunneling dielectric film is less than 1nm, the conversion efficiency of the heterojunction battery is lower than 0.05%, and the effect of the tunneling dielectric film passivating the semiconductor substrate layer is not obvious; if the thickness of the tunneling dielectric film is greater than 10nm, the conversion efficiency of the heterojunction battery is lower than 0.05%, which will cause the effect of carrier tunneling through the tunneling dielectric film to be not obvious.

[0060] In this embodiment, the material of the tunnel dielectric film includes silicon oxide. In other embodiments, the material of the tunnel dielectric film may also be other materials.

[0061] The tunnel dielectric film can not only passivate the surface of the semiconductor substrate layer, but also the micropores in the tunnel dielectric film can prevent carriers from being hindered during transmission, which is conducive to better transmission of carriers.

[0062] In one embodiment, the diameter of the micropore 2 is 1nm-500nm, for example, 200nm, and the micropore 2 has a better effect of carrier transport. If the diameter of the micropore is less than 1nm, the carrier transport effect is not obvious, and the short-circuit current is not significantly improved; if the diameter of the micropore is greater than 500nm, the tunnel dielectric film passivates the semiconductor substrate layer and the open circuit voltage is not significantly improved.

[0063] In one embodiment, the micropores are evenly distributed, which can improve the effect of carrier transport; in other embodiments, the micropores are unevenly distributed.

[0064] In one embodiment, the ratio of the surface area of ​​the micropore 2 to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is 1%-30%. If the ratio of the surface area of ​​the micropore to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is less than 1%, the carrier transport effect will not be obvious and the short-circuit current will not be improved significantly. If the ratio of the surface area of ​​the micropore to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is greater than 30%, the tunnel dielectric film will not passivate the semiconductor substrate layer and the open circuit voltage will not be improved significantly.

[0065] Continue to refer Figure 3 The step of forming a tunneling dielectric film on at least one side surface of the semiconductor substrate layer 1 includes: forming a first tunneling dielectric film 201 on one side surface of the semiconductor substrate layer 1; and forming a second tunneling dielectric film 202 on the other side surface of the semiconductor substrate layer 1.

[0066] Specifically, the thickness of the first tunneling dielectric film 201 is 1nm-10nm, for example, 5nm; if the thickness of the first tunneling dielectric film 201 is less than 1nm, the effect of the tunneling dielectric film passivating the semiconductor substrate layer is not obvious; if the thickness of the first tunneling dielectric film 201 is greater than 10nm, the effect of carrier tunneling through the tunneling dielectric film is not obvious.

[0067] In this embodiment, the material of the first tunnel dielectric film 201 includes silicon oxide. In other embodiments, the material of the first tunnel dielectric film may also be other materials.

[0068] Specifically, the thickness of the second tunneling dielectric film 202 is 1nm-10nm, for example, 5nm; if the thickness of the second tunneling dielectric film 202 is less than 1nm, the effect of the tunneling dielectric film passivating the semiconductor substrate layer is not obvious; if the thickness of the second tunneling dielectric film 202 is greater than 10nm, the effect of carrier tunneling through the tunneling dielectric film is not obvious.

[0069] In this embodiment, the material of the second tunnel dielectric film 202 includes silicon oxide. In other embodiments, the material of the second tunnel dielectric film may also be other materials.

[0070] refer to Figure 4 A semiconductor layer is doped on the surface of the tunnel dielectric film on the side away from the semiconductor substrate layer, and the step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer 301 on the surface of the first tunnel dielectric film on the side away from the semiconductor substrate layer; forming a second doped semiconductor layer 302 on the surface of the second tunnel dielectric film on the side away from the semiconductor substrate layer.

[0071] In one embodiment, the thickness of the first doped semiconductor layer 301 is 5 nm-15 nm, for example, 10 nm; the thickness of the second doped semiconductor layer 302 is 5 nm-15 nm, for example, 3 nm.

[0072] In one embodiment, the conductivity type of the first doped semiconductor layer 301 is P type, and the process for forming the first doped semiconductor layer 301 is a plasma chemical vapor deposition process. The parameters for forming the first doped semiconductor layer 301 include: the gases used include silane, hydrogen and diborane, the flow rate of silane is 1 sccm-10000 sccm, the flow rate of hydrogen is 0.1 slm-50 slm, the flow rate of diborane is 1 sccm-8000 sccm, the chamber pressure is 1 mbar-1000 mbar, and the temperature is 50°C-300°C.

[0073] In a specific embodiment, the flow ratio of hydrogen to silane is 1:50; in other embodiments, the flow ratio of hydrogen to silane can also be other values.

[0074] In one embodiment, the flow rate of diborane can be set according to specific doping requirements. In one embodiment, the conductivity type of the second doped semiconductor layer 302 is N-type, and the process for forming the second doped semiconductor layer 302 is a plasma chemical vapor deposition process. The parameters for forming the second doped semiconductor layer 302 include: the gases used include silane, hydrogen and phosphine, the flow rate of silane is 1sccm-10000sccm, the flow rate of hydrogen is 0.1slm-50slm, the flow rate of phosphine is 1sccm-8000sccm, the chamber pressure is 1mbar-1000mbar, and the temperature is 50℃-300℃. In one embodiment, a tunneling dielectric film is formed only on one side of the semiconductor substrate, and the tunneling dielectric film is located on the side of the first doped semiconductor layer facing the semiconductor substrate. The conductivity type of the first doped semiconductor layer is P-type. When the tunneling dielectric film is located on the PN junction surface of the heterojunction battery, the carrier transportation effect is better.

[0075] In one embodiment, a tunnel dielectric film is formed only on one side of the semiconductor substrate, the tunnel dielectric film is located on a side of the second doped semiconductor layer facing the semiconductor substrate, and the conductivity type of the second doped semiconductor layer is N-type.

[0076] refer to Figure 5 A first transparent conductive film 401 is formed on a side of the first doped semiconductor layer 301 away from the semiconductor substrate layer 1, and a second transparent conductive film 402 is formed on a side of the second doped semiconductor layer 302 away from the semiconductor substrate layer 1. The process of forming the first transparent conductive film 401 and the second transparent conductive film 402 includes a physical vapor deposition process. The thickness of the first transparent conductive film 401 is 100nm-150nm, and the thickness of the second transparent conductive film 402 is 100nm-150nm.

[0077] The preparation method further comprises: after forming the first transparent conductive film 401 and the second transparent conductive film 402 , forming a gate line (not shown in the figure) on a side of the doped semiconductor layer away from the semiconductor substrate layer 1 .

[0078] Specifically, a first gate line is formed on a side of the first transparent conductive film 401 away from the semiconductor substrate layer 1 ; and a second gate line is formed on a side of the second transparent conductive film 402 away from the semiconductor substrate layer 1 .

[0079] In one embodiment, the first gate lines include first fine gate lines and first main gate lines, the number of the first fine gate lines is 70-105, the number of the first main gate lines is 5-12, the second gate lines include second fine gate lines and second main gate lines, the number of the second fine gate lines is 70-105, and the number of the second main gate lines is 5-12.

[0080] After forming the first gate line and the second gate line, a light injection annealing treatment is performed, and the light injection annealing treatment includes a first temperature zone light injection annealing treatment to an Nth temperature zone light injection annealing treatment performed sequentially, where N is an integer greater than or equal to 1; the temperature of the first temperature zone light injection annealing treatment to the Nth temperature zone light injection annealing treatment is 100°C-250°C.

[0081] In one embodiment, N is an integer equal to or greater than 8, the temperature of the first temperature zone annealing treatment to the third temperature zone annealing treatment is 138°C-142°C, the temperature of the fourth temperature zone annealing treatment to the sixth temperature zone annealing treatment is 155°C-175°C, the temperature of the sixth temperature zone annealing treatment to the Nth temperature zone annealing treatment is 145°C-155°C, and the temperature from the sixth temperature zone to the Nth temperature zone decreases gradually.

[0082] In one embodiment, the temperature difference between adjacent temperature zones is within 10° C., meeting the temperature fluctuation requirement of the temperature zones.

[0083] In one embodiment, the first temperature zone annealing treatment to the third temperature zone annealing treatment is used to fully volatilize the organic matter in the silver paste; the purpose of the fourth temperature zone annealing treatment to the sixth temperature zone annealing treatment is to solidify the silver paste to the surface of the first doped semiconductor layer or the surface of the second doped semiconductor layer; the purpose of the sixth temperature zone annealing treatment to the Nth temperature zone annealing treatment is to slowly solidify the silver paste, which is beneficial to improve the stability of the heterojunction battery.

[0084] The heterojunction battery after light injection annealing treatment is tested. Specifically, the electrical performance of the heterojunction battery is tested. The instrument used for the test includes a voltage tester; the electrical performance includes the conversion efficiency (Eta), open circuit voltage (Uoc), short circuit current (Isc), fill factor (FF), series resistance (Rs), parallel resistance (Rsh), leakage current (Irev2), etc. of the heterojunction battery.

[0085] In one embodiment, the conversion efficiency (Eta) of the heterojunction battery is 23%-25%, the open circuit voltage (Uoc) is 743mV-743mV, such as 743mV, the short circuit current (Isc) is 10A-11A, such as 10.6A; the fill factor (FF) is 83%-84%, such as 83.5%; the series resistance (Rs) is 0.0014 ohm-0.0021 ohm (the numerical range obtained by testing different devices is slightly different, this is the Halm test result); the leakage current (Irev2) is 0.0013A-0.0015A, such as 0.0013A.

[0086] This embodiment also provides a heterojunction battery, referring to Figure 5 ,include: Semiconductor substrate layer 1; A tunnel dielectric film located on at least one side of the semiconductor substrate layer 1, wherein the tunnel dielectric film has a plurality of micropores; The doped semiconductor layer is located on the surface of the tunnel dielectric film on a side away from the semiconductor substrate layer.

[0087] In one embodiment, the thickness of the tunneling dielectric film is 1nm-10nm, for example, 5nm; if the thickness of the tunneling dielectric film is less than 1nm, the effect of the tunneling dielectric film in passivating the semiconductor substrate layer is not obvious; if the thickness of the tunneling dielectric film is greater than 10nm, the effect of carrier tunneling through the tunneling dielectric film is not obvious.

[0088] In this embodiment, the material of the tunnel dielectric film includes silicon oxide. In other embodiments, the material of the tunnel dielectric film may also be other materials.

[0089] The micropores are used to enable better transport of charge carriers.

[0090] In one embodiment, the diameter of the micropore 2 is 1nm-500nm, for example, 200nm, and the micropore 2 has a better effect of carrier transport. If the diameter of the micropore is less than 1nm, the carrier transport effect is not obvious, and the short-circuit current is not significantly improved; if the diameter of the micropore is greater than 500nm, the tunnel dielectric film passivates the semiconductor substrate layer and the open circuit voltage is not significantly improved.

[0091] In one embodiment, the micropores are evenly distributed, which can improve the effect of carrier transport; in other embodiments, the micropores are unevenly distributed.

[0092] In one embodiment, the ratio of the surface area of ​​the micropore 2 to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is 1%-30%. If the ratio of the surface area of ​​the micropore to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is less than 1%, the carrier transport effect will not be obvious and the short-circuit current will not be improved significantly. If the ratio of the surface area of ​​the micropore to the area of ​​the semiconductor substrate layer away from the tunnel dielectric film is greater than 30%, the tunnel dielectric film will not passivate the semiconductor substrate layer and the open circuit voltage will not be improved significantly.

[0093] Continue to refer Figure 5 The tunnel dielectric film includes: a first tunnel dielectric film 201 located on one side surface of the semiconductor substrate layer 1; and a second tunnel dielectric film 202 located on the other side surface of the semiconductor substrate layer.

[0094] Specifically, the thickness of the first tunneling dielectric film 201 is 1nm-10nm, for example, 5nm; if the thickness of the first tunneling dielectric film 201 is less than 1nm, the effect of the tunneling dielectric film passivating the semiconductor substrate layer is not obvious; if the thickness of the first tunneling dielectric film 201 is greater than 10nm, the effect of carrier tunneling through the tunneling dielectric film is not obvious.

[0095] In this embodiment, the material of the first tunnel dielectric film 201 includes silicon oxide. In other embodiments, the material of the first tunnel dielectric film may also be other materials.

[0096] Specifically, the thickness of the second tunneling dielectric film 202 is 1nm-10nm, for example, 5nm; if the thickness of the second tunneling dielectric film 202 is less than 1nm, the effect of the tunneling dielectric film passivating the semiconductor substrate layer is not obvious; if the thickness of the second tunneling dielectric film 202 is greater than 10nm, the effect of carrier tunneling through the tunneling dielectric film is not obvious.

[0097] In this embodiment, the material of the second tunnel dielectric film 202 includes silicon oxide. In other embodiments, the material of the second tunnel dielectric film may also be other materials.

[0098] The heterojunction battery also includes: a first doped semiconductor layer 301 located on a surface of the first tunneling dielectric film 201 that is away from the semiconductor substrate layer 1; a second doped semiconductor layer 302 located on a surface of the second tunneling dielectric film 202 that is away from the semiconductor substrate layer, the conductivity type of the first doped semiconductor layer 301 is P type, and the conductivity type of the second doped semiconductor layer 302 is N type.

[0099] In one embodiment, the thickness of the first doped semiconductor layer 301 is 5 nm-15 nm, for example, 3 nm; the thickness of the second doped semiconductor layer 302 is 5 nm-15 nm, for example, 3 nm.

[0100] The heterojunction battery also includes: a first transparent conductive film 401 on the first doped semiconductor layer 301 away from the semiconductor substrate layer 1, and a second transparent conductive film 402 on the second doped semiconductor layer 302 away from the semiconductor substrate layer 1, the thickness of the first transparent conductive film 401 is 100nm-150nm, and the thickness of the second transparent conductive film 402 is 100nm-150nm.

[0101] The heterojunction battery further includes: a gate line (not shown in the figure) on a side of the doped semiconductor layer away from the semiconductor substrate layer 1 .

[0102] Specifically, a first gate line is provided on a side of the first transparent conductive film 401 away from the semiconductor substrate layer 1 , and a second gate line is provided on a side of the second transparent conductive film 402 away from the semiconductor substrate layer 1 .

[0103] In one embodiment, the first gate lines include first fine gate lines and first main gate lines, the number of the first fine gate lines is 70-105, the number of the first main gate lines is 5-12, the second gate lines include second fine gate lines and second main gate lines, the number of the second fine gate lines is 70-105, and the number of the second main gate lines is 5-12.

[0104] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A heterojunction battery, characterized in that: include: Semiconductor substrate layer; A tunnel dielectric film is stacked on at least one surface of the semiconductor substrate layer; The tunnel dielectric film has a plurality of micropores, and the pore diameter of the micropores is 1nm-500nm; and, The doped semiconductor layer is stacked on the surface of the tunnel dielectric film away from the semiconductor substrate layer.

2. The heterojunction battery according to claim 1, characterized in that: The heterojunction cell satisfies at least one of the following conditions: The material of the tunnel dielectric film includes silicon oxide; The thickness of the tunnel dielectric film is 1 nm-10 nm; and The thickness of the doped semiconductor layer is 5nm-15nm.

3. The heterojunction battery according to claim 1, characterized in that: The heterojunction battery further comprises a transparent conductive film, which is stacked on a surface of the doped semiconductor layer away from the semiconductor substrate layer; Optionally, the thickness of the transparent conductive film is 100nm-150nm; Optionally, it further comprises a gate line, which is arranged on the surface of the transparent conductive film away from the semiconductor substrate layer.

4. The heterojunction battery according to claim 1, characterized in that: The micropores extend from the tunnel dielectric film into the semiconductor substrate layer; Optionally, the extension depth of the micropores in the semiconductor substrate layer is less than the thickness of the semiconductor substrate layer; Optionally, the micropores are uniformly distributed in the tunnel dielectric film and the optional semiconductor substrate layer.

5. The heterojunction battery according to claim 1, characterized in that: The heterojunction battery comprises a first tunnel dielectric film, a second tunnel dielectric film, a first doped semiconductor layer and a second doped semiconductor layer; The first tunneling dielectric film and the first doped semiconductor layer are sequentially stacked on the first surface of the semiconductor substrate layer; The second tunneling dielectric film and the second doped semiconductor layer are sequentially stacked on the second surface of the semiconductor substrate layer; The first doped semiconductor layer and the second doped semiconductor layer have different conductivity types.

6. The heterojunction battery according to claim 5, characterized in that: The heterojunction cell satisfies at least one of the following conditions: The materials of the first tunnel dielectric film and the second tunnel dielectric film include silicon oxide respectively; The thickness of the first tunnel dielectric film and the second tunnel dielectric film are the same or different, and are independently 1 nm-10 nm; The conductivity type of the first doped semiconductor layer is P type, the conductivity type of the second doped semiconductor layer is N type, and the first surface of the semiconductor substrate layer is a front surface; as well as The thickness of the first doped semiconductor layer and the second doped semiconductor layer are the same or different, and are independently 5 nm to 15 nm.

7. The heterojunction battery according to claim 5, characterized in that: The heterojunction battery comprises a first transparent conductive film and a second transparent conductive film; the first transparent conductive film is stacked on a surface of the first doped semiconductor layer away from the semiconductor substrate layer; the second transparent conductive film is stacked on a surface of the second doped semiconductor layer away from the semiconductor substrate layer; Preferably, the thickness of the first transparent conductive film and the second transparent conductive film are the same or different, and are independently 100 nm-150 nm.

8. The heterojunction battery according to claim 7, characterized in that: The heterojunction battery comprises a first gate line and a second gate line; the first gate line is arranged on a surface of the first transparent conductive film away from the semiconductor substrate layer; the second gate line is arranged on a surface of the second transparent conductive film away from the semiconductor substrate layer; Optionally, the first gate line includes a first thin gate line and a first main gate line; the second gate line includes a second thin gate line and a second main gate line; Optionally, the number of the first thin gate lines and the number of the second thin gate lines are independently 70 to 105; the number of the first main gate lines and the number of the second main gate lines are independently 5 to 12.

9. A method for preparing a heterojunction battery, characterized in that: The following steps are involved: S1, forming an initial dielectric film on at least one surface of the semiconductor substrate layer, wherein the process of forming the initial dielectric film includes an oxidation process; annealing the initial dielectric film to form a tunneling dielectric film having micropores on at least one surface of the semiconductor substrate layer; The annealing conditions include: annealing temperature of 600°C-950°C, time of 1min-80min; S2. Forming a doped semiconductor layer on a surface of the tunnel dielectric film away from the semiconductor substrate layer.

10. The method according to claim 9, characterized in that In step S1, the semiconductor substrate layer includes a first surface and a second surface; step S1 includes: forming a first initial dielectric film on a first surface of the semiconductor substrate layer, and forming a second initial dielectric film on a second surface of the semiconductor substrate layer; The first initial dielectric film and the second initial dielectric film are subjected to the annealing treatment respectively to form a first tunnel dielectric film on a surface of the first initial dielectric film away from the semiconductor substrate layer, and to form a second tunnel dielectric film on a surface of the second initial dielectric film away from the semiconductor substrate layer.

11. The method according to claim 9, characterized in that At least one of the following conditions is met in step S1: The gas used in the oxidation process includes oxygen, and the concentration of oxygen is 1slm-1000slm, preferably 500slm-1000slm; The temperature of the oxidation process is 650°C-970°C, and the oxidation time is 5min-180min; preferably, the oxidation temperature is 800°C-970°C, and the oxidation time is 35min-180min; The oxidation process is carried out in a hot oxygen furnace; and The annealing treatment conditions include: annealing temperature of 750° C.-950° C., and time of 40 min-80 min.

12. The method according to claim 10, characterized in that In step S2, plasma chemical deposition is used to form the doped semiconductor layer; Preferably, the plasma chemical deposition process is selected from at least one of the following two methods: Method (1): using a first reaction gas, wherein the first reaction gas includes: silane, hydrogen and diborane; the flow rate of the silane is 1 sccm-10000 sccm, the flow rate of the hydrogen is 0.1 slm-50 slm, and the flow rate of the diborane is 1 sccm-8000 sccm; the chamber pressure is 1 mbar-1000 mbar, and the temperature is 50°C-300°C; and / or Method (2): using a second reaction gas, wherein the second reaction gas includes: silane, hydrogen and phosphine; wherein the flow rate of the silane is 1 sccm-10000 sccm, the flow rate of the hydrogen is 0.1 slm-50 slm, and the flow rate of the phosphine is 1 sccm-8000 sccm; the chamber pressure is 1 mbar-1000 mbar, and the temperature is 50°C-300°C.

13. The method according to claim 12, characterized in that In step S2, on one of the surfaces of the first tunnel dielectric film and the second tunnel dielectric film away from the semiconductor substrate layer, the P-type doped semiconductor layer is formed by adopting the method (1), and on the other of the surfaces of the first tunnel dielectric film and the second tunnel dielectric film, the N-type doped semiconductor layer is formed by adopting the method (2); Preferably, according to the method (1), a P-type first doped semiconductor layer is formed on a surface of the first tunneling dielectric film away from the semiconductor substrate layer; According to the method (2), an N-type second doped semiconductor layer is formed on the surface of the second tunnel dielectric film away from the semiconductor substrate layer; the first surface of the semiconductor substrate layer is the front surface.

14. The method according to claim 13, characterized in that The method further includes: S3, forming a transparent conductive layer on the surface of the doped semiconductor layer away from the semiconductor substrate layer; Preferably, a first transparent conductive layer is formed on a surface of the first doped semiconductor layer away from the semiconductor substrate layer; and a second transparent conductive layer is formed on a surface of the second doped semiconductor layer away from the semiconductor substrate layer.

15. The method according to claim 14, characterized in that The method further includes: Forming gate lines on a surface of the transparent conductive layer away from the semiconductor substrate layer and performing light injection annealing treatment; Optionally, the light injection annealing treatment includes sequentially performing a first temperature zone light injection annealing treatment to an Nth temperature zone light injection annealing treatment, where N is an integer greater than or equal to 1; wherein the temperature of the first temperature zone light injection annealing treatment to the Nth temperature zone light injection annealing treatment is 100° C.-250° C.; preferably, the temperature difference between adjacent temperature zones is less than 10° C.; Preferably, N is an integer greater than or equal to 8; wherein the temperature of the light injection annealing treatment from the first temperature zone to the third temperature zone is 138°C-142°C, the temperature of the light injection annealing treatment from the fourth temperature zone to the sixth temperature zone is 155°C-175°C, and the temperature of the light injection annealing treatment from the sixth temperature zone to the Nth temperature zone is 145°C-155°C, wherein the temperature of the light injection annealing treatment from the sixth temperature zone to the Nth temperature zone decreases gradually; Preferably, the gate lines are formed and the light injection annealing treatment is performed on the surfaces of the first transparent conductive layer and the second transparent conductive layer away from the semiconductor substrate layer, respectively.

16. A heterojunction battery prepared according to the method according to any one of claims 9 to 15.

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