Light emitting diode chip capable of improving light extraction efficiency and preparation method thereof

Abstract

The embodiment of the invention provides a light emitting diode chip capable of improving light extraction efficiency and a preparation method of the light emitting diode chip, and belongs to the technical field of semiconductors. The light-emitting diode chip comprises a light-emitting structure and an insulating layer located on the surface of the light-emitting structure, an air cavity exists between the insulating layer and the light-emitting structure and is used for reflecting light emitted by the light-emitting structure to the light-emitting surface of the light-emitting diode chip, and the light-emitting surface of the light-emitting diode chip is located on the side, away from the insulating layer, of the light-emitting structure. According to the embodiment of the invention, the luminous efficiency of the LED chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode chip with improved light extraction efficiency and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) has been widely used in various light source fields such as backlight, lighting, and landscaping due to its small size, long service life, rich colors, and low energy consumption.

[0003] In the related art, an LED chip includes a light-emitting structure and an insulating layer located on the surface of the light-emitting structure. The insulating layer is generally formed by deposition, and the insulating layer and the light-emitting structure are closely attached. The light-emitting surface of the LED chip is located on the side of the light-emitting structure away from the insulating layer.

[0004] However, due to the high refractive index of the insulating layer, the difference in refractive index between the light-emitting structure and the insulating layer is small, that is, the total reflection angle of the interface between the light-emitting structure and the insulating layer is large, and only a small part of the light with a large incident angle will be totally reflected at the interface, while the light with a small incident angle will enter the insulating layer. The light entering the insulating layer will be partially absorbed by the insulating layer, resulting in light loss, thereby affecting the light output efficiency of the LED chip. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode chip with improved light extraction efficiency and a method for manufacturing the same, which can improve the light extraction efficiency of the LED chip. The technical solution is as follows:

[0006] On the one hand, a light-emitting diode chip is provided, comprising a light-emitting structure and an insulating layer located on the surface of the light-emitting structure, wherein an air cavity exists between the insulating layer and the light-emitting structure, and the air cavity is used to reflect light emitted by the light-emitting structure toward a light-emitting surface of the light-emitting diode chip, and the light-emitting surface of the light-emitting diode chip is located on a side of the light-emitting structure away from the insulating layer.

[0007] Optionally, the light-emitting structure includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence along a direction close to the insulating layer, and the light-emitting structure has a groove extending from a surface of the second semiconductor layer away from the light-emitting layer to the first semiconductor layer; the air cavity includes a first air cavity, and the first air cavity is located between the insulating layer, the side wall of the groove and the bottom surface of the groove.

[0008] Optionally, in the stacking direction of the first semiconductor layer, the light-emitting layer and the second semiconductor layer, the height of the first air cavity is greater than or equal to the distance between the surface of the light-emitting layer away from the first semiconductor layer and the bottom of the groove, and is less than the distance between the surface of the second semiconductor layer away from the light-emitting layer and the bottom of the groove.

[0009] Optionally, an angle between a side wall of the groove and a bottom surface of the groove is 40° to 80°.

[0010] Optionally, the light-emitting diode chip further comprises a substrate, which is located on a surface of the light-emitting structure away from the insulating layer; the air cavity comprises a second air cavity, which is located between the insulating layer, the side wall of the light-emitting structure and the surface of the substrate.

[0011] Optionally, the light-emitting structure includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence along a direction close to the insulating layer; in the stacking direction of the first semiconductor layer, the light-emitting layer and the second semiconductor layer, the height of the second air cavity is greater than the distance between the surface of the light-emitting layer close to the first semiconductor layer and the surface of the substrate, and is less than or equal to the distance between the surface of the light-emitting layer away from the first semiconductor layer and the surface of the substrate.

[0012] Optionally, an angle between a side wall of the light emitting structure and a surface of the substrate is 40° to 80°.

[0013] Optionally, the refractive index of the insulating layer is 1.05 to 1.5.

[0014] On the other hand, a method for preparing a light-emitting diode chip is provided, comprising: providing a light-emitting structure; forming an insulating layer on the light-emitting structure, wherein an air cavity exists between the insulating layer and the light-emitting structure, and the air cavity is used to reflect light emitted by the light-emitting structure toward a light-emitting surface of the light-emitting diode chip, and the light-emitting surface of the light-emitting diode chip is located on a side of the light-emitting structure away from the insulating layer.

[0015] Optionally, forming the insulating layer on the light emitting structure comprises: coating an insulating material solution on the light emitting structure; and hardening the insulating material solution to obtain the insulating layer.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, there is an air cavity between the insulating layer and the light-emitting structure, and the air cavity is used to reflect the light emitted by the light-emitting structure to the light-emitting surface of the LED chip, and the light-emitting surface of the LED chip is located on the side of the light-emitting structure away from the insulating layer. Compared with the refractive index of the insulating layer, the refractive index of the light-emitting structure is larger, and the refractive index of the air cavity is smaller, that is, the difference in refractive index between the light-emitting structure and the air cavity is larger than the difference in refractive index between the light-emitting structure and the insulating layer. Since when light enters a film layer with a higher refractive index from a film layer with a lower refractive index, the greater the difference in the refractive index of the film layer, the smaller the total reflection angle, so the total reflection angle of the interface between the light-emitting structure and the air cavity is smaller than the total reflection angle of the interface between the light-emitting structure and the insulating layer. When the light emitted by the light-emitting structure is directed to the air cavity, more light with a smaller incident angle will be totally reflected, which can reduce the probability of this part of the light entering the insulating layer and being absorbed and causing light loss, thereby improving the light extraction efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a schematic diagram of the structure of an LED chip provided by an embodiment of the present disclosure;

[0020] Figure 2 is a partial structural schematic diagram of an LED chip provided by an embodiment of the present disclosure;

[0021] Figure 3 is a partial structural schematic diagram of an LED chip provided by an embodiment of the present disclosure;

[0022] Figure 4 is a flow chart of a method for preparing an LED chip provided by an embodiment of the present disclosure;

[0023] Figure 5 This is a flow chart of another method for preparing an LED chip provided in an embodiment of the present disclosure.

[0024] Reference numerals:

[0025] 10: light-emitting structure; 10a: first side wall; 11: first semiconductor layer; 12: light-emitting layer; 13: second semiconductor layer; 14: groove; 20: insulating layer; 30: air cavity; 31: first air cavity; 32: second air cavity; 40: substrate; 50: distributed Bragg reflection (DBR) layer; 60: transparent conductive layer; 61: current blocking layer; 70: first connecting electrode; 71: second connecting electrode; 72: third connecting electrode; 73: fourth connecting electrode; 74: first pad electrode; 75: second pad electrode; 80: first through hole; 81: second through hole; 82: third through hole; 83: fourth through hole. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0027] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity restriction, but indicate that there is at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0028] Figure 1 Schematic diagram of the structure of an LED chip provided by the embodiment of the present disclosure. Figure 1 As shown, the LED chip includes a light-emitting structure 10 and an insulating layer 20 located on the surface of the light-emitting structure 10. There is an air cavity 30 between the insulating layer 20 and the light-emitting structure 10. The air cavity 30 is used to reflect the light emitted by the light-emitting structure 10 toward the light-emitting surface of the LED chip. The light-emitting surface of the LED chip is located on the side of the light-emitting structure 10 away from the insulating layer 20.

[0029] In the embodiment of the present disclosure, there is an air cavity 30 between the insulating layer 20 and the light emitting structure 10. The air cavity 30 is used to reflect the light emitted by the light emitting structure 10 to the light emitting surface of the LED chip. The light emitting surface of the LED chip is located on the side of the light emitting structure 10 away from the insulating layer 20. Compared with the refractive index of the insulating layer 20, the refractive index of the light emitting structure 10 is larger, and the refractive index of the air cavity 30 is smaller, which is about 1. That is, the refractive index difference between the light emitting structure 10 and the air cavity 30 is larger than the refractive index difference between the light emitting structure 10 and the insulating layer 20. Since when light enters a film layer with a higher refractive index from a film layer with a lower refractive index, the greater the refractive index difference of the film layers, the smaller the total reflection angle. Therefore, the total reflection angle of the interface between the light emitting structure 10 and the air cavity 30 is smaller than the total reflection angle of the interface between the light emitting structure 10 and the insulating layer 20.

[0030] Figure 2 It is a schematic diagram of the partial structure of an LED chip provided in an embodiment of the present disclosure. Figure 2 The middle arrow indicates the propagation path of the light near the air cavity 30 in the LED chip. Figure 2 As shown, when the light emitted by the light emitting structure 10 is directed toward the insulating layer 20, the light with a smaller incident angle may not generate total reflection and enter the insulating layer 20, while when the light emitted by the light emitting structure 10 is directed toward the air cavity 30, more light with a smaller incident angle will be totally reflected, which can reduce the probability of this part of the light entering the insulating layer 20 and being absorbed and generating light loss, thereby improving the light extraction efficiency of the LED chip. In the disclosed embodiment, the total reflection angle refers to the minimum incident angle that allows total reflection to occur. Total reflection means that when light enters a film layer with a higher refractive index from a film layer with a lower refractive index and the incident angle is greater than or equal to the total reflection angle, all incident light is reflected and does not enter the film layer with a lower refractive index to generate refracted light. When total reflection occurs, the reflectivity is equal to 1.

[0031] like Figure 1 and Figure 2 As shown, the light emitting structure 10 includes a first semiconductor layer 11, a light emitting layer 12, and a second semiconductor layer 13 stacked in sequence in a direction close to the insulating layer 20. The light emitting structure 10 has a groove (MESA) 14 extending from the surface of the second semiconductor layer 13 away from the light emitting layer 12 to the first semiconductor layer 11. The insulating layer 20 is located on the surface of the second semiconductor layer 13 away from the light emitting layer 12, the sidewall of the light emitting structure 10, the sidewall of the groove 14, and the bottom surface of the groove 14.

[0032] Exemplarily, the air cavity 30 includes a first air cavity 31, and the first air cavity 31 is located between the insulating layer 20, the side wall of the groove 14, and the bottom surface of the groove 14. In this way, in the corner area between the insulating layer 20, the side wall of the groove 14, and the bottom surface of the groove 14, when the light emitted by the light emitting structure 10 is emitted from the side wall of the groove 14 to the first air cavity 31, more light with a smaller incident angle will be totally reflected, thereby improving the light extraction efficiency of the LED chip.

[0033] like Figure 2 As shown, in the stacking direction of the first semiconductor layer 11, the light emitting layer 12, and the second semiconductor layer 13, the height H1 of the first air cavity 31 is greater than or equal to the distance H2 between the surface of the light emitting layer 12 away from the first semiconductor layer 11 and the bottom surface of the groove 14, and is less than the distance H3 between the surface of the second semiconductor layer 13 away from the light emitting layer 12 and the bottom surface of the groove 14. In this way, the first air cavity 31 can cause more light emitted by the light emitting layer 12 and directed to the side wall of the groove 14 with a smaller incident angle to be totally reflected, which is beneficial to improving the light extraction efficiency of the LED chip.

[0034] Optionally, the angle α between the side wall of the groove 14 and the bottom surface of the groove 14 can be 40° to 80°. In this way, the light emitting area of ​​the light emitting structure 10 can be large, the brightness of the LED chip can be high, and it is beneficial to form a first air cavity 31 with good quality between the insulating layer 20, the side wall of the groove 14 and the bottom surface of the groove 14 during the preparation process of the LED chip.

[0035] For example, the angle α between the sidewall of the groove 14 and the bottom surface of the groove 14 may be 60° to 75°. For example, the angle α between the sidewall of the groove 14 and the bottom surface of the groove 14 may be 60°, 65° or 75°.

[0036] Figure 3 FIG. 1 is a schematic diagram of a partial structure of an LED chip provided by an embodiment of the present disclosure. Figure 1 and Figure 3 As shown, the LED chip further includes a substrate 40 , which is located on a surface of the light emitting structure 10 away from the insulating layer 20 .

[0037] Exemplarily, the air cavity 30 includes a second air cavity 32, and the second air cavity 32 is located between the insulating layer 20, the side wall of the light emitting structure 10, and the surface of the substrate 40. In this way, in the corner area between the insulating layer 20, the side wall of the light emitting structure 10, and the surface of the substrate 40, when the light emitted by the light emitting structure 10 is emitted from the side wall of the light emitting structure 10 toward the second air cavity 32, more light with a smaller incident angle will be totally reflected, thereby improving the light extraction efficiency of the LED chip.

[0038] like Figure 3As shown, the side wall of the light emitting structure 10 includes a first side wall 10a, which is connected to the surface of the substrate 40 and not connected to the bottom surface of the groove 14, and the second air cavity 32 is located between the insulating layer 20, the first side wall 10a of the light emitting structure 10 and the surface of the substrate 40.

[0039] Figure 3 The middle arrow indicates the propagation path of the light near the first side wall 10a of the light emitting structure 10 in the LED chip. Figure 3 As shown, in the corner area between the insulating layer 20, the first side wall 10a of the light emitting structure 10 and the surface of the substrate 40, when the light emitted by the light emitting structure 10 is emitted from the first side wall 10a toward the insulating layer 20, the light with a smaller incident angle may not be totally reflected and enter the insulating layer 20, while the second air cavity 32 can cause more light emitted by the light emitting structure 10 and emitted to the first side wall 10a with a smaller incident angle to be totally reflected, thereby reducing the probability of light in this area entering the insulating layer 20 and being absorbed and causing light loss, thereby improving the light extraction efficiency of the LED chip.

[0040] like Figure 3 As shown, in the stacking direction of the first semiconductor layer 11, the light emitting layer 12, and the second semiconductor layer 13, the height H4 of the second air cavity 32 is greater than the distance H5 between the surface of the light emitting layer 12 close to the first semiconductor layer 11 and the surface of the substrate 40, and is less than or equal to the distance H6 between the surface of the light emitting layer 12 away from the first semiconductor layer 11 and the surface of the substrate 40. In this way, the second air cavity 32 can cause more light emitted by the light emitting layer 12 and incident on the first side wall 10a with a small incident angle to be totally reflected, which is beneficial to improving the light extraction efficiency of the LED chip. And the quality of the second air cavity 32 can be guaranteed to be good.

[0041] Optionally, the angle β between the side wall of the light emitting structure 10 and the surface of the substrate 40 can be 40° to 80°. In this way, the light emitting area of ​​the light emitting structure 10 can be large, the brightness of the LED chip can be high, and it is beneficial to form a second air cavity 32 with good quality between the insulating layer 20, the side wall of the light emitting structure 10 and the surface of the substrate 40 during the preparation process of the LED chip.

[0042] For example, the angle β between the sidewall of the light emitting structure 10 and the surface of the substrate 40 may be 60° to 75°. For example, the angle β between the sidewall of the light emitting structure 10 and the surface of the substrate 40 may be 60°, 65° or 75°.

[0043] Optionally, the angle α between the sidewall of the groove 14 and the bottom surface of the groove 14 and the angle β between the sidewall of the light emitting structure 10 and the surface of the substrate 40 may be equal.

[0044] In other embodiments, the angle α between the sidewall of the groove 14 and the bottom surface of the groove 14 and the angle β between the sidewall of the light emitting structure 10 and the surface of the substrate 40 may also be unequal, which is not limited in the present disclosure.

[0045] Optionally, the refractive index of the insulating layer 20 is 1.05 to 1.5.

[0046] For example, the refractive index of the insulating layer 20 may be 1.05 to 1.1. For example, the refractive index of the insulating layer 20 may be 1.05, 1.07, or 1.1.

[0047] In other embodiments, the refractive index of the insulating layer 20 may be 1.4 to 1.5. For example, the refractive index of the insulating layer 20 may be 1.4, 1.45, or 1.5.

[0048] The refractive index of the insulating layer 20 is within a relatively small range, which is beneficial to increase the refractive index difference between the light-emitting structure 10 and the insulating layer 20, so that the total reflection angle of the interface between the light-emitting structure 10 and the insulating layer 20 is smaller, which is beneficial to the total reflection of the light emitted by the light-emitting structure 10 at the interface between the light-emitting structure 10 and the insulating layer 20, thereby reducing the probability of light loss caused by the insulating layer 20 absorbing light.

[0049] Optionally, the insulating layer 20 may be SiO 2 Layer. SiO 2 The insulating layer 20 can better protect the light emitting structure 10, and the SiO 2 The light transmittance is good, which can reduce the light absorption effect of the insulating layer 20 and improve the light extraction efficiency of the LED chip.

[0050] In other embodiments, the insulating layer 20 may also include TiO 2 layer, SiN layer and Al 2 O 3 At least one of the layers, which is not limited in the present disclosure.

[0051] like Figure 1 As shown, the LED chip further includes a DBR layer 50, which is located on the surface of the insulating layer 20 away from the light emitting structure 10. Since the DBR layer 50 has a high reflectivity to light, the DBR layer 50 can better reflect part of the light entering the insulating layer 20, and reflect the part of the light back to the side of the light emitting structure 10 away from the insulating layer 20, that is, reflect it back to the light emitting surface of the LED chip, thereby improving the luminous efficiency of the LED chip.

[0052] Optionally, the DBR layer 50 includes a plurality of SiO 2 Layers and multiple TiO 2The number of periods of the DBR layer 50 may be 20 to 50. For example, the DBR layer 50 may include 20 SiO layers alternately stacked periodically. 2 layer and 20 TiO 2 layer.

[0053] Optionally, the substrate 40 is a sapphire substrate, which has good light transmittance, high mechanical strength, and is easy to handle and clean.

[0054] In other embodiments, the substrate 40 may also be a Si substrate or a SiC substrate, which is not limited in the present disclosure.

[0055] Optionally, the LED chip may further include a buffer layer, and the buffer layer is located between the substrate 40 and the light emitting structure 10 .

[0056] Exemplarily, the buffer layer may be a GaN buffer layer.

[0057] Optionally, the first semiconductor layer 11 may be an N-type GaN layer, and the second semiconductor layer 13 may be a P-type GaN layer.

[0058] Exemplarily, the first semiconductor layer 11 is a Si-doped GaN layer, and the second semiconductor layer 13 is a Mg-doped GaN layer.

[0059] Optionally, the light-emitting layer 12 is a multi-quantum well layer, including multiple pairs of InGaN layers and GaN layers stacked alternately. Different materials can be selected for the light-emitting layer 12 according to the different light-emitting wavelength ranges of the LED chip. For example, the light-emitting layer 12 of the blue-green LED chip can use multiple pairs of InGaN layers and GaN layers stacked alternately; the light-emitting layer 12 of the red LED chip can use multiple pairs of AlGaInP quantum barrier layers and AlGaInP quantum well layers stacked alternately, wherein the Al component content of the AlGaInP quantum barrier layer is greater than the Al component content of the AlGaInP quantum well layer.

[0060] Exemplarily, the light emitting layer 12 includes 3 to 8 pairs of InGaN layers and GaN layers stacked alternately, for example, 5 pairs of InGaN layers and GaN layers stacked alternately, and of course other pairs are also possible, which is not limited in the present disclosure.

[0061] In the embodiment of the present disclosure, the refractive index of the GaN material is about 2.3, and the refractive index of the air cavity 30 is about 1, so the total reflection angle of the light emitted by the light emitting structure 10 at the interface between the light emitting structure 10 and the air cavity 30 is about 25.5°. In addition, when the refractive index of the insulating layer 20 is 1.1, the total reflection angle of the light emitted by the light emitting structure 10 at the interface between the light emitting structure 10 and the insulating layer 20 is about 28°, which can effectively increase the probability of total reflection of light with a small incident angle, and improve the light extraction efficiency of the LED chip.

[0062] Optionally, the LED chip further includes a transparent conductive layer 60 , and the transparent conductive layer 60 is located between the second semiconductor layer 13 and the insulating layer 20 .

[0063] like Figure 1 As shown, the insulating layer 20 covers the transparent conductive layer 60 away from the surface of the second semiconductor layer 13 and the sidewall of the transparent conductive layer 60. The transparent conductive layer 60 can also be called a current spreading layer, which can make the current spread laterally to various regions of the second semiconductor 13 to ensure the luminous efficiency of the LED chip.

[0064] Optionally, the transparent conductive layer 60 may be an indium tin oxide (ITO) layer. ITO has good transmittance and low resistivity, so it can ensure the light emitting effect of the LED chip, and also facilitate carrier conduction and improve carrier injection efficiency.

[0065] Optionally, the LED chip further includes a current blocking layer 61 , and the current blocking layer 61 is located between the second semiconductor layer 13 and the transparent conductive layer 60 .

[0066] like Figure 1 As shown, the transparent conductive layer 60 covers the surface of the current blocking layer 61 away from the second semiconductor layer 13 and the sidewall of the current blocking layer 61. The current blocking layer 61 can cooperate with the transparent conductive layer 60 to improve the uniformity of the current flow of the LED chip, thereby further improving the luminous efficiency of the LED chip.

[0067] Optionally, the current blocking layer 60 may be SiO 2 layer.

[0068] like Figure 1 As shown, the LED chip also includes a first connecting electrode 70 and a second connecting electrode 71. The first connecting electrode 70 is located on the bottom surface of the groove 14 and connected to the first semiconductor layer 11. The second connecting electrode 71 is located on the surface of the transparent conductive layer 60 away from the current blocking layer 61 and connected to the transparent conductive layer 60.

[0069] Exemplarily, the insulating layer 20 covers the surface of the first connection electrode 70 away from the first semiconductor layer 11, the sidewall of the first connection electrode 70, the surface of the second connection electrode 71 away from the transparent conductive layer 60, and the sidewall of the second connection electrode 71. In addition, the insulating layer 20 has a first through hole 80 exposing the first connection electrode 70 and a second through hole 81 exposing the second connection electrode 71.

[0070] like Figure 1As shown, the LED chip also includes a third connecting electrode 72 and a fourth connecting electrode 73. The third connecting electrode 72 and the fourth connecting electrode 73 are located on the surface of the insulating layer 20 away from the substrate 40. The third connecting electrode 72 is connected to the first connecting electrode 70 through the first through hole 80, and the fourth connecting electrode 73 is connected to the second connecting electrode 71 through the second through hole 81.

[0071] Exemplarily, the DBR layer 50 covers the surface of the third connection electrode 72 away from the substrate 40, the sidewalls of the third connection electrode 72, the surface of the fourth connection electrode 73 away from the substrate 40, and the sidewalls of the fourth connection electrode 73. In addition, the DBR layer 50 has a third through hole 82 exposing the third connection electrode 72 and a fourth through hole 83 exposing the fourth connection electrode 73.

[0072] like Figure 1 As shown, the LED chip also includes a first pad electrode 74 and a second pad electrode 75. The first pad electrode 74 and the second pad electrode 75 are located on the surface of the DBR layer 50 away from the substrate 40. The first pad electrode 74 is connected to the third connecting electrode 72 through a third through hole 82, and the second pad electrode 75 is connected to the fourth connecting electrode 73 through a fourth through hole 83.

[0073] Figure 4 FIG. 1 is a flow chart of a method for preparing an LED chip provided by an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:

[0074] In step S101 , a light-emitting structure is provided.

[0075] In step S102 , an insulating layer is formed on the light emitting structure.

[0076] There is an air cavity between the insulating layer and the light emitting structure, and the air cavity is used to reflect the light emitted by the light emitting structure toward the light emitting surface of the LED chip. The light emitting surface of the LED chip is located on the side of the light emitting structure away from the insulating layer.

[0077] In the disclosed embodiment, there is an air cavity between the insulating layer and the light-emitting structure, and the air cavity is used to reflect the light emitted by the light-emitting structure to the light-emitting surface of the LED chip, and the light-emitting surface of the LED chip is located on the side of the light-emitting structure away from the insulating layer. Compared with the refractive index of the insulating layer, the refractive index of the light-emitting structure is larger, and the refractive index of the air cavity is smaller, that is, the difference in refractive index between the light-emitting structure and the air cavity is larger than the difference in refractive index between the light-emitting structure and the insulating layer. Since when light enters a film layer with a higher refractive index from a film layer with a lower refractive index, the greater the difference in the refractive index of the film layer, the smaller the total reflection angle, so the total reflection angle of the interface between the light-emitting structure and the air cavity is smaller than the total reflection angle of the interface between the light-emitting structure and the insulating layer. When the light emitted by the light-emitting structure is directed to the air cavity, more light with a smaller incident angle will be totally reflected, which can reduce the probability of this part of the light entering the insulating layer and being absorbed and causing light loss, thereby improving the light extraction efficiency of the LED chip.

[0078] Figure 5 FIG. 1 is a flow chart of another method for preparing an LED chip provided by an embodiment of the present disclosure. Figure 5 As shown, the preparation method comprises:

[0079] In step S201 , a light emitting structure is formed on a substrate.

[0080] Optionally, the substrate may be a sapphire substrate.

[0081] For example, the sapphire substrate may be pretreated first, the sapphire substrate may be placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, and the sapphire substrate may be baked for 12 to 18 minutes to clean the sapphire substrate.

[0082] Optionally, the light emitting structure includes a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence, and the light emitting structure has a groove extending from a surface of the second semiconductor layer away from the light emitting layer toward the first semiconductor layer.

[0083] Illustratively, a photoresist structure can be obtained on the surface of the second semiconductor layer away from the light-emitting layer through processes such as photoresist coating, exposure, and development, and the surface of the second semiconductor layer away from the substrate can be etched using the photoresist structure as a mask through methods such as inductively coupled plasma (ICP) etching, and the etching depth extends from the surface of the second semiconductor layer away from the light-emitting layer to the first semiconductor layer, and a groove exposing the first semiconductor layer is formed after removing the photoresist structure.

[0084] Optionally, before forming the light emitting structure, a buffer layer may be formed on the substrate.

[0085] In step S202 , a current blocking layer is formed on the second semiconductor layer.

[0086] Exemplarily, an initial current blocking layer can be deposited on the entire surface of the second semiconductor layer, and a photoresist structure can be obtained on the initial current blocking layer through processes such as photoresist coating, exposure, and development. The initial current blocking layer is etched using the photoresist structure as a mask, and the current blocking layer is formed after removing the photoresist structure.

[0087] In step S203 , a transparent conductive layer is formed on the current blocking layer.

[0088] Exemplarily, an initial ITO layer can be deposited on the entire surface of the second semiconductor layer, and a photoresist structure can be obtained on the initial ITO layer through processes such as photoresist coating, exposure, and development. The initial ITO layer is etched using an ITO etching solution using the photoresist structure as a mask, and a transparent conductive layer is formed after the photoresist structure is removed.

[0089] In step S204 , a first connecting electrode is formed on the bottom surface of the groove and a second connecting electrode is formed on the transparent conductive layer.

[0090] Exemplarily, a photoresist structure can be obtained on the surface of the product obtained in step S203 through processes such as photoresist coating, exposure, and development, and a first connecting electrode and a second connecting electrode are formed by an electron beam evaporation process and a stripping process using the photoresist structure as a mask. The first connecting electrode is located at the bottom of the groove and is connected to the first semiconductor layer, and the second connecting electrode is located on the surface of the transparent conductive layer away from the current blocking layer and is connected to the transparent conductive layer.

[0091] In step S205 , an insulating material solution is coated on the light emitting structure.

[0092] Exemplarily, an insulating material solution may be coated on the surface of the product obtained in step S203 .

[0093] Optionally, the relative dielectric constant of the insulating material solution is 3.8 to 4. The relative dielectric constant refers to the ratio of the capacitance of the material to the capacitance of the same electrode distance in a vacuum when the dielectric strength is the same. The larger the relative dielectric constant, the better the insulating performance of the material. When the relative dielectric constant of the insulating material solution is within this range, the insulating layer can better protect the light-emitting structure.

[0094] Exemplarily, the relative dielectric constant of the insulating material solution may be 3.9 to 3.97. For example, the relative dielectric constant of the insulating material solution may be 3.9, 3.95, or 3.97.

[0095] In step S206, the insulating material solution is hardened to obtain an insulating layer.

[0096] The insulating layer is located on the surface of the second semiconductor layer away from the light emitting layer, the side wall of the light emitting structure, the side wall of the groove and the bottom surface of the groove. An air cavity exists between the insulating layer and the light emitting structure, and the air cavity includes a first air cavity and a second air cavity, the first air cavity is located between the insulating layer, the side wall of the groove and the bottom surface of the groove, and the second air cavity is located between the insulating layer, the side wall of the light emitting structure and the surface of the substrate.

[0097] Exemplarily, the sidewall of the light emitting structure includes a first sidewall connected to the surface of the substrate and not connected to the bottom surface of the groove, and the second air cavity is located between the insulating layer, the first sidewall of the light emitting structure and the surface of the substrate.

[0098] Exemplarily, the insulating layer covers the surface of the transparent conductive layer away from the second semiconductor layer, the side wall of the transparent conductive layer, the surface of the first connecting electrode away from the first semiconductor layer, the side wall of the first connecting electrode, the surface of the second connecting electrode away from the transparent conductive layer, and the side wall of the second connecting electrode. The insulating layer has a first through hole exposing the first connecting electrode and a second through hole exposing the second connecting electrode.

[0099] Optionally, the temperature for hardening the insulating material solution is 350°C to 600°C. If the temperature of the hardening film is too low or too high, it may be difficult to form a first air cavity between the insulating layer, the side wall of the groove and the bottom surface of the groove, and to form a second air cavity between the insulating layer, the side wall of the light-emitting structure and the surface of the substrate. When the temperature of the hardening film is within this range, the molecules of the insulating material solution can approach each other during the hardening film process, causing the material to shrink, which is conducive to forming an air cavity with better quality. Moreover, the temperature within this range will not affect the quality of the light-emitting structure. Here, since the thickness of the first semiconductor layer located below the bottom surface of the groove is relatively small, an air cavity will not be formed at the side wall position of the first semiconductor layer located below the bottom surface of the groove and connected to the bottom surface of the groove.

[0100] Exemplarily, the temperature for hardening the insulating material solution may be 350° C. to 550° C. For example, the temperature for hardening the insulating material solution may be 350° C., 450° C., or 550° C., etc.

[0101] In other embodiments, the temperature for hardening the insulating material solution may be greater than 550° C. and less than or equal to 600° C. For example, the temperature for hardening the insulating material solution may be 560° C., 580° C., or 600° C., etc.

[0102] Optionally, the duration of hardening the insulating material solution is 300s to 500s. The duration of hardening within this range is conducive to forming a first air cavity between the insulating layer, the sidewall of the groove and the bottom surface of the groove through hardening, and forming a second air cavity between the insulating layer, the sidewall of the light-emitting structure and the surface of the substrate.

[0103] Exemplarily, the duration of hardening the insulating material solution may be 300 s to 400 s. For example, the duration of hardening the insulating material solution may be 300 s, 350 s, or 400 s.

[0104] In other embodiments, the duration of hardening the insulating material solution may be greater than 400 seconds and less than or equal to 500 seconds. For example, the duration of hardening the insulating material solution may be 430 seconds, 460 seconds, or 500 seconds.

[0105] Through the above steps S205 to S206, an insulating layer can be formed on the light emitting structure.

[0106] In step S207 , a third connection electrode and a fourth connection electrode are formed on the insulating layer.

[0107] Exemplarily, a photoresist structure can be obtained on the insulating layer through processes such as photoresist coating, exposure, and development, and the third connecting electrode and the fourth connecting electrode are formed by an electron beam evaporation process and a stripping process using the photoresist structure as a mask. The third connecting electrode is connected to the first connecting electrode through the first through hole, and the fourth connecting electrode is connected to the second connecting electrode through the second through hole.

[0108] In step S208 , a DBR layer is formed on the insulating layer.

[0109] Exemplarily, an initial DBR layer may be deposited on the entire surface of the product obtained in step S207, a photoresist structure may be obtained on the DBR layer by processes such as photoresist coating, exposure, and development, and the initial DBR layer may be etched using the photoresist structure as a mask, and the DBR layer may be formed after the photoresist structure is removed. The DBR layer covers the surface of the third connection electrode away from the substrate, the side wall of the third connection electrode, the surface of the fourth connection electrode away from the substrate, and the side wall of the fourth connection electrode. The DBR layer has a third through hole exposing the third connection electrode and a fourth through hole exposing the fourth connection electrode.

[0110] In step S209 , a first pad electrode and a second pad electrode are formed on the DBR layer.

[0111] Exemplarily, a photoresist structure can be obtained on the DBR layer through processes such as photoresist coating, exposure, and development, and the first pad electrode and the second pad electrode are formed by an electron beam evaporation process and a stripping process using the photoresist structure as a mask. The first pad electrode is connected to the third connecting electrode through the third through hole, and the second pad electrode is connected to the fourth connecting electrode through the fourth through hole.

[0112] Optionally, the structure, material, shape, angle, etc. of each layer can be found in Figures 1 to 3The detailed description of the related embodiments is omitted here.

[0113] The brightness of the LED chips provided in the embodiments of the present disclosure is exemplarily described below. Figures 1 to 3 The LED chip in the relevant embodiment adopts Figure 5 The control group LED chip refers to the LED chip in the related art. The difference between the control group LED chip and the experimental group LED chip is that the insulating layer of the control group LED chip is formed by plasma enhanced chemical vapor deposition (PECVD), and the insulating layer and the light-emitting structure are tightly fitted without air cavity.

[0114] The brightness of the three control group LED chips and the experimental group LED chips were tested under the condition of 5 mA current. Table 1 shows the brightness test results of the control group LED chips and the experimental group LED chips.

[0115] Table 1 Brightness test results

[0116]

[0117]

[0118] After testing, it was found that the brightness of the LED chips in the experimental group was higher than that in the control group, and the brightness of the LED chips in the experimental group was increased by about 1% to 1.5% relative to that in the control group. Therefore, the LED chips provided in the embodiments of the present disclosure improve the brightness of the LED chips.

[0119] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A light emitting diode chip, characterized in that: It comprises a light emitting structure (10) and an insulating layer (20) located on the surface of the light emitting structure (10), An air cavity (30) exists between the insulating layer (20) and the light-emitting structure (10), and the air cavity (30) is used to reflect light emitted by the light-emitting structure (10) toward a light-emitting surface of the light-emitting diode chip, wherein the light-emitting surface of the light-emitting diode chip is located on a side of the light-emitting structure (10) away from the insulating layer (20).

2. The light emitting diode chip according to claim 1, characterized in that: The light emitting structure (10) comprises a first semiconductor layer (11), a light emitting layer (12) and a second semiconductor layer (13) which are sequentially stacked in a direction close to the insulating layer (20); the light emitting structure (10) has a groove (14) extending from a surface of the second semiconductor layer (13) away from the light emitting layer (12) toward the first semiconductor layer (11); The air cavity (30) comprises a first air cavity (31), wherein the first air cavity (31) is located between the insulating layer (20), the side wall of the groove (14) and the bottom surface of the groove (14).

3. The light emitting diode chip according to claim 2, characterized in that: In the stacking direction of the first semiconductor layer (11), the light-emitting layer (12) and the second semiconductor layer (13), the height of the first air cavity (31) is greater than or equal to the distance between the surface of the light-emitting layer (12) away from the first semiconductor layer (11) and the bottom surface of the groove (14), and is less than the distance between the surface of the second semiconductor layer (13) away from the light-emitting layer (12) and the bottom surface of the groove (14).

4. The light emitting diode chip according to claim 2 or 3, characterized in that: The included angle between the side wall of the groove (14) and the bottom surface of the groove (14) is 40° to 80°.

5. The light emitting diode chip according to claim 1, characterized in that: The light-emitting diode chip further comprises a substrate (40), wherein the substrate (40) is located on a surface of the light-emitting structure (10) away from the insulating layer (20); The air cavity (30) comprises a second air cavity (32), wherein the second air cavity (32) is located between the insulating layer (20), the side wall of the light emitting structure (10) and the surface of the substrate (40).

6. The light emitting diode chip according to claim 5, characterized in that: The light emitting structure (10) comprises a first semiconductor layer (11), a light emitting layer (12) and a second semiconductor layer (13) which are sequentially stacked in a direction close to the insulating layer (20); In the stacking direction of the first semiconductor layer (11), the light-emitting layer (12) and the second semiconductor layer (13), the height of the second air cavity (32) is greater than the distance between the surface of the light-emitting layer (12) close to the first semiconductor layer (11) and the surface of the substrate (40), and is less than or equal to the distance between the surface of the light-emitting layer (12) far from the first semiconductor layer (11) and the surface of the substrate (40).

7. The light emitting diode chip according to claim 5 or 6, characterized in that: The angle between the side wall of the light emitting structure (10) and the surface of the substrate (40) is 40° to 80°.

8. The light emitting diode chip according to any one of claims 1 to 3 and claims 5 to 6, characterized in that: The refractive index of the insulating layer (20) is 1.05 to 1.

5.

9. A method for preparing a light emitting diode chip, characterized in that: include: Providing a light-emitting structure (10); An insulating layer (20) is formed on the light-emitting structure (10), an air cavity (30) exists between the insulating layer (20) and the light-emitting structure (10), and the air cavity (30) is used to reflect light emitted by the light-emitting structure (10) toward a light-emitting surface of the light-emitting diode chip, wherein the light-emitting surface of the light-emitting diode chip is located on a side of the light-emitting structure (10) away from the insulating layer (20).

10. The preparation method according to claim 9, characterized in that: The step of forming an insulating layer (20) on the light emitting structure (10) comprises: coating an insulating material solution on the light-emitting structure (10); The insulating material solution is hardened to obtain the insulating layer (20).

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